A variable dead-time strategy for suppressing low-order harmonics of single-phase inverters

Abstract

The application relates to a variable dead zone strategy for inhibiting low-order harmonics of a single-phase inverter, and particularly relates to injecting a sinusoidal variable dead zone time into the single-phase inverter, so that the error voltage caused by the dead zone is in a sinusoidal wave rule, is consistent with the sinusoidal wave voltage output in an ideal state, and ensures that the actual output voltage is still a sinusoidal wave, thereby overcoming the waveform distortion caused by the dead zone. Compared with the prior art, the application has the advantages of being capable of inhibiting the output low-order harmonics caused by the dead zone to the maximum extent, reducing the influence of the dead zone effect, guaranteeing the output power quality and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inverter dead-time harmonic suppression, and particularly to a variable dead-time strategy for suppressing low-order harmonics of a single-phase inverter. BACKGROUND

[0002] In recent years, due to the shortage of traditional fossil energy, the development and utilization of new energy has become a research hotspot. In new energy power generation, inverter technology is the core technology, and the inverter is the core device. In order to improve the efficiency and quality of the output power of the circuit, the attention to the dead time of the inverter is increasing. The measures taken for the dead time at present are divided into two categories: dead time elimination and dead time compensation. Dead time elimination is based on the principle of dead time generation. According to the different directions of the output inductor current, only one switching device in the same bridge arm is allowed to switch, so as to avoid the shoot-through of the upper and lower switching tubes, and then the dead time is not needed. Dead time compensation usually uses the idea of feedback control. For example, the current feedback type detects the polarity of the output current of the inverter to obtain the corresponding error voltage square wave signal, which is superimposed on the modulation wave to control the circuit.

[0003] In the specific implementation scheme of the dead time elimination strategy, due to the influence of inductor current ripple, the judgment of the current direction at the zero-crossing point is fuzzy, which requires high precision of the detection equipment, increasing the research cost and difficulty. In the specific implementation scheme of the dead time compensation strategy, due to the influence of zero-current clamping, the judgment of the current direction at the zero-crossing region is also fuzzy, which will make the error square wave signal inaccurate, resulting in false compensation.

[0004] A PWM complementary output method with variable dead time is disclosed in Chinese patent CN101860251B. The patent circuit is simple, the dead time is wide-range adjustable, and is suitable for integration into a microcontroller with a PWM waveform generator. However, the patent cannot suppress the output low-order harmonics caused by the dead time to the maximum extent, reduce the influence of the dead time effect, and effectively ensure the quality of the output power. SUMMARY

[0005] The present application is to overcome the defects of the prior art and provide a variable dead-time strategy for suppressing low-order harmonics of a single-phase inverter, which can suppress the output low-order harmonics caused by the dead time to the maximum extent, reduce the influence of the dead time effect, and ensure the quality of the output power.

[0006] The object of the present application can be achieved by the following technical solutions:

[0007] A variable dead-time strategy for suppressing low-order harmonics of a single-phase inverter, the variable dead-time strategy specifically comprises:

[0008] The dead time of the single-phase inverter is injected with a sinusoidal variation, so that the error voltage caused by the dead time is in a sinusoidal wave, which is consistent with the ideal output sinusoidal wave voltage, so that the actual output voltage is still a sinusoidal wave, thereby overcoming the waveform distortion caused by the dead time.

[0009] As a preferred technical solution, the variable dead zone strategy further comprises:

[0010] The strategy effectiveness is verified by a strategy verification model, and the strategy verification model is specifically:

[0011] Step 1: constructing a mathematical model of the output voltage of the single-phase inverter in an ideal case;

[0012] Step 2: constructing a mathematical model of the output voltage of the inverter in the case of dead zone;

[0013] Step 3: analyzing the harmonic generation reason by the dead zone setting mode, and verifying the effectiveness of the variable dead zone strategy.

[0014] As a preferred technical solution, the step 1 is specifically:

[0015] The Fourier expression of the mathematical model of the output voltage of the single-phase inverter in an ideal case is:

[0016]

[0017] Wherein, A 00 is a DC component; A 0n +jB 0n is a low-order harmonic component; A mn +jB mn is a high-order harmonic component.

[0018] As a preferred technical solution, the step 1 further comprises:

[0019] After mathematical operation, the DC component A 00 = 0, and the low-order harmonic component is:

[0020]

[0021] It is shown that in an ideal case, only the fundamental component exists in the output of the single-phase inverter, and there is no low-order harmonic.

[0022] As a preferred technical solution, the step 2 is specifically:

[0023] The Fourier expression of the mathematical model of the output voltage of the inverter in the case of dead zone is:

[0024]

[0025] Wherein, A 00 ' is a DC component; A0n '+jB 0n 'is low harmonic component; A mn '+jB mn 'is high harmonic component.

[0026] As a preferred technical solution, the step 2 further comprises:

[0027] determining the DC component of the dead-time effect:

[0028] C 00 =A 00 -A 00 '

[0029] determining the low harmonic component:

[0030] C 0n +jD 0n =(A 0n +jB 0n )-(A 0n '+jB 0n ').

[0031] As a preferred technical solution, the step 3 specifically comprises:

[0032] Step 3-1: determining the low harmonic source by using fixed dead-time setting mode;

[0033] Step 3-2: verifying the effectiveness of variable dead-time by using variable dead-time setting mode.

[0034] As a preferred technical solution, the step 3-1 specifically comprises:

[0035] using fixed dead-time setting mode, i.e. the dead-time in a cycle is a fixed value, setting the current phase to 0, when the dead-time width is fixed, i.e. T d =T s , calculating the DC component C 00 =0, and the low harmonic component is:

[0036]

[0037] Therefore, the low harmonic in the actual voltage is generated by the set fixed dead-time.

[0038] As a preferred technical solution, the step 3-2 specifically comprises:

[0039] taking different values of the dead-time amplitude T m , verifying the low harmonic component and the fundamental component output by the inverter, and confirming the best variable dead-time setting scheme.

[0040] As a preferred technical scheme, the optimal variable dead zone setting mode confirmed in the step 3-2 is specifically as follows:

[0041] The variable dead zone setting mode that the dead zone time varies in a sinusoidal mode, that is, T v = |T m sinω r t| = T m |sinω 00 t|, the direct current component C ao = 0, and the low-order harmonic component is:

[0042]

[0043] Therefore, when the dead zone time varies in a sinusoidal mode, the output voltage only contains the fundamental component and does not contain the low-order harmonic.

[0044] Compared with the prior art, the present application has the following beneficial effects:

[0045] The variable dead zone strategy in the present application proposes a dead zone control strategy that the dead zone time varies in real time in a power frequency cycle, that is, the dead zone time in each switching cycle is not the same, and the dead zone time varies in a sinusoidal mode as a whole. According to the mathematical model, it can be concluded that the present application can most effectively suppress the output low-order harmonic caused by the dead zone, reduce the influence of the dead zone effect, and ensure the output power quality. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 It is a single-phase voltage source inverter topology in the embodiment of the present application;

[0047] Figure 2 It is a switching state diagram in the working process of the inverter circuit in the embodiment of the present application;

[0048] Among them, Figure 2 (a) represents an ideal gate drive signal, Figure 2 (b) represents an actual gate drive signal after inserting a dead zone, Figure 2 (c) represents an ideal output voltage U ao * , Figure 2 (d) represents an actual output voltage U ao (i a > 0) after inserting a dead zone, Figure 2 (e) represents an error voltage (i a > 0) caused by the dead zone in a period;

[0049] Figure 3 It is a half-wave symmetric dead zone time diagram inserted according to different current polarities in the embodiment of the present application;

[0050] Among them, Figure 3(a) represents the fixed dead time inserted, Figure 3 (b) represents the variable dead time inserted with sinusoidal variation. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work should fall within the protection scope of the present application.

[0052] The embodiment provides a variable dead time strategy for suppressing low-order harmonics of a single-phase inverter, in particular:

[0053] The dead time with sinusoidal variation is injected into the single-phase inverter, so that the error voltage caused by the dead time presents a sinusoidal wave rule, which is consistent with the sinusoidal wave voltage output in an ideal state, thereby ensuring that the actual output voltage is still a sinusoidal wave, and the waveform distortion caused by the dead time is overcome.

[0054] The embodiment first analyzes the working state of the single-phase inverter circuit, so as to Figure 1 As can be seen from the single-phase voltage source inverter, in order to prevent the short circuit of the direct current side caused by the short circuit of the upper and lower bridge arms, the dead time must be inserted in the switching cycle to ensure the safety of the circuit. Assuming that S1 is turned on and S2 is turned off, if the switching state is switched to turn on S2, S1 must be turned off first, and then S2 is turned on after the dead delay ends. Therefore, three time variables are involved, the turn-on delay T on , the turn-off delay T off and the dead time T d . Due to the existence of the dead time and the switching delay, the deviation of the output voltage from the expected voltage is caused, and at the same time, due to the uncontrollability in the dead time, the current waveform is distorted, harmonics are introduced, and due to the current clamping in the zero-crossing region, the voltage waveform is distorted, and finally the power quality of the output is affected. The actual working state of the circuit after the dead time is inserted is shown in Figure 2 . Figure 2 (a) represents the ideal gate drive signal (a group of signal drives for the switching tubes S1 and S4, and a group of signal drives for S2 and S3), (b) represents the actual gate drive signal after the dead time is inserted (a group of signal drives for the switching tubes S1 and S4, and a group of signal drives for S2 and S3), Figure 2 (c) represents the ideal output voltage U ao * , Figure 2 (d) represents the actual output voltage U ao (ia >0), Figure 2 (e) represents the error voltage caused by dead zone in one cycle a >0). Define error voltage ΔU ao = U ao * -U ao , modulation wave u r = U rm sin Y, current sign(i a ) represents the direction of current signal,

[0055] carrier U c represents as follows:

[0056]

[0057] Let modulation ratio M = U rm / U cm , carrier ratio N = ω c / ω r , X = ω c t, Y = ω r t, ω c , ω r are the angular frequencies of carrier and modulation wave respectively. In one carrier cycle, i.e. -π + 2kπ ≤ ω c t ≤ π + 2kπ, Figure 2 the coordinate values of each point in the middle are as follows:

[0058] X a = -π + 2kπ,

[0059] X d = π + 2kπ

[0060] The voltage of bridge arm a to the midpoint o can be represented as:

[0061]

[0062] Let m be the harmonic number relative to the carrier, and n be the harmonic number relative to the modulation wave.

[0063] First, analyze the working process of the inverter circuit in the ideal state. The bridge arm voltage u ao is as follows:

[0064]

[0065] Wherein the direct current component A 00 is as follows:

[0066]

[0067] The final result is calculated as A 00 = 0

[0068] Low-order harmonic component A 0n +jB 0n As follows:

[0069]

[0070] The final result is calculated as:

[0071]

[0072] Harmonic A at the switching frequency m0 +jB m0 and the harmonic A of the switching frequency sideband mn +jB mn mn≠0 all belong to high-order harmonics, because the inverter system has a filter circuit, so the influence of high-order harmonics is not considered here.

[0073] From the above analysis, when the inverter circuit works in an ideal state, the DC component of the output voltage is 0 and only contains the fundamental component, without harmonic components.

[0074] Next, analyze the working process when the circuit is set with a dead time T d , the voltage of the bridge arm a to the midpoint o can be expressed as follows:

[0075]

[0076] The double Fourier expression is as follows:

[0077]

[0078] DC component A 00 ' as follows:

[0079]

[0080] Low-order harmonic component A 0n '+jB 0n ' as follows:

[0081]

[0082] Then the output DC component C caused by the dead zone 00 =A 00 -A 00 ';

[0083] The final result is calculated as:

[0084]

[0085] Low-order harmonic components in the output caused by the dead zone: C 0n +jD 0n =(A 0n +jB 0n )-(A 0n '+jB 0n ')

[0086] The final result after calculation is:

[0087]

[0088] The above analysis shows that the low-order harmonic components in the actual output voltage are caused by the dead zone, and each harmonic can be equivalently regarded as a function of the dead zone, sign(i). a )T s There exists Ef in Fourier analysis c The relationship is multiple. For ease of analysis, assume the current phase is 0, when sign(i a )T s satisfy Figure 3 When the half-wave symmetric odd function is shown, C 00 =0,C 0n =0, set the dead time T according to the traditional fixed dead time strategy. d T is a constant. d =T s At that time, the DC component C of the dead zone 00 =0, the lower harmonic components are calculated as follows:

[0089]

[0090] That is, a fixed dead zone causes the output to produce low-order harmonic components.

[0091] Further analysis of the variable dead-time strategy proposed in this invention, i.e., the dead-time according to... Figure 3 (b) shows the regular variation of the sinusoidal function. Ideally, the sinusoidal dead-time function T... d =|T m sinω r t|,T m For the set maximum dead time, Y = ω r If t, then:

[0092] sign(i a )T d =sign(i a )|T m sinω r t|

[0093] =T m sinY

[0094] According to the foregoing analysis, the direct current component C 00 As follows:

[0095]

[0096] Low harmonic component C 0n +jD 0n As follows:

[0097]

[0098] Variable dead zone equivalent:

[0099]

[0100] The expression can be seen that the variable dead zone error voltage is a pure positive sine wave.

[0101] From the above analysis: ideal sine variable dead zone time does not produce low harmonic, only contains the fundamental component. Theoretically, it can inhibit the low harmonic problem caused by the dead zone to the greatest extent, and can effectively improve the output waveform and reduce THD.

[0102] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A variable dead-band strategy for suppressing low order harmonics of a single phase inverter, characterized by, The variable dead-time strategy specifically is: The single-phase inverter is injected with a sinusoidal variable dead-time, and the function of the sinusoidal variable dead-time is: wherein T m is the set maximum dead time, ω r is the angular frequency of the modulation wave; The error voltage caused by the dead-time is in a sinusoidal wave form, which is consistent with the ideal output sinusoidal wave voltage, so that the actual output voltage is still a sinusoidal wave, thereby overcoming the waveform distortion caused by the dead-time.

2. A variable dead-band strategy for suppressing low order harmonics of a single phase inverter as claimed in claim 1, wherein, The variable dead-time strategy further includes: The strategy validity is verified by a strategy verification model, and the strategy verification model specifically is: Step 1: constructing a single-phase inverter output voltage mathematical model in an ideal case; Step 2: constructing an inverter output voltage mathematical model in a dead-time case; Step 3: analyzing the harmonic generation reason through a dead-time setting mode and verifying the validity of the variable dead-time strategy.

3. A variable dead-band strategy for suppressing low order harmonics of a single phase inverter as claimed in claim 2, wherein, The step 1 specifically is: The Fourier expression of the single-phase inverter output voltage mathematical model in the ideal case is: wherein is the direct current component; is the low harmonic component; is the high harmonic component.

4. A variable dead-band strategy for suppressing low order harmonics of a single phase inverter as claimed in claim 3 wherein, The step 1 further includes: After mathematical operation, the direct current component is obtained The low-order harmonic component is: It is indicated that only the fundamental wave component exists in the ideal single-phase inverter output, and there is no low-order harmonic.

5. A variable dead-band strategy for suppressing low order harmonics of single phase inverters as claimed in claim 2, wherein, The step 2 specifically is: The Fourier expression of the inverter output voltage mathematical model in the dead-time case is: wherein is a direct current component; is a low order harmonic component; is a high order harmonic component.

6. A variable dead-band strategy for suppressing low order harmonics of a single phase inverter as claimed in claim 5 wherein, The step 2 further includes: The direct current component of the dead-time effect is determined: The low-order harmonic component is determined: 。 7. A variable dead-band strategy for suppressing low order harmonics of single phase inverter as claimed in claim 2 wherein, The step 3 specifically is: Step 3-1: a fixed dead-time setting mode is adopted to determine the low-order harmonic source; Step 3-2: the validity of the variable dead-time strategy is verified by using a variable dead-time setting mode.

8. A variable dead-band strategy for suppressing low order harmonics of a single phase inverter as claimed in claim 7, wherein, The step 3-1 specifically is: Adopt the fixed dead zone setting mode, that is, the dead zone time in a cycle is a fixed value, set the current phase to 0, when the dead zone width is fixed, that is , the calculated direct current flow , the low harmonic component is: Therefore, the low-order harmonic in the actual voltage is generated by the set fixed dead-time.

9. A variable dead-band strategy for suppressing low order harmonics of single phase inverters as claimed in claim 7, wherein, The step 3-2 specifically is: Dead time magnitude T m Taking different values, verify the low harmonic component and fundamental component of inverter output, confirm the best variable dead zone setting scheme.

10. A variable dead-band strategy for suppressing low order harmonics of a single phase inverter as claimed in claim 9 wherein, The variable dead-time setting mode without low-order harmonic screened out in the step 3-2 specifically is: The variable dead zone setting mode of sine variation dead zone time is adopted, that is , the direct current component is calculated as , and the low harmonic component is Therefore, when the dead-time changes in a sinusoidal wave form, the output voltage only contains the fundamental wave component, and there is no low-order harmonic.

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