High performance phase-locked loop

Abstract

This invention discloses a high-performance phase-locked loop, comprising: a plurality of partial phase comparators for: acquiring at least one reference signal phase and acquiring a plurality of local oscillator signal phases; forming at least three partial phase error signals, wherein each partial phase error signal is formed by comparing the phase of the at least one reference signal phase with a corresponding phase among the plurality of local oscillator signal phases; applying a corresponding weighting factor to each of the at least three partial phase error signals, wherein each weighting factor is selected from a matrix weighting factor configuration related to the phase offset between the reference signal and the local oscillator signals; and a summing circuit for generating a composite phase error signal by analog summing of the plurality of partial phase error signals, and adjusting a fixed phase of the local oscillator in response to the composite phase error signal.

Description

[0001] This application is a divisional application of patent application No. 201780036606.2, filed on April 21, 2017, entitled "High-performance phase-locked loop".

[0002] Cross-reference to related applications

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 326,591, filed April 22, 2016, by Armin Tajalli, entitled “High-Performance Phase-Locked Loop”, the contents of which are incorporated herein by reference in their entirety.

[0004] References

[0005] The following references are incorporated herein by reference in their entirety for all purposes:

[0006] The U.S. patent application, titled "Orthogonal Differential Vector Signaling," was filed on May 20, 2010, with publication number 2011 / 0268225, application number 12 / 784,414, and inventors Harm Cronie and Amin Shokrollahi. It is hereinafter referred to as "Cronie 1."

[0007] U.S. patent application No. 2011 / 0302478, application No. 12 / 982,777, application date December 30, 2010, inventors Harm Cronie and Amin Shokrollahi, entitled “High pin utilization and high power utilization chip communication with common-mode noise immunity and synchronous switching output noise immunity”, hereinafter referred to as “Cronie 2”;

[0008] The U.S. patent application with application number 13 / 030,027, filed on February 17, 2011, and inventors Harm Cronie, Amin Shokrollahi, and Armin Tajalli, entitled “Method and System for Noise-resistant, High Pin Utilization, and Low-Power Communication Using Sparse Signaling Codes”, hereinafter referred to as “Cronie 3”;

[0009] The U.S. patent application with application number 13 / 176,657, filed on July 5, 2011, and inventors Harm Cronie and Amin Shokrollahi, entitled “Method and System for Low-Power High-Pin-Utilization Communication Using Superimposed Signaling Codes”, hereinafter referred to as “Cronie 4”;

[0010] The U.S. patent application with application number 13 / 542,599, filed on July 5, 2012, and inventors Armin Tajalli, Harm Cronie, and Amin Shokrollahi, entitled “Method and Circuit for Efficient Processing and Detection of Balanced Codes”, hereinafter referred to as “Tajalli 1”;

[0011] The U.S. patent application with application number 13 / 842,740, filed on March 15, 2013, and inventors Brian Holden, Amin Shokrollahi, and Anant Singh, entitled “A method and system for skew tolerance of vector signaling codes for inter-chip communication and an advanced detector for vector signaling codes for inter-chip communication”, hereinafter referred to as Holden 1;

[0012] The U.S. provisional patent application, entitled "Clock Embedded Vector Signaling Code", with application number 61 / 946,574 and application date of February 28, 2014, is authored by Amin Shokrollahi, Brian Holden, and Richard Simpson and is referred to as "Shokrollahi 1".

[0013] The U.S. patent application with application number 14 / 612,241, filed on August 4, 2015, and inventors Amin Shokrollahi, Ali Hormati, and Roger Ulrich, entitled “Method and apparatus for low-power inter-chip communication with low inter-symbol interference ratio”, hereinafter referred to as “Shokrollahi 2”.

[0014] The U.S. patent application with application number 13 / 895,206, filed on May 15, 2013, and inventors Roger Ulrich and Peter Hunt, entitled “Circuit for Efficiently Detecting Vector Signaling Codes for Inter-Chip Communication via Difference Sum”, hereinafter referred to as “Ulrich 1”;

[0015] The U.S. patent application with application number 14 / 816,896, filed on August 3, 2015, and inventors Brian Holden and Amin Shokrollahi, entitled "Orthogonal Differential Vector Signaling Code with Embedded Clock", hereinafter referred to as Holden2;

[0016] The U.S. patent application with application number 14 / 926,958, filed on October 29, 2015, and inventors Richard Simpson, Andrew Stewart, and Ali Hormati, entitled "Clock Data Alignment System for Vector Signaling Code Communication Links", hereinafter referred to as "Stewart 1";

[0017] The U.S. patent application with application number 14 / 925,686, application date October 28, 2015, inventor Armin Tajalli, entitled "Improved Phase Interpolator", hereinafter referred to as "Tajalli 2";

[0018] The U.S. provisional patent application, entitled "High-Frequency Gain Improved Voltage Sampling Driver," with application number 62 / 286,717 and filing date of January 25, 2016, is authored by Armin Tajalli and is referred to as "Tajalli3".

[0019] In addition, the following prior art references are cited in this application:

[0020] The patent number is 6,509,773, the application date is April 30, 2001, the inventor is Buchwald et al., and the title is "Phase Interpolator Apparatus and Method", hereinafter referred to as "Buchwald".

[0021] "Linear phase detection using a two-phase latch", A. Tajalli et al., IEEE Electronics Letters, 2003, hereinafter referred to as "Tajalli 4";

[0022] "Low jitter and low phase noise 10 GHz subharmonic injection locked phase-locked loop with 65 nm CMOS self-aligned DLL", Hong-Yeh Chang, Yen-Liang Yeh, Yu-Cheng Liu, Meng-Han Li and Kevin Chen, IEEE Transactions on Microwave Theory and Technique, Vol. 62, No. 3, March 2014, pp. 543-555, hereinafter referred to as "Chang et al."

[0023] "Low Phase-Noise 77GHz Fraction-N Frequency-Locked Loop with Delay-Locked Loop-Based Reference Multiplier for FMCW Radar," Herman Jalli Ng, Rainer Stuhlberger, Linus Maurer, Thomas Sailer and Andreas Stelzer, Proceedings of the 6th European Conference on Microwave Integrated Circuits, October 10-11, 2011, pp. 196-199, hereinafter referred to as "Ng et al."

[0024] "Highly Noise Robust Clock Data Recovery Design Using Bandwidth Adaptive Hybrid PLL / DLL", Han-Yuan Tan, Harvard University Doctoral Dissertation, November 2006, hereinafter referred to as "Tan". Technical Field

[0025] The embodiments of the present invention generally relate to communication system circuits, and more particularly to obtaining a phase-correct, stable receiver clock signal through a high-speed multi-line interface for inter-chip communication. Background Technology

[0026] In modern digital systems, digital information must be processed efficiently and reliably. In this context, digital information must be understood as information contained within discrete values ​​(i.e., discontinuous values). Digital information can be represented not only by bits and sets of bits, but also by numbers within a finite set.

[0027] To increase overall bandwidth, most chip-to-chip or device-to-device communication systems use multiple lines for communication. Each or each pair of these lines is called a channel or link, and multiple channels form a communication bus between electronic components. At the physical circuit level, the bus within a chip-to-chip communication system typically consists of packaged electrical conductors between the chip and the motherboard, packaged electrical conductors on the printed circuit board (PCB), or packaged electrical conductors within cables and connectors between PCBs. Furthermore, in high-frequency applications, microstrip or strip PCB lines can also be used.

[0028] Common bus line signal transmission methods include single-ended signaling and differential signaling. In applications requiring high-speed communication, these methods can be further optimized in terms of power consumption and pin utilization (especially in high-speed communication). Recently proposed vector signaling methods offer a more optimized trade-off between power consumption, pin utilization, and noise robustness in inter-chip communication systems. Such vector signaling systems convert digital information at the transmitter into different representation spaces in the form of vector codewords, and select different vector codewords based on the characteristics of the transmission channel and the design constraints of the communication system to achieve a better trade-off between power consumption, pin utilization, and speed. This process is referred to as "encoding" in this application. The encoded codewords are transmitted from the transmitter to one or more receivers as a set of signals. At the receiver, the received signals corresponding to the codewords are converted back into the original digital information representation space. This process is referred to as "decoding" in this application.

[0029] Regardless of the encoding method, the signal received by the receiving device must be sampled at intervals (or its signal value must be recorded in other ways). Moreover, regardless of the delay, interference, and noise conditions of the transmission channel, the sampling interval must ensure that the sampled value can best represent the original transmitted value. This clock data recovery (CDR) process not only needs to determine the appropriate sampling timing, but may also need to be performed continuously to achieve dynamic compensation under different signal propagation conditions.

[0030] Many known CDR systems employ phase-locked loops (PLLs) or delay-locked loops (DLLs) to synthesize a local receive clock with frequencies and phases suitable for achieving accurate data sampling. Summary of the Invention

[0031] In order to reliably detect data values ​​transmitted by a communication system, the receiver must be able to accurately measure the amplitude of the received signal value at carefully selected time points. Currently, there are various known methods that facilitate such reception measurements, including methods for receiving one or more dedicated clock signals associated with the transmitted data stream, methods for extracting embedded clock signals from the transmitted data stream, and methods for synthesizing a local receive clock based on known properties of the transmitted data stream.

[0032] Generally, the receiver-side implementation of this timing method is called clock data recovery (CDR), and it typically uses a phase-locked loop (PLL) or delay-locked loop (DLL) to synthesize a local receive clock with the desired frequency and phase characteristics.

[0033] In various PLL and DLL implementations, an error signal is generated by comparing the relative phase of the received reference signal and the local clock signal (or, in some variations, their relative frequencies) using a phase comparator. This error signal is then used to correct the phase and / or frequency of the local clock source, thereby minimizing the error. Since this feedback loop behavior results in a fixed phase relationship (e.g., a 0-degree or 90-degree phase shift) between the reference signal and the local clock in a given PLL implementation, this phase shift is typically set to a target value (e.g., a 45-degree phase shift) different from the aforementioned value by introducing additional fixed or variable phase adjustment to facilitate data detection by the receiver.

[0034] In the following method and system: N local clock signal phases and M reference signal phases are received, where M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2; a plurality of partial phase error signals are generated, each partial phase error signal being formed at least partially by comparing (i) a corresponding phase among the M reference signal phases with (ii) a corresponding phase among the N local clock signal phases; a composite phase error signal is generated by adding the plurality of partial phase error signals; and the fixed phase of the local oscillator is adjusted in a responsive manner using the composite phase error signal.

[0035] In some implementations, M = 1, and the composite phase error signal is generated by adding N partial phase error signals together. Alternatively, the plurality of partial phase error signals comprises M = N partial phase error signals, and a single partial phase error signal is generated using a given phase from the N local clock signal phases and a given phase from the M reference signal phases. In other alternative implementations, the plurality of partial phase error signals comprises M × N partial phase error signals, and each phase of the N local clock signal phases is compared with each phase of the M reference signal phases.

[0036] In some embodiments, each of the plurality of partial phase error signals is assigned a corresponding weight value. In some embodiments, the weight values ​​are selected based on an M×N matrix.

[0037] In some implementations, the M reference signal phases are received from a delay-locked loop that processes the input reference signal.

[0038] In some embodiments, at least one of the N local clock signal phases is generated by a phase interpolator that processes the local oscillator signal and the phase offset signal. In some embodiments, generating at least one of the N local clock signal phases includes inserting four phases using four differential pairs within the phase interpolator, wherein each of the four phases is inserted based on a corresponding differential pair connected to an independently adjustable current source.

[0039] In some implementations, at least one partial phase error signal is formed by a pair of flip-flops, wherein a given phase of the M reference signal phases clocks a first flip-flop in the pair of flip-flops, and a given phase of the N local clock signal phases clocks a second flip-flop.

[0040] In some implementations, each phase error signal is an analog signal generated by a corresponding charge pump that receives a corresponding charge pump control signal, which is generated based on a comparison between a corresponding phase among the M reference signal phases and a corresponding phase among the N local clock signal phases.

[0041] In the embodiments described in this application, by combining the phase detection element with the phase adjustment element, the circuit node capacitance and circuit delay are reduced, thereby improving loop stability and PLL lockout characteristics, including reducing clock jitter and improving power supply noise suppression by increasing the loop lockout bandwidth.

[0042] In other embodiments described in this application, the received reference clock signal is converted into multiple reference clock phases via a DLL, thereby converting the phase comparison operation of the PLL into multiple comparisons between the reference clock phases and local clock phases, and the sum or weighted sum of the results of these multiple comparisons is subsequently used as the error feedback signal of the PLL. In another embodiment described in this application, multiple comparisons are performed between a single received reference clock phase and multiple local clock phases, and the weighted sum of the results of these multiple comparisons is used as the error feedback term of the PLL. In at least one of these other embodiments, the weighted sum includes a two-dimensional time-domain filter. Attached Figure Description

[0043] Figure 1 This is a block diagram of an implementation method capable of encoding and transmitting five data bits and one clock cycle over an eight-line communication channel.

[0044] Figure 2 As a kind of with Figure 1 Block diagram of a transmitter-compatible receiver implementation.

[0045] Figure 3 As a kind Figure 2 A block diagram illustrating the implementation of the clock recovery circuit used in the receiver.

[0046] Figure 4A , Figure 4B and Figure 4C The diagram shows three implementations of phase comparators for phase-locked loop elements suitable for clock recovery circuits.

[0047] Figure 5 This is a schematic diagram of an implementation that integrates an XOR phase comparator and a clock phase interpolator.

[0048] Figure 6A This is a schematic diagram of a clock-controlled data latch; Figure 6B A schematic diagram of an implementation of another clock-controlled data latch that integrates a clock phase interpolator.

[0049] Figure 7A and Figure 7B This is a schematic diagram of an implementation that integrates a state machine phase comparator and a clock phase interpolator.

[0050] Figure 8 This is a schematic diagram of a charge pump implementation suitable for further integration with a phase comparator implementation.

[0051] Figure 9 This is a block diagram illustrating another implementation that compares multiple reference clock phases with multiple local clock phases.

[0052] Figure 10A block diagram of another implementation of performing multiple comparisons between a single reference clock and multiple local clock phases.

[0053] Figure 11A This is a weighted XOR phase comparator according to some implementations.

[0054] Figure 11B This is a block diagram illustrating an implementation method for matrix phase comparison of M reference phases and N local clock phases.

[0055] Figure 12A and Figure 12B for Figure 5 The diagram shows an alternative implementation that integrates a phase comparator and a phase interpolator.

[0056] Figure 13A This is a timing diagram of a folded phase comparator according to some implementations.

[0057] Figure 13B This is a timing diagram of the reverse clipping effect according to some implementation methods.

[0058] Figure 14A and Figure 14B Timing diagrams for an array XOR phase comparator and a single XOR phase comparator according to some implementations are shown.

[0059] Figure 15 This is a flowchart of a method according to some implementation methods. Detailed Implementation

[0060] As described in *Cronie 1*, *Cronie 2*, *Cronie 3*, and *Cronie 4*, extremely high-bandwidth data communication links can be established between, for example, two integrated circuit devices within a system using vector signaling codes. Figure 1 As shown in the implementation, vector signaling code symbols are transmitted via multiple data communication channels, working together to transmit the codeword of the vector signaling code. Depending on the specific vector signaling code used, the number of channels constituting the communication link can range from two to eight or more, and one or more clock signals can be transmitted on different communication channels, or the clock signal can be transmitted as a sub-channel component of the vector signaling code. Figure 1 In this embodiment, the illustrated communication link 120 consists of eight lines 125, which together transmit five data values ​​100 and a clock signal 105 between the transmitter 110 and the receiver 130.

[0061] Each symbol (e.g., each symbol transmitted in any single communication channel) can use multiple signal levels (typically three or more). When operating at channel rates above 10 Gbps, deep pipelined or parallel signal processing is required, further complicating the receiving process and rendering known receiving methods, where the previously received value is the current received value, unusable.

[0062] The embodiments described in this application can also be applied to existing permutation and combination sorting methods not covered by the vector processing methods described in Cronie 2, Cronie 3, Cronie 4 and / or Tajalli 1. More generally, these embodiments can be applied to any communication or storage method that requires the mutual coordination of multiple channels or channel elements to generate a coherent overall result.

[0063] Receiver data detection

[0064] The following description uses a typical high-speed receiver implementation from Stewart 1 as a background to illustrate various embodiments. These embodiments are for illustrative purposes only and do not constitute a limitation.

[0065] like Figure 2 As shown, this exemplary data receiver includes eight identical continuous-time linear equalization (CTLE) processing stages 210 for processing data previously received in [the context of the previous data]. Figure 1 The signals received by the eight lines, denoted as 120, are processed.

[0066] As described in *Tajalli 1*, *Holden 1*, and *Ulrich 1*, efficient detection of vector signaling codes can be achieved by linearly combining the input signals using a multi-input comparator (MIC) or mixer. For the 5b6w code used by the illustrated receiver above, detection of five data bits can be achieved by processing a weighted subset of the six received input data signals using five such mixers, without further decoding. Similarly, clock signal detection can be achieved by processing a combination of two received clock signals using an additional mixer. Figure 2 In this process, the received equalized signal is processed by a set of six MIC mixers 220 to generate six detected signals MIC0 to MIC5.

[0067] Because of the high data rate involved, multiple parallel receive processing stages can be used in the illustrated receiver. In one embodiment, the five detected data signals MIC0 to MIC4 are processed by four parallel receive data processing stages, each stage 230 including five data samplers and a downstream buffer. The outputs of these four stages are then recombined into a receive data stream. Figure 2 In the scenario shown, this recombination process is performed by multiplexer 240.

[0068] Clock recovery circuitry (also known in the art as clock data recovery or CDR) supports the aforementioned sampling measurements by extracting timing information from the data line itself or from a dedicated clock signal input, and uses the extracted information to generate a clock signal to control the time interval used by the data line sampling device. The actual clock extraction operation can be performed by well-known circuits such as phase-locked loops (PLLs) or delay-locked loops (DLLs), which can also generate higher-frequency internal clocks, multiple clock phases, etc., during operation to support receiver operation. Figure 2 In this implementation, the detected clock signal is obtained by MIC5 and then processed by 300 to extract the timing-correct sampling clock for the four data processing stages.

[0069] Phase-locked loop overview

[0070] Existing literature provides a detailed description of phase-locked loops (PLLs). A typical PLL consists of a phase comparator that compares an external reference signal with an internal clock signal, a low-pass filter that generates a clock signal by smoothing the resulting error value, and a variable-frequency clock source (typically a voltage-controlled oscillator (VCO)) that controls and generates the internal clock signal for processing by the phase comparator based on the smoothed error value. In a well-known variation of this PLL design, a clock divider can be placed between the VCO and the phase comparator to phase-lock a higher-frequency clock output to a lower-frequency reference signal.

[0071] In an alternative implementation, the variable frequency clock source is replaced by a variable delay element, such that its output (optionally multiple tapped outputs) represents one or more successive time-delayed forms of the original input signal, rather than successive oscillator cycles to be phase-compared with a reference input signal. For the purposes of this application, in such applications, particularly when these components—phase comparators, phase interpolators, and charge pumps—are associated, the delay-locked loop (DLL) is considered to function equivalently to a PLL.

[0072] Various forms of phase comparators are known in this art. As one example without limitation, Figure 4A The simplified XOR gate shown can be used to compare two square wave signals. Those skilled in the art will recognize that such a digital XOR output is a waveform with a variable duty cycle. When the two input signals have a 90-degree phase offset, this waveform, after being low-pass filtered into an analog error signal, can generate a proportional error signal centered at the center of its analog signal range.

[0073] Figure 4B The diagram shows a more complex state machine phase comparator, consisting of two edge-triggered latches clocked by a reference clock signal and an internal clock signal, respectively. A first received clock edge causes one of the "before" or "after" outputs to begin generating an output signal. Once either output begins, the latches reset to await the next comparison time interval. In other embodiments, a timing delay can be added to the reset path to implement additional reset pulse timing control. Generally, the "before" and "after" phase comparison outputs serve as the "rising" and "falling" inputs of a charge pump, whose output is the aforementioned analog error value. That is, the rising signal activates the first transistor circuit that charges the capacitor, thereby increasing the analog voltage; while the falling signal activates the second transistor circuit that discharges the capacitor, thereby decreasing the voltage. Therefore, when the phase offset between the two input clock signals is 0 degrees, the analog error value remains unchanged, keeping the phase-locked loop in a stable locked state. Various known implementations of equivalent state machine phase comparators exist in the art, and these implementations can be equally applied in this application, but this does not imply limitation on the invention. Some state machine implementations may be sensitive to both phase and frequency differences between the input signals, thereby facilitating faster PLL locking at startup.

[0074] like Figure 4C As shown, a single edge-clocked D flip-flop can also be used as a phase comparator. At each rising edge of the local clock (CkPLL), the D input samples the state of the reference input (CkRef) (a square wave in this example). If its state is "high" (e.g., it has undergone a transition), the Q output is also "high," indicating that the reference signal is "forward"; if its state is "low" (e.g., it has not undergone a transition), the Q output is also "low," indicating that the reference signal is "backward." Compared to the previous example, this so-called binary (Bang-Bang) phase comparator provides less subtlety in the error results, allowing for a higher level of filtering to achieve loop stability.

[0075] Those skilled in the art will recognize that similar functional operation can be achieved regardless of the type of phase comparator used in a PLL design; therefore, the choice of phase comparator is not a limitation in terms of overall performance. Furthermore, secondary design factors, including lock-in time, stability, and power consumption, must be considered during the design process.

[0076] Receiver clock recovery

[0077] Figure 3The illustrated receiver employs a PLL implementation. This PLL uses the received clock signal R5 as its phase-locked reference signal. In some embodiments, a logic level shifter 310 may be used as an interface between the signal level provided by the detection MIC and the preferred phase comparator input level. The phase comparator 320 generates an output value after comparing the reference clock with the local clock provided by the VCO. This output value is low-pass filtered to provide an error value for subsequent correction of the operating frequency of the VCO 340. In some embodiments, the phase comparator 320 outputs a digital waveform that needs to be converted into an analog error signal via implicit or explicit digital-to-analog conversion, or via an interface element such as a charge pump. In some embodiments, the conversion may be combined with or in part with the entire low-pass filtering operation via a digital filtering action, which is only a non-limiting example illustrated as a charge pump switching action controlled by a digital control signal to generate an analog signal output.

[0078] In at least one embodiment, a ring oscillator 340, consisting of a series of identical gate devices forming a closed loop, is used as the timing source for the internal voltage-controlled oscillator (VCO) of the PLL. The frequency of the VCO can be adjusted by simulating at least one of the gate propagation delay, gate rise / fall time, and gate switching threshold of the ring oscillator. This can be achieved using a switched capacitor bank, wherein, as a non-limiting embodiment, the RC time constant is changed by applying a digital control signal to selectively combine capacitive elements in parallel and / or series. Furthermore, the output switching rise / fall time can be changed by increasing or decreasing the current source used to drive the ring oscillator gates, thereby adjusting the effective delay. By sampling the output at equal intervals along the series of gates constituting the ring oscillator (i.e., sampling every equal number of ring oscillator gates), four data phase sampling clocks are obtained, referred to in this application as the 0-degree clock, 90-degree clock, 180-degree clock, and 270-degree clock, respectively.

[0079] In one embodiment, the ring oscillator consists of eight identical sets of logic gates (i.e., one set of inverter circuits), such that the phase difference between any two sets is 45 degrees. In this embodiment, for example, the 0-degree, 90-degree, 180-degree, and 270-degree outputs can be obtained from the second, fourth, sixth, and eighth outputs, respectively. Since various variations of this design are known in the art, the number of components within the ring oscillator and the specific taps providing the specific outputs should not be construed as constituting any limitation. For example, the 0-degree tap can be in any position, because those skilled in the art will recognize that, regardless of the initial phase, the PLL can align the ring oscillator phase with the external reference phase during normal operation. Similarly, in other equivalent designs, the output clock phase may not have a square wave duty cycle; one example is the use of AND gates or OR gates with inputs obtained from different tap positions. In the illustrated receiver, the VCO preferably operates at a multiple of the receiving reference clock frequency; therefore, a frequency divider 350 is provided upstream of the phase comparator to divide the VCO output by a corresponding coefficient. In one embodiment, the correct sampling clock rate is obtained by employing a binary (coefficient of 2) frequency divider 350. In another embodiment, instead of using a frequency divider, the VCO output is directly provided to the phase interpolator.

[0080] Each of the four sampling clock phases is appropriately timed to sample received data for one of the four parallel processing stages. Specifically, internal clock ph000 is aligned to optimally trigger the data sampler in processing stage 0, internal clock ph090 is aligned to optimally trigger the data sampler in processing stage 1, internal clock ph180 is aligned to optimally trigger the data sampler in processing stage 2, and internal clock ph270 is aligned to optimally trigger the data sampler in processing stage 3.

[0081] To offset the overall phase of the locked PLL signal from the phase of the reference clock input, a local clock output is provided to the phase comparator from the phase interpolator 360, whose output phase is controllably positioned between its input clock phases. Thus, not only is the PLL locked to its fixed phase relationship, but the phase delay introduced by the fixed-phase-offset phase interpolator 350 under the control of the signal phase offset correction function is also eliminated. Phase interpolators known in the art exist, such as those described in *Buchwald 1* and *Tajalli 2*.

[0082] In one embodiment, a phase interpolator 360 receives multiple local clock phases with a 90-degree phase difference from a ring oscillator 340. The phase interpolator can be controlled to select two adjacent clock input phases and then interpolate between them, thereby generating an output with a selected phase offset between the two selected values. For descriptive purposes, it can be assumed that the phase comparators used lock the PLL such that the phase difference between the two phase comparator inputs is zero. Thus, in this example, when clock phases of 0 degrees and 90 degrees are applied as inputs to the phase interpolator, the phase of the PLL can be adjusted to lead the reference clock input by 0 to 90 degrees.

[0083] It is readily understood that using two clocks with different degrees and / or other phase comparator designs can still yield equivalent results with similar phase shifts. However, as mentioned above, the locked phase difference in this case differs from the previous example. Therefore, the specific selected phase clock and specific phase comparator design described in this application do not constitute a limitation.

[0084] Phase comparator with interpolator

[0085] As communication channel data rates increase, the inherent and parasitic circuit node capacitances cause circuit delays and limit the effective loop response bandwidth, making it increasingly difficult to maintain acceptable PLL locking range and accuracy. Figure 5 The illustration shows an embodiment that provides improved response characteristics suitable for such high-speed operation. Those skilled in the art will recognize that this embodiment is a CMOS design that provides symmetrical operation for positive and negative output offsets and integrates elements from both phase interpolators and phase comparators. This tight integration reduces node capacitance and facilitates the required high-speed operation, while its balanced differential structure simplifies control of charge and discharge currents.

[0086] Consistent with conventional designs, the PLL's VCO (or clock divider driven by the VCO) provides local oscillator inputs to phase interpolator elements 510 and 515, which are used to jointly set the effective local clock phase. As shown, there are four local oscillator phases offset from each other by 90 degrees, equivalent to two phases being orthogonal and their complementary signals, thus labeled +I, +Q and -I, -Q respectively, enabling phase adjustment across the entire 360 ​​degrees, or "four-quadrant" phase adjustment. In other embodiments, the number of local oscillator phases can be reduced to two, or oscillator phases with a phase difference of less than 90 degrees can be used, or clock phases can be selected from a set of four or more inputs; as a non-limiting example, at least two clock phases to be interpolated can be selected from a set of eight input clock phases.

[0087] In a first embodiment, the phase interpolator element 510 includes four mixer elements, each including a pair of differential transistors and a controlled current source, and having a common differential output driven by the four parallel mixer elements. Therefore, the configuration of the current source IA(i) controls the amount of the local oscillator phase +I supplied to the common output ckp. Similarly, the current source IA(-i) controls the amount of the complementary output phase -1, IA(q) controls the amount of phase +Q, and IA(-q) controls the amount of phase -Q. It will be apparent to those skilled in the art that the four current sources can be configured to generate an output clock at ckp with any desired phase relationship relative to the PLL local clock input.

[0088] Similarly, the current sources IB(i), IB(-i), IB(q), and IB(-q) of the phase interpolator element 515 can be configured to obtain an output clock at the Ckn terminal with any desired phase relationship relative to the PLL local clock input. In some embodiments, CkPLLp and CkPLLn can be configured to have a complementary relationship, thereby providing balanced complementary positive and negative current amplitudes for the phase comparator 520. However, non-complementary IA and IB values ​​can also be configured to obtain specific results. As a non-limiting example, in one embodiment, the IA and IB values ​​can be adjusted separately, thereby obtaining a higher resolution phase adjustment compared to embodiments that maintain completely complementary IA and IB values.

[0089] The second input of phase comparator 520 is an external reference clock CkRef+ / CkRef-, used to generate the phase error output current VCOctl+NCOctl-. In an improved embodiment, the two external reference clocks have opposite polarities but are not necessarily complementary phases, so that positive polarity comparisons and negative polarity comparisons represent different phase comparisons. This improved embodiment can be combined with non-complementary IA and IB bias configurations to achieve independent local clock phase adjustment during the aforementioned different phase comparison processes. That is, in one embodiment, the CkRef input at the top of phase comparator 520 is a first phase selected from the available reference clock phases in the circuit, and the current IA is adjusted to provide a corresponding insertion phase offset relative to the selected first phase. Simultaneously, the CkRef input at the bottom of phase comparator 520 is a second phase selected from the available reference clock phases in the circuit, and the current IB is adjusted to provide a corresponding insertion phase offset relative to the selected second phase. These two relative phase offsets are equal in magnitude.

[0090] The value of the phase interpolator current source can be configured by external control logic, including but not limited to hardware configuration registers, control processor output registers, and hardware CDR adjustment logic.

[0091] Other phase comparator implementations

[0092] Figure 5 The phase comparator 520 in the illustrated embodiment is a phase comparator with... Figure 4A The same XOR device is used to generate the phase error output VCOctl by mixing the local clock CkPLL with the external reference clock CkRef. Figure 12A In other embodiments shown, a folded phase comparator 1220 is employed, which is driven by the current generated by the combination of current sink Ifix2 and phase interpolator 510, and current source Ifix1 and phase interpolator 515. The following will discuss... Figure 12A The folded phase comparator embodiment shown is described in further detail. Consistent with the embodiment described above, current sources IA(i), IA(-i), IA(q), and IA(-q) are configured to insert the PLL clocks i, -i, q, and -q into the interpolator output CkPLLp in a desired manner. In this context, current sources IB(i), IB(-i), IB(q), and IB(-q) are configured to insert the PLL clocks i, -i, q, and -q into the interpolator outputs CkPLLn and ... In the middle, phase comparator 1220 is also driven by the received reference clocks CkRef+ and CkRef- to produce phase comparison results: phase error (+) and phase error (-). In some embodiments, the relative DC component of the inserted clock signal can be determined by monitoring a circuit node labeled "circuit balance feedback," and then the relative DC component can be adjusted by adjusting the values ​​of the configured current sources in 510 and 515. In some embodiments, each current source IA and IB receives seven control bits. It should be noted that the embodiments of the invention are not limited to receiving seven control bits, and any number of control bits can be used, for example, depending on the design constraints of the phase interpolator resolution. In some embodiments, current sources IA and IB are equal (e.g., IA = IB for + / -i and + / -q). In such embodiments, the resolution of phase interpolators 510 and 515 is 7 bits. In other embodiments, additional resolution can be achieved by shifting IB relative to IA, or by shifting IA relative to IB. In one exemplary embodiment, IA = IB + 8, where 8 is the decimal shift amount of the control bit of each current source IB obtained by adding it to the control bit of each current source IA. In this embodiment, the P-side phase interpolator 510 and the N-side phase interpolator 515 receive two different VCO phases, and the phase comparator acquires information from the different phases of the VCO. Because the phase interpolators 510 and 515 fuse information from the different phases of the VCO, the PLL has more detailed PLL phase information, and the bandwidth of this PLL is higher than that of a conventional PLL.

[0093] The implementation of "IA = IB + shift amount" is a special case of a matrix phase comparator with two partial phase comparators. The first partial phase comparator (N-side XOR comparator) compares the reference phase with a set of VCO feedback phases, while the second partial phase comparator (P-side XOR comparator) compares the reference clock phase with another set of VCO feedback phases. The implementation of the matrix phase comparator will be described in more detail below.

[0094] In some implementations, the following methods may be used: Figure 12A The folding structure shown. Figure 12A and Figure 5The illustrated implementation is similar, but differs in that a folded phase comparator 1220 is used instead of phase comparator 520. As shown, the folded phase comparator 1220 includes current sources Ifix1 and Ifix2, which can be configured to provide a larger voltage margin to the PMOS phase interpolator current source IA and the NMOS phase interpolator current source IB. Furthermore, the phase comparator 1220 includes a pair of transistor branches connected to CkPLLp and CkPLLn. For illustrative purposes, it is assumed that phase interpolators 510 and 515 only have IA(i) and IB(i), with these two current sources turned on to represent the VCO phase ph0000. When CkRef is offset by 90 degrees relative to ph0000, the folded phase comparator 1220 will be in a locked state. Figure 13A As shown, during the first 180 degrees (1) of a cycle, for the preceding 90 degrees (2), the PMOS phase interpolator 510 charges the (-) terminal of the phase error signal with current Ip via transistor 1206. Simultaneously, the NMOS phase interpolator 515 discharges the (-) terminal of the phase error signal with current In via transistor 1208. Similarly, during the following 90 degrees (3), the (+) terminal of the phase error signal is charged with current Ip via transistor 1202 and discharged with current In via transistor 1204. As shown, Ifix2 absorbs a fixed amount of current from the current supplied by the PMOS phase interpolator 510, while Ifix1 provides a certain amount of current to the NMOS phase interpolator 515 to prevent the current source in the NMOS phase interpolator from absorbing excessive current from the phase error signal. This technique achieves a reverse clipping effect. Those skilled in the art will note that adjusting the amplitudes of the currents Ifix by equal amounts can affect the range of the phase error signal. In some implementations, increasing the amplitude of Ifix will reduce the amplitude range of the phase error signal, while decreasing the amplitude of Ifix will increase the amplitude range of the phase error signal. This relationship is as follows: Figure 13B As shown.

[0095] Figure 13B This is a timing diagram of the aforementioned reverse clipping characteristics. Figure 13B The figure shows the amplitude of current Ip under two Ifix2 values, A and B, within the first 180 degrees (1), where A > B. As shown, when Ifix2 = A, the amplitude of Ip is smaller. When Ifix2 = B, the amplitude range of Ip is relatively larger. Those skilled in the art will note that a similar effect can occur when the folded phase comparator 1220 performs In discharge.

[0096] In some implementations, such as Figure 12AAs shown, circuit balance feedback can be achieved using the back 180 degrees (4). In this circuit balance feedback phase (4), current can be charged via PMOS phase interpolator 510 and discharged via NMOS phase interpolator 515. If there is an imbalance between the charging / discharging currents, the circuit balance feedback signal will be non-zero, thus indicating this imbalance. The cause of this imbalance is, for example, a mismatch between transistors. This circuit balance feedback signal can then be used to adjust Ifix1 or Ifix2 to achieve a balance between the charging / discharging currents. Once balance is achieved, the balance feedback signal becomes zero. In some embodiments, the voltage of the charge pump circuit can be monitored. If they are equal, it indicates that the circuit has reached the correct balance state, i.e., Ip = In. Figure 12B for Figure 12A A simplified schematic diagram of a phase comparator circuit.

[0097] Alternatively, the phase comparator described in Tajalli 4, either 520 or 1220, can be used to achieve the same high signal margin phase detection in embodiments employing low supply voltages. Furthermore, in this embodiment, 520 may also include... Figure 4A , Figure 4B and Figure 4C All the variations shown are replaced by other phase comparators.

[0098] As an example of such an alternative implementation method Figure 4B The state machine phase / frequency detector shown can be used with Figure 5 This is combined with the phase interpolator design.

[0099] Figure 6A This is a schematic diagram of a traditional CML clock latch implementation. The latch consists of output Q and... The clocked feedback latches for the two results are configured such that the states of these two results are determined by the clocked differential inputs D and initialization. Figure 6B The circuit shown is the same, but it uses a phase interpolator 615 to adjust the phase of the clock source. The operating principle of this phase interpolator is explained above. Figure 5 The description.

[0100] When Figure 6B The clock latch circuit was replaced with Figure 4B Each D trigger instance is formed Figure 7A and Figure 7BThe alternative implementation is shown. The D flip-flop 710 is clocked by a received clock CkRef, which is transmitted via a phase interpolator 715. As an example for illustrative purposes, if no phase offset is set (or when the desired offset is 0 degrees), the current source IA will be set to the "mixer" input CkRef at 100% ratio, while the other three current sources will be set to zero current. The D flip-flop 720 is clocked by a local clock CkPLL, which is obtained by setting the current sources IB(i), IB(-i), IB(q), and IB(-q) of the phase interpolator 725, which further controls the relative proportions and polarities of the combined I and Q clocks. In one implementation, as... Figure 3 As shown, I is obtained from ph000, -I is obtained from ph180, Q is obtained from ph090, and -Q is obtained from ph270. Furthermore, the reset functions of flip-flops 710 and 720 are driven by a simple CML OR gate 730.

[0101] It should be noted that in this embodiment, most of the functions of the phase interpolator 715 are disabled. Its purpose is only to maintain the same parasitic load characteristics as the phase interpolator 725 in operation, so as to maximize circuit symmetry and minimize side effects such as detection bias and drift by maintaining balanced load characteristics.

[0102] Interconnected phase comparator, interpolator and charge pump

[0103] As mentioned above, the phase comparator output of a PLL is typically used to drive a charge pump circuit (CPC), which outputs an analog error signal to control the VCO. The improvements in low capacitance and high circuit speed achieved by integrating the PLL phase comparator with a clock-adjusting phase interpolator can be further extended by integrating the charge pump element in the same manner.

[0104] In this integrated implementation, Figure 7A and Figure 7B The charge pump control signals UPp, UPn, DOWNp, and DOWNn provided in the illustrated embodiment are... Figure 8 The charge pump implementation shown for generating IOUT output is directly controlled. Current source I CPC and reference voltage V REF Configurable to I OUT The range can be scaled and adjusted. Those skilled in the art will note that... Figure 8 The circuit's very high symmetry can be achieved at V REPLICA and I OUT Precise tracking is performed between the generation of signals.

[0105] Figure 8This is a schematic diagram of a charge pump circuit with improved charge / discharge current balance according to some embodiments. Circuit 800 includes two charge pumps 802 and 804 connected in parallel: two differential pairs within charge pump 804 generate an output current representing the phase error signal generated with rising and falling pulses; as described below, two differential pairs of charge pump 802 are used to set the discharge current equal to the charging current. Specifically, current source I... CPC The corresponding bias voltage V is provided by a current mirror circuit. BP In this manner, the charging current level is set to drive the top current sources 806 and 808 of the two charge pumps, thereby increasing I... CPC Similarly, this is provided to each charge pump 802, 804. When UPn decreases and causes the field-effect transistor (FET) 810 to turn on, node 812 is charged by the charging current I provided by the field-effect transistors 806, 810. CPC Charging (capacitive element 814 can be either a discrete cap or a parasitic cap) is performed. Under balanced conditions (i.e., no phase error), the amount of current discharged through the bottom-side field-effect transistor 816 when DOWNp is at a high signal level should restore node 812 to V. REF Value. If the discharge current is too low and the voltage V REPLICA Upgrade to V REF Therefore, amplifier 820 will increase the bias voltage V on discharge current field-effect transistor 818. BN To increase the amount of discharge current to match the charging current I CPC Equal, and make the voltage V on node 812 equal. REPLICA Restore to V REF On the other hand, if V BN If the discharge current set on the field-effect transistor 818 is too high, the voltage V will be affected. REPLICA The voltage will become too low, and amplifier 820 will then reduce the bias voltage V on discharge field-effect transistor 818. BN This restores the charge pump current to balance.

[0106] Other implementations can be obtained through other equivalent combinations of phase comparators, phase interpolators, and charge pump elements.

[0107] Input reference signal oversampling

[0108] For example Figure 7A and 7BThe reason for using the phase interpolator asymmetrically is that the local clock and the reference clock source are different in nature. The former is obtained from a multiphase clock source (such as an oscillator or frequency divider), which itself can provide multiphase inputs for the phase interpolation element to use. The latter is generally a single-phase clock obtained from the same receiving clock source.

[0109] In the prior art, *Tan* describes a combined DLL / PLL structure in which the PLL's VCO uses two identical voltage-controlled delay lines as input delay lines, which act on the reference clock input and are controlled by a single feedback error signal. *Ng* and *Chang* also describe using the front-end DLL as a frequency multiplier to generate extremely high-frequency clocks.

[0110] However, when tapping such a controlled delay line, if the controlled delay line is configured such that the differential delay between each tap is proportional to the time between the edges of the received clock, the received clock passing through this delay line will produce a set of outputs with certain polyphase clock characteristics. As a non-limiting example, the equally spaced outputs of a four-tap delay line with a total delay similar to the reference clock period will produce outputs with characteristics similar to the quadrature phase-controlled clock signal. In this example, when each such output is compared with the correctly selected local clock phase, a more accurate total clock error signal can be generated for the VCO of the PLL by combining the generated series of phase error results. The various delay forms of the received clock allow the clock from the VCO to have additional opportunities for phase comparison, thereby enabling a higher update rate for the controlled loop and increasing the loop bandwidth of the PLL. This reduces jitter and achieves better noise immunity. In other words, this technique increases the loop update rate, allowing the circuit to track and correct the effects of noise and jitter at higher frequencies.

[0111] In order for the aforementioned delay phase comparison to provide meaningful information to the PLL, the delay intervals provided by the delay lines must be coordinated with the time intervals between the local clock phases. This control method can provide the delay element with multiple functions of a delay-locked loop (DLL). Figure 9 As shown in the block diagram, DLL 910 provides an external clock reference input to the PLL implementation 300 described above. After the received clock signal R5 is provided to the tapped delay line 916, a series of received clock phases 918 are generated. The DLL control loop is provided by a phase comparator 912, which generates an error value by comparing the received clock with the delayed clock. This error value is then low-pass filtered by 915 to generate a delay adjustment signal for controlling the timing of the delay line.

[0112] Thus, in the PLL 300, the above simple phase comparison ( Figure 3 The 320 in the figure is implemented by a multi-phase comparator 920. In at least one embodiment, an XOR gate compares the phase of each received reference clock signal on N lines (N is, for example, equal to 2, 4, 8, etc., and may also include odd numbers to produce other phases such as 60, 120, 180, 240, 300, etc.) 918 with different clock phases among the N local clock signal phases on line 965 of the phase interpolator 360. Each XOR gate output represents a partial phase error signal that can be converted into an analog signal value, and as described above, all such analog partial phase error signals are summed by a summing circuit 935 to generate a composite phase error signal for controlling the ring oscillator 340. In another embodiment, the summation 935 is implemented by a weighted summing node similar to the MIC mixer described above, where different weight values ​​selected in the summation enable further control over the static and dynamic operating characteristics of the PLL. Alternatively, the summation operation can also be implemented by driving a corresponding transistor circuit to inject or remove charge from a capacitive element with each XOR output. Furthermore, Figure 9 The PLL 340 can be configured to provide the desired phase offset, wherein each inserted phase has the same offset relative to the tapped delay line signal to which it is to be XOR compared.

[0113] In some system environments, such as when the communication protocol uses multiple clock signals, the multi-phase reference clock can be obtained directly from the receiver.

[0114] The additional feedback information provided by the aforementioned comparison operations can also be obtained without the aforementioned delay-locked loop front end. Figure 10In the illustrated embodiment, a single received reference signal 1018 is input into a multi-phase comparator 920, wherein this single received reference signal is compared with each of two or more phases of a local clock signal 965. In one embodiment, a partial phase error signal is formed by an XOR partial phase comparator by comparing the phase of the single received reference clock phase 918 with different phases of the local clock signal 965 from a phase interpolator 360. Each partial phase error signal can be converted into an analog signal value, and as described above, a composite phase error signal for controlling the ring oscillator 340 can be generated by summing all such analog partial phase error signals. In another embodiment, the summation 935 is performed by a weighted summation node similar to the MIC mixer described above, where different weight values ​​selected in the summation enable further control over the static and dynamic operating characteristics of the PLL. Specifically, by adjusting the weight values, additional closed-loop poles and / or zeros can be generated in the time-domain transfer function of the PLL, thereby achieving further loop stability control.

[0115] Figure 14A Timing diagram comparing the reference signal CKREF with the four VCO phases (feedback from the PLL):

[0116] XOR(CKREF,VCO'000)

[0117] XOR(CKREF,VCO'090)

[0118] XOR(CKREF,VCO'180)

[0119] XOR(CKREF,VCO'270)

[0120] like Figure 14A As shown, it is assumed that all weight values ​​are equal. However, this assumption is purely illustrative and should not be construed as constituting a limitation in any way. Figure 14A This also includes summing the four XOR outputs. It can be seen that, in the locked state, the integral of the bottom waveform is zero, therefore the PLL achieves correct locking. For convenience, Figure 14B A conventional phase comparator based on the XOR operation is also shown, in which the reference phase is compared with only one VCO phase. In the locked state, the reference phase is phase-shifted by 90 degrees with the VCO phase, and the output of this XOR operation is a rectangular waveform with a zero average value. Thus, the two waveforms ( Figure 14B Simple XOR operation and Figure 14AThe difference lies in the array XOR operation, where in both cases the average value for a given time period is zero, and the PLL is locked. The implementation using a partial phase comparator array results in more transitions than using a single XOR phase comparator. Since each transition carries edge-related information, more transitions mean the phase comparator can extract more information from the VCO and CKREF.

[0121] It is important to note that in array XOR implementations, some comparisons may need to be performed using XNOR (Exclusive NOR gate). Thus, system stability can be ensured by carefully selecting between XOR and XNOR for different phase comparisons.

[0122] In at least one embodiment, the weight values ​​used in the summation are set to decrease proportionally to the timing difference between the comparison clock phase and the PLL "normal lock" phase. As a non-limiting example, when the PLL's normal lock phase is ph090, the comparison weight between ph090 and the received reference signal is 1; the comparison weight between ph000 and ph180 (e.g., offset by one tap relative to the normal lock phase) is 1 / 2; the comparison weight between the received reference signal and ph270 (offset by two taps relative to the normal lock phase) is 1 / 4; and so on. These different weighted comparison results are added to form a composite signal, which, after being low-pass filtered by 330, becomes the error value used to control the VCO 340 of the PLL.

[0123] In at least one embodiment employing multiple phase comparators, when equal phase comparator weights are used, it has been observed that the multiple phase comparisons produce deterministic jitter at a rate of 12.5 GHz. Although the amplitude of this jitter is extremely small and the jitter occurrence rate is much higher than the loop filter cutoff frequency, this deterministic jitter can still be significantly reduced by adjusting the aforementioned weight values. The weight values ​​decrease proportionally to their distance from the primary reference signal sample. In some embodiments, a discrete-time filter is constructed by using different weight values ​​in the comparator circuit. This characteristic can be used to simplify the design of the analog filter 330. For example, when the weights used are correct, discrete zero values ​​can be constructed in the time-domain transfer function, thereby creating conditions for achieving loop robustness.

[0124] Consistent with the examples above, other implementations can be obtained through other equivalent combinations of phase comparators, phase interpolators, and charge pump elements.

[0125] Matrix phase comparison

[0126] The multi-phase comparison between the multiple phases of the received reference signal and the multiple phases of the local PLL clock can also be extended to a matrix phase comparator, one implementation of which is as follows: Figure 11B As shown, each phase comparator 1110 in the matrix (in Figure 11B One implementation of what can be called a partial phase comparator is... Figure 11A The figure shows a single-phase comparator 1110. For illustrative purposes, the various phase comparators in the figure are arranged in a 4×4 matrix; however, this arrangement is for illustrative purposes only and does not constitute a limitation. In various embodiments, rectangular, square, or sparse matrices with any M and N dimensions are also used, and the elements of the matrix can be composed of any of the phase comparators described in this application, and any weighting factor calculation method described in this application may be used. In this application, a sparse matrix refers to any embodiment where at least one of the elements has a weight value of zero.

[0127] In a full matrix comparison, each of the M phases from the received reference signal is compared with each of the N phases from a local clock, which can be received from a PLL, a VCO, or other clock sources. For illustrative purposes, the N local clock phases here are received from the aforementioned PLL. Each resulting phase error signal is weighted by a preset or predetermined value, and all (M×N) weighted results are summed to produce the total error. One such phase comparator is, for example, a... Figure 11A As shown in 1110, the comparator is composed of an XOR phase comparator 1112, the output of which is fed to a weighting factor 1118.

[0128] Figure 11B One embodiment of the full matrix phase comparator 1120 consists of M×N instances of partial phase comparators 1110. Each partial phase comparator receives one phase from the M reference signal phases (denoted as CkRef0, CkRef1, CkRef2, CkRef3 in this application) and one phase from the N local clock phase input phases (denoted as CkPLL0, CkPLL1, CkPLL2, CkPLL3 in this application), and generates a weighted result (such as multiple partial phase error signals 1131, 1132, 1133, 1134). This weighted result is input into a summation function 935 to generate a composite phase error signal 1145.

[0129] Those skilled in the art will recognize that the above Figure 9The multi-phase comparator 920 in the matrix is ​​equivalent to a partial instance of this matrix comparator, meaning only the comparators on the matrix diagonal are instantiated. Functionally, when the weights of the comparators on the entire matrix diagonal are set to non-zero values ​​and the weights of all other comparators are set to zero values, the exact same result is obtained. Therefore, by selectively configuring the matrix weighting factors, other functions mentioned above, including the simulation of phase shifts and the introduction of zero values ​​in the loop time domain, can be achieved in a similar manner.

[0130] Figure 15 The diagram shows a flowchart of method 1500 according to some embodiments. As shown, method 1500 includes: in block 1502, receiving N local clock signal phases and M reference signal phases, where M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2. The method further includes: in block 1504, generating a plurality of partial phase error signals, each partial phase error signal being formed at least in part by comparing (i) a corresponding phase among the M reference signal phases with (ii) a corresponding phase among the N local clock signal phases. In block 1506, a composite phase error signal is generated by adding the plurality of partial phase error signals, and then the fixed phase 1508 of the local oscillator is adjusted with the composite phase error signal.

[0131] In some implementations, M = 1, and the composite phase error signal is generated by adding the N partial phase error signals. Alternatively, the plurality of partial phase error signals comprises M = N partial phase error signals, and a single partial phase error signal is generated using a given phase from the N local clock signal phases and a given phase from the M reference signal phases. In other alternative implementations, the plurality of partial phase error signals comprises M × N partial phase error signals, and each of the N local clock signal phases is compared with each of the M reference signal phases.

[0132] In some implementations, each of the plurality of partial phase error signals is assigned a corresponding weight value.

[0133] In some implementations, the M reference signal phases are received from a delay-locked loop that processes the input reference signal.

[0134] In some embodiments, at least one of the N local clock signal phases is generated by a phase interpolator that processes the local oscillator signal and the phase offset signal. In some embodiments, generating at least one of the N local clock signal phases includes inserting four phases using four differential pairs within the phase interpolator, each of the four phases being inserted according to a corresponding differential pair connected to an independently adjustable current source.

[0135] In some implementations, at least one partial phase error signal is formed by a pair of flip-flops, wherein a given phase of the M reference signal phases clocks a first flip-flop in the pair of flip-flops, and a given phase of the N local clock signal phases clocks a second flip-flop.

[0136] In some implementations, each phase error signal is an analog signal generated by a corresponding charge pump that receives a corresponding charge pump control signal generated based on a comparison between a corresponding phase among the M reference signal phases and a corresponding phase among the N local clock signal phases.

[0137] Other implementation methods

[0138] Transmitted and from two dedicated clock lines Figure 2 The ease of receiving a clock signal at MIC5 is the same as the ease of receiving a clock signal transmitted as a vector signaling codesub channel carrying the same data, for example, from MIC4. This method of embedding the clock within the vector signaling codesub channel is as described in "Shokrollahi 2" and "Holden 3". All clock embedding implementations described therein can be combined with the PLL and timing control mechanisms described in this application to produce beneficial effects, but this does not constitute any limitation.

[0139] Similarly, other known methods for clock signal transmission using data line edge transitions can be combined with the PLL and timing control mechanisms described in this application. Particularly suitable vector signaling codes for this combination are those capable of maintaining transition density over extended periods, such as those described in Shokrollahi 1.

Claims

1. A method for adjusting a local oscillator, characterized in that, include: Acquire at least one reference signal phase and acquire multiple local oscillator signal phases; At least three partial phase error signals are formed, wherein each partial phase error signal is formed by comparing the phase of the at least one reference signal phase with a corresponding phase among the plurality of local oscillator signal phases; A corresponding weighting factor is applied to each of the at least three partial phase error signals, wherein each weighting factor is selected from a matrix weighting factor configuration related to the phase offset between the reference signal and the local oscillator signal; and A composite phase error signal is generated by analog summing of at least three partial phase error signals, and the fixed phase of the local oscillator is adjusted in response to the composite phase error signal.

2. The method as described in claim 1, characterized in that, The weighting factor applied to a given partial phase error signal decreases proportionally to the time difference between the phase in the at least one reference signal phase and the phase in the plurality of local oscillator signal phases.

3. The method as described in claim 1, characterized in that, The multiple local oscillator signal phases include four phases.

4. The method as described in claim 3, characterized in that, The four phases include 0°, 90°, 180° and 270° phases.

5. The method as described in claim 1, characterized in that, Applying a corresponding weighting factor to each partial phase error signal includes controlling the magnitude of the current in each partial phase error signal.

6. The method as described in claim 1, characterized in that, Each partial phase error signal is generated by applying a logic XOR phase comparator to the corresponding phase of the at least one reference signal phase and the corresponding phase of the plurality of local oscillator signal phases.

7. The method as described in claim 6, characterized in that, The partial phase error signal is generated as a current-mode output signal, wherein applying the weighting factor includes controlling the magnitude of the current-mode output signal.

8. The method as described in claim 1, characterized in that, Each partial phase error signal is generated by comparing the reference signal with a corresponding differential current via a differential pair that receives the phase of the local oscillator signal, wherein the magnitude of the differential current is determined by the weighting factor.

9. The method as described in claim 1, characterized in that, Generating the composite phase error signal includes: simulating the summation of multiple differential currents on a pair of differential nodes, wherein each differential current is generated in response to providing a phase from the multiple local oscillator signal phases to a pair of differential transistors connected to the pair of differential nodes; and The composite phase error signal is generated on a pair of differential output nodes based on the phase of the at least one local oscillator signal.

10. The method as described in claim 1, characterized in that, Four partial phase error signals are generated by comparing the phase of a single reference signal with the phases of four local oscillator signals.

11. A device for adjusting a local oscillator, characterized in that, include: Multiple partial phase comparators are used for: Acquire at least one reference signal phase and acquire multiple local oscillator signal phases; At least three partial phase error signals are formed, wherein each partial phase error signal is formed by comparing the phase of the at least one reference signal phase with a corresponding phase among the plurality of local oscillator signal phases; A corresponding weighting factor is applied to each of the at least three partial phase error signals, wherein each weighting factor is selected from a matrix weighting factor configuration related to the phase offset between the reference signal and the local oscillator signal; and A summing circuit is used to generate a composite phase error signal by analog summing of at least three partial phase error signals, and to adjust the fixed phase of a local oscillator in response to the composite phase error signal.

12. The apparatus as claimed in claim 11, characterized in that, The weighting factor applied to a given partial phase error signal decreases proportionally to the time difference between the phase in the at least one reference signal phase and the phase in the plurality of local oscillator signal phases.

13. The apparatus as claimed in claim 11, characterized in that, The multiple local oscillator signal phases include four phases.

14. The apparatus as claimed in claim 13, characterized in that, The four phases include 0°, 90°, 180° and 270° phases.

15. The apparatus as claimed in claim 11, characterized in that, The partial phase comparator is used to apply a corresponding weighting factor to each partial phase error signal by controlling the magnitude of the current of each partial phase error signal.

16. The apparatus as claimed in claim 11, characterized in that, The plurality of partial phase comparators include logic XOR phase comparators applied to the phase in the at least one reference signal phase and the phase in the plurality of local oscillator signal phases.

17. The apparatus as claimed in claim 16, characterized in that, The partial phase error signal is generated as a current-mode output signal, wherein the partial phase comparator is used to apply the weighting factor by controlling the magnitude of the current-mode output signal.

18. The apparatus as claimed in claim 11, characterized in that, The plurality of partial phase comparators are used to generate each of the partial phase error signals by comparing a reference clock with a differential current via a differential pair that receives the phase of a local oscillator signal, wherein the magnitude of the differential current is determined by the weighting factor.

19. The apparatus as claimed in claim 11, characterized in that, The summing circuit includes a pair of differential nodes, wherein the plurality of partial phase comparators are used to perform analog summation of a plurality of differential currents on the pair of differential nodes, wherein each differential current is generated in response to providing a phase of the plurality of local oscillator signal phases to a pair of differential transistors connected to the pair of differential nodes.

20. The apparatus as claimed in claim 11, characterized in that, Four partial phase error signals are generated by comparing one of the reference signal phases with the four local oscillator signal phases.

Images