Method and system for mutual conversion between Ethernet data primary group data and secondary group data

Abstract

The present invention discloses a method and system for simultaneously transmitting Ethernet data and primary group data and converting them with secondary group data. The method comprises the following steps: a transmitting end extracts a first co-frequency clock, a first decoding clock, a multiplexing clock and a first coding clock according to the primary group data, HDB3 decoding the primary group data, multiplexing the HDLC data after HDLC encoding the synchronization data and the Ethernet data packet and the decoded primary group data according to the frame structure and then encoding and outputting; a receiving end extracts a second co-frequency clock, a second decoding clock, a tapping clock and a second coding clock according to the secondary group data, and tapping them according to the frame structure, the tapped primary group data is output after being encoded by HDB3, and the tapped Ethernet data is output according to the standard format after being decoded by HDLC. The present invention is all realized in the FGPA chip, has low requirements on the peripheral circuit, is simple in principle, and has strong practical value.

Description

Technical Field

[0001] The present invention relates to the technical field of information transmission, and more particularly to a method and system for simultaneously transmitting Ethernet data and primary group data and converting between secondary group data. Background Art

[0002] Ethernet is the most widely used local area network transmission method, and the technology is quite mature. Ethernet is the preferred solution for broadband access due to its advantages such as low cost, simple network management, and easy upgrade, but its disadvantage is that the transmission distance is limited. Faced with the abundant E1 (primary group, rate is 2048kb / s) and E2 (secondary group, rate is 8448kb / s) interface resources provided by a large number of SDH, PDH and other communication equipment, a more realistic solution is to use these existing resources to transmit Ethernet data. The existing E1 / Ethernet protocol converters are based on the transmission capacity of the entire E1 when converting data.

[0003] E1, E2 interfaces and Ethernet interfaces are universal interfaces. Primary group data is transmitted together with Ethernet data and converted into secondary group data, which can facilitate the expansion and compatibility of different services and greatly improve equipment performance.

[0004] Therefore, how to provide a method and system for simultaneously transmitting Ethernet data and primary group data and converting them with secondary group data is a problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] In view of this, the present invention provides a method and system for simultaneously transmitting Ethernet data and primary group data and converting them with secondary group data. The present invention is implemented in the FGPA chip, has low requirements on peripheral circuits, is simple in principle, and has strong practical value.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] The method for simultaneously transmitting Ethernet data and primary group data and converting Ethernet data and primary group data to and from secondary group data comprises:

[0008] Step 1: The transmitting end extracts the first co-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock according to the primary group data, and performs HDB3 decoding on the primary group data based on the first decoding clock, multiplexes the HDLC data after HDLC encoding of the synchronization data and Ethernet data packet and the primary group data after HDB3 decoding according to the frame structure, and then encodes and outputs them to convert them into secondary group data;

[0009] Step 2: The receiving end extracts the second frequency clock, the second decoding clock, the tapped clock and the second encoding clock according to the secondary group data, and taps them according to the frame structure. The tapped primary group data is encoded by HDB3 and then output. The tapped Ethernet data is decoded by HDLC and then output in the standard format.

[0010] Preferably, step 1 specifically includes:

[0011] Step 11: extracting a synchronized first co-frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock from the primary group data, and deriving data multiplexing enable according to the frame structure, including synchronous data multiplexing enable, primary group data multiplexing enable, Ethernet data multiplexing enable and HDLC data multiplexing enable;

[0012] Step 12: HDB3 decoding is performed on the primary group data based on the extracted first decoding clock, and the HDB3-decoded primary group data is stored in the E1 receiving FIFO module based on the first co-frequency clock;

[0013] Step 13: Store the valid Ethernet data packet into the MII receiving FIFO module through the Ethernet associated clock, read the Ethernet data packet from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing is enabled, and convert the Ethernet data packet into HDLC data;

[0014] Step 14: When the base group data multiplexing enable is valid, the decoded base group data is read from the E1 receiving FIFO module based on the multiplexing clock. When the synchronization data multiplexing enable is valid, the synchronization data is read from the synchronization code ROM based on the multiplexing clock. When the HDLC data multiplexing enable is valid, the HDLC data is read from the HDLC framing module based on the multiplexing clock. According to the corresponding frame structure, the synchronization data, the decoded base group data and the HDLC data are multiplexed and converted into a continuous stream. The continuous stream data is HDB3 encoded based on the first encoding clock and sent to the port, that is, it becomes secondary group data.

[0015] Preferably, step 2 specifically includes:

[0016] Step 21: extracting a synchronized second frequency clock, a second decoding clock, a tapping clock and a second encoding clock from the continuous secondary group data;

[0017] Step 22: after decoding the secondary group data based on the second decoding clock, extract the primary group data, Ethernet data and data tapping enable from the secondary group data according to the corresponding frame structure, the data tapping enable includes Ethernet data tapping enable and primary group data tapping enable, and when the primary group data tapping enable is valid, store the primary group data into the E1 transmit FIFO module based on the second co-frequency clock;

[0018] Step 23: after reading the data in the E1 transmission FIFO module based on the tapped clock, HDB3 encoding is performed based on the second encoding clock, thereby restoring the primary group data;

[0019] Step 24: When the Ethernet data demultiplexing is enabled, the Ethernet data is HDLC deframed, and valid Ethernet data packets are extracted and stored in the MII send FIFO module. The Ethernet data packets are then read out through the Ethernet clock and sent to the port in a standard format.

[0020] Preferably, the first in-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock are extracted from the primary group data by means of cascade phase locking.

[0021] Preferably, the second in-frequency clock, the second decoding clock, the tapped clock and the second encoding clock are extracted from the secondary group data by means of cascade phase locking.

[0022] A system for simultaneously transmitting Ethernet data and primary group data and converting them to and from secondary group data, including: converting primary group data and Ethernet data to secondary group data units and converting secondary group data to primary group data and Ethernet data units;

[0023] The primary group data and Ethernet data conversion unit is used to extract the first co-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock according to the primary group data, and perform HDB3 decoding on the primary group data based on the first decoding clock, multiplex the HDLC data after HDLC encoding of the synchronization data and Ethernet data packet and the primary group data after HDB3 decoding according to the frame structure, and then encode and output them to convert them into secondary group data;

[0024] Convert secondary group data to primary group data and Ethernet data unit: extract the second co-frequency clock, second decoding clock, tapping clock and second encoding clock based on the secondary group data, and tap them according to the frame structure. The tapped primary group data is encoded by HDB3 and then output. The tapped Ethernet data is decoded by HDLC and then output in the standard format.

[0025] Preferably, the primary group data and Ethernet data conversion secondary group data unit comprises: a first clock cascade phase locking module, a first HDB3 decoding module, an E1 receiving FIFO module, an MII receiving FIFO module, an HDLC framing module, a multiplexing module and a first HDB3 encoding module;

[0026] The first clock cascade phase-locked module is used to extract a synchronized first same-frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock from the primary group data, and obtain data multiplexing enable according to the frame structure, including synchronous data multiplexing enable, primary group data multiplexing enable, Ethernet data multiplexing enable and HDLC data multiplexing enable;

[0027] The first HDB3 decoding module performs HDB3 decoding on the primary group data based on the extracted first decoding clock, and stores the HDB3-decoded primary group data into the E1 receiving FIFO module based on the first co-frequency clock;

[0028] The MII receiving FIFO module is used to store valid Ethernet data packets detected by the Ethernet associated clock;

[0029] The HDLC framing module is used to read the Ethernet data packets from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing enable is valid, and convert the Ethernet data packets into HDLC data;

[0030] The multiplexing module is used to read the decoded primary group data from the E1 receiving FIFO module based on the multiplexing clock when the primary group data multiplexing enable is valid, read the synchronous data from the synchronous code ROM based on the multiplexing clock when the synchronous data multiplexing enable is valid, and read the HDLC data from the HDLC framing module based on the multiplexing clock when the HDLC data multiplexing enable is valid, and multiplex the synchronous data, the decoded primary group data and the HDLC data into a continuous stream according to the corresponding frame structure;

[0031] The first HDB3 encoding module is used to perform HDB3 encoding on the continuous stream data based on the first encoding clock and then send the continuous stream data to the port to convert it into secondary group data.

[0032] Preferably, the secondary group data to primary group data and Ethernet data unit comprises a second clock cascade phase locking module, a second HDB3 decoding module, an E1 transmission FIFO module, an MII transmission FIFO module, an HDLC deframing module, a tapping module and a second HDB3 encoding module;

[0033] The second clock cascade phase-locked module is used to extract a synchronized second same-frequency clock, a second decoding clock, a tapping clock and a second encoding clock from the continuous secondary group data;

[0034] The second HDB3 decoding module is used for decoding the secondary group data based on the second decoding clock;

[0035] The tap module is used to extract primary group data, Ethernet data and data tap enable from the secondary group data according to the corresponding frame structure, wherein the data tap enable includes Ethernet data tap enable and primary group data tap enable;

[0036] The E1 transmit FIFO module is used to read and store the primary group data based on the second co-frequency clock when the primary group data tapping enable is valid;

[0037] The second HDB3 encoding module is used for reading the data in the E1 transmission FIFO module based on the tapped clock and performing HDB3 encoding based on the second encoding clock, thereby restoring the primary group data;

[0038] The HDLC de-framing module is used to perform HDLC de-framing on Ethernet data when the Ethernet data tapping is enabled, and extract valid Ethernet data packets;

[0039] The MII send FIFO module is used to store valid Ethernet data packets, read out Ethernet data packets through the Ethernet clock, and send them to the port in a standard format.

[0040] Preferably, the first clock cascade phase locking module extracts the first same-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock from the primary group data by means of cascade phase locking.

[0041] Preferably, the second clock cascade phase locking module extracts the second same-frequency clock, the second decoding clock, the tapped clock and the second encoding clock from the secondary group data by means of cascade phase locking.

[0042] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a method and system for simultaneously transmitting Ethernet data and primary group data and converting them into secondary group data, which transmits the primary group data together with the Ethernet data and converts them into secondary group data to facilitate the expansion and compatibility of different services, thereby greatly improving the performance of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0044] Figure 1 The accompanying drawing is a flow chart of a method for simultaneously transmitting Ethernet data and primary group data and converting Ethernet data and primary group data to and from secondary group data provided by the present invention.

[0045] Figure 2 The accompanying drawing is a block diagram of the system principle of the present invention for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data.

[0046] Figure 3 The accompanying drawing is a block diagram of the cascade phase locking principle provided by the present invention.

[0047] Figure 4 The accompanying drawing is a block diagram of the XOR phase-detection principle provided by the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] The embodiment of the present invention discloses a method for simultaneously transmitting Ethernet data and primary group data and converting Ethernet data and secondary group data to each other. Figure 1 As shown, the method is implemented in the FPGA chip, including:

[0050] Step 1: The transmitting end extracts the first co-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock according to the primary group data, and decodes the primary group data based on the first decoding clock, multiplexes the synchronous data and Ethernet data packets after HDLC encoding and the primary group data after HDB3 decoding according to the frame structure, and then encodes and outputs them, and converts them into secondary group data; specifically:

[0051] Step 11: The primary group data received by FPGA is two-way differential HDB3 data. In order to have sufficient phase detection information, the two-way data is merged and then clock cascade phase locked. Figure 3 As shown, the first frequency clock 2048kHz, the first decoding clock 4096kHz, the multiplexed clock 8448kHz and the first encoding clock 16896kHz are obtained. Figure 4 As shown, the accumulator bit width is 32 bits, the loop gain is 100ppm, and the calculated frequency words are 0X01E81081 and 0X0FBA8826, and the loop gains are 0X00000C7E and 0X00006714 respectively.

[0052] Step 12: Decode the received two-way differential HDB3 data using the first decoding clock 2048kHz, and store them in the E1 receiving FIFO module based on the first co-frequency clock. The FIFO width is 1 bit and the depth is 256.

[0053] Step 13: The Ethernet data received by FPGA is received by Ethernet packets through the clock, the leading code of the Ethernet packet (7 0X55 and one 0X5D) is removed, and converted into 32-bit parallel data, which is stored in the MII receiving FIFO module. At the same time, the CRC check and frame length are counted by bytes, and the frame length is stored in the FIFO header. Only when the CRC check is passed, the stored data is valid. In order to facilitate processing, each Ethernet packet is stored in a FIFO separately. Since Ethernet data is bursty and has a high rate, in order to avoid the Ethernet data coming later from flushing the previous one, the receiving end FIFO is 48, with a width of 32 bits and a depth of 512.

[0054] Using the multiplexing clock 8448kHz, the synchronous data multiplexing enable, the primary group data multiplexing enable and the Ethernet data multiplexing enable are generated according to the frame structure.

[0055] When the synchronous data multiplexing enable arrives, the multiplexing clock is used to read 1-bit data framing from the ROM memory containing fixed data 0X1D.

[0056] When the primary data multiplexing enable arrives, the multiplexing clock is used to read data from the E1 receiving FIFO module for framing.

[0057] When Ethernet data multiplexing is enabled, the MII receiving FIFO is checked to see if it is not empty. If it is empty, the serial stream of the HDLC frame identifier 0X7E is continuously sent. If it is not empty, the multiplexing clock is used to read data from the MII receiving FIFO and convert it into a bit stream according to the HDLC protocol. The HDLC protocol stipulates that "01111110" (0X7E) is the frame identifier, but the transmitted data combination may be the same as the frame identifier. In order to prevent the receiving end from misjudging it as a frame header or frame tail, a "0" bit is automatically inserted between the frame header and the frame tail of a frame after each transmission of 5 consecutive "1" bits. This "0" does not perform CRC calculation. The Ethernet frame byte length stored in the FIFO header is used to determine the length of the data read from the FIFO and is not transmitted. According to the frame structure, it can be seen that Ethernet data only occupies 99 bits in a frame of data, and an Ethernet data packet requires multiple frames to be sent out. 0X7E is also required to be used between two Ethernet packets.

[0058] Step 14: After the synchronization data, primary group data and Ethernet data are framed, the data rate is 8448 kbps. Since the return-to-zero code is used, HDB3 encoding is performed with a 16896 kHz clock. The encoded two-way data is sent to the port, completing the conversion of the primary group data and Ethernet data into secondary group data.

[0059] Step 2: The receiving end extracts the second frequency clock, the second decoding clock, the tapped clock and the second encoding clock according to the secondary group data, and taps them according to the frame structure. The tapped primary group data is encoded by HDB3 and then output. The tapped Ethernet data is decoded by HDLC and then output in a standard format, specifically:

[0060] Step 21: The secondary group data received by FPGA is two-way differential HDB3 data. In order to have sufficient phase detection information, the two-way data is merged and then clock cascade phase locked. Figure 3 As shown, the second frequency clock 8448kHz, the second decoding clock 16896kHz, the tapped clock 2048kHz and the second encoding clock 4096kHz are obtained. Figure 4As shown, the accumulator bit width is 32 bits, the loop gain is 100ppm, and the calculated frequency words are 0X07DD4413 and 0X03D02102, and the loop gains are 0X0000338A and 0X000018FD respectively.

[0061] Step 22: Decode the received HDB3 data using the second decoding clock 16896kHz, perform frame synchronization on the decoded data, and then demultiplex the primary group data, Ethernet data and corresponding data enable according to the frame structure, including Ethernet data demultiplex enable and primary group data demultiplex enable.

[0062] Step 23: When the primary data tapping is enabled, the data is stored in the E1 transmit FIFO using the 8448kHz clock. The FIFO width is 1 bit and the depth is 256. The data is continuously read from the E1 transmit FIFO using the 2048kHz clock. The data becomes a continuous stream. Due to the use of return-to-zero code, the HDB3 encoding is performed using the 4096kHz clock. The encoded two-way data is returned to zero and sent to the port, thereby restoring the primary data.

[0063] Step 24: When Ethernet data tapping is enabled, use the 8448kHz clock to perform HDLC de-framing on the Ethernet data, extract valid Ethernet data packets and store them in the MII send FIFO module. Each Ethernet data packet is stored in a separate FIFO. To avoid data loss, there are 4 send FIFOs with a width of 32 bits and a depth of 512. Then use the Ethernet clock to read it out, add the preamble, and send it to the port in the standard format to restore the Ethernet data.

[0064] The above are specific implementations of the present invention, which are all implemented in the FGPA chip, have low requirements on peripheral circuits, are simple in principle, and have strong practical value.

[0065] The embodiment of the present invention discloses a system for simultaneously transmitting Ethernet data and primary group data and converting Ethernet data and secondary group data to each other. Figure 2 As shown, it includes: converting primary group data and Ethernet data into secondary group data units and converting secondary group data into primary group data and Ethernet data units;

[0066] The primary group data and Ethernet data conversion unit is used to extract the first co-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock according to the primary group data, and perform HDB3 decoding on the primary group data based on the first decoding clock, multiplex the HDLC data after HDLC encoding of the synchronization data and Ethernet data packet and the primary group data after HDB3 decoding according to the frame structure, and then encode and output them to convert them into secondary group data;

[0067] Convert secondary group data to primary group data and Ethernet data unit: extract the second co-frequency clock, second decoding clock, tapping clock and second encoding clock based on the secondary group data, and tap them according to the frame structure. The tapped primary group data is encoded by HDB3 and then output. The tapped Ethernet data is decoded by HDLC and then output in the standard format.

[0068] The primary group data and Ethernet data conversion secondary group data unit includes: a first clock cascade phase locking module, a first HDB3 decoding module, an E1 receiving FIFO module, an MII receiving FIFO module, an HDLC framing module, a multiplexing module and a first HDB3 encoding module;

[0069] The first clock cascade phase-locked module is used to extract a synchronized first same-frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock from the primary group data, and obtain data multiplexing enable according to the frame structure, including synchronous data multiplexing enable, primary group data multiplexing enable, Ethernet data multiplexing enable and HDLC data multiplexing enable;

[0070] The first HDB3 decoding module performs HDB3 decoding on the primary group data based on the extracted first decoding clock, and stores the HDB3-decoded primary group data into the E1 receiving FIFO module based on the first co-frequency clock;

[0071] The MII receiving FIFO module is used to store valid Ethernet data packets detected by the Ethernet associated clock;

[0072] The HDLC framing module is used to read the Ethernet data packets from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing enable is valid, and convert the Ethernet data packets into HDLC data;

[0073] The multiplexing module is used to read the decoded primary group data from the E1 receiving FIFO module based on the multiplexing clock when the primary group data multiplexing enable is valid, read the synchronous data from the synchronous code ROM based on the multiplexing clock when the synchronous data multiplexing enable is valid, and read the HDLC data from the HDLC framing module based on the multiplexing clock when the HDLC data multiplexing enable is valid, and multiplex the synchronous data, the decoded primary group data and the HDLC data into a continuous stream according to the corresponding frame structure;

[0074] The first HDB3 encoding module is used to perform HDB3 encoding on the continuous stream data based on the first encoding clock and then send it to the port to convert it into secondary group data. The secondary group data conversion base group data and Ethernet data unit includes a second clock cascade phase locking module, a second HDB3 decoding module, an E1 transmission FIFO module, an MII transmission FIFO module, an HDLC de-framing module, a demultiplexing module and a second HDB3 encoding module;

[0075] The second clock cascade phase-locked module is used to extract a synchronized second same-frequency clock, a second decoding clock, a tapping clock and a second encoding clock from the continuous secondary group data;

[0076] The second HDB3 decoding module is used for decoding the secondary group data based on the second decoding clock;

[0077] The tap module is used to extract primary group data, Ethernet data and data tap enable from the secondary group data according to the corresponding frame structure, wherein the data tap enable includes Ethernet data tap enable and primary group data tap enable;

[0078] The E1 transmit FIFO module is used to read and store the primary group data based on the second co-frequency clock when the primary group data tapping enable is valid;

[0079] The second HDB3 encoding module is used for reading the data in the E1 transmission FIFO module based on the tapped clock and performing HDB3 encoding based on the second encoding clock, thereby restoring the primary group data;

[0080] The HDLC de-framing module is used to perform HDLC de-framing on Ethernet data when the Ethernet data tapping is enabled, and extract valid Ethernet data packets;

[0081] The MII send FIFO module is used to store valid Ethernet data packets, read out Ethernet data packets through the Ethernet clock, and send them to the port in a standard format.

[0082] Among them, in the HDB3 encoding and decoding module, the HDB3 code is an improved version of the AMI code, which eliminates the state of continuous "0". The encoding principle can be briefly described as follows: when the number of continuous "0" in the original code exceeds 3, the fourth "0" code is replaced by the destruction pulse code V code. The V code has the same polarity as the previous non-"0" code. To ensure that the adjacent V codes must alternate in polarity, when the number of non-"0" codes between two adjacent V codes is an even number, the first "0" code after the previous non-"0" code of the current V code becomes the B code, and the polarity of the B code is opposite to that of the previous non-"0" code. After HDB3 encoding, the output is reset to zero.

[0083] The first clock cascade phase-locking module and the second clock cascade phase-locking module have the same principle. Figure 3 As shown, a plurality of cascade clocks are generated through a phase-locked loop, and the fixed frequency words and gains K0 of the plurality of regenerated clocks are calculated respectively. The phase accumulation of the plurality of regenerated clocks is controlled in the same manner according to the phase detection output.

[0084] HDLC framing and deframing module, when framing, it is converted into a bit stream according to the HDLC protocol. The HDLC protocol stipulates that a complete frame information starts with a flag word and ends with the flag word, with 01111110 (0X7E) as the flag word, but the transmitted data combination may be the same as the flag word. In order to prevent the receiving end from misjudging it as a frame header or frame tail, a "0" bit is automatically inserted between the frame header and the frame tail of a frame after every 5 consecutive "1" bits are transmitted, and this "0" is not calculated by CRC. When deframing, after receiving the frame header, every time 5 consecutive "1" bits are received, the "0" bit after it is automatically deleted to restore the original form of the information.

[0085] The multiplexing and demultiplexing modules perform multiplexing and demultiplexing according to the frame structure. The synchronization data occupies 1 bit in each frame. After determining the synchronization data rate, the number of bits of the primary group data and Ethernet data in a frame of data can be determined, thereby determining the frame structure. Determine the appropriate frame structure, and frame and deframe the synchronization data, primary group data, and Ethernet data according to the frame structure. The frame structure is 1S+32E+99IP, where S represents the frame synchronization sequence, E represents the primary group data, and IP represents the Ethernet data.

[0086] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0087] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for simultaneously transmitting Ethernet data and primary group data and converting them to and from secondary group data, characterized in that: include: Step 1: The transmitting end extracts the first co-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock according to the primary group data, and performs HDB3 decoding on the primary group data based on the first decoding clock, multiplexes the HDLC data after HDLC encoding of the synchronization data and Ethernet data packet and the primary group data after HDB3 decoding according to the frame structure, and then encodes and outputs them to convert them into secondary group data; Step 2: The receiving end extracts the second frequency clock, the second decoding clock, the tapped clock and the second encoding clock according to the secondary group data, and taps them according to the frame structure. The tapped primary group data is encoded by HDB3 and then output. The tapped Ethernet data is decoded by HDLC and then output in a standard format. Step 1 specifically includes: Step 11: extracting a synchronized first co-frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock from the primary group data, and deriving data multiplexing enable according to the frame structure, including synchronous data multiplexing enable, primary group data multiplexing enable, Ethernet data multiplexing enable and HDLC data multiplexing enable; Step 12: HDB3 decoding is performed on the primary group data based on the extracted first decoding clock, and the HDB3-decoded primary group data is stored in the E1 receiving FIFO module based on the first co-frequency clock; Step 13: Store the valid Ethernet data packet into the MII receiving FIFO module through the Ethernet associated clock, read the Ethernet data packet from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing is enabled, and convert the Ethernet data packet into HDLC data; Step 14: When the base group data multiplexing enable is valid, the decoded base group data is read from the E1 receiving FIFO module based on the multiplexing clock. When the synchronization data multiplexing enable is valid, the synchronization data is read from the synchronization code ROM based on the multiplexing clock. When the HDLC data multiplexing enable is valid, the HDLC data is read from the HDLC framing module based on the multiplexing clock. According to the corresponding frame structure, the synchronization data, the decoded base group data and the HDLC data are multiplexed and converted into a continuous stream. The continuous stream data is HDB3 encoded based on the first encoding clock and sent to the port, that is, it becomes secondary group data.

2. The method for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data according to claim 1, characterized in that: Step 2 specifically includes: Step 21: extracting a synchronized second frequency clock, a second decoding clock, a tapping clock and a second encoding clock from the continuous secondary group data; Step 22: after decoding the secondary group data based on the second decoding clock, extract the primary group data, Ethernet data and data tapping enable from the secondary group data according to the corresponding frame structure, the data tapping enable includes Ethernet data tapping enable and primary group data tapping enable, and when the primary group data tapping enable is valid, store the primary group data into the E1 transmit FIFO module based on the second co-frequency clock; Step 23: after reading the data in the E1 transmission FIFO module based on the tapped clock, HDB3 encoding is performed based on the second encoding clock, thereby restoring the primary group data; Step 24: When the Ethernet data demultiplexing is enabled, the Ethernet data is HDLC deframed, and valid Ethernet data packets are extracted and stored in the MII send FIFO module. The Ethernet data packets are then read out through the Ethernet clock and sent to the port in a standard format.

3. The method for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data according to claim 1, characterized in that: A first co-frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock are extracted from the primary group data in a cascade phase-locked manner.

4. The method for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data according to claim 2, characterized in that: A second co-frequency clock, a second decoding clock, a tapping clock and a second encoding clock are extracted from the secondary group data in a cascade phase-locked manner.

5. A system for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data, characterized in that: include: Converting primary group data and Ethernet data into secondary group data units and converting secondary group data into primary group data and Ethernet data units; The primary group data and Ethernet data conversion unit is used to extract the first co-frequency clock, the first decoding clock, the multiplexing clock and the first encoding clock according to the primary group data, and perform HDB3 decoding on the primary group data based on the first decoding clock, multiplex the HDLC data after HDLC encoding of the synchronization data and Ethernet data packet and the primary group data after HDB3 decoding according to the frame structure, and then encode and output them to convert them into secondary group data; Convert secondary group data to primary group data and Ethernet data unit: extract the second frequency clock, second decoding clock, tapping clock and second encoding clock according to the secondary group data, and tap them according to the frame structure. The tapped primary group data is output after HDB3 encoding, and the tapped Ethernet data is output according to the standard format after HDLC decoding; The primary group data and Ethernet data conversion secondary group data unit includes: a first clock cascade phase locking module, a first HDB3 decoding module, an E1 receiving FIFO module, an MII receiving FIFO module, an HDLC framing module, a multiplexing module and a first HDB3 encoding module; The first clock cascade phase-locked module is used to extract a synchronized first same-frequency clock, a first decoding clock, a multiplexing clock and a first encoding clock from the primary group data, and obtain data multiplexing enable according to the frame structure, including synchronous data multiplexing enable, primary group data multiplexing enable, Ethernet data multiplexing enable and HDLC data multiplexing enable; The first HDB3 decoding module performs HDB3 decoding on the primary group data based on the extracted first decoding clock, and stores the HDB3-decoded primary group data into the E1 receiving FIFO module based on the first co-frequency clock; The MII receiving FIFO module is used to store valid Ethernet data packets detected by the Ethernet associated clock; The HDLC framing module is used to read the Ethernet data packets from the MII receiving FIFO module according to the multiplexing clock when the Ethernet data multiplexing enable is valid, and convert the Ethernet data packets into HDLC data; The multiplexing module is used to read the decoded primary group data from the E1 receiving FIFO module based on the multiplexing clock when the primary group data multiplexing enable is valid, read the synchronous data from the synchronous code ROM based on the multiplexing clock when the synchronous data multiplexing enable is valid, and read the HDLC data from the HDLC framing module based on the multiplexing clock when the HDLC data multiplexing enable is valid, and multiplex the synchronous data, the decoded primary group data and the HDLC data into a continuous stream according to the corresponding frame structure; The first HDB3 encoding module is used to perform HDB3 encoding on the continuous stream data based on the first encoding clock and then send the continuous stream data to the port to convert it into secondary group data.

6. The system for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data according to claim 5, characterized in that: The secondary group data to primary group data and Ethernet data unit includes a second clock cascade phase locking module, a second HDB3 decoding module, an E1 transmission FIFO module, an MII transmission FIFO module, an HDLC deframing module, a tapping module and a second HDB3 encoding module; The second clock cascade phase-locked module is used to extract a synchronized second same-frequency clock, a second decoding clock, a tapping clock and a second encoding clock from the continuous secondary group data; The second HDB3 decoding module is used for decoding the secondary group data based on the second decoding clock; The tap module is used to extract primary group data, Ethernet data and data tap enable from the secondary group data according to the corresponding frame structure, wherein the data tap enable includes Ethernet data tap enable and primary group data tap enable; The E1 transmit FIFO module is used to read and store the primary group data based on the second co-frequency clock when the primary group data tapping enable is valid; The second HDB3 encoding module is used for reading the data in the E1 transmission FIFO module based on the tapped clock and performing HDB3 encoding based on the second encoding clock, thereby restoring the primary group data; The HDLC de-framing module is used to perform HDLC de-framing on Ethernet data when the Ethernet data tapping is enabled, and extract valid Ethernet data packets; The MII send FIFO module is used to store valid Ethernet data packets, read out Ethernet data packets through the Ethernet clock, and send them to the port in a standard format.

7. The system for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data according to claim 5, characterized in that: The first clock cascade phase locking module extracts a first same-frequency clock, a first decoding clock, a multiplexed clock and a first encoding clock from the primary group data by means of cascade phase locking.

8. The system for simultaneous transmission of Ethernet data and primary group data and conversion between Ethernet data and secondary group data according to claim 6, characterized in that: The second clock cascade phase locking module extracts a second same-frequency clock, a second decoding clock, a tapping clock and a second encoding clock from the secondary group data by means of cascade phase locking.

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