High Dynamic Range Receiver for LIDAR Sensors

Abstract

The receiver circuit (281) for a LIDAR sensor includes a photosensitive input circuit (36) and a logarithmic signal circuit (38), and the logarithmic signal circuit (38) includes a PN junction (50) coupled to a pulsed voltage node (52). The pulsed voltage node is coupled to the P-type terminal of the PN junction and the output (46) of the photosensitive input circuit. The logarithmic voltage compression of the logarithmic signal circuit (38) improves the dynamic range of the receiver circuit (281). The photosensitive input circuit (36) and the logarithmic signal circuit (38) can be coupled to an impedance reduction circuit (84) and a current bypass circuit (86). The impedance reduction circuit (84) is coupled between the photosensitive input circuit (36) and the node (52) and includes two transistors: a common-gate transistor (88) and a bias transistor (96). The current bypass circuit (86) includes a bypass transistor (104). The bypass transistor (104) is used to shunt the bias current provided by the bias transistor (96) to ground, thereby reducing the bias current delivered to the logarithmic signal circuit (50), thus ensuring that the diode (50) exhibits a large dynamic resistance for small photocurrent pulses. During operation of the receiver circuit (281), the common-gate transistor (88) reduces the impedance seen by the photosensitive input circuit (36), thereby reducing the effect of the photodiode built-in capacitance (42). In some examples, the receiver circuit (281) can also include a linear signal circuit and / or a square root signal circuit to achieve further voltage compression and thus a high dynamic range.

Description

Background Art

[0001] One or more computers in an autonomous vehicle (or self-driving car) can be programmed to navigate the vehicle based on vehicle sensor data. The vehicle computer can rely on object detection data such as "point cloud" data generated from light detection and ranging (LIDAR) sensor data to navigate the vehicle to a destination. Object detection sensors typically include a receiver to detect electromagnetic waves, such as light received from the sensor's field of view. However, current methods and techniques for sensor receivers may not provide a high enough dynamic range for detecting objects. Brief Description of the Drawings

[0002] Figure 1A is a schematic diagram of an example vehicle including an object detection sensor.

[0003] Figure 1B is a schematic illustration of Figure 1A the functional blocks of the electrical system of the vehicle shown.

[0004] Figure 1C is an exemplary block diagram of a LIDAR sensor.

[0005] Figure 2 is Figure 1A , 1B , an exemplary block diagram of the object detection sensor shown in 1C, which shows a schematic diagram of the sensor receiver.

[0006] Figure 3 is Figure 2 the exemplary receiver circuit of the sensor receiver shown.

[0007] Figures 4A - 4B is Figure 2 an example of the filter shown.

[0008] Figure 5 is a circuit schematic showing a buffer circuit and an analog memory circuit (both shown in Figure 2 ).

[0009] Figure 6 is an electrical schematic of a receiver circuit further including an impedance reduction circuit and a current bypass circuit.

[0010] Figure 7 is an electrical schematic of a receiver circuit further including a servo loop circuit.

[0011] Figure 8 is an electrical schematic of a receiver circuit including a linear signal circuit, a square root signal circuit, and a logarithmic signal circuit.

[0012] Figure 9A is with respect to that by Figure 12Graph of the voltage pulse amplitude plotted against the photocurrent generated by the receiver circuit, which shows linear, square root, and logarithmic distributions.

[0013] Figure 9B is Figure 12 Graph of the voltage pulse response of the receiver circuit.

[0014] Figure 10 is an electrical schematic diagram of an exemplary receiver circuit including an impedance reduction circuit, a square root signal circuit, and a linear signal circuit.

[0015] Figure 11 is an electrical schematic diagram of a receiver circuit that also includes an AC (alternating current) test circuit and a DC (direct current) test circuit.

[0016] Figure 12 is an electrical schematic diagram of an exemplary receiver circuit that also includes a servo loop circuit coupled to the impedance reduction circuit.

[0017] Figure 13 is an electrical schematic diagram of an exemplary receiver circuit that also includes a common mode noise suppression circuit.

[0018] Figure 14 is another example of an electrical schematic diagram of a receiver circuit and a common mode noise suppression circuit. Detailed Description

[0019] According to one aspect of the present disclosure, a light detection and ranging (LIDAR) sensor includes a light pulse transmitter and a light receiver. The receiver includes a plurality of pixels. Each pixel includes a receiver circuit. Each receiver circuit includes a photosensitive input circuit having at least two terminals, wherein the first terminal is coupled to a detector voltage source and the second terminal is coupled to a pulse voltage node. Each receiver includes a logarithmic signal circuit that includes at least one PN junction, wherein the P-type terminal is coupled to the pulse voltage node and the N-type terminal is coupled to a constant potential.

[0020] A LIDAR sensor may include an impedance reduction circuit electrically coupled to a photosensitive input circuit and a logarithmic signal circuit. The impedance reduction circuit includes at least a common-gate transistor coupled to a pulsed voltage node. The impedance reduction circuit may include a bias transistor, where the bias transistor provides a DC bias current to the common-gate transistor. The LIDAR sensor may include a common-mode noise suppression circuit that includes a capacitor coupled between the gate of the common-gate transistor and a detector voltage source and adapted to suppress common-mode noise on the detector voltage source. The common-mode noise suppression circuit may include a selectively actuated switch coupled between the gate of the common-gate transistor and a reference voltage, where the switch is in a closed position when no photocurrent pulse is expected and where the switch is in an open position when a photoelectric pulse is expected. The LIDAR sensor may include a bypass circuit electrically coupled to the logarithmic signal circuit and including at least a bypass transistor having a terminal coupled to the pulsed voltage node, where the bypass circuit is adapted to reduce the bias current delivered to the logarithmic signal circuit. The LIDAR sensor may include a servo loop circuit that includes an amplifier having first and second inputs and an output, where the first amplifier input is coupled to the pulsed voltage node, the second amplifier input is a reference voltage, and the amplifier output is coupled to the gate of the bypass transistor of the bypass circuit and adapted to control the current at the logarithmic signal circuit. The LIDAR sensor may include a servo loop circuit that includes an amplifier having first and second inputs and an output, where the first amplifier input is coupled to the pulsed voltage node, the second amplifier input is a reference voltage, and the amplifier output is coupled to the gate of the bias transistor of the impedance reduction circuit.

[0021] A LIDAR sensor may include a linear signal circuit that includes a resistor coupled between a pulsed voltage node and a constant potential. The LIDAR sensor may include a square root signal circuit that includes a transistor having a first terminal coupled to the pulsed voltage node and a second terminal coupled to the constant potential. The source of the transistor of the square root signal circuit may be coupled to the pulsed voltage node, the drain of the transistor may be coupled to the constant potential, and the gate of the transistor may be coupled to a control voltage. The photocurrent may primarily: flow through the linear signal circuit when the photocurrent is less than a first threshold; flow through the square root signal circuit when the photocurrent is greater than the first threshold and less than a second threshold; and flow through the logarithmic signal circuit when the photocurrent is greater than the second threshold.

[0022] A LIDAR sensor may include an analog memory circuit coupled to the pulsed voltage node, where the analog memory circuit includes a plurality of sequentially selected capacitive circuits that store voltage samples of return pulses received by the photosensitive input circuit, where each of the plurality of sequentially selected capacitive circuits is readable by a computer.

[0023] The LIDAR sensor may include an adjustable low - pass filter circuit coupled to a pulsed voltage node, wherein the bandwidth of the filter circuit is adjusted by a computer - controlled output. The bandwidth of the filter circuit can be changed by adjusting the resistance value.

[0024] The LIDAR sensor may include a computer that includes a digital processor and a digital memory storing instructions executable by the digital processor to determine a range associated with a return pulse by the following steps: selecting and exciting each of a plurality of capacitor circuits, wherein the plurality of capacitor circuits are coupled to a photosensitive input circuit via the pulsed voltage node; and wherein exciting includes moving a switch from an open position to a closed position and then back to the open position; then, reading the voltage stored in each capacitor circuit.

[0025] According to another aspect of the present disclosure, a light detection and ranging (LIDAR) sensor includes a light pulse emitter and a light receiver. The receiver includes a plurality of pixels, wherein each pixel includes a receiver circuit. Each receiver circuit includes a photosensitive input circuit having at least two terminals, wherein a first terminal is coupled to a detector voltage source and a second terminal is coupled to the pulsed voltage node. Each receiver circuit includes a logarithmic signal circuit that includes at least one PN junction, wherein a P - type terminal is coupled to the pulsed voltage node and an N - type terminal is coupled to a constant potential. Each receiver circuit includes a linear signal circuit that includes a resistor coupled between the pulsed voltage node and the constant potential. Each receiver circuit includes a square - root signal circuit that includes a transistor having a first terminal coupled to the pulsed voltage node and a second terminal coupled to the constant potential.

[0026] According to another aspect of the present disclosure, a light detection and ranging (LIDAR) sensor includes a light pulse emitter and a light receiver. The receiver includes a plurality of pixels, where each pixel includes a receiver circuit. Each receiver circuit includes a photosensitive input circuit having at least two terminals, where one terminal is coupled to a detector voltage source and the other terminal is coupled to a pulse voltage node. Each receiver circuit includes a logarithmic signal circuit including a PN junction, where the P-type terminal is coupled to the pulse voltage node and the N-type terminal is coupled to a constant potential. Each receiver circuit includes a linear signal circuit including a resistor coupled between the pulse voltage node and the constant potential. Each receiver circuit includes a square root signal circuit including a transistor having a first terminal coupled to the pulse voltage node and a second terminal coupled to the constant potential. Each receiver circuit includes an impedance reduction circuit coupled to the photosensitive input circuit, the linear signal circuit, the square root signal circuit, and the logarithmic signal circuit, where the impedance reduction circuit includes a common-gate transistor coupled to the pulse voltage node and a bias transistor that provides a DC bias current to the common-gate transistor.

[0027] The LIDAR sensor may include a common-mode noise suppression circuit including a capacitor coupled between the gate of the common-gate transistor and the detector voltage source and adapted to suppress common-mode noise on the detector voltage source.

[0028] The LIDAR sensor may include a servo loop circuit including an amplifier having first and second inputs and an output, where the first amplifier input is coupled to the pulse voltage node, the second amplifier input is a reference voltage, and the amplifier output is coupled to the gate of the bias transistor of the impedance reduction circuit.

[0029] The LIDAR sensor may include a current pulse injection circuit coupled to the pulse voltage node, where the current pulse injection circuit is adapted to provide a test of functionality or performance.

[0030] According to at least one example, a computer is disclosed that is programmed to perform any combination of the above examples.

[0031] According to at least one example, a computer is disclosed that is programmed to perform any combination of the examples of the above method(s).

[0032] According to at least one example, a computer program product is disclosed that includes a computer-readable medium storing instructions executable by a computer processor, where the instructions include any combination of the instruction examples described above.

[0033] According to at least one example, a computer program product is disclosed that includes a computer-readable medium storing instructions executable by a computer processor, where the instructions include any combination of examples of the above (one or more) methods.

[0034] Various examples of receiver circuits for sensors are described. According to one non-limiting example, the sensor is a light detection and ranging (LIDAR) sensor; thus, its receiver circuit receives and processes reflected light pulses emitted by the sensor such that the range between the sensor and an object can be determined. Examples of the receiver circuit improve the dynamic range of the receiver, thereby enabling accurate range determination over a wide range of incident light powers.

[0035] In this context and throughout the specification, "coupled to" means "directly electrically coupled to" or "indirectly electrically coupled to". "Directly electrically coupled to" means that given two electrical components, there are no electrical components between them, only electrical conductors such as wires, traces, etc. And "indirectly electrically coupled to" means that given two electrical components, there is an electrical circuit path between the two electrical components, where one or more electrical components (such as resistors, switches, transistors, etc.) can be connected along the path and between them.

[0036] Figure 1A is a schematic diagram of an exemplary vehicle 10 and an object 12. The vehicle 10 shown in FIG. 1 is a passenger vehicle that includes at least one computer 16 and an object detection sensor 14; they are used together to detect the object 12. However, as other examples, the vehicle 10 can be any suitable manned or unmanned vehicle, including trucks, motorcycles, airplanes, satellites, drones, boats, robots, etc. The object 12 can be a moving or stationary object located outside the vehicle 10, such as another vehicle, a pedestrian, vegetation, a building, etc.

[0037] The computer 16 can include any suitable computing device programmed to operate the sensor 14 and / or other vehicle components. In at least one example, the computer 16 includes a processor 18 and a memory 20. The processor 18 and the memory 20 are digital. Non-limiting examples of the processor 18 include a microprocessor, a microcontroller or a controller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), one or more circuits including discrete digital and / or analog electronic components configured to perform a predetermined task or instruction, etc.

[0038] Memory 20 may include any non-transitory computer-usable or readable medium, which may include one or more storage devices or articles. Exemplary non-transitory computer-usable storage devices include conventional hard disks, solid state memories, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and any other volatile or non-volatile medium. Non-volatile media includes, for example, optical or magnetic disks and other permanent memories, and volatile media may also include, for example, dynamic random access memory (DRAM). These storage devices are non-limiting examples; for example, there are other forms of computer-readable media, and which includes magnetic media, compact disk ROM (CD-ROM), digital video disk (DVD), other optical media, any suitable memory chip or cartridge, or any other medium from which a computer can read. Generally, memory 20 may store one or more computer program products, which may be implemented as software, firmware, or other programming instructions executable by processor 18.

[0039] Computer 16 may include other hardware elements (not shown), such as an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and one or more discrete circuits, such as various switches in the electronic circuitry for controlling or otherwise enabling sensor 14. In one example, sensor 14 may include computer 16, such as a computer 16 physically located within the housing of sensor 14. In another example, computer 16 may be a separate component from sensor 14 and located at any suitable location within vehicle 10.

[0040] Although not depicted in the illustration, sensor 14 and computer 16 may be communicatively coupled via any suitable wired and / or wireless communication network (e.g., within vehicle 10) - for example, to allow computer 16 to send and / or receive instructions and / or data between it, the components of vehicle 10, and / or sensor 14.

[0041] Figure 1Bis a system block diagram showing the relationship and connection of the main functional blocks of a vehicle electrical system and a central processing unit (CPU) with a LIDAR sensor system. The LIDAR system controller 272 communicates with all LIDAR sensors 14 mounted on the vehicle 10. In an exemplary installation, two long-range units LRU1 246 and LRU2 248 are connected to the LIDAR system controller 272 via a set of bi-directional electrical connections 250. The electrical connections can also have optical waveguides and optical transmitters and receivers to bi-directionally transfer data, control, and status signals between the long-range LIDAR sensors 246, 248 and the LIDAR system controller 272. The LIDAR system controller 272 also communicates with four short-range units SRU1 252, SRU2 254, SRU3 256, and SRU4 258, each via a set of bi-directional electrical connections 260. The electrical connections can also have optical waveguides and optical transmitters and receivers to bi-directionally transfer data, control, and status signals between the short-range LIDAR sensors 252 - 258 and the LIDAR system controller 272. Each LIDAR sensor can include a data processor to reduce the processing load; for example, forming a point cloud and isolating / segmenting objects and object velocities in the field of view from the point cloud. Conventional 2D visible light or infrared observation cameras 262 can be embedded within the LIDAR sensor subsystem and can be part of a sub-assembly containing the LIDAR sensors. These cameras 262 can share the same connections 250 or 260 to the LIDAR system controller 272. A plurality (n) of other visible light 2D static cameras or video cameras 276 can be directly connected to the vehicle collision processor 275 and generate scene data complementary to the 3D data generated by the various LIDAR sensors mounted on the vehicle. The 2D static cameras or video cameras 276 can also operate at visible or infrared wavelengths. The field of view of the 2D static cameras or video cameras 276 can be designed to overlap with the field of view of the LIDAR sensors (246, 248, and 252 - 258) mounted on the vehicle 10. Bi-directional electrical connections 278 are also used to transfer 3D data maps, status, and control signals between the LIDAR system controller 272 and the vehicle electrical system and the central processing unit (CPU) 280. At the core of the vehicle 10, the electronic brain can control all functions of the vehicle 10 and generally control all other subsystems and coprocessors. Here, the electronic brain, i.e., the central processing unit (CPU 280), is integrated with the basic electrical system of the vehicle (including the battery, headlights, wiring harness, etc.). Additionally or alternatively, as Figure 2As shown, computer 16 is the central computer of vehicle 10. The vehicle suspension system 286 receives control commands and returns status via a two-way electrical connection, and is capable of independently modifying the ride height, spring stiffness, and damping rate of each wheel of the vehicle. The inertial reference 284 also has a vertical reference or gravity sensor as an input to CPU 280. The Global Positioning System (GPS) reference 279 can also be connected to the vehicle CPU 280. The GPS reference 279 can also have a database of all available roads and conditions in the area, which can be periodically updated via a wireless link. The duplex radio link 282 can also be connected to the CPU 280 and can communicate directly with other vehicles in the vicinity to share position, speed, direction, and vehicle-specific information for collision avoidance and free traffic flow. The duplex radio link can also receive local position references, road data, weather conditions, and other information important to the operation of vehicle 10 from a central road conditions database via a roadside antenna or cellular station. Vehicle 10 can also provide vehicle status and road condition updates to the central road conditions database via radio uplink 282, thus allowing the central road conditions database to be augmented by any and all vehicles equipped with LIDAR sensors and radio link 282. The collision processor and airbag control unit (ACU) 275 is also connected to the CPU 280 bidirectionally, thus receiving inputs from multiple accelerometers, brake sensors, wheel rotation sensors, LIDAR sensors, etc. The ACU 275 makes decisions regarding the timing and deployment of airbags and other restraints. Although Figure 1B the system is shown as having vehicle 10, on which the system is nominally mounted, and the vehicle is typically an automobile, but the system and any of the described components and subsystems can be designed to be mounted on any number of mobile vehicles, which can be actively driven, semi-autonomously navigated, or fully autonomously steered and controlled, and which can be manned or unmanned, including airplanes, trains, automobiles, motorcycles, helicopters, boats, ships, spacecraft, hovercraft, airships, off-road vehicles, trucks, robotic tracked vehicles, gliders, multi-purpose carriers, road sweepers, submersibles, amphibious vehicles, and sleds.

[0042] Figure 1CIt is a block diagram of LIDAR sensors that depict exemplary long-range LIDAR sensors 246, 248 and short-range LIDAR sensors 252-258. Adaptations of the pulsed laser transmitter 306, the transmit optics 310, the receive optics 312, and in some cases the sampling circuitry of the readout integrated circuit 318 can be implemented to provide range enhancement, wider or narrower fields of view, and reduced size and cost. The first embodiment provides a 128×128 or 128×64 detector array 316 of light detection elements located on a single insulating sapphire substrate, which is stacked on top of the readout integrated circuit 318 using a hybrid assembly method. In other embodiments of this design, M×N focal plane arrays of light detection elements are anticipated, where M and N have values ranging from 2 to 1024 and greater. The functional elements shown in Figure 1C can first be described with respect to the elements of a typical long-range LIDAR sensor 246. The control processor 394 controls the functions of the major components of the LIDAR sensor 246. The control processor 394 is connected to the pulsed laser transmitter 306 through a bi-directional electrical connection (with interface logic, analog-to-digital (A / D) and digital-to-analog (D / A) converters 396), which conveys commands from the control processor 394 to the pulsed laser transmitter 306 and returns monitoring signals from the pulsed laser transmitter 306 to the control processor 394. The interface logic, including the analog-to-digital (A / D) and digital-to-analog (D / A) converters 396, can be located entirely or partially on the readout integrated circuit 318. A photodiode detector (flash detector) 304 is placed at the rear end face of the laser to intercept a portion of the laser pulses generated by the pulsed laser transmitter 306. An optical sample of the output laser pulses taken from the front end face of the pulsed laser transmitter 306 is typically routed through an optical fiber cable to a corner of the detector array 316 as an auto range correction (ARC) signal. The pulsed laser transmitter 306 can be a solid-state laser, a monolithic laser, a semiconductor laser, a fiber laser, or an array of semiconductor lasers. It can also employ more than one individual laser to increase the data rate. In the preferred embodiment, the pulsed laser transmitter 306 is a vertical cavity surface emitting laser (VCSEL) array. In an alternative embodiment, the pulsed laser transmitter 306 is a disk-shaped solid-state laser of erbium-doped phosphate glass pumped by a 976-nanometer semiconductor laser.

[0043] In operation, the control processor 394 issues laser illumination pulses by sending logic commands or modulation signals to the pulsed laser emitter 306, which responds by emitting a strong burst of laser light through the emission filter 308 and the emission optics 310. In the case of a Q-switched solid-state laser based on erbium glass, neodymium YAG, or other solid-state gain media, a simple two-level logic command can initiate the pumping of a laser diode into the gain medium for a period of time, which will ultimately result in a single flash of the pulsed laser emitter 306. In the case of a semiconductor laser that is electrically pumped and can be instantaneously modulated by the modulation of the current signal injected into the laser diode, modulation signals of a more general nature are possible and can be used with major beneficial effects. The modulation signal can be a flat-topped square or trapezoidal pulse, or a Gaussian pulse, or a pulse train. The modulation signal can also be a sine wave, a gated or pulsed sine wave, a chirped sine wave, or a frequency-modulated (FM) sine wave, or an amplitude-modulated (AM) sine wave, or a pulse-width modulation (PWM) series of pulses. The modulation signal is typically stored in the on-chip memory 398 as a look-up table of digital memory words representing analog values; the look-up table is sequentially read out by the control processor 394 and converted to an analog value by the on-board digital-to-analog (D / A) converter 396 and is passed to the pulsed laser emitter 306 driver circuit. The combination of the look-up table stored in the memory 398 and the D / A converter, together with the necessary logic circuits, clocks, and timers 300 resident on the control processor 394, constitutes an arbitrary waveform generator (AWG) circuit block. The AWG circuit block can alternatively be embedded within the laser driver that is part of the pulsed laser emitter 306. The emission optics 310 diffuses the high-intensity spots generated by the pulsed laser emitter 306 substantially uniformly over the desired field of view to be imaged by the LIDAR sensor 246. The emission filter 308 is used to limit the laser output to the design wavelength, thereby removing any stray emissions outside the design wavelength of the pulsed laser emitter 306. An optical sample of the emitted laser pulse (referred to as the ARC signal) is also sent via an optical fiber to the detector array 316. Some of the pixels in the detector array 316 corner are illuminated by the ARC signal, which establishes a zero-time reference for the timing circuits in the readout integrated circuit (ROIC) 318. Each unit cell of the readout integrated circuit 318 has an associated timing circuit that starts counting via an electrical pulse derived from the ARC signal. Alternatively, in a second timing mode, the flash detector 304 signal can be used as the zero reference. Although the ARC signal subtly removes some of the variable delays associated with the transit time through the detector array 316, this results in additional cost and complexity. Given a digital representation of an image frame, the same task can be handled in software / firmware by an embeddable processor such as the data reduction processor 326.When a portion of the emitted laser pulse is reflected from a feature in the scene within the field of view of the LIDAR sensor 246, it can be incident on the receiving optics 312, which typically includes the lens of the headlamp assembly and a microlens array on top of the detector array 316. Alternative embodiments use enhanced detectors that may not require the use of microlenses. Other alternative embodiments of the receiving optics 312 employ diffraction arrays to collect the incident light and direct it to the individual elements of the detector array 316. The pulsed laser reflected from a feature in the scene within the field of view of the receiving optics 312 is collected, filtered by the receiving filter 314, and focused onto individual detector elements of the detector array 316. The reflected laser light signal is then detected by the affected detector elements and converted into current pulses, which are then amplified by the associated unit cell circuits of the readout integrated circuit 318 and the time of flight is measured. Thus, the range to each reflected feature in the scene within the field of view can be measured by the LIDAR sensor 246. As. Figure 1A As shown, the emission optics 310, which consists of a spherical lens, a cylindrical lens, a holographic diffuser, a diffraction grating array, or a microlens array, adjusts the output beam of the pulsed laser emitter 306 into an appropriate conical, elliptical, or rectangular beam for illuminating the central portion of the scene or object in the path of the vehicle 10.

[0044] Continue Figure 1C, the receiving optical device 312 can be a convex lens, a spherical lens, a cylindrical lens, or a diffraction grating array. The receiving optical device 312 collects the light reflected from the scene and focuses the collected light on the detector array 316. The receiving filter 314 restricts the incident light to an appropriate wavelength band associated with the emitter of the same LIDAR sensor 246. In a preferred embodiment, the detector array 316 is formed in a thin film of indium gallium arsenide epitaxially deposited on top of an indium phosphide semiconductor substrate. Generally, the detector array 316 will have a set of cathode contacts exposed to light and a set of anode contacts electrically connected to support the readout integrated circuit 318 through a plurality of indium bumps deposited on the detector array 316. Then, the cathode contacts of the individual detectors of the detector array 316 will be connected to a high-voltage detector bias gate on the illuminated side of the array. Thus, each anode contact of the detector elements of the detector array 316 is independently connected to the input of the unit cell electronic circuit of the readout integrated circuit 318. This conventional hybrid assembly of the detector array 316 and the readout integrated circuit 318 can still be used, but the new technology can reduce the inter-element coupling or crosstalk, and reduce the leakage (dark) current and improve the efficiency of the individual detector elements of the detector array 316. In a preferred embodiment, the elements of the detector array 316 can be formed on top of a substantially single-crystalline sapphire wafer. Silicon-on-sapphire (SOS) substrates with a thin layer of substantially single-crystalline silicon epitaxially grown thereon are commercially available and are known for their excellent performance characteristics. Germanium and silicon-germanium detectors are also compatible with monolithic silicon integrated circuit processes and can be alternatively employed. The detector array 316 of APD, PIN, or PN junction detectors can be formed by a sequence of layers of p-type and n-type silicon through epitaxial regrowth on an SOS wafer. Boron and aluminum can be used as dopants for any p-type silicon epitaxial layer. Phosphorus, arsenic, and antimony can be used as dopants for any n-type silicon epitaxial layer. Sapphire substrates with epitaxially grown thin layers of single-crystalline gallium nitride are also commercially available (gallium nitride on sapphire, or GNOS), and are widely considered to be very suitable substrates for manufacturing high-brightness blue LEDs. The detector array 316 of APD, PIN, or PN junction detectors can be formed by a sequence of layers of p-type and n-type gallium nitride (GaN) or indium gallium nitride (InGaN) through epitaxial regrowth on a GNOS wafer. Silicon and germanium can be used as dopants for any n-type GaN layer. In some cases, magnesium can be used as a dopant for the p-type layer in GaN. In a further development, the detector array 316 can be directly monolithically fabricated on top of the readout IC 318. The detector array 316 can also be formed in a more conventional manner from compounds of indium gallium arsenide, indium aluminum arsenide, silicon carbide, diamond, mercury cadmium telluride, zinc selenide, or other well-known semiconductor detector materials. The readout integrated circuit 318 includes a rectangular array of unit cell circuits.Each unit cell or pixel has the ability to receive a photocurrent pulse generated by a photodetector element of detector array 316, convert the photocurrent pulse into a voltage pulse, and sample the voltage pulse. Typically, the unit cell is also capable of detecting the presence of an electrical pulse associated with a light pulse reflected from a scene and intercepted by a detector element of detector array 316. Detector array 316 can be an avalanche photodiode array, capable of optoelectronic amplification and modulated by an incident optical signal of a designed wavelength. The detector array 316 elements can also be of P-intrinsic-N design or N-intrinsic-P design, where the majority carriers are holes or electrons, respectively; in such cases, the corresponding ROIC 318 will have a correspondingly adjusted bias voltage and the polarity of the amplifier input. The hybrid assembly of detector array 316 and readout integrated circuit 318 of the preferred embodiment is mounted to a support circuit assembly, typically on an FR-4 substrate or a ceramic substrate. The circuit assembly typically provides support circuitry that, while receiving and recording the range and intensity outputs for the individual elements of detector array 316 from readout integrated circuit 318, provides, among other support functions, adjusted power, a reference clock signal, calibration constants, and select inputs for reading out columns and rows. Many of these support functions can be implemented by a reduced instruction set computer (RISC) processor residing on the same circuit substrate. The detector bias converter circuit 350 applies a time-varying detector bias to detector array 316, which provides an optimal detector bias level to reduce the risk of saturation in the near field of detector array 316 while maximizing the likelihood of detection of distant objects in the field of view of detector array 316. The profile of the time-varying detector bias provided by detector bias converter 350 is developed by control processor 394 based on feedback from data reduction processor 326, which indicates the reflectivity and distance of an object or point in the scene within the field of view of detector array 316. Control processor 394 also provides several clock and timing signals from timing core 300 to readout integrated circuit 318, data reduction processor 326, analog-to-digital converter 322, object tracking processor 334, and its associated memory. Control processor 394 relies on a temperature-stable or temperature-compensated frequency reference 348 to generate the various clock and timing signals. The temperature-stable frequency reference 348 can be a temperature-compensated crystal oscillator (TCXO), a dielectric resonator oscillator (DRO), or a surface acoustic wave device (SAW). The timing core 300 residing on control processor 394 can include a high-frequency tunable oscillator, a programmable prescaler divider, a phase comparator, and an error amplifier.

[0045] Continue Figure 1C, the control processor 394, the data reduction processor 326, and the object tracking processor 334 each have associated memories for storing programs, data, constants, and the results of operations and calculations. These memories (each associated with an accompanying digital processor) can include ROM, EPROM, or other non-volatile memories such as flash memory. They can also include volatile memories such as SRAM or DRAM, and both volatile and non-volatile memories can be integrated into each of the respective processors. The common frame memory 330 is used to hold multiple frames, each frame being an image obtained from a single laser transmission sequence. The laser transmission sequence can be a single pulse, or a sequence of pulses, depending on the type of laser employed. The operating mode in a preferred embodiment using a single laser illumination pulse is described in this section. Both the data reduction processor 326 and the object tracking processor 334 can perform 3D image processing to reduce the load on a scene processing unit (not shown) typically associated with the LIDAR system controller 272. There are two data collection modes. The first is SULAR, or a row-by-row scan in depth. Each laser pulse typically produces 20 data "slices", similar to a CAT scan, and each "slice" can be stored as a single page in the common frame memory 330. For each pixel sampling at 2 nanosecond intervals, each slice is a layer of the image space with a depth difference of approximately 1 foot. The 20 slices represent one frame of data, and the sampling of subsequent laser pulses can start 20 feet further in depth, such that the entire image space with a range or depth up to 1000 feet can be swept out in 50 consecutive laser pulses. In some cases, the frame memory can be large enough to hold all 50 data frames. The number of stored slices can be sufficient to map out any relevant distances without the need for trigger mode operation. Then, the reduction of the data can be performed in an external computer, as in the case of data for mapping an underwater surface, or a forest with tree cover, or any static terrain, where complex post-processing techniques in software can produce excellent accuracy or resolution. The second data acquisition mode is the "trigger" mode, where each pixel individually looks for a pulse response, and when a certain pulse threshold criterion is met, 20 analog samples including the pulse arrival time are retained in the pixel analog memory, and the running digital counter is frozen with a nominal range measurement. The 20 analog samples are output from each pixel through the "A" and "B" outputs 320 of the readout integrated circuit 318. The "A" and "B" outputs 320 are analog outputs, and the analog samples presented there are converted to digital values by a two-channel analog-to-digital (A / D) converter 322. The larger detector array 316 and the readout IC 318 can have more than two analog outputs. The digital output 324 of the A / D converter 322 is connected to the input of the data reduction processor 326. The A / D converter 322 can also be integrated into the readout integrated circuit 318.The digital output is typically a 10 - or 12 - bit digital representation of the uncorrected analog samples measured at each pixel of the read - out IC 318, but other representations with more or fewer bits can also be used depending on the application. The rate of the digital output depends on the frame rate and the number of pixels in the array. In the "trigger" mode, a significant amount of data reduction has been performed because the entire range or depth space can be swept out within the time frame of a single laser pulse, and the data reduction processor 326 will operate only on the 20 analog samples stored in each unit cell in order to refine the nominal range measurements received from each pixel (unit cell) of the array. The data reduction processor 326 refines the nominal range measurements received from each pixel by curve - fitting the analog samples to the shape of the outgoing laser illumination pulse retained by the reference ARC pulse signal. These pulses are typically Gaussian pulses, but can also be square, trapezoidal, haversine, sine functions, etc., and the fitting algorithm can employ Fourier analysis, least - squares analysis, or fitting to polynomials, exponentials, etc. Range measurements can also be refined by curve - fitting to well - known reference pulse characteristic shapes. In the "trigger" acquisition mode, the frame memory 330 only needs to store the "point cloud" image for each illuminating laser pulse. The term "point cloud" refers to an image created by the range and intensity of the reflected light pulses detected by each pixel of the pixel array. In the "trigger" mode, the data reduction processor 326 is mainly used to refine the R&I measurements made by each pixel before passing the range and intensity (R&I) data to the frame memory 330 via the data bus 328, and in this acquisition mode, no "slice" data or analog samples are retained in the memory independently of the R&I "point cloud" data. The frame memory 330 provides single or multiple frames or the complete point cloud image to the control processor 394 via the data bus 344 as needed, and provides single or multiple frames or the complete point cloud image to the optional object tracking processor 334 via the data bus 332.

[0046] Reference Figure 1C, the data reduction processor 326 and the control processor 394 can be of the same type, i.e., a hardware-implemented reduced instruction set (RISC) digital processor with integer and floating-point arithmetic units. The object tracking processor 334 can also be of the same type as the RISC processors 326 and 394, but in some cases can also be a more capable processor suitable for highly complex graphics processing. In addition to the hardware-implemented integer and floating-point arithmetic units, the object tracking processor 334 can also have multiple hardware-implemented matrix arithmetic functions, including but not limited to matrix determinant, matrix multiplication, and matrix inversion. In operation, the control processor 394 controls the readout integrated circuit 318, the A / D converter 322, the frame memory 330, the data reduction processor 326, and the object tracking processor 334 via a bidirectional control bus 346, which enables the control processor 394 to pass commands to the subordinate peripheral blocks based on priority; the readout IC 318, the A / D converter 322, the frame memory 330, the data reduction processor 326, and the object tracking processor 334. The bidirectional control bus 346 is also used to return status and processing parameter data from the readout IC 318, the A / D converter 322, the frame memory 330, the data reduction processor 326, and the object tracking processor 334 to the control processor 394. The data reduction processor 326 refines the nominal range data and adjusts each pixel intensity data generated from the digitized analog samples received from the A / D converter 322, and outputs the full image frame to the frame memory 330 via a unidirectional data bus 328, which is a dual-port memory and has the ability to store from several frames to thousands of frames depending on the application. The object tracking processor 334 has an internal memory with sufficient capacity to hold multiple frames of image data, enabling multi-frame synthesis processing, including video compression, single-frame or multi-frame resolution enhancement, statistical processing, and object recognition and tracking. The output of the object tracking processor 334 is transmitted via a unidirectional data bus 336 to the communication port 302, which can reside on the control processor 394. Then, all slice data, range and intensity data, control, and communication are passed between the communication port 302 and the centralized LIDAR system controller 272 via a bidirectional connection 350. Power and ground connections (not shown) can be provided via an electromechanical interface. The bidirectional connection 350 can be an electrical or optical transmission line, and the electromechanical interface can be a DB-25 electrical connector, or a hybrid optical and electrical connector, or a dedicated automotive connector configured to carry signals bidirectionally for the LIDAR sensor 246. The bidirectional connection 260 (see Figure 1BConnect the LIDAR system controller 272 to the auxiliary light assembly, which may have a short-range LIDAR sensor 258 embedded therein. The bi-directional connection 150 (260) can be a high-speed serial connection such as Ethernet, Universal Serial Bus (USB), or Fibre Channel, or it can also be a parallel high-speed connection such as Infiniband, etc., or it can be a combination of high-speed serial and parallel connections, not limited to those listed here. The bi-directional connection 150 (260) is also used to upload information to the control processor 394, including program updates for the data reduction processor 326, the object tracking processor 334, and the global position reference data, as well as dedicated control parameters for the remaining part of the functional block of the LIDAR sensor 246. Inertial and vertical reference 284 (see Figure 1BAlso, as needed, data is provided from the host vehicle 10 to the short-range LIDAR sensors 252-258 and the long-range LIDAR sensors 246-48 via the vehicle electrical system and the CPU 280 and the LIDAR system controller 272. Similarly, any other data from the host vehicle 10 that may be useful to the LIDAR sensor 246 can be provided in the same manner as the inertial and vertical reference data. In addition to the external position reference, the control processor 394 can also utilize the inertial and vertical reference data, which can pass the position and inertial reference data to the data reduction processor 326 to adjust the range and intensity data, and to the object tracking processor 334 for use in multi-frame data synthesis processing. The vertical reference typically provides measurements of pitch and roll, and is adapted to read out the elevation angle and the twist angle (similar to roll) relative to the horizontal plane perpendicular to gravity. The short-range LIDAR sensors 252-258 typically employ semiconductor lasers, which can be modulated in a variety of different ways. The long-range LIDAR sensors 246-248 typically employ Q-switched solid-state lasers, which can produce a single output pulse with a Gaussian distribution if appropriately controlled. The pulse shape of this type of solid-state laser is not easily modulated, and thus must be processed "as is" by the receiver portion of the long-range LIDAR sensors 246-248. With some exceptions, the operation of the short-range LIDAR sensors 252-258 of the type typically embedded in auxiliary lamp assemblies such as taillights, turn signals, or stoplights is the same as the operation of the long-range LIDAR sensors 246-248. The long-range LIDAR sensors 246-248 and the short-range LIDAR sensors 252-258 can differ only in the type of laser employed and the type of laser modulation. Due to the different fields of view of the long-range LIDAR sensors 246-248 and the short-range LIDAR sensors 252-258, the transmit optics 310 and the receive optics 312 can also be different. The differences in the transmit laser pulse modulation between the long-range LIDAR sensors 246-248 and the short-range LIDAR sensors 252-258 can be accommodated by the flexible nature of the readout IC 318 sampling mode and the programmability of the data reduction processor 326. The host vehicle 10 can have a plurality of connector sockets, which are typically available for receiving mating connector plugs from USB, Ethernet, RJ-45, or other interface connections, and which can alternatively be used to attach long-range LIDAR sensors 246-248 or short-range LIDAR sensors 252-258 of the type described herein.

[0047] In a short-range LIDAR sensor 252, a relatively small transmit power is required, so a semiconductor laser and a multi-pulse modulation scheme can be used. An example of a semiconductor laser is a vertical-cavity surface-emitting laser (VCSEL), which is used in a preferred embodiment due to several advantageous characteristics. A VCSEL typically has a circular beam profile and a low peak power density at the aperture. A VCSEL also requires fewer auxiliary mechanical operations such as dicing, polishing, etc., and can be formed into an array relatively easily. The use of a semiconductor laser allows the drive current pulse to be adjusted to produce a Gaussian optical pulse shape with only slight deviations. The VCSEL response time is in the sub-nanosecond range, and at the half-power point, the typical pulse optical width can be 5 - 10 nanoseconds. In Figure 1C the figure of, the VCSEL and the laser driver will be part of the pulsed laser transmitter 306, and the required pulse or waveform itself is generated by a digital-to-analog converter 396 with a typical conversion rate of 200 - 300 MHz. Thus, any deviation of the output pulse shape from the Gaussian ideal can be compensated for in a look-up table in the memory 398 associated with the control processor 394, which serves as a digital reference for the drive current waveform supplied by the D / A converter 396 to the laser driver within the pulsed laser transmitter 306. Given the limited optical power available from the VCSEL, then, the Gaussian single-pulse modulation scheme works well at short ranges. More complex modulation schemes (such as multi-pulse sequences, sine-wave bursts, etc.) can be used to extend the range of the VCSEL transmitter. The modulation scheme and VCSEL described here with reference to the short-range LIDAR sensor 252 are alternatives to the solid-state lasers typically used in the pulsed laser transmitter 306 of long-range LIDAR sensors 246. The use of a VCSEL array in the pulsed laser transmitter 306 has the potential to reduce cost, size, power consumption, and / or enhance reliability. The LIDAR sensor can be mounted at many points on the vehicle 10: headlamps, auxiliary lamps, door panels, rearview mirrors, bumpers, etc. When equipped with a more sensitive detector array 316 (such as an APD array, a SPAD array, or an image-tube FPA), a LIDAR sensor of the type described here can use a VCSEL array as an illumination source and can support a much longer range. When referring to Figure 1CWhen referring to the main functions of the LIDAR sensor, it is sometimes convenient to refer to the "optical transmitter" as those functions that support and / or create light bursts for illuminating the scene in the field of view. These elements are typically the control processor 394 that initiates the process, the pulsed laser transmitter 306, the transmit filter 308, and the transmit optics 310. The term "optical receiver" can be used to refer to those elements required to collect the light reflected from the scene in the field of view, filter the received light, convert the received light into a plurality of pixelated electrical signals, amplify these pixelated electrical signals, detect the pulses or modulations thereon, perform distance measurements, and refine or streamline the received data. These functions will include the receive optics 312, the receive filter 314, the detector array 316, the readout IC 318, the A / D converter 322, and the data reduction processor 326.

[0048] Referring to FIGS. 1-5, the object detection sensor 14 in the illustrated example can be any suitable light detection and ranging (LIDAR) sensor, e.g., the long range sensor units LRU1 246 and LRU2 248, the short range sensor units SRU1 252, SRU2 254, SRU3 256, and SRU4 258. For example, the sensor 14 can be a solid state sensor (e.g., a flash LIDAR sensor). The sensor 14 can emit light pulses into the illumination field, and when an object 12 is within the field of view of the sensor, the sensor 14 can detect the object 12 based on the reception of the reflection of the light reflected from the object 12.

[0049] According to at least Figure 2 In the example shown, the sensor 14 includes one or more optical pulse transmitters 22 (hereinafter referred to as "transmitter 22") (e.g., including the pulsed laser transmitter 306, the transmitter optics 310, etc.) and one or more receivers 24 (e.g., including the receive optics 312, the receive filter 314, the detector array 316, the readout IC 318). According to one example, each transmitter 22 is the same, and each receiver 24 is the same; thus, only one of each will be described below.

[0050] The transmitter 22 can be any suitable electronically excitable device for emitting light. For example, it can be a semiconductor laser, such as a vertical cavity surface emitting laser (VCSEL), an edge emitting laser diode, or a diode pumped solid state laser (DPSSL), to name just a few non-limiting examples. The transmitter 22 can be designed to emit pulsed flashes (e.g., pulsed beams) according to any suitable power and wavelength, i.e., the transmitter 22 can be a pulsed laser transmitter. According to one example, the pulsed beam is in the infrared spectrum; however, visible light and ultraviolet light can also be used in some applications.

[0051] The receiver 24 may include any suitable electronics for detecting light transmitted by the transmitter 22 and reflected from the object 12. Refer to Figure 1C and 2 , according to one example, the receiver 24 includes one or more pixels 26. In the example shown, the receiver 24 includes an array of pixels 26 (see Figure 2 ). In at least one example, each pixel 26 may be the same; thus, only one will be described. The pixel 26 may include a receiver circuit 28, a filter circuit 30, a buffer circuit 32, and an analog memory circuit 34.

[0052] In Figures 2 - 3 the example shown, the receiver circuit 28 includes a photosensitive input circuit 36 (or photodetector) and a logarithmic signal circuit 38. The photosensitive input circuit 36 may include a photosensitive element 40 having an internal capacitance 42 (shown as a capacitor coupled in parallel (dashed line) with the element 40 in Figure 3 ). In one example, the photosensitive element 40 is a PIN photodiode, but it could also be an APD or other type. A photodiode is a semiconductor device designed to convert received light into an electric current. The photodiode may be attached with a filter for selecting the wavelength of the incident light. The photodetector may also employ a lens designed to collect and focus the incident light. As described above, the capacitor 42 represents the internal capacitance formed in the solid-state junction of the photodiode. According to one example, the internal capacitance is typically in the range of 50 to 500 femtofarads (fF).

[0053] In Figure 3 the photosensitive element 40 includes an input 44 coupled to a voltage source V det (e.g., 8V DC) and an output 46 coupled to a node 47. Also shown is a light input 48 to the photosensitive element 40 — thus, when a light input 48 is received at the element 40, a current i pe is induced at the output 46. The configuration shown enables the photodiode 40 to operate in a photoconductive mode. The logarithmic signal circuit 38 may include a forward-biased PN junction, hereinafter referred to as diode 50. The anode of the forward-biased diode 50 (e.g., the p-type terminal of the PN junction) may be connected via a pulsed voltage node 52 (having a voltage V pThe node 52) is coupled to node 47 (in this example, nodes 46, 47, and 52 are the same). The terminal 53 of the logarithmic signal circuit 38 (such as the cathode of the diode 50 (such as the n-type terminal of the PN junction)) can be coupled to ground. The term "ground" is used in this context to describe a reference point in the circuit (i.e., having a constant potential) from which voltages are measured and which is a common return path for current; in some examples, the receiver circuit 28 can include a local and / or global ground. In at least one example, the logarithmic circuit 38 does not include an amplifier directly coupled to the photosensitive input circuit 36. The receiver circuit 28 can be coupled to the filter circuit 30 through node 52.

[0054] As Figure 4A shown, the filter circuit 30 can be any suitable circuit for filtering unwanted noise from the system. According to one example, the filter circuit 30 includes an adjustable low-pass filter. In this context, an "adjustable filter" means having a variable bandwidth. According to the example shown, the adjustable low-pass filter circuit 30 includes an optional buffer 58 (such as a buffer amplifier) coupled to an RC filter, and the RC filter can include an adjustable resistor circuit 54. In the embodiment shown in the figure, the resistor circuit 54 can be an optional resistor, but can alternatively be a potentiometer or other adjustable resistor. The adjustable resistor circuit 54 is connected to the first terminal of the capacitor 56, and the second terminal of the capacitor 56 is connected to a constant potential such as ground. More specifically, the input 60 of the filter circuit 30 (and to the buffer 58) can be connected to node 52 (voltage V p ), and the output of the buffer 58 can be connected to the resistor circuit 54 at node 68. The output 62 of the filter circuit 30 is generated at node 63 (voltage V f ). In this embodiment, node 63 is located between the resistor circuit 54 and the capacitor 56. Exemplary values for the resistor circuit 54 include a resistance range from 1 kOhm to 100 kOhm, and exemplary values for the capacitor 56 include from 10 fF to 100 fF. The buffer circuit 58 (when included in the circuit 30) can increase the electrical isolation between the input node 52 (V p ) and the filtered output V f at node 63, and minimize the undesired reduction of the electrical signal source by reducing the impedance load. The buffer amplifier 58 is thus used for the known purpose of driving a low-impedance load from a high-impedance source without losing the signal. By adjusting the resistance of the resistor circuit 54, the filter circuit 30 can adjust the bandwidth of the circuit 30.

[0055] As Figure 4B shown, there are also other examples of filter circuits. For example, a filter circuit 30' is shown, which includes a resistor circuit 54'; other elements of the filter circuit can be the same as those in the referenceFigure 4A Those described components are similar or identical (therefore, they will not be described here again).

[0056] The resistor circuit 54' may include a first resistor 64a connected in parallel with the first bypass switch 66a, and a second resistor 64b connected in parallel with the second bypass switch 66b. The resistors 64a, 64b and the switches 66a, 66b are each connected to each other at the node 65. The switches 66a, 66b can be selectively actuated via an electronic control unit or a computer (e.g., including but not limited to computer 16) to control the resistance, and thus control the bandwidth of the filter circuit 30'. The switch 66a is controlled by an electrical input 67a, and the switch 66b is controlled by a control input 67b. For example, considering the exemplary total resistance of the filter circuit 30' (as shown in Table I), where the resistance of the resistor 64a is denoted as "R1", and where the resistance of the resistor 64b is denoted as "R2". The resistance of the switches 66a and 66b when closed is Rs, which is typically much lower than R1 and R2. According to at least one example, R1 can be 15 kOhm, R2 can be 30 kOhm, and Rs can be 1 kOhm; however, these resistance values are merely examples.

[0057] Table I

[0058] Bypass switch 66a Bypass switch 66b Total resistance Open Open R1 + R2 Open Closed R1 + Rs Closed Open R2 + Rs Closed Closed 2Rs

[0059] Therefore, by selectively controlling the switches 66a, 66b of the resistor circuit 54', the bandwidth of the filter circuit 30' can be adjusted. It should be understood that there are also other examples of the resistor circuit 54' - for example, including additional arrangements using resistors coupled in series and / or parallel.

[0060] Figure 5 An analog sampling circuit including a buffer circuit 32 and an analog memory circuit 34 is shown. The buffer circuit 32 can be a source follower, push - pull, unity - gain feedback amplifier or other suitable electronic buffer amplifier. Those skilled in the art should understand these other implementations of the buffer circuit 32. The output 62 (voltage V f ) of the filter circuit 30 is connected to the input 73 of the buffer circuit 32, and the output 75 (voltage V b ) of the buffer circuit 32 is connected to the input 76 of the analog memory circuit 34 at the node 77.

[0061] Figure 5An exemplary implementation of the analog memory circuit 34 is also shown. According to at least the example shown, the analog memory circuit 34 includes a plurality of analog sampling circuits 79. Each analog sampling circuit 79 includes a capacitor 72, where the first terminal is connected to the output of the switch 78 and the second terminal is connected to a constant potential such as ground. The switch 78 has an input connected to node 77 and a control input 80 that is excited by a digital sampling clock signal. The analog memory circuit 34 includes a plurality of these sequentially clocked analog sampling circuits 79, each also coupled to node 77. According to one non-limiting example, the analog memory circuit 34 can include between 10 and 1000 sequentially clocked analog sampling circuits 79 - thus having an appropriate number to store data on a number of return pulses. For clarity, Figure 5 only three exemplary analog sampling circuits 79 are shown. According to at least one example, each of the analog sampling circuits 79 can be the same; therefore, only one will be described.

[0062] The sequentially clocked analog sampling circuit 79 generally includes a switch 78 and a capacitor 72, where the switch 78 is connected between node 77 and node 81 (voltage V i ), and where the capacitor 72 is coupled between node 81 and ground. (Each circuit 79 can have a different input voltage as a function of time; therefore the "i" in V i can be designated as 1, 2,..., n). As will be explained in more detail below, by selectively exciting the switch 78 (i.e., closing one of the switches 78), each circuit 79 can be used to store a "time sample" (e.g., a sampled voltage) of a portion of the electrical signal received via node 77.

[0063] The voltages V1, V2,..., V n of the analog memory circuit 34 can be digitized by an analog-to-digital converter (not shown) and received by the computer 16 as digitized voltage samples, as Figure 2 best shown in. In some cases, the processor 18 will have an on-board ADC for analog-to-digital conversion, which is a common feature on many signal processing microcomputer integrated circuits. Therefore, the computer 16 is coupled to the analog memory circuit 34. More specifically, the computer 16 can be coupled to each node 81 such that it can read the stored time slices.

[0064] There are also other examples of the receiver circuit 28 of pixel 26. However, before describing some of these examples, an exemplary operation of sensor 14 will be described. According to one non-limiting example, computer 16 can be programmed to control multiple transmitter / receiver pairs 22, 24 of sensor 14 to detect an object (such as object 12) within the field of view of the sensor. Since the operation of each pair 22, 24 can be similar, the operation of only one transmitter / receiver pair 22, 24 will be described.

[0065] The general operation of sensor 14 can include sensor 14 and computer 16 being powered by a power source (not shown) onboard vehicle 10. At an appropriate time before moving the vehicle, the power source is activated. Thereafter, computer 16 can start a sampling clock and command the laser to emit pulses from transmitter 22. The light can be reflected from the surface of object 12, and the activated receiver 24 can receive the reflected light beam (also referred to as a return, return beam, or return pulse). As used herein, the activated state means that sensor 14 is powered and receiver 24 (and its components, such as receiver circuit 28) is ready to receive the return pulse. After receiving the return pulse, computer 16 can use time-of-flight (TOF) calculations to determine the range (e.g., distance) between sensor 14 and the surface of object 12. A typical TOF calculation would be the speed of light multiplied by the measured change in time (Δt) of the return pulse; where Δt is equal to the time of the return after the time the clock was started. Generally, sensor device 14 includes multiple transmitter / receiver pairs 22, 24; thus, many range measurements from various fields of view are received, and computer 16 uses these measurements to determine what is referred to as a three-dimensional (3D) point cloud. A point cloud is a general term for a set of points that can define one or more surfaces of object 12. The point cloud data can be used by computer 16 to generate a 3D map of the area around sensor 14, such as the sides of a building, trees, road surface, etc. Thereafter, computer 16 onboard vehicle 10 or other computers can control vehicle propulsion, braking, and / or steering based on the detection of object 12, etc.

[0066] The following is a more specific description of the operation of receiver 24. Referring again to Figure 3 , powering receiver 24 can include providing a predetermined detector voltage source (e.g., 8V) at V det . In some examples, switches 66a, 66b, input 80, etc. ( Figure 4A , 4B , 5) can also be powered by a digital logic voltage level of 2.5V or other suitable voltage. In this way, when a return pulse is received at pixel 26, the photosensitive element 40 can provide a photocurrent pulse (i pe ) corresponding to the amount of received and converted light via output 46. Here, the current i peAlso known as the optoelectronic pulse current, as it is generated by receiving the returned pulse.

[0067] At node 52, the pulse current i pe flows through the logarithmic signal circuit 38 to ground, thereby being converted into a voltage pulse V p . The circuit 38 is called a logarithmic signal circuit based on the gradual (e.g., logarithmic) change of voltage (V p ) with current i pe . Generally, the logarithmic voltage compression of the logarithmic signal circuit 38 improves the dynamic range of the receiver circuit 28. The dynamic range refers to the ratio of the maximum optoelectronic pulse current that the receiver circuit 28 can receive to the minimum optoelectronic pulse current. The maximum optoelectronic pulse current is the highest optoelectronic pulse current that does not cause saturation of the photosensitive element 40 or the voltage at nodes 60, 62, or 76. The minimum optoelectronic pulse current is M times higher than the input reference noise of the receiver. The factor M depends on the required detection probability of the returned pulse. For a higher detection probability, the factor M will be higher, so the calculated dynamic range is slightly smaller. Therefore, the dynamic range is a somewhat subjective characteristic of the pulse receiver subsystem.

[0068] The filter circuit 30 can suppress the noise frequency of the voltage pulse V p that exceeds a predetermined filter cut-off frequency, such that node 63 measures the filtered voltage V f . According to at least one example, as described above, the resistor circuit 54 is appropriately tuned to adjust the filter bandwidth. The selection of the bandwidth can be calculated dynamically or set in a factory calibration sequence, and can depend on various factors, such as the rise / fall time of the emitted laser pulse, the frequency and amplitude response of the photodiode, the dark current or background noise level of the photodetector, and the sampling frequency of the analog memory circuit 34. According to another example of bandwidth adjustment, the computer 16 determines whether to energize (and thus close) the switch 66a, 66b, or both.

[0069] The buffer circuit 32 receives the voltage V Figure 5 at the input 73 ( f ). Thereafter, the buffer amplifier circuit 32 replicates the input signal and provides a low-impedance driving capability to the output 75 (voltage V b ), without loading the input signal at node 73. Buffer techniques and the circuits used to implement such buffer techniques are well known to those skilled in the art.

[0070] According to the example shown, the analog memory circuit 34 receives the voltage V b, this voltage is continuously sampled by one of the sampling circuits 79. According to one example, only one switch 78 can be actuated to the closed position at a time - as controlled by the computer 16 via the corresponding input 80. Additionally, the switches 78 can be selectively moved to the closed position one at a time according to a predetermined sequence in order to capture voltage information regarding the pulse return. When the switch 78 of one of the circuits 79 is in the closed position, the corresponding capacitor 72 is charged to the voltage present at node 77. Once the corresponding switch 78 is actuated back to the open position, the sampled voltage value is stored on the capacitor 72 until the computer 16 reads out this value. For example, by sequentially repeating this operation, the voltage values of the return pulses can be sampled at 1 nanosecond intervals (e.g., as multiple time slices), and the computer 16 is able to reconstruct the shape and profile of the return pulses having a width of 5 nanoseconds. Additionally, the computer 16 is able to determine the peak of the return pulses, and this peak can be used to accurately calculate Δt and thereby determine the range of the corresponding return pulses.

[0071] As described above, there are also other examples of the receiver circuit 28 of the pixel 26. In each subsequent example, similar or identical elements are denoted by the same reference numerals. For example, Figure 6 An exemplary receiver circuit 281 is shown. According to this example, the photosensitive input circuit 36 and the logarithmic signal circuit 38 can be coupled to an impedance reduction circuit 84 (also referred to as a common - gate amplifier circuit) and a current bypass circuit 86. Some aspects of the receiver circuit 281 can be the same as those of the receiver circuit 28 ( Figure 3 of).

[0072] According to one example, the impedance reduction circuit 84 is coupled between the photosensitive input circuit 36 and node 52. The impedance reduction circuit 84 can include two transistors: a common - gate transistor 88 and a bias transistor 96, connected as shown. For example, the common - gate transistor 88 can be a p - channel metal - oxide - semiconductor field - effect transistor (MOSFET), and the bias transistor 96 can also be a p - channel MOSFET. The common - gate transistor 88 includes a first terminal 90, a second terminal 92, and a third terminal 94 (e.g., gate, source, and drain respectively), and the bias transistor 96 includes a first terminal 98, a second terminal 100, and a third terminal 102 (e.g., gate, source, and drain respectively). The second terminal 100 is connected to a power supply (e.g., 2.5V), and the first terminal 98 can be coupled to a reference voltage, typically the output of a digital - to - analog converter (DAC) programmed by the computer 16. The computer 16 can be a microprocessor of the controller type having several on - board DACs. The computer / controller 16 is able to adapt the reference voltage (V pbiasto activate the bias transistor 96 to provide a bias current to the common-gate transistor 88 through the third terminal 102. The common-gate transistor 88 requires a minimum level of bias current to be provided at the second terminal 92. The first terminal 90 is connected to a reference voltage (V cg to set the common-gate transistor 88 for proper operation. The reference voltage (V cg is typically provided by the DAC output, which is also driven by the computer / controller 16. The common-gate transistor 88 is connected to the node 52. Specifically, the third terminal 94 is connected to the node 52.

[0073] The current bypass circuit 86 includes a bypass transistor 104 (e.g., an n-channel MOSFET) having a first terminal 106, a second terminal 108, and a third terminal 110 (e.g., gate, drain, and source, respectively). The first terminal 106 is connected to a bias voltage (V nbias ). The bias voltage (V nbias is typically generated by the DAC. In the embodiment shown in the figure, the DAC is integrated with the computer / controller 16, and the computer / controller 16 calculates the optimal voltage (V nbias ) to the gate terminal 106 of the bypass transistor 104. The bypass transistor 104 is used to divert the bias current provided by the bias transistor 96 to ground because the second terminal 108 is connected to the node 52 and the third terminal 110 is connected to ground. In this way, the bypass transistor 104 is adapted to reduce the bias current transmitted to the logarithmic signal circuit 50, thereby ensuring that the diode 50 exhibits a large dynamic resistance for small photocurrent pulses.

[0074] During the operation of the receiving circuit 281, the common-gate transistor 88 can reduce the impedance seen by the photosensitive input circuit 36, thereby reducing the impact of the photodiode built-in capacitance 42. The photodiode built-in capacitance 42 is used to limit the frequency response of the pulse receiver circuit 28. Without the impedance reduction circuit 84 installed, this impact would be much greater. This impact is essentially the same as a low-pass filter, thereby reducing the high-frequency components in the received pulse. Excessive low-pass filtering is used to reduce the received pulse amplitude and increase the received pulse width. Any reduction in the received pulse amplitude is undesirable because it negatively affects the maximum range of the LIDAR system. Therefore, the impedance reduction circuit 84 is used to improve the frequency response, amplitude response, and thus improve the maximum range of the LIDAR system. The bias current provided by the bias transistor 102 is added to the photocurrent from the detector element 48 and input to the node 52 as i cg = (i pe + i bp ), where i bprepresents the bias current of the impedance reduction circuit 84. Accordingly, the current bypass circuit 86 is configured to reduce this current accordingly. The current bypass circuit 86 is designed to divert the bias current required for the operation of the impedance reduction circuit 84, as well as the dark current and the DC background photocurrent received from the photosensitive input circuit 36, to ground. The dark current is a relatively small current that flows through a photosensitive element, such as a photodiode, even when no photons enter the element; it is caused by the charge generated in the photosensitive element when no external radiation enters the photosensitive element. The DC background photocurrent can be generated by light emitted from a light source other than the transmitter 22 received via the receiver 24 (e.g., street lighting, daylight, vehicle headlights, etc.).

[0075] Equation (1) shows the current i through the diode 50 diode and the current i pe , i bp and i bn relationship. Here, i bn is the bypass current generated by the bypass transistor 104. The voltage value V nbias (and the bypass current i bn ) is typically selected to set the current i diode , the current i diode equal to i pe minus any dark current and DC background photocurrent.

[0076] Equations (2)-(3) show the voltage V at node 52 p and the current i through the logarithmic signal circuit 38 diode relationship, where K = 1.3806×10 -23 J / K is the Boltzmann constant, T is the absolute temperature (in K), q = 1.602×10 -19 C is the charge of an electron, I s represents the reverse saturation current of the diode 50 (in A), and the operator ln is the natural logarithm operator of the logarithm to the base of the mathematical constant e. Thus, as shown in Equation (3), the voltage V p can have a logarithmic relationship with the current i diode that provides a high dynamic range. Equation (4) defines the mutual impedance r of the receiver circuit 281 m as the dynamic resistance of the diode 50 at the operating point defined by the current i diode . As shown in Equation (4), the mutual impedance r of the receiver circuit 281 m increases as the current i diode decreases. Therefore, in order to keep i diode small and thus r m large, it is important to offset the common-gate bias current i with the bypass current i bn bp ​。Having a large mutual impedance r m is beneficial for detecting small photocurrent pulses.

[0077]

[0078] Figure 7 Shows another example of a receiver circuit including a servo loop circuit - receiver circuit 282. Some aspects of receiver circuit 282 can be the same as those shown in Figure 6 those shown therein.

[0079] Figure 7 Shows buffer circuit 120 and a servo loop circuit 112 connected to receiver circuit 28 shown in Figure 6 Figure. Buffer circuit 120 can include any suitable buffer amplifier. Buffer circuit 120 has an input 121 and an output 123. In the embodiment shown in the figure, it is similar to buffer circuit 32. In this example, buffer circuit 120 is connected between node 52 and node 125 (voltage V p ).

[0080] Servo loop circuit 112 includes an amplifier 114, which can be an operational amplifier, having a reference input 118 provided by voltage V ref , a feedback input 116 connected to node 125, and an output 119 (control voltage V nbias ) connected to the first terminal 106 of bypass transistor 104.

[0081] Thus, in operation, servo loop circuit 112 controls the current i bn of current bypass circuit 86. When the reference voltage V ref is provided to input 118 and the voltage at node 125 (V p ) is fed back into amplifier 114, a control voltage V bn that generates the control bypass current i nbias at amplifier output 119 is produced. The net effect of servo loop circuit 112 is to keep the DC part of voltage V p equal to voltage V ref . This DC bias level can be maintained regardless of the dark current of photosensitive element 40 and / or any DC background photocurrent detected by sensor 14. Servo loop circuit 112 acts as a low-pass filter with a 3 dB corner frequency (usually below 1 MHz). The selection of the 3 dB corner frequency is chosen to avoid any interaction with the high-frequency content of the return pulses.

[0082] Figure 8Another example of a receiver circuit (receiver circuit 283) is shown, which includes a logarithmic signal circuit 38 and two other signal circuits: a linear signal circuit 126 and a square root signal circuit 128. As discussed above with respect to the logarithmic signal circuit 38, the linear and square root signal circuits 126, 128 describe the voltage response characteristics of the receiver circuit 28 to the photocurrent from the detected return pulse. For example, when voltage is plotted relative to photocurrent, the linear signal circuit 126 produces a linear curve; similarly, when voltage is plotted relative to the input photocurrent, the square root signal circuit 128 produces a square root curve. Some aspects of the receiver circuit 283 may be the same as those shown in the previous example.

[0083] In Figure 8 the photosensitive input circuit 36 and the logarithmic signal circuit 38 are shown connected to node 52. In at least one example, the diode 50 of the logarithmic signal circuit 38 is coupled between node 52 and a predetermined voltage V clamp instead of between node 52 and ground as in the previous example.

[0084] The linear signal circuit 126 may include a resistor 130 that can be coupled between node 52 and ground. The value of the resistor is typically in the range of 10K to 200K Ohm.

[0085] The square root signal circuit 128 is a p-channel MOSFET 132, which includes a first terminal 134, a second terminal 136, and a third terminal 138 (gate, drain, and source, respectively). The first terminal 134 is connected to a computer 16 having an output DAC that provides a threshold voltage (V knee ). The second terminal 136 is connected to node 52, and the third terminal 138 is connected to a constant potential, such as ground.

[0086] The following is an example of the operation of the receiver circuit 283. As described above, the logarithmic signal circuit 38, the linear signal circuit 126, and the square root signal circuit 128 can produce electrical signals (at node 52) characterized by a logarithmic distribution, a linear distribution, and a square root distribution, respectively. More specifically, the receiver circuit 283 can be designed such that the photocurrent mainly flows through one of the circuits 38, 126, 128 according to the input signal level. Figure 9A The simulated amplitude of the voltage pulse at node 52 (V p ) is plotted as a function of the amplitude of the photocurrent pulse generated by the photosensitive element 40. This is obtained using the Figure 12 receiver circuit 286. Regions 920, 930, and 940 are the linear, square root, and logarithmic regions, respectively. It should be noted that this is a semi-logarithmic graph, where the x-axis is logarithmic but the y-axis is linear; this explains why the linear region 920 does not appear linear visually.

[0087] The current can flow through one of three circuits 38, 126, 128 based on the magnitude of the current (i pe ). For example, when the current (i pe ) is less than a first threshold, it mainly flows through the linear signal circuit 126 (see region 920, Figure 9A ). When the current (i pe ) is greater than the first threshold and less than a second threshold, it mainly flows through the square root signal circuit 128 (see region 930, Figure 9A ). And when the current (i pe ) is greater than the second threshold, it mainly flows through the logarithmic signal circuit 38 (see region 940, Figure 9A ). For the linear region 920, the voltage V p is less than V knee , for the square root region 930, the voltage V p is between V knee and V clamp , and for the logarithmic region 940, the voltage V p is greater than V clamp . In other words, the voltage V knee controls the first threshold, and the voltage V clamp controls the second threshold. Thus, the voltage V p pulse amplitude as a function of the photocurrent pulse amplitude has: a substantially linear distribution when the current i pe level is at a low level (region 920); a substantially square root distribution when the current i pe level is in an intermediate range (region 930); and, a substantially logarithmic distribution when the current i pe level is in a higher range (region 940). By having three regions 920, 930, 940, the receiver circuit 283 achieves voltage compression and thus a high dynamic range.

[0088] Figure 9B shows a graph of a plurality of curves 950 with analog return pulses, the graph being of the voltage V p (with the DC component removed) versus time in nanoseconds, and the curve being the electrical signal processed by the Figure 12 receiver circuit 286. The curve is for photocurrent pulse amplitudes from 100 nA to 10 mA. Depending on the amplitude of the photocurrent, the return pulse may have passed through any one, two, or all three of the linear signal distribution, square root signal distribution, or logarithmic signal distribution regions. As can be seen from the curve, the shape of the voltage pulse is substantially consistent and the voltage pulse amplitude is not saturated. Thus, the curve 950 is intended to illustrate that consistent-shaped and non-saturated voltage pulses can be generated over a wide range of input photocurrent signal amplitudes.

[0089] There are also other examples of receiver circuits that can produce a similar curve. For example, according to another example, the diode 50 can be the source-to-body PN junction of a p-channel MOSFET transistor (132). Such a configuration can produce results similar to those shown in Figures 9A - 9B those shown.

[0090] Figure 10 Yet another example of a receiver circuit (receiver circuit 284) is shown, which includes a linear signal circuit 126, a square root signal circuit 128, and a logarithmic signal circuit 38' combined with an impedance reduction circuit 84. Some aspects of receiver circuit 284 can be the same as those shown in the previous examples.

[0091] More specifically, the impedance reduction circuit 84 can be connected to the photosensitive input circuit 36 in the same manner as Figure 6 (receiver circuit 281). Additionally, the linear signal circuit 126 and the square root signal circuit 128 can be connected to node 52 in the same manner as Figure 8 (receiver circuit 283). The logarithmic signal circuit 38' can be coupled to node 47 (indirectly coupled to node 52); more specifically, it can be connected between node 47 and voltage (V clamp ). Receiver circuit 284 may also include Figure 10 some parasitic capacitance represented as capacitor 140 connected between node 52 and ground. The capacitance value of capacitor 140 is typically much smaller than the capacitance value of the photodiode built-in capacitance 42 (e.g., 1 / 10 as small).

[0092] The following is a non-limiting example of the operation of receiver circuit 284. For current i within the linear region 920 pe , current i pe produces a voltage V pe that grows substantially linearly with i p . The shape of the voltage pulse at V p and the transfer impedance of receiver circuit 284 are mainly determined by resistor 130 and capacitor 140.

[0093] For current i within the square root region 930 pe , voltage V p is greater than voltage V knee , transistor 132 turns on and conducts most of current i pe , resulting in a square root distribution, as described above. The shape of the voltage pulse at V p and the transfer impedance of receiver circuit 284 are mainly determined by the drain-to-source resistance of transistor 132 and capacitor 140.

[0094] For the current i within the logarithmic region 940 pe , the voltage at node 47 is greater than the voltage V clamp , and diode 50 becomes forward-biased and conducts most of the current i pe . As a result, the voltage at node 47 grows logarithmically with the current i pe . In the logarithmic region 940, the voltage V p at node 52 is substantially equal to the voltage at node 47 because transistor 88 operates in the triode region. Thus, in this region, the voltage pulse amplitude of V p has a substantially logarithmic distribution with respect to the current i pe . The shape of the voltage pulse at V p and the mutual impedance of the receiver circuit 284 are mainly determined by the resistance of diode 50 and the capacitance at node 47. The latter is typically controlled by the built-in capacitance 42 of the photodiode. The fact that the logarithmic signal circuit 38' is directly coupled to node 47 rather than node 52 has the following advantages: the mutual impedance in the logarithmic region 940 is not limited by the source impedance of transistor 88, and the receiver circuit 284 is more resistant to latch-up because large photocurrent pulses i pe in the logarithmic region 940 are directly shunted to V clamp .

[0095] Figure 11 shows another example of a receiver circuit (receiver circuit 285), which includes the receiver circuit 284 plus an AC test circuit 144 (i.e., a current pulse injection circuit 144) and / or a DC test circuit 146. Some aspects of the receiver circuit 285 may be the same as those shown in the previous example.

[0096] The AC test circuit 144 generally includes a transistor 148 (e.g., a p-channel MOSFET) and a switch 156. The transistor 148 has a first terminal 150, a second terminal 152, and a third terminal 154 (gate, source, and drain, respectively). The first terminal 150 is connected to the DAC output of the computer 16, which provides a bias voltage (V pbias-pulse ) to activate the transistor 148. The second terminal 152 is connected to a voltage source (e.g., 2.5V), and the third terminal 154 is connected to the switch 156. The switch 156 is connected between the third terminal 154 and node 47. Thus, when the switch 156 is activated to the closed position by a control signal (en_actest) through the input 158, the third terminal 154 is connected to node 47.

[0097] In the operation of the AC test circuit 144, the computer 16 activates the switch 156 to the closed position and provides the voltage V pbias_pulse。The duration of switch 156 in the closed position can simulate the width of the photocurrent pulse, and the amplitude of the simulated photocurrent pulse can be determined by the current generated by transistor 148 when biased with voltage V pbias_pulse The current pulse injection circuit 144 is adapted to provide a test of the functionality or performance of the receiver circuit 285.

[0098] The DC test circuit 146 includes a pair of switches 164, 160. Switch 164 is connected between the terminal (node 163) of resistor 130 and ground. Switch 160 is connected between node 163 and the first terminal 134 of transistor 132 (of the square root signal circuit 128). During normal operation of the receiver circuit 285, switch 164 is closed while switch 160 is open. During DC testing, switch 164 is actuated to the open position via input 168 by a control signal (~en_dctest, where "~" represents logical NOT), and switch 160 is actuated to the closed position via input 162 by a control signal (en_dctest).

[0099] According to at least one example, during DC testing, the computer 16 can turn off the common-gate transistor 88 by providing a voltage (V cg ) equal to the supply voltage at terminal 90. At the same time, the computer 16 can provide control signals to inputs 162, 168 to open switch 164 and close switch 160. In this state, the computer 16 can perform a scan of the bias voltage V knee at terminal 134 to test the functionality, DC offset, gain, and voltage range of the analog signal chain downstream of the receiver circuit 285. As Figure 2 shown, the analog signal chain can include a filter circuit 30, a buffer circuit 32, and an analog memory circuit 34.

[0100] Figure 12 A receiver circuit 286 is shown, which includes a receiver circuit (e.g., such as the receiver circuit 284 shown in Figure 10 ) coupled to a servo loop circuit 170. Figure 12 The schematic diagram shown in

[0101] also shows the receiver circuit 286 coupled to the filter circuit 30, buffer circuit 32, and analog memory circuit 34 as described above. The servo loop circuit 170 includes an amplifier 171, a switch 172, and a switch 173 that control the bias current of the impedance reduction circuit 84. Some aspects of the receiver circuit 286 may be the same as those shown in the previous examples. ref), a feedback input 175 coupled to node 77 (the output of buffer circuit 32) and an output 176 coupled to node 177 via switch 172. Switch 172 is connected between output 176 and the first terminal 98 of bias transistor 96. When a control signal (∼pd_servo, where "∼" represents logical NOT) is provided through input 178 of switch 172, switch 172 moves from a closed position to an open position.

[0102] Switch 173 is connected between node 177 and an input 179 that provides voltage V pbias as described above. When the control signal (pd_servo) is provided to input 180 of switch 173, switch 173 moves from a closed position to an open position.

[0103] Thus, when the servo loop is disabled or powered off (the control signal pd_servo is set to logical high), switch 172 is in the open position, switch 173 is in the closed position, and voltage V pbias is provided to the first terminal 98 of bias transistor 96, thereby establishing a DC bias current i bp . When the servo loop is enabled (the control signal pd_servo is set to logical low), switch 172 is in the closed position, switch 173 is in the open position, and the output of amplifier 171 is connected to the first terminal 98 of bias transistor 96. Other aspects of the operation can be similar to those described above with reference to the servo loop circuit shown in receiver circuit 282 ( Figure 7 ). For example, the output 176 of amplifier 171 adjusts the DC bias current i bp of transistor 96, thereby changing the DC voltage at node 52 and thus the DC voltage at node 77 until the latter becomes equal to the reference voltage V ref .

[0104] In Figure 12 the embodiment shown, the bandwidth of servo loop circuit 170 can be low enough such that servo loop circuit 170 is relatively insensitive to voltage pulses generated by the return pulses (e.g., insensitive to photocurrent pulses i pe of the photosensitive input circuit 36). The servo loop including amplifier 171 and the feedback connection to node 77 is designed to establish a DC voltage level equal to the reference voltage V ref at node 77 regardless of the DC background photocurrent and / or dark current of the photosensitive input circuit 36.

[0105] Figure 13Shows another example of a receiver circuit (receiver circuit 287), which includes a receiver circuit connected to a noise suppression circuit 182 (also known as a static gate decoupling circuit). Some aspects of receiver circuit 287 may be the same as those shown in the previous example.

[0106] The noise suppression circuit 182 includes a capacitor 184 and a resistor 186 connected to a reference voltage source 188 (V cg ). The capacitor 184 is coupled between node 187 and node 189. Node 187 is the input 44 of the detector voltage source V det and the photosensitive input circuit 36. Node 189 is at the first terminal 90 of the common-gate transistor 88. The resistor 186 is connected between node 189 and the reference voltage source 188. The reference voltage source 188 is connected between the resistor 186 and ground. The resistor 186 may represent a physical resistor. Alternatively, the resistor 186 may represent the output impedance of an amplifier that generates the reference voltage V cg .

[0107] The capacitor 184 is adapted to suppress the common-mode noise on the detector voltage source such that, in operation, the noise suppression circuit 182 couples the voltage perturbation on the detector voltage source V det to the first terminal 90 of the common-gate transistor 88 via the capacitor 184. Since the V det voltage perturbation is also coupled to the second terminal 92 of the common-gate transistor 88 via the photodiode intrinsic capacitance 42, the net effect is that the drain current of the common-gate transistor 88 and thus the voltage V p at node 52 are largely unaffected by the V det voltage perturbation. A decrease in the detector voltage source at node 187 can be caused by a current i pe surge due to the photosensitive input circuit 36 receiving a return pulse, or due to any number of adjacent pixels receiving strong return pulses. The product of the resistance of the resistor 186 and the capacitance of the capacitor 184 establishes a time constant. In a preferred embodiment, this time constant is much longer than the width of the V det voltage drop.

[0108] Figure 14 Shows another example of a receiver circuit (receiver circuit 288), which includes a receiver circuit having a noise suppression circuit 182' (also known as a dynamic gate decoupling circuit). In Figure 14 the embodiment shown, the receiver circuit 288 may be the same as the receiver circuit 287 except that a switch 192 replaces the resistor 186. Aspects of the receiver circuit 288 that are the same as the previous example will not be explained again.

[0109] The computer 16 controls the switch 192 to move from the open position to the closed position through a control signal. Energizing the switch 192 to the closed position resets the noise suppression circuit 182' by setting the voltage at the first terminal 90 of the common-gate transistor 88 to a reference voltage V cg For example, this can occur before emitting a laser pulse or when the computer 16 anticipates no input return pulse.

[0110] A sensor is described that includes a transmitter and a receiver. The receiver can include one or more pixels. At least one pixel includes a receiver circuit that at least includes a photosensitive input circuit and a logarithmic signal circuit. Various examples of receiver circuits that can improve sensor performance have been described.

[0111] Regarding the processes, systems, methods, etc. described herein, it should be understood that although the steps of such processes, etc. have been described as occurring in a specific order, such processes can be implemented with the described steps executed in an order different from that described herein. It should also be understood that certain steps can be performed simultaneously, other steps can be added, or certain steps described herein can be omitted. In other words, the description of the processes herein is provided for the purpose of illustrating certain embodiments and should in no way be construed as limiting the claims.

[0112] Accordingly, it should be understood that the above description is intended to be illustrative and not restrictive. After reading the above description, many embodiments and applications other than the provided examples should be apparent. The scope should not be determined with reference to the above description, but rather with reference to the appended claims and the full scope of the equivalents given by these claims. It is expected and anticipated that developments will occur in the technologies discussed herein in the future, and the disclosed systems and methods will be incorporated into such future embodiments. In summary, it should be understood that this application is capable of modification and variation.

Claims

1. A light detection and ranging LIDAR sensor (14), comprising: A light pulse emitter (22); And A light receiver (24), wherein the receiver (24) comprises: A plurality of pixels (26), wherein each pixel (26) comprises a receiver circuit (28), and each receiver circuit (28) comprises: A photosensitive input circuit (36) having at least two terminals (44, 46), wherein a first terminal (46) is coupled to a detector voltage source, and a second terminal (46) is coupled to a pulse voltage node; A logarithmic signal circuit (38) comprising at least one PN junction (50), wherein a P-type terminal is coupled to the pulse voltage node, and an N-type terminal (53) is coupled to a constant potential; and An impedance reduction circuit (84) electrically coupled to the photosensitive input circuit (36) and the logarithmic signal circuit (38), the impedance reduction circuit (84) at least comprising a common-gate transistor (88) coupled to the pulse voltage node, Wherein the impedance reduction circuit (84) comprises a bias transistor (96), and the bias transistor (96) supplies a DC bias current to the common-gate transistor (88).

2. The LIDAR sensor (14) according to claim 1, further comprising a common-mode noise suppression circuit (182), the common-mode noise suppression circuit comprising a capacitor (184) coupled between a gate (90) of the common-gate transistor (88) and the detector voltage source (188) and adapted to suppress common-mode noise on the detector voltage source (188).

3. The LIDAR sensor (14) according to claim 2, wherein, The common-mode noise suppression circuit (182) further comprises a selectively actuated switch (192) coupled between the gate (90) of the common-gate transistor (88) and a reference voltage, wherein when no photocurrent pulse is expected, the switch (192) is in a closed position, and wherein when a photocurrent pulse is expected, the switch (192) is in an open position.

4. The LIDAR sensor (14) according to claim 1 further includes a bypass circuit (86), the bypass circuit being electrically coupled to the logarithmic signal circuit (38) and including at least a bypass transistor (104), the bypass transistor (104) having a terminal coupled to the pulsed voltage node, wherein, The bypass circuit (86) is adapted to reduce the bias current delivered to the logarithmic signal circuit (38).

5. The LIDAR sensor (14) according to claim 4, further comprising: A servo loop circuit (112) comprising an amplifier (114) having a first input (116) and a second input (118) and an output (119), wherein the first input (116) is coupled to the pulse voltage node, the second input (118) is a reference voltage, and the output (119) of the amplifier (114) is coupled to a gate (98) of the bypass transistor (104) of the bypass circuit (86) and is adapted to control the current at the logarithmic signal circuit (38).

6. The LIDAR sensor (14) according to claim 1, further comprising: A servo loop circuit (170) includes an amplifier (171) having a first input (174), a second input (175), and an output (176), wherein the first input (175) is coupled to the pulse voltage node, the second input (174) is a reference voltage, and the output (176) of the amplifier (171) is coupled to the gate (98) of the bias transistor (96) of the impedance reduction circuit (84).

7. The LIDAR sensor (14) according to claim 1, further comprising: A linear signal circuit (126) includes a resistor (130) coupled between the pulse voltage node and a constant potential; And A square root signal circuit (128) includes a transistor (132), and the transistor (132) includes a first terminal (136) coupled to the pulse voltage node and a second terminal (138) coupled to a constant potential.

8. The LIDAR sensor (14) according to claim 7, wherein, The source of the transistor of the square root signal circuit is coupled to the pulse voltage node, the drain of the transistor is coupled to a constant potential, and the gate of the transistor is coupled to a control voltage.

9. The LIDAR sensor (14) according to claim 7, wherein, The photocurrent mainly: when the photocurrent is less than a first threshold, it flows through the linear signal circuit; when the photocurrent is greater than the first threshold and less than a second threshold, it flows through the square root signal circuit; and when the photocurrent is greater than the second threshold, it flows through the logarithmic signal circuit.

10. The LIDAR sensor (14) according to claim 1, further comprising: An analog memory circuit (34) coupled to the pulse voltage node, wherein the analog memory circuit includes a plurality of sequentially selected capacitor circuits that store voltage samples of the return pulses received by the photosensitive input circuit, and each of the plurality of sequentially selected capacitor circuits is readable by a computer.

11. The LIDAR sensor (14) according to claim 1, further comprising an adjustable low-pass filter circuit (30) coupled to the pulsed voltage node, wherein, The bandwidth of the filter circuit is adjusted by computer control output.

12. The LIDAR sensor (14) according to claim 11, wherein, The bandwidth of the filter circuit is changed by adjusting the resistance value.

13. The LIDAR sensor (14) according to claim 1, further comprising: A computer, the computer includes a digital processor and a digital memory storing instructions, and the instructions are executable by the digital processor to: Determine the range associated with the return pulse by the following steps: Select and energize each of a plurality of capacitor circuits, wherein the plurality of capacitor circuits are coupled to the photosensitive input circuit via the pulse voltage node; and wherein the energization includes moving a switch from an open position to a closed position and then back to the open position; and After that, read the voltage stored in each capacitor circuit.

14. A light detection and ranging LIDAR sensor, comprising: A light pulse emitter; And A light receiver, wherein the receiver includes: A plurality of pixels, and each pixel includes a receiver circuit, and each receiver circuit includes: A photosensitive input circuit having at least two terminals, wherein the first terminal is coupled to a detector voltage source and the second terminal is coupled to the pulse voltage node; A logarithmic signal circuit includes at least one PN junction, wherein the P-type terminal is coupled to the pulse voltage node, and the N-type terminal is coupled to a constant potential; A linear signal circuit, comprising a resistor coupled between the pulsed voltage node and a constant potential; and A square root signal circuit, comprising a transistor having a first terminal coupled to the pulsed voltage node and a second terminal coupled to a constant potential.

15. An optical detection and ranging LIDAR sensor (14), comprising: An optical pulse emitter; And An optical receiver, wherein the receiver comprises: A plurality of pixels, wherein each pixel comprises a receiver circuit, and each receiver circuit comprises: A photosensitive input circuit having at least two terminals, one of which is coupled to a detector voltage source and the other is coupled to a pulsed voltage node; A logarithmic signal circuit comprising a PN junction, wherein the P-type terminal is coupled to the pulsed voltage node and the N-type terminal is coupled to a constant potential; A linear signal circuit comprising a resistor coupled between the pulsed voltage node and a constant potential; A square root signal circuit, comprising a transistor having a first terminal coupled to the pulsed voltage node and a second terminal coupled to a constant potential; and An impedance reduction circuit coupled to the photosensitive input circuit, the linear signal circuit, the square root signal circuit, and the logarithmic signal circuit, wherein the impedance reduction circuit comprises a common-gate transistor coupled to the pulsed voltage node and a bias transistor that provides a DC bias current to the common-gate transistor.

16. The LIDAR sensor (14) according to claim 15, further comprising a common-mode noise suppression circuit, the common-mode noise suppression circuit comprising a capacitor coupled between the gate of the common-gate transistor and the detector voltage source and adapted to suppress common-mode noise on the detector voltage source.

17. The LIDAR sensor (14) according to claim 15, further comprising a servo loop circuit, the servo loop circuit comprising an amplifier having first and second inputs and an output, wherein, A first amplifier input is coupled to the pulsed voltage node, a second amplifier input is a reference voltage, and an amplifier output is coupled to the gate of the bias transistor of the impedance reduction circuit.

18. The LIDAR sensor (14) according to claim 15, further comprising a current pulse injection circuit coupled to the pulsed voltage node, wherein, The current pulse injection circuit is adapted to provide a test of functionality or performance.

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