Optical sensor array substrate and optical fingerprint collector

Abstract

An optical sensor array substrate (30) and an optical fingerprint collector. The optical sensor array substrate (30) comprises a substrate (31), the substrate (31) comprising a detection area (30A) and a peripheral area (30R) surrounding the detection area (30A), wherein the detection area (30A) comprises a plurality of photosensitive pixels (30a), at least one of the plurality of photosensitive pixels (30a) comprising: a thin film transistor (32) disposed on the substrate (31) and having a gate (32a), an active layer (32b), a source (32c) and a drain (32d); a storage capacitor (33) disposed on the substrate (31) and having a first capacitor plate (33a) and a second capacitor plate (33b), the second capacitor plate (33b) being located on a side of the first capacitor plate (33a) away from the substrate (31) and electrically connected with the source (32c) or the drain (32d) of the thin film transistor (32); a photosensitive element (39) located on a side of the storage capacitor (33) away from the substrate (31) and electrically connected with one end of the second capacitor plate (33b); and a first electrode layer (36a) located on a side of the photosensitive element (39) away from the substrate (31) and electrically connected with the other end of the photosensitive element (39), wherein a normal projection of the second capacitor plate (33b) on the substrate (31) at least partially overlaps with a normal projection of the first electrode layer (36a) on the substrate (31).

Description

Technical Field

[0001] This disclosure relates to the field of sensors, and more particularly to an optical sensor array substrate and an optical fingerprint collector. Background Technology

[0002] Based on the uniqueness of fingerprints, fingerprint imaging recognition technology is widely used in fingerprint acquisition, mobile phone fingerprint locks, and other fields. For optical fingerprint scanners, the optical sensor is the key component for fingerprint acquisition, which converts the light signal reflected from the finger surface into an electrical signal to achieve fingerprint acquisition. Summary of the Invention

[0003] In one aspect of this disclosure, an optical sensor array substrate is provided, including a substrate, the substrate including a detection region and a peripheral region surrounding the detection region, wherein the detection region includes a plurality of photosensitive pixels, at least one of the plurality of photosensitive pixels including:

[0004] A thin-film transistor is disposed on the substrate and has a gate, an active layer, a source, and a drain.

[0005] A storage capacitor is disposed on the substrate and has a first capacitor plate and a second capacitor plate, wherein the second capacitor plate is located on the side of the first capacitor plate away from the substrate and is electrically connected to the source or drain of the thin film transistor.

[0006] A photosensitive element is located on the side of the storage capacitor away from the substrate, and one end is electrically connected to the second capacitor plate;

[0007] The first electrode layer is located on the side of the photosensitive element away from the substrate and is electrically connected to the other end of the photosensitive element.

[0008] Wherein, the orthographic projection of the second capacitor plate on the substrate at least partially overlaps with the orthographic projection of the first electrode layer on the substrate.

[0009] In some embodiments, the first capacitor plate is located on the same layer as the gate of the thin-film transistor and is made of the same material, and the second capacitor plate is located on the same layer as the source and drain of the thin-film transistor and is made of the same material.

[0010] In some embodiments, the first capacitor plate and the gate of the thin-film transistor are located on the same layer and made of the same material, and the second capacitor plate and the source and drain of the thin-film transistor are located on different layers.

[0011] In some embodiments, the orthographic projection of the photosensitive element onto the substrate lies within the orthographic projections of the second capacitor plate and the first capacitor plate onto the substrate.

[0012] In some embodiments, the photosensitive pixel includes:

[0013] The readout data line extending along the first direction is located on the same layer as and connected to the source of the thin-film transistor; and

[0014] A gate line extending along a second direction is located on the same layer as and connected to the gate of the thin-film transistor, and the second direction is perpendicular to the first direction;

[0015] Wherein, one end of the source of the thin-film transistor is connected to the readout data line, and the other end extends along the second direction relative to the readout data line;

[0016] The drain of the thin-film transistor is L-shaped and has a first part, a second part, and a bend portion connecting the first part and the second part. The first part extends in the opposite direction to the first direction relative to the bend portion, and the second part extends in the opposite direction to the second direction relative to the bend portion.

[0017] One end of the gate of the thin-film transistor is connected to the gate line, and the other end extends along the first direction relative to the gate line.

[0018] The orthographic projection of the gate of the thin-film transistor onto the substrate partially coincides with the orthographic projections of the drain and source of the thin-film transistor onto the substrate.

[0019] In some embodiments, at least one of the plurality of photosensitive pixels further includes:

[0020] A first light-shielding metal layer is located on the side of the thin-film transistor and the photosensitive element away from the substrate.

[0021] Wherein, the orthographic projection of the first light-shielding metal layer on the substrate at least partially overlaps with the orthographic projection of the thin-film transistor on the substrate, and the orthographic projection of the first light-shielding metal layer on the substrate does not overlap with the orthographic projection of the photosensitive element on the substrate.

[0022] In some embodiments, the peripheral region has a dummy region located on at least one side of the detection region; the dummy region includes a plurality of dummy pixels, at least one of the plurality of dummy pixels including: the thin film transistor, the storage capacitor, the photosensitive element, the first electrode layer and the second light-shielding metal layer, the second light-shielding metal layer being located on the side of the thin film transistor and the photosensitive element away from the substrate, and the orthographic projection of the thin film transistor and the photosensitive element onto the substrate being located within the orthographic projection of the second light-shielding metal layer onto the substrate.

[0023] In some embodiments, each of the plurality of dummy pixels includes the second light-shielding metal layer, and the second light-shielding metal layer of the plurality of dummy pixels covers the dummy area entirely.

[0024] In some embodiments, at least one of the plurality of dummy pixels and the plurality of photosensitive pixels includes:

[0025] A gate insulating layer is located on the side of the substrate adjacent to the active layer of the thin-film transistor and covers the gate of the thin-film transistor;

[0026] The first passivation layer is located on the side of the source and drain of the thin-film transistor away from the substrate, and covers the source and drain of the thin-film transistor;

[0027] A planarization layer is located on the side of the first passivation layer away from the substrate;

[0028] The second passivation layer is located on the side of the planarization layer away from the substrate.

[0029] The source and drain of the thin-film transistor are located on the surface of the gate insulating layer away from the substrate. The photosensitive element is located in the planarization layer and is electrically connected to the second capacitor plate through a via penetrating the first passivation layer. The first electrode layer is electrically connected to the photosensitive element.

[0030] In some embodiments, at least one of the plurality of dummy pixels and the plurality of photosensitive pixels includes:

[0031] The second electrode layer is electrically connected to the bias voltage signal terminal, located on the side of the second passivation layer away from the substrate, and is electrically connected to the first electrode layer through a via penetrating the second passivation layer and the planarization layer.

[0032] In some embodiments, the plurality of photosensitive pixels and the plurality of dummy pixels are arranged in multiple rows and multiple columns according to the row direction and column direction of the array, and each column of photosensitive pixels and each column of dummy pixels includes a readout data line extending continuously along the column direction and a gate line extending continuously along the row direction.

[0033] In this configuration, the second electrode layers of each column of photosensitive pixels are sequentially connected along the column direction to form a complete second electrode layer. The orthographic projection of the complete second electrode layer onto the substrate coincides with the orthographic projection of each column of photosensitive pixels onto the substrate, but does not coincide with part or all of the readout data lines of each column of photosensitive pixels; and / or

[0034] The second electrode layers of each column of dummy pixels are sequentially connected along the column direction to form a whole second electrode layer. The orthographic projection of the whole second electrode layer on the substrate coincides with the orthographic projection of each column of dummy pixels on the substrate, and does not coincide with part or all of the readout data lines of each column of dummy pixels.

[0035] In some embodiments, at least one of the plurality of dummy pixels and the plurality of photosensitive pixels includes:

[0036] The third passivation layer is located on the side of the second passivation layer away from the substrate;

[0037] An electrostatic shielding layer is located on the side of the third passivation layer away from the substrate.

[0038] In some embodiments, the optical sensor array substrate further includes:

[0039] The electrostatic discharge area is located on the side of the dummy area away from the detection area and has multiple electrostatic discharge units.

[0040] The plurality of photosensitive pixels and the plurality of dummy pixels are arranged in multiple rows and columns according to the row and column directions of the array. The plurality of electrostatic discharge units are arranged in the column direction and correspond one-to-one with the photosensitive pixels and dummy pixels in the multiple rows.

[0041] In some embodiments, at least one of the plurality of electrostatic discharge units includes:

[0042] The first transistor has a gate, a source, and a drain;

[0043] The second transistor has a gate, a source, and a drain.

[0044] In this configuration, the gate of the first transistor is electrically connected to the drain of the first transistor and is configured to connect to the gate signal output terminal of the gate circuit. The drain of the second transistor is electrically connected to the source of the first transistor. Both the gate and the source of the second transistor are configured to connect to a first voltage terminal, and the voltage of the first voltage terminal is lower than the gate signal voltage of the gate signal output terminal.

[0045] In some embodiments, the peripheral region includes a dummy region located on at least one side of the detection region; the dummy region includes a plurality of dummy pixels, at least one of the plurality of dummy pixels including: the thin film transistor, the storage capacitor and the second light-shielding metal layer, the second light-shielding metal layer being located on the side of the thin film transistor away from the substrate, and the orthographic projection of the thin film transistor on the substrate being located within the orthographic projection of the second light-shielding metal layer on the substrate.

[0046] In some embodiments, the peripheral region includes a dummy region located on at least one side of the detection region; the dummy region includes a plurality of dummy pixels, at least one of the plurality of dummy pixels including: the thin film transistor, the storage capacitor, a second light-shielding metal layer and a dummy element, the dummy element including a material having the same dielectric constant as the photosensitive element but not having photosensitive properties, the second light-shielding metal layer being located on the side of the thin film transistor away from the substrate, and the orthographic projection of the thin film transistor on the substrate being located within the orthographic projection of the second light-shielding metal layer on the substrate.

[0047] In some embodiments, the peripheral region includes a dummy region located on at least one side of the detection region; the dummy region includes a plurality of dummy pixels, at least one of the plurality of dummy pixels including: the thin film transistor, the storage capacitor and a dummy element, the dummy element comprising a material having the same dielectric constant as the photosensitive element but not possessing photosensitive properties.

[0048] In some embodiments, the peripheral region includes a junction region located on at least one side of the detection region; the junction region includes:

[0049] Multiple first fan-out metal structures are electrically connected to the readout data lines of each column of photosensitive pixels and dummy pixels;

[0050] Multiple second fan-out metal structures are electrically connected to the gate lines of each row of photosensitive pixels and dummy pixels.

[0051] In some embodiments, at least one of the plurality of first fan-out metal structures and the plurality of second fan-out metal structures includes a bimetallic layer; the bimetallic layer includes:

[0052] The first metal layer is located in the same layer as the readout data line and is made of the same material.

[0053] The second metal layer is located on the same layer as the gate line and is made of the same material, and is electrically connected to the first metal layer through a via penetrating the gate insulating layer.

[0054] In another aspect of this disclosure, an optical fingerprint scanner is provided, comprising:

[0055] Backlight module;

[0056] The aforementioned optical sensor array substrate is located on the light-emitting side of the backlight module;

[0057] The driving circuit board is electrically connected to the backlight module and signal-connected to the optical sensor array substrate.

[0058] In some embodiments, the optical fingerprint scanner further includes:

[0059] A filter layer is located on the side of the optical sensor array substrate away from the backlight module;

[0060] The material of the filter layer includes a filter material, which is configured to block light outside a preset wavelength range and transmit light within a preset wavelength range, wherein the preset wavelength range is 450 to 500 nm.

[0061] In some embodiments, the optical fingerprint scanner further includes:

[0062] A rigid coating is located on the side of the filter layer away from the backlight module.

[0063] The hard cladding layer is made of SiO2 and Si3C4, forming a periodic stacked structure with alternating layers of the two materials.

[0064] In some embodiments, the optical fingerprint scanner further includes:

[0065] The anti-fingerprint layer is located on the side of the hard coating away from the backlight module.

[0066] In some embodiments, the backlight module includes:

[0067] Back panel;

[0068] A light guide plate is located on the side of the back plate adjacent to the optical sensor array substrate;

[0069] A reverse prism is located on the surface of the light guide plate on the side away from the back plate;

[0070] A privacy screen protector is located on the surface of the privacy screen protector away from the back panel.

[0071] In some embodiments, the optical fingerprint scanner further includes:

[0072] Two sets of readout circuits are located on the first and second sides of the optical sensor array substrate and are electrically connected to the driving circuit board. The first side is opposite to the second side.

[0073] The optical sensor array substrate has two dummy regions located on the third and fourth sides of the detection region. The third side is opposite to the fourth side, and both the third and fourth sides are adjacent to the first and second sides.

[0074] The virtual area includes multiple virtual pixels. The multiple photosensitive pixels and the multiple virtual pixels are arranged in multiple rows and columns according to the row and column directions of the array, and are divided into multiple pixel groups according to the columns.

[0075] Each readout circuit group includes multiple readout circuits. The pins of all readout circuits in the two groups are electrically connected to multiple pixel groups one-to-one through a first fan-out metal structure. All readout circuits in the two groups are staggered in the row direction.

[0076] In some embodiments, the optical fingerprint scanner further includes:

[0077] Two gate circuits are located on the third side of the optical sensor array substrate and are electrically connected to the plurality of photosensitive pixels and the plurality of dummy pixels through a second fan-out metal structure.

[0078] A flexible circuit board is located on the third side of the optical sensor array substrate, between the two gate circuits. The pins of the flexible circuit board are electrically connected to the pins of the two gate circuits via metal traces, and are also electrically connected to the driving circuit board.

[0079] The width of the metal trace is greater than 40 μm.

[0080] In some embodiments, the optical fingerprint scanner further includes:

[0081] A light-absorbing frame is located on the side of the optical sensor array substrate away from the backlight module, and the non-light-absorbing portion of the light-absorbing frame exposes the detection area and the two dummy areas. Attached Figure Description

[0082] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0083] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0084] Figure 1 This is a schematic diagram illustrating the structure and working principle of an embodiment of the optical fingerprint scanner according to the present disclosure;

[0085] Figure 2 This is a schematic diagram of the spectrum of sunlight passing through a finger;

[0086] Figure 3 This is a schematic diagram of the backlight module in one embodiment of the optical fingerprint scanner according to the present disclosure;

[0087] Figure 4A This is a schematic diagram of the arrangement of the detection region and the peripheral region in a substrate in one embodiment of the optical sensor array substrate disclosed herein;

[0088] Figure 4BThis is a schematic diagram of the combined structure of the optical sensor array substrate, readout circuit, gate circuit and flexible circuit board in one embodiment of the optical fingerprint collector according to the present disclosure.

[0089] Figure 5 This is a schematic diagram of the connection structure of the array substrate, readout circuit pins, gate circuit pins and flexible circuit board pins according to one embodiment of the optical sensor array substrate of this disclosure.

[0090] Figure 6 This is a schematic diagram of the electrostatic discharge circuit in one embodiment of the optical sensor array substrate according to the present disclosure;

[0091] Figure 7A and Figure 7B They are Figure 5 Schematic diagram of the structure of the detection zone and the virtual zone;

[0092] Figures 7C-7E These are schematic diagrams of the structure of the dummy region in some embodiments of the optical sensor array substrate according to this disclosure;

[0093] Figure 7F This is a schematic diagram of the detector area in another embodiment of the optical sensor array substrate according to the present disclosure;

[0094] Figure 8A and Figure 8B yes Figure 5 Schematic diagram of the coverage area of ​​the light-shielding metal layer in the detection area and the virtual area, respectively;

[0095] Figure 9 This is a schematic diagram showing the overlap of the gate, source, and drain of a TFT in one embodiment of the optical sensor array substrate disclosed herein;

[0096] Figure 10A This is a schematic diagram of the arrangement of readout data lines, source and drain of TFTs in one embodiment of the optical sensor array substrate disclosed herein;

[0097] Figure 10B This is a schematic diagram of the arrangement of gate lines and TFT gates in one embodiment of the optical sensor array substrate disclosed herein;

[0098] Figure 11 This is a schematic diagram of the arrangement of readout data lines, gate lines, and second electrode layer in an array of photosensitive pixels or dummy pixels in one embodiment of the optical sensor array substrate disclosed herein.

[0099] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0100] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0101] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "contains" mean that the element preceding the word encompasses the element listed after it, and do not exclude the possibility of encompassing other elements as well. Terms such as "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, this relative positional relationship may also change accordingly.

[0102] In this disclosure, when a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other devices without an intermediary device, or it may be not directly connected to the other devices but have an intermediary device.

[0103] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0104] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0105] In related technologies, optical fingerprint scanners need improvement in their resistance to strong light. Therefore, this disclosure provides an optical sensor array substrate and an optical fingerprint scanner that can effectively improve resistance to strong light.

[0106] Figure 1 This is a schematic diagram illustrating the structure and working principle of an embodiment of the optical fingerprint scanner according to the present disclosure. Figure 2This is a schematic diagram of the spectrum of sunlight passing through a finger.

[0107] refer to Figure 1 In some embodiments, the optical fingerprint scanner includes a driver circuit board 10, a backlight module 20, and an optical sensor array substrate 30. The driver circuit board 10 may be disposed on the side of the backlight module 20 away from the optical sensor array substrate 30 and electrically connected to the optical sensor array substrate 30 for driving the optical sensor array substrate 30. The driver circuit board 10 may also be electrically connected to the backlight module 20 for driving the backlight module 20, for example, driving the backlight module 20 to emit backlight of different intensities.

[0108] In some embodiments, the driver board 10 includes a field-programmable gate array (FPGA). In other embodiments, the driver board 10 may include a microprocessor, such as an x86 processor or an ARM processor, or a digital signal processor (DSP).

[0109] The optical sensor array substrate 30 is located on the light-emitting side of the backlight module 20. Figure 1 In the middle, the backlight module 20 is located below the optical sensor array substrate. The light L1 emitted by the backlight module 20 reaches the surface of the finger F through the light-transmitting part of the optical sensor array substrate 10. After being reflected by the valleys and ridges on the surface of the finger F, the reflected light L2 returns to the optical sensor array substrate 20 and is sensed by the photosensitive element in the optical sensor array substrate 20.

[0110] For the light rays L1 reaching the finger, a significant portion of the light is lost during reflection at the valleys, resulting in weaker reflected light L2 from the valleys. Conversely, the light rays reaching the ridges are directly reflected to the optical sensor array substrate 30, leading to stronger reflected light L2 from the ridges. The optical sensor array substrate 20 receives reflected light of varying intensities from different parts of the finger surface and performs photoelectric conversion to identify fingerprint valley and ridge information.

[0111] Considering that optical fingerprint scanners may be used in strong light environments (e.g.) Figure 1 When used in a sunlight-exposed environment (as shown), strong ambient light (such as sunlight L3) is a significant interfering factor for the backlight. Therefore, the design of an optical fingerprint scanner needs to improve its resistance to strong external light. Because blood is constantly circulating in the finger (F), the hemoglobin in the blood and the finger muscles can absorb light other than red light from the ambient light, causing the light L4 passing through the finger to be red light. However, the finger surface has a keratin layer, so the light L1 reaching the finger from the backlight does not penetrate into the finger and therefore does not convert to red light.

[0112] refer to Figure 2 Sunlight L3 encompasses the entire visible light spectrum, while the light L4 passing through the fingers is primarily visible light with wavelengths greater than 580nm (i.e., red and orange light). To overcome the interference of red light passing through the fingers on the backlight, refer to... Figure 1 In some embodiments, the optical fingerprint scanner further includes a filter layer 40 located on the side of the optical sensor array substrate 30 away from the backlight module 20. The filter layer 40 is made of a filter material. The filter material is configured to block light outside a preset wavelength range and transmit light within a preset wavelength range.

[0113] The preset wavelength range here can be set to 450–500 nm. This allows the portion of the light reaching the filter layer 40 with a peak wavelength of 450–500 nm to pass through the filter layer 40 as much as possible and reach the optical sensor array substrate 10, for example, with a transmittance greater than 90%. However, light with a wavelength less than 450 nm or greater than 500 nm that passes through the finger will be blocked by the filter layer 40 (for example, with a transmittance less than 0.3%) and will not reach the optical sensor array substrate 30. This improves the accuracy of the optical fingerprint scanner.

[0114] In some embodiments, the filter layer 40 may be formed on the surface of the optical sensor array substrate 30 by a coating process (e.g., spin coating), and the filter material may be resin or ink. In other embodiments, the filter layer 40 may also be disposed on other structures (e.g., transparent cover plates) independent of the optical sensor array substrate 30, and the filter layer 40 may be located on the side of the optical sensor array substrate 30 away from the backlight module 20.

[0115] Considering that the filter material used in the filter layer 40 is usually relatively soft, in order to increase the hardness of the optical fingerprint scanner and prevent scratches, refer to Figure 1 In some embodiments, the optical fingerprint scanner further includes a hard coating layer 50. The hard coating layer 50 is located on the side of the filter layer 40 away from the backlight module 20. In some embodiments, the material of the hard coating layer 50 may include SiO2 and Si3C4, with the two materials forming a periodic stacked structure. This stacked structure achieves a high-transmittance ultra-hard film, thereby effectively improving the hardness of the optical fingerprint scanner.

[0116] To prevent user fingerprints from remaining on optical fingerprint scanners during use, refer to... Figure 1 In some embodiments, the optical fingerprint scanner further includes an anti-fingerprint layer 60 located on the side of the hard coating 50 away from the backlight module 20. In some embodiments, the anti-fingerprint layer 60 may be made of an organofluorine compound material to prevent fingerprint residue on the surface of the optical fingerprint scanner and make it easier to clean.

[0117] Figure 3 This is a schematic diagram of the backlight module in one embodiment of the optical fingerprint scanner according to the present disclosure.

[0118] refer to Figure 3 In some embodiments, the backlight module 20 includes a backplate 21 and a light guide plate 23. The light guide plate 23 is located on the side of the backplate 21 adjacent to the optical sensor array substrate 30. Figure 3 In the backlight module 20, a reflector 22, a light source 27, and a frame 26 may also be included. Figure 3 In this backlight module 20, the reflector 22 is located on one side of the backplate 21, and the light guide plate 23 is located on the side of the reflector 22 away from the backplate 21. The light source 27 is located on one side of the light guide plate 23 along a direction perpendicular to the light emission direction of the light guide plate 23, forming a side-lit backlight module. In other embodiments, the light source may also be located on the side opposite to the light emission direction of the light guide plate 23, forming a direct-lit backlight module. The frame 26 may be located on the side of the light guide plate 23 away from the backplate 21 to protect the backlight module 20.

[0119] To meet the overall image uniformity requirements of optical fingerprint scanners, the backlight module 20 needs to ensure uniformity across the entire surface while improving the valley-ridge difference. Accordingly, refer to... Figure 3 In some embodiments, the backlight module 20 further includes a reverse prism 24 and a privacy screen 25. The reverse prism 24 is located on the side of the light guide plate 23 away from the back plate 21, and can refract the light emitted from the light guide plate 23 in a direction perpendicular to the surface of the optical sensor array substrate 30, thereby achieving a light collimation effect. The privacy screen 25 achieves the light collimation effect by constraining the light. The combination of the reverse prism 24 and the privacy screen 25 achieves a better light collimation effect, improving the overall image uniformity of the optical fingerprint collector.

[0120] Figure 4A This is a schematic diagram of the arrangement of the detection region and the peripheral region in a substrate in one embodiment of the optical sensor array substrate disclosed herein. Figure 4B This is a schematic diagram of the combined structure of the optical sensor array substrate, readout circuit, gate circuit and flexible circuit board in one embodiment of the optical fingerprint collector according to the present disclosure. Figure 5 This is a schematic diagram of the connection structure of the array substrate, readout circuit pins, gate circuit pins and flexible circuit board pins according to one embodiment of the optical sensor array substrate of this disclosure.

[0121] refer to Figure 4A , Figure 4B and Figure 5In some embodiments, the optical fingerprint scanner further includes a readout integrated circuit (ROIC) 61, a gate circuit (Gate IC) 62, and a flexible printed circuit (FPC) 63. The readout circuit 61, gate circuit 62, and flexible printed circuit 63 are located around the optical sensor array substrate 30. The readout circuit 61 and flexible printed circuit 63 are electrically connected to the driving circuit board 10, and the gate circuit 62 is electrically connected to the flexible printed circuit board 63 via a metal trace 64. The driving circuit board 10 can achieve fine control over the operating state of the optical sensor array substrate 30 through the readout circuit 61, gate circuit 62, and flexible printed circuit board 63.

[0122] refer to Figure 4A and Figure 4B In some embodiments, the optical sensor array substrate 30 includes a substrate 31, which includes a detection region 30A (AA region) and a peripheral region 30R surrounding the detection region 30A. In some embodiments, the peripheral region 30R may include a dummy region 30B and a bonding region 30E. Figure 5 In the process, the detection area 30A includes multiple photosensitive pixels 30a. The dummy area 30B also includes multiple dummy pixels 30b. The dummy pixels 30b are configured to collect dark-state noise, i.e., noise signals caused by non-illumination reasons, to characterize the noise of each row of photosensitive pixels 30a, so as to reduce the random noise of each row of photosensitive pixels 30a through compensation.

[0123] The plurality of photosensitive pixels 30a and the plurality of dummy pixels 30b are arranged in multiple rows and columns according to the row and column directions of the array. The plurality of photosensitive pixels 30a and the plurality of dummy pixels 30b can be divided into multiple pixel groups by column. For example, if the resolution of the detection area 30A is 1600×1500 and the pixel pitch is 50.8μm, the two columns of dummy pixels 30b and the plurality of columns of photosensitive pixels can be divided into six groups by column. The first group consists of the first column of dummy pixels and columns 1 to 255 of photosensitive pixels from the left; the second group consists of columns 256 to 511 of photosensitive pixels; the third group consists of columns 512 to 767 of photosensitive pixels; and so on for the fourth to sixth groups.

[0124] exist Figure 4B In the optical fingerprint scanner, two sets of readout circuits 61 are located on the first and second sides of the optical sensor array substrate 30, respectively, with the first side being the opposite side of the second side (e.g., Figure 4B (Left and right sides of the detection area 30A). In some embodiments, the dummy area 30B is disposed on at least one side of the detection area 30A. For example, in Figure 4B and Figure 5In the middle, the two dummy regions 30B are located on the third and fourth sides of the detection region 30A, respectively (e.g., Figure 4B The third side is the opposite side of the fourth side, and both the third side and the fourth side are adjacent to the first side and the second side.

[0125] refer to Figure 4A and Figure 5 In some embodiments, the bonding region 30E is located on at least one side of the detection region 30A, such as the upper and lower sides and the left side of the detection region 30A. The bonding region 30E includes a plurality of first fanout metal structures 612 and a plurality of second fanout metal structures 622.

[0126] exist Figure 4B In the process, each group of readout circuits 61 includes three readout circuits 61. The pins 611 of the three readout circuits 61 located on the first side of the optical sensor array substrate 30 are electrically connected to the first group, the third group and the fifth group of pixels in the junction area 30E through the first fan-out metal structure 612, so as to read the sensing signals of each photosensitive pixel 30a and dummy pixel 30b in these three groups respectively. Figure 4B The pins 611 of the three readout circuits 61 located on the second side of the optical sensor array substrate 30 are electrically connected to the second, fourth and sixth groups of pixels in the junction area 30E through the first fan-out metal structure 612, so as to read the sensing signals of each photosensitive pixel 30a and dummy pixel 30b in these three groups respectively. Thus, the six readout circuits 61 realize the reading of the sensing signals of all columns of photosensitive pixels 30a in the entire detection area 30A and all dummy pixels 30b in the dummy area 30B.

[0127] The multiple first fan-out metal structures 612 here can be electrically connected to the readout data lines of each column of photosensitive pixels 30a and dummy pixels 30b, respectively. In some embodiments, the first fan-out metal structures 612 can be implemented using a double metal layer (e.g., Mo-AL double metal layer) to reduce resistance, especially for cases with long connection distances (e.g., greater than 5.11 mm), where the double metal layer structure can effectively ensure signal conduction. The double metal layers can be electrically connected through vias penetrating the insulating layer, for example, through more than two 4μm*4μm square vias.

[0128] exist Figure 5 In the middle, multiple readout circuits in the two sets of readout circuits 61 are in the row direction (i.e. Figure 4BThe photosensitive pixels 30a in the detection area 30A are staggered in the left and right directions, so that each photosensitive pixel 30a in the detection area 30A can be driven by a different readout circuit 102 according to the area, thereby simplifying the circuit layout and data processing, and making it easier to achieve uniformity of signal reading through equal resistance wiring. In some embodiments, the readout circuit 61 can be an integrated circuit disposed on the thin film, i.e., ROIC COF (Chip on Film), that is, the readout circuit is attached to the outer periphery of the optical sensor array substrate 30 through the thin film.

[0129] refer to Figure 4B In some embodiments, the optical sensor array substrate 30 is rectangular, and both the gate circuit 62 and the flexible circuit board 63 can be disposed on the third side of the optical sensor array substrate 30, with the third side adjacent to both the first and second sides. Figure 5 In the process, the pins 621 of the two gate circuits 62 are electrically connected to each row of photosensitive pixels 30a and dummy pixels 30b in the junction region 30E through the second fan-out metal structure 622.

[0130] In some embodiments, the plurality of first fan-out metal structures 612 can be electrically connected to the gate lines of each column of photosensitive pixels 30a and dummy pixels 30b, respectively. The second fan-out metal structure 622 can also be implemented by a double metal layer (e.g., Mo-AL double metal layer) to realize the electrical connection between the gate circuit 62 and the photosensitive pixel 30a.

[0131] In some embodiments, the dual-metal layer includes a first metal layer and a second metal layer. The first metal layer is located on the same layer as the readout data line and is made of the same material. The second metal layer is located on the same layer as the gate line and is made of the same material, and is electrically connected to the first metal layer through a via penetrating the gate insulating layer.

[0132] The gate circuit 62 is configured to control the switching of each row of photosensitive pixels 30a and dummy pixels 30b. The driver circuit board 10 can be connected to the pin 621 of the gate circuit 62 via the pin 631 of the flexible circuit board 63 to turn one or more rows of photosensitive pixels and dummy pixels on or off by means of an input signal.

[0133] To reduce the resistance of the metal trace 64, in some embodiments, the width of the metal trace 64 may be greater than 40 μm. (Reference) Figure 4BTo prevent light from the surrounding area of ​​the optical sensor array substrate 30 from interfering with the detection area 30A and the dummy area 30B, in some embodiments, the optical fingerprint collector further includes a light-absorbing frame 30D, such as a black light-absorbing frame. The light-absorbing frame 30D is located on the side of the optical sensor array substrate 30 away from the backlight module 20. The light-absorbing portion of the light-absorbing frame 30D can cover the peripheral area 30R, exposing the dummy area 30B, for example, covering the pins of the readout circuit 61, the gate circuit 62, and the flexible circuit board 63, as well as their respective junction areas 30E. This allows the detection area 30A and the dummy area 30B to be exposed from the non-light-absorbing portion of the light-absorbing frame 30D, thereby enabling both light sensing and preventing interference from ambient light.

[0134] Figure 6 This is a schematic diagram of the electrostatic discharge circuit in one embodiment of the optical sensor array substrate according to the present disclosure.

[0135] refer to Figure 4B and Figure 5 In some embodiments, the optical sensor array substrate further includes an electrostatic discharge region 30C, which may be located on the side of the dummy region 30B away from the detection region 30A. Multiple electrostatic discharge units 30c are arranged in a column direction. (See reference) Figure 6 In some embodiments, the electrostatic discharge unit 30c includes a first transistor 301 and a second transistor 302. Both the first transistor 301 and the second transistor 302 include a gate, a source, and a drain. The gate of the first transistor 301 is electrically connected to the drain of the first transistor 301 and is connected to the gate signal output terminal of the gate circuit 62.

[0136] The drain of the second transistor 302 is electrically connected to the source of the first transistor 301. Both the gate and source of the second transistor 302 are connected to a first voltage terminal with a lower voltage, such as VGL or GND. The voltage at the first voltage terminal is lower than the gate signal voltage at the gate signal output terminal. The first transistor 301 and the second transistor 302 can realize heavily doped N-type conductive regions to complete forward and reverse conduction current paths.

[0137] When a normal gate signal passes through the electrostatic discharge unit 30c corresponding to each row of pixels, the source and drain of the first transistor 301 are turned on, while the source and drain of the second transistor 302 are turned off, thus the electrostatic discharge unit 30c is in a closed state. However, when an abnormally high voltage signal is generated by static electricity, the gate of the first transistor 301 is at a high potential, causing the source and drain of the first transistor 301 to turn on. This voltage signal then reaches the drain of the second transistor 302 via the source and drain of the first transistor 301. The abnormally high voltage signal can cause the second transistor 302 to reach the edge of breakdown. This voltage signal then reaches VGL or GND via the drain and source of the second transistor 302, thus achieving electrostatic discharge and preventing static electricity from entering the detection area 30A, the dummy area 30B, and the various driving circuits, which could damage the optical fingerprint scanner.

[0138] refer to Figures 4A-6 In some embodiments, multiple electrostatic discharge units arranged in the column direction correspond one-to-one with multiple rows of photosensitive pixels 30a in the detection area 30A and dummy pixels 30b in the dummy area 30B, that is, each electrostatic discharge unit 30c corresponds to one row of photosensitive pixels 30a and one row of dummy pixels 30b.

[0139] Figure 7A and Figure 7B They are Figure 5 A schematic diagram of the structure of the detection zone and the virtual zone. Figures 7C-7E These are schematic diagrams of the structure of the dummy region in some embodiments of the optical sensor array substrate according to this disclosure. Figure 7F This is a schematic diagram of the detector area in another embodiment of the optical sensor array substrate according to the present disclosure. Figure 8A and Figure 8B yes Figure 5 Schematic diagram of the coverage area of ​​the light-shielding metal layer in the detection area and the virtual area, respectively.

[0140] refer to Figure 7A The photosensitive pixel 30a includes a thin film transistor (TFT) 32, a storage capacitor 33, a photosensitive element 39, and a first light-shielding metal layer 37 located on a substrate 31. The TFT 32 is electrically connected to both the storage capacitor 33 and the photosensitive element 39, and can be used to control the operating state of the photosensitive element 39.

[0141] refer to Figure 8AThe first light-shielding metal layer (also called top metal) 37 is located on the side of the TFT 32 and photosensitive element 39 away from the substrate 31d, and its coverage area is a portion of the photosensitive pixel. The orthographic projection of the first light-shielding metal layer 37 onto the substrate 31 at least partially coincides with the orthographic projection of the TFT 32 onto the substrate 31, but does not coincide with the orthographic projection of the photosensitive element 39 onto the substrate 31. This helps to prevent light from adversely affecting the TFT (e.g., causing the TFT to become photosensitive and resulting in leakage current), and does not affect the light reception of the photosensitive element 39.

[0142] refer to Figure 7B The dummy pixel 30b includes a TFT 32, a storage capacitor 33, a photosensitive element 39, and a second light-shielding metal layer 37' located on a substrate 31. The thin-film transistor 32 is electrically connected to both the storage capacitor 33 and the photosensitive element 39. In some embodiments, the photosensitive pixel 30a and the dummy pixel 30b may employ the same or different TFTs 32, storage capacitors 33, and photosensitive elements 39. In some embodiments, the photosensitive element 39 may include a photodiode.

[0143] refer to Figure 8B The second light-shielding metal layer 37' is located on the side of the TFT 32 and photosensitive element 39 away from the substrate 31d. Accordingly, the orthographic projection of the thin-film transistor 32 and the photosensitive element 39 onto the substrate 31 lies within the orthographic projection of the second light-shielding metal layer 37' onto the substrate 31. This helps to prevent light from adversely affecting the TFT (e.g., causing the TFT to become photosensitive and resulting in leakage current), and also prevents the photosensitive element 39 in the dummy pixel 30b from receiving light. In some embodiments, a plurality of dummy pixels 30b each include the second light-shielding metal layer 37', and the second light-shielding metal layer of the plurality of dummy pixels 30b completely covers the dummy area.

[0144] exist Figure 7A and Figure 7B In the optical sensor array substrate 30, a gate insulating layer 34a, a first passivation layer 34b, a planarization layer 35, and a second passivation layer 34c are included. The thin-film transistor 32 includes a gate 32a, an active layer 32b, a source 32c, and a drain 32d. The gate 32a is located between the substrate 31 and the active layer 32b. The gate insulating layer 34a is located on the side of the substrate 31 adjacent to the active layer 32b and covers the gate 32a. The source 32c and drain 32d are located on the surface of the gate insulating layer 34a away from the substrate 31 and are electrically connected to the active layer 32b, respectively.

[0145] The first passivation layer 34b is located on the side of the source electrode 32c and drain electrode 32d away from the substrate 31, and covers the source electrode 32c and drain electrode 32d. The planarization layer 35 is located on the side of the first passivation layer 34b away from the substrate 31, and its thickness can be adjusted as needed, for example, from 300 to 1000 nm. The photosensitive element 39 is located within the planarization layer 35. The second passivation layer 34c is located on the side of the planarization layer 35 away from the substrate 31.

[0146] The storage capacitor 33 includes a first capacitor plate 33a and a second capacitor plate 33b. The first capacitor plate 33a is located on the same layer as the gate 32a of the TFT 32 and is made of the same material, and can be fabricated using the same patterning process to simplify the manufacturing process. The second capacitor plate 33b is located on the same layer as the source 32c and drain 32d of the TFT 32 and is made of the same material, and can be fabricated using the same patterning process to simplify the manufacturing process. The second capacitor plate 33b is electrically connected to the source 32c or drain 32d of the TFT 32 and at least partially overlaps with the orthographic projection of the first capacitor plate 33a onto the substrate 31.

[0147] refer to Figure 7F In other embodiments, the first capacitor plate 33a and the gate 32a of the thin-film transistor 32 are located on the same layer and made of the same material, while the second capacitor plate 33b' and the source 32c and drain 32d of the thin-film transistor 32 are located on different layers. For example, in Figure 7F In the middle, the second capacitor plate 33b' is electrically connected to the source 32c or drain 32d of the TFT 32 through a via penetrating the first passivation layer 34b.

[0148] refer to Figure 7A and Figure 7B In some embodiments, one end of the photosensitive element 39 is electrically connected to the second capacitor plate 33b through a via penetrating the first passivation layer 34b. In some embodiments, the second capacitor plate 33b is used in conjunction with the bottom electrode of the photosensitive element 39. The orthographic projection of the photosensitive element 39 onto the substrate 31 lies within the orthographic projections of the second capacitor plate 33b and the first capacitor plate 33a onto the substrate 31. The first capacitor plate 33a and the second capacitor plate 33b are made of opaque metals, such as Au, Mu, Al, etc., which allows the first capacitor plate 33a and the second capacitor plate 33b to block backlight from the underside of the photosensitive element 30, eliminating interference from backlight on the photosensitive element 30.

[0149] A first electrode layer 36a is disposed at the other end of the photosensitive element 39, and the first electrode layer 36a is electrically connected to the photosensitive element 39. The first electrode layer 36a can increase the conductive electrode area of ​​the photosensitive element 39. The first electrode layer 36a can be formed using indium tin oxide (ITO).

[0150] A second electrode layer 36b, electrically connected to a bias voltage signal terminal, may be disposed on the side of the second passivation layer 34c away from the substrate 31. The second electrode layer 36b is electrically connected to the first electrode layer 36a through a via penetrating the second passivation layer 34c and the planarization layer 35. The second electrode layer 36b may be formed of ITO material.

[0151] The orthographic projection of the first electrode layer 36a on the substrate 31 at least partially overlaps with the orthographic projection of the second capacitor plate 33b on the substrate 31. This allows the storage capacitor 33 formed by the first capacitor plate 33a and the second capacitor plate 33b to be connected in parallel with the storage capacitor formed by the first electrode layer 36a and the second capacitor plate 33b, which can effectively increase the pixel's ability to store charge and improve the optical fingerprint sensor's resistance to strong light.

[0152] refer to Figure 7A and Figure 7B In some embodiments, the optical sensor array substrate 30 further includes a third passivation layer 34d and an electrostatic shielding layer 38. The third passivation layer 34d is located on the side of the second passivation layer 34c away from the substrate 31 and covers the second electrode layer 36b, the first light-shielding metal layer 37, and the second light-shielding metal layer 37'. The electrostatic shielding layer 38 is located on the side of the third passivation layer 34d away from the substrate 31 and is grounded to conduct away static electricity from the surface.

[0153] In other embodiments, the virtual pixel 30b may also employ other structures. For example, see reference... Figure 7C In some embodiments, the dummy pixel 30b may not include the photosensitive element 39. The dummy region includes a plurality of dummy pixels 30b, at least one of which includes a TFT 32, a storage capacitor 33, and a second light-shielding metal layer 37'. The second light-shielding metal layer 37' is located on the side of the TFT 32 away from the substrate 31, and the orthographic projection of the TFT 32 onto the substrate 31 lies within the orthographic projection of the second light-shielding metal layer onto the substrate 31. Compared to the photosensitive pixel 30a, the dummy pixel 30b includes the same insulating layers as in the photosensitive pixel 30a at positions corresponding to the photosensitive element 39.

[0154] refer to Figure 7DIn some embodiments, the dummy pixel 30b may include a dummy element 39' in addition to the TFT 32, storage capacitor 33, and second light-shielding metal layer 37'. The dummy element 39' comprises a material having the same dielectric constant as the photosensitive element 39 but lacking photosensitive properties. The two ends of the dummy element 39' may be electrically connected to the second capacitor plate 33b and the first electrode layer 36a, respectively. The dummy pixel 30b may or may not include the second light-shielding metal layer 37'. The second light-shielding metal layer 37' is located on the side of the TFT 32 away from the substrate 31, and the orthographic projection of the TFT 32 onto the substrate 31 lies within the orthographic projection of the second light-shielding metal layer onto the substrate 31. (Reference) Figure 7E In other embodiments, it is possible to Figure 7D The second light-shielding metal layer 37' is omitted from the embodiment.

[0155] Figure 9 This is a schematic diagram showing the overlap of the gate, source, and drain of a TFT in one embodiment of the optical sensor array substrate disclosed herein. Figure 10A This is a schematic diagram showing the arrangement of readout data lines, the source and drain of the TFT in one embodiment of the optical sensor array substrate disclosed herein. Figure 10B This is a schematic diagram of the arrangement of the gate lines and the gates of the TFTs in one embodiment of the optical sensor array substrate disclosed herein.

[0156] refer to Figure 9 and Figure 10A In some embodiments, the orthographic projection of the gate 32a of the TFT 32 onto the substrate 31 partially coincides with the orthographic projections of the drain 32d and source 32c of the TFT 32 onto the substrate 31, respectively. The overlapping portion A is shown in the figure. Figure 9 As shown, the orthographic projection of the active layer 32b onto the substrate 31 also coincides with the overlapping portion A.

[0157] refer to Figure 9 In some embodiments, the photosensitive pixel 30a (or possibly a dummy pixel 30b) includes: a readout data line 321 extending along a first direction y and a gate line 322 extending along a second direction x. The second direction x is perpendicular to the first direction y. Figure 10B In the diagram, gate line 322 and gate 32a of TFT 32 are located on the same layer and connected (gate line 322 and gate 32a are divided by dashed lines). One end of gate 32a of TFT 32 is connected to gate line 322, and the other end extends relative to gate line 322 along the first direction y.

[0158] exist Figure 10AIn the diagram, the readout data line 321 and the source electrode 32c of the TFT 32 are located on the same layer and connected (the readout data line 321 and the source electrode 32c are divided by a dashed line). One end of the source electrode 32c is connected to the readout data line 321, and the other end extends relative to the readout data line 321 along the second direction x. The drain electrode 32d of the TFT 32 is L-shaped and has a first portion 32d1, a second portion 32d2, and a bend portion 32d3. The bend portion 32d3 connects the first portion 32d1 and the second portion 32d2. The first portion 32d1 extends relative to the bend portion 32d3 along the opposite direction of the first direction y, and the second portion 32d2 extends relative to the bend portion 32d3 along the opposite direction of the second direction x.

[0159] pass Figure 10A and Figure 10B The TFT structures shown respectively can obtain Figure 9 The effect is that the orthographic projection of the gate 32a of the TFT 32 onto the substrate 31 partially overlaps with the orthographic projections of the drain 32d and source 32c of the TFT 32 onto the substrate 31.

[0160] Compared to the parallel strips used for the drain and source of the TFT in related technologies, this embodiment can reduce the overlapping area of ​​the orthographic projection of the drain 32d and source 32c of the TFT 32 onto the substrate 31 and the orthographic projection of the gate 32a onto the substrate 31, thereby reducing the capacitance formed by the drain 32d and source 32c and the gate 32a, and thus reducing the noise of the optical sensor array substrate 30.

[0161] Figure 11 This is a schematic diagram of the arrangement of readout data lines, gate lines, and second electrode layer in an array of photosensitive pixels or dummy pixels in one embodiment of the optical sensor array substrate disclosed herein.

[0162] refer to Figure 5 , Figure 7A , Figure 7B and Figure 11 In some embodiments, the plurality of photosensitive pixels 30a and the plurality of dummy pixels 30b are arranged in multiple rows and columns according to the row direction (e.g., the second direction x) and column direction (e.g., the first direction y) of the array. Figure 11 The diagram shows four adjacent photosensitive pixels 30a or dummy pixels 30b in two rows and two columns. Each column of photosensitive pixels 30a (or each column of dummy pixels 30b) includes a readout data line 321 extending continuously along the column direction and a gate line 322 extending continuously along the row direction.

[0163] The second electrode layers 36b of each column of photosensitive pixels 30a are sequentially connected along the column direction to form a whole second electrode layer. To reduce the interference of the capacitance formed by the second electrode layer 36b and the readout data line 321 on the readout data line 321, the orthographic projection of the entire second electrode layer onto the substrate 31 can be made to coincide with the orthographic projection portion of each column of photosensitive pixels 30a onto the substrate 31, and not coincide with part or all of the readout data line 321 of each column of photosensitive pixels 30a. Thus, by reducing or eliminating the projection overlap area between the second electrode layer 36b and the readout data line 321, the capacitance formed by the second electrode layer 36b and the readout data line 321 can be effectively reduced, thereby reducing the interference of this capacitance on the readout data line 321.

[0164] Similarly, the second electrode layers 36b of the dummy pixels 30b are all sequentially connected to the entire second electrode layer along the column direction. To reduce the interference of the capacitance formed by the second electrode layer 36b and the readout data line 321 on the readout data line 321, the orthographic projection of the entire second electrode layer onto the substrate 31 can be made to coincide with the orthographic projection portion of each column of dummy pixels 30b onto the substrate 31, and not coincide with part or all of the readout data line 321 of each column of dummy pixels 30b. Thus, by reducing or eliminating the projection overlap area between the second electrode layer 36b and the readout data line 321, the capacitance formed by the second electrode layer 36b and the readout data line 321 can be effectively reduced, thereby reducing the interference of this capacitance on the readout data line 321.

[0165] The various embodiments of the optical sensor array substrate disclosed herein can be applied to various devices for detecting surface textures of objects, such as detecting human fingerprints or palm prints. Accordingly, the optical fingerprint collector provided herein, including the aforementioned optical sensor array substrate, can realize single-finger or multi-finger (e.g., two-finger, three-finger, or four-finger) fingerprint recognition and detection, or palm print recognition and detection, etc. The optical fingerprint collector can be used for fingerprint collection and detection in application scenarios such as customs security.

[0166] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0167] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. An optical sensor array substrate, comprising a substrate, the substrate including a detection region and a peripheral region surrounding the detection region, wherein, The detection area includes a plurality of photosensitive pixels, at least one of the plurality of photosensitive pixels including: A thin-film transistor is disposed on the substrate and has a gate, an active layer, a source, and a drain. A storage capacitor is disposed on the substrate and has a first capacitor plate and a second capacitor plate, wherein the second capacitor plate is located on the side of the first capacitor plate away from the substrate and is electrically connected to the source or drain of the thin film transistor. A photosensitive element is located on the side of the storage capacitor away from the substrate, and one end is electrically connected to the second capacitor plate; The first electrode layer is located on the side of the photosensitive element away from the substrate and is electrically connected to the other end of the photosensitive element. Wherein, the orthographic projection of the second capacitor plate on the substrate at least partially overlaps with the orthographic projection of the first electrode layer on the substrate, the peripheral region includes a dummy region located on at least one side of the detection region and including a plurality of dummy pixels, the dummy pixels being configured to acquire noise signals caused by non-lighting reasons to characterize the noise of each row of photosensitive pixels.

2. The optical sensor array substrate according to claim 1, wherein, The first capacitor plate is located on the same layer as the gate of the thin-film transistor and is made of the same material. The second capacitor plate is located on the same layer as the source and drain of the thin-film transistor and is made of the same material.

3. The optical sensor array substrate according to claim 1, wherein, The first capacitor plate is located on the same layer as the gate of the thin-film transistor and is made of the same material, while the second capacitor plate is located on a different layer from the source and drain of the thin-film transistor.

4. The optical sensor array substrate according to claim 1, wherein, The orthographic projection of the photosensitive element onto the substrate lies within the orthographic projections of the second capacitor plate and the first capacitor plate onto the substrate.

5. The optical sensor array substrate according to claim 1, wherein, The photosensitive pixels include: The readout data line extending along the first direction is located on the same layer as and connected to the source of the thin-film transistor; and A gate line extending along a second direction is located on the same layer as and connected to the gate of the thin-film transistor, and the second direction is perpendicular to the first direction; Wherein, one end of the source of the thin-film transistor is connected to the readout data line, and the other end extends along the second direction relative to the readout data line; The drain of the thin-film transistor is L-shaped and has a first part, a second part, and a bend portion connecting the first part and the second part. The first part extends in the opposite direction to the first direction relative to the bend portion, and the second part extends in the opposite direction to the second direction relative to the bend portion. One end of the gate of the thin-film transistor is connected to the gate line, and the other end extends along the first direction relative to the gate line. The orthographic projection of the gate of the thin-film transistor onto the substrate partially coincides with the orthographic projections of the drain and source of the thin-film transistor onto the substrate.

6. The optical sensor array substrate according to claim 1, wherein, At least one of the plurality of photosensitive pixels further includes: A first light-shielding metal layer is located on the side of the thin-film transistor and the photosensitive element away from the substrate. Wherein, the orthographic projection of the first light-shielding metal layer on the substrate at least partially overlaps with the orthographic projection of the thin-film transistor on the substrate, and the orthographic projection of the first light-shielding metal layer on the substrate does not overlap with the orthographic projection of the photosensitive element on the substrate.

7. The optical sensor array substrate according to any one of claims 1 to 6, wherein, At least one of the plurality of dummy pixels includes: the thin-film transistor, the storage capacitor, the photosensitive element, the first electrode layer and the second light-shielding metal layer, wherein the second light-shielding metal layer is located on the side of the thin-film transistor and the photosensitive element away from the substrate, and the orthogonal projection of the thin-film transistor and the photosensitive element onto the substrate is located within the orthogonal projection of the second light-shielding metal layer onto the substrate.

8. The optical sensor array substrate according to claim 7, wherein, The plurality of dummy pixels each include the second light-shielding metal layer, and the second light-shielding metal layer of the plurality of dummy pixels completely covers the dummy area.

9. The optical sensor array substrate according to claim 7, wherein, At least one of the plurality of dummy pixels and the plurality of photosensitive pixels includes: A gate insulating layer is located on the side of the substrate adjacent to the active layer of the thin-film transistor and covers the gate of the thin-film transistor; The first passivation layer is located on the side of the source and drain of the thin-film transistor away from the substrate, and covers the source and drain of the thin-film transistor; A planarization layer is located on the side of the first passivation layer away from the substrate; The second passivation layer is located on the side of the planarization layer away from the substrate. The source and drain of the thin-film transistor are located on the surface of the gate insulating layer away from the substrate. The photosensitive element is located in the planarization layer and is electrically connected to the second capacitor plate through a via penetrating the first passivation layer. The first electrode layer is electrically connected to the photosensitive element.

10. The optical sensor array substrate according to claim 9, wherein, At least one of the plurality of dummy pixels and the plurality of photosensitive pixels includes: The second electrode layer is electrically connected to the bias voltage signal terminal, located on the side of the second passivation layer away from the substrate, and is electrically connected to the first electrode layer through a via penetrating the second passivation layer and the planarization layer.

11. The optical sensor array substrate according to claim 10, wherein, The plurality of photosensitive pixels and the plurality of dummy pixels are arranged in multiple rows and multiple columns according to the row direction and column direction of the array. Each column of photosensitive pixels and each column of dummy pixels includes a readout data line that extends continuously along the column direction and a gate line that extends continuously along the row direction. In this configuration, the second electrode layers of each column of photosensitive pixels are sequentially connected along the column direction to form a complete second electrode layer. The orthographic projection of the complete second electrode layer onto the substrate coincides with the orthographic projection of each column of photosensitive pixels onto the substrate, but does not coincide with part or all of the readout data lines of each column of photosensitive pixels; and / or The second electrode layers of each column of dummy pixels are sequentially connected along the column direction to form a whole second electrode layer. The orthographic projection of the whole second electrode layer on the substrate coincides with the orthographic projection of each column of dummy pixels on the substrate, and does not coincide with part or all of the readout data lines of each column of dummy pixels.

12. The optical sensor array substrate according to claim 11, wherein, At least one of the plurality of dummy pixels and the plurality of photosensitive pixels includes: The third passivation layer is located on the side of the second passivation layer away from the substrate; An electrostatic shielding layer is located on the side of the third passivation layer away from the substrate.

13. The optical sensor array substrate according to claim 7, further comprising: The electrostatic discharge area is located on the side of the dummy area away from the detection area and has multiple electrostatic discharge units. The plurality of photosensitive pixels and the plurality of dummy pixels are arranged in multiple rows and columns according to the row and column directions of the array. The plurality of electrostatic discharge units are arranged in the column direction and correspond one-to-one with the photosensitive pixels and dummy pixels in the multiple rows.

14. The optical sensor array substrate according to claim 13, wherein, At least one of the plurality of electrostatic discharge units includes: The first transistor has a gate, a source, and a drain; The second transistor has a gate, a source, and a drain. In this configuration, the gate of the first transistor is electrically connected to the drain of the first transistor and is configured to connect to the gate signal output terminal of the gate circuit. The drain of the second transistor is electrically connected to the source of the first transistor. Both the gate and the source of the second transistor are configured to connect to a first voltage terminal, and the voltage of the first voltage terminal is lower than the gate signal voltage of the gate signal output terminal.

15. The optical sensor array substrate according to any one of claims 1 to 6, wherein, At least one of the plurality of dummy pixels includes: the thin-film transistor, the storage capacitor, and the second light-shielding metal layer, wherein the second light-shielding metal layer is located on the side of the thin-film transistor away from the substrate, and the orthogonal projection of the thin-film transistor onto the substrate is located within the orthogonal projection of the second light-shielding metal layer onto the substrate.

16. The optical sensor array substrate according to any one of claims 1 to 6, wherein, At least one of the plurality of dummy pixels includes: the thin-film transistor, the storage capacitor, the second light-shielding metal layer, and the dummy element, wherein the dummy element comprises a material having the same dielectric constant as the photosensitive element but not having photosensitive properties, the second light-shielding metal layer is located on the side of the thin-film transistor away from the substrate, and the orthographic projection of the thin-film transistor on the substrate is located within the orthographic projection of the second light-shielding metal layer on the substrate.

17. The optical sensor array substrate according to any one of claims 1 to 6, wherein, At least one of the plurality of dummy pixels includes: the thin-film transistor, the storage capacitor, and the dummy element, wherein the dummy element comprises a material having the same dielectric constant as the photosensitive element but without photosensitive properties.

18. The optical sensor array substrate according to claim 11, wherein, The surrounding area includes a junction area located on at least one side of the detection area; the junction area includes: Multiple first fan-out metal structures are electrically connected to the readout data lines of each column of photosensitive pixels and dummy pixels; Multiple second fan-out metal structures are electrically connected to the gate lines of each row of photosensitive pixels and dummy pixels.

19. The optical sensor array substrate according to claim 18, wherein, At least one of the plurality of first fan-out metal structures and the plurality of second fan-out metal structures includes a bimetallic layer; the bimetallic layer includes: The first metal layer is located in the same layer as the readout data line and is made of the same material. The second metal layer is located on the same layer as the gate line and is made of the same material, and is electrically connected to the first metal layer through a via penetrating the gate insulating layer.

20. An optical fingerprint scanner, comprising: Backlight module; The optical sensor array substrate according to any one of claims 1 to 19 is located on the light-emitting side of the backlight module; The driving circuit board is electrically connected to the backlight module and signal-connected to the optical sensor array substrate.

21. The optical fingerprint scanner according to claim 20, further comprising: A filter layer is located on the side of the optical sensor array substrate away from the backlight module; The material of the filter layer includes a filter material, which is configured to block light outside a preset wavelength range and transmit light within a preset wavelength range, wherein the preset wavelength range is 450~500nm.

22. The optical fingerprint scanner according to claim 21, further comprising: A rigid coating is located on the side of the filter layer away from the backlight module. The hard cladding layer is made of SiO2 and Si3C4, forming a periodic stacked structure with alternating layers of the two materials.

23. The optical fingerprint scanner according to claim 22, further comprising: The anti-fingerprint layer is located on the side of the hard coating away from the backlight module.

24. The optical fingerprint scanner according to any one of claims 20 to 23, wherein, The backlight module includes: Back panel; A light guide plate is located on the side of the back plate adjacent to the optical sensor array substrate; A reverse prism is located on the surface of the light guide plate on the side away from the back plate; A privacy screen protector is located on the surface of the privacy screen protector away from the back panel.

25. The optical fingerprint scanner according to any one of claims 20 to 23, further comprising: Two sets of readout circuits are located on the first and second sides of the optical sensor array substrate and are electrically connected to the driving circuit board. The first side is opposite to the second side. The optical sensor array substrate has two dummy regions located on the third and fourth sides of the detection region. The third side is opposite to the fourth side, and both the third and fourth sides are adjacent to the first and second sides. The virtual area includes multiple virtual pixels. The multiple photosensitive pixels and the multiple virtual pixels are arranged in multiple rows and columns according to the row and column directions of the array, and are divided into multiple pixel groups according to the columns. Each readout circuit group includes multiple readout circuits. The pins of all readout circuits in the two groups are electrically connected to multiple pixel groups one-to-one through a first fan-out metal structure. All readout circuits in the two groups are staggered in the row direction.

26. The optical fingerprint scanner according to claim 25, further comprising: Two gate circuits are located on the third side of the optical sensor array substrate and are electrically connected to the plurality of photosensitive pixels and the plurality of dummy pixels through a second fan-out metal structure. A flexible circuit board is located on the third side of the optical sensor array substrate, between the two gate circuits. The pins of the flexible circuit board are electrically connected to the pins of the two gate circuits via metal traces, and are also electrically connected to the driving circuit board. The width of the metal trace is greater than 40 μm.

27. The optical fingerprint scanner according to claim 25, further comprising: A light-absorbing frame is located on the side of the optical sensor array substrate away from the backlight module, and the non-light-absorbing portion of the light-absorbing frame exposes the detection area and the two dummy areas.

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