Semiconductor storage devices

Abstract

A semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes blocks of memory cells. The peripheral circuitry can execute a first programming verification cycle in response to a first write operation on a first word line in a word line group, thereby programming the memory cell associated with the first word line into multiple states. The word line group includes one or more word lines. The peripheral circuitry then determines a verification start cycle of multiple states based on sensing results in the first programming verification cycle, and executes a second programming verification cycle with the determined verification start cycle of multiple states in response to a second write operation on a second word line in the word line group.

Description

Technical Field

[0001] This application describes embodiments that generally relate to semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose data when power is off. Non-volatile memory devices can even retain stored data when power is off. To achieve higher data storage density, semiconductor manufacturers have developed vertical device technologies, such as 3D NAND flash memory technology. 3D NAND flash memory devices are a type of non-volatile memory device. Summary of the Invention

[0003] This disclosure provides a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes blocks of memory cells. The peripheral circuitry is configured to execute a first programming verification cycle in response to a first write operation to a first word line in a word line group, to program the memory cells associated with the first word line into multiple states. The word line group includes one or more word lines. The peripheral circuitry then determines a verification start cycle for the multiple states based on sensing results in the first programming verification cycle, and executes a second programming verification cycle with the determined verification start cycle for the multiple states in response to a second write operation to a second word line in the word line group.

[0004] In some embodiments, the peripheral device is configured to count the total number of active memory cells of a state during a first programming verification cycle, and to determine a cycle as a verification start cycle of a state when the total number of active memory cells of a state in the cycle meets a requirement. In an embodiment, the peripheral circuitry includes: a first counter circuit configured to count the total number of active memory cells of a state; a second counter circuit configured to count the number of cycles in the first programming verification cycle; and a comparator circuit configured to compare the total number of active memory cells of a state with a threshold. The comparator circuitry may store the number of cycles as a verification start cycle of a state in response to the total number of active memory cells of a state being equal to or greater than the threshold.

[0005] According to an aspect of this disclosure, the peripheral circuitry includes a page buffer circuit with a latch circuit coupled to a bit line. During the first programming verification cycle, the value in the latch circuit indicates the sensing result in the first programming verification cycle.

[0006] In some examples, the peripheral circuitry includes a memory configured to store a defined verification start cycle of multiple states associated with a word line group. In the example, the memory is a volatile memory that loses the defined verification start cycle of multiple states in response to a power outage.

[0007] In some examples, the peripheral circuitry is configured to perform a first programming verification loop in response to power-up of the semiconductor memory device and a first write operation to a first word line in the word line group.

[0008] In one example, a word line group is defined as including the first word line. In another example, a word line group is defined as including the first word line and one or more other word lines of the memory block. In yet another example, a word line group is defined as including the memory block.

[0009] In some examples, word line groups are defined in the non-volatile portion of a semiconductor memory device.

[0010] It should be noted that the second character line can be the first character line or another character line in the character line group.

[0011] In some embodiments, multiple states represent the values ​​of multiple binary bits respectively.

[0012] This disclosure provides a method for programming a semiconductor memory device. For example, the method includes executing a first programming verification cycle in response to a first write operation to a first word line in a group of word lines comprising one or more word lines. The first programming verification cycle programs a memory cell associated with the first word line in the group of word lines into multiple states. Furthermore, the method includes: determining a verification start cycle for the multiple states based on sensing results during the first programming verification cycle; and executing a second programming verification cycle with the determined verification start cycle for the multiple states in response to a second write operation to a second word line in the group of word lines.

[0013] This disclosure also provides a method for forming a semiconductor memory device. For example, the method includes dividing a block of memory cells into one or more word line groups based on a programming speed characterization. Memory cells associated with word lines are configured to be programmed into multiple states according to a programming verification cycle in response to a write operation to the word line. Furthermore, the method includes defining one or more word line groups in the non-volatile portion of the semiconductor memory device. Attached Figure Description

[0014] When read in conjunction with the accompanying drawings, aspects of this disclosure can be better understood in light of the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0015] Figure 1 Block diagrams of semiconductor memory devices according to some embodiments of the present disclosure are shown.

[0016] Figure 2The illustration shows a programming verification loop used in a write operation on a word line group according to some embodiments of the present disclosure.

[0017] Figure 3 Cross-sectional views of semiconductor memory devices and reference numerals for memory cell strings are shown according to some embodiments of the present disclosure.

[0018] Figure 4 A block diagram of a group-based verification start loop determination circuit according to some embodiments of the present disclosure is shown.

[0019] Figure 5 An exemplary lookup table is shown that stores values ​​associated with states and groups.

[0020] Figure 6 A flowchart is shown illustrating a process for determining and defining word line groups according to some embodiments of the present disclosure.

[0021] Figure 7 A flowchart summarizing a process for programming a semiconductor memory device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature relative to another element(s) or feature(s) as shown in the accompanying drawings. In addition to the orientations described in the accompanying drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly in a similar manner.

[0024] This disclosure provides semiconductor memory devices and techniques for forming and using semiconductor memory devices. Typically, a semiconductor memory device includes a memory cell array portion and a peripheral circuit portion. The peripheral circuit portion interfaces the memory cell array portion with external circuitry and provides various controls to the memory cell array portion.

[0025] According to some aspects of this disclosure, the memory cell array portion includes memory cells configured to store a plurality of binary bits in each memory cell. Typically, a memory cell can be configured to two states to store binary bits, and can be configured to more than two states to store a plurality of binary bits. In an example, each memory cell is configured to store two binary bits, and the memory cell can be configured to four states based on a threshold voltage of the memory cell. For example, a memory cell can be erased and have a threshold voltage within a first range (e.g., [-3V, -1V]) corresponding to a first state (e.g., binary "11") corresponding to two bits; a memory cell can be programmed to have a threshold voltage within a second range (e.g., [0V, 1V]) corresponding to a second state (e.g., binary "01") corresponding to two bits; a memory cell can be programmed to have a threshold voltage within a third range (e.g., [1V, 2V]) corresponding to a third state (e.g., binary "10") corresponding to two bits; and a memory cell can be programmed to have a threshold voltage within a fourth range (e.g., [2V, 3V]) corresponding to a fourth state (e.g., binary "00") corresponding to two bits.

[0026] It should be noted that although two binary bits are used in some examples of this disclosure, this disclosure is not limited to two binary bits. In some examples, each storage unit is similarly configured to store other suitable numbers of binary bits, such as three bits, four bits, etc.

[0027] According to aspects of this disclosure, multiple binary bits can be written to a memory cell using a programming verification cycle. Each programming verification cycle includes a programming step and a verification step. In the programming step, for example, a programming pulse (e.g., a pulse voltage higher than 18V) can be applied to the gate terminal of the memory cell with other suitable biases by injecting electrons into the floating gate of the memory cell to appropriately increase the threshold voltage. In the verification step, a verification voltage can be applied to the gate terminal with other suitable biases to determine whether the threshold voltage of the memory cell is within an appropriate range. When the threshold voltage is outside the appropriate range on the low side (e.g., the memory cell is turned off in response to the verification voltage), another programming verification cycle can be executed. The programming verification cycle can be executed until the threshold voltage of the memory cell is within the appropriate range (the memory cell is turned on in response to the verification voltage). In some examples, for example, the voltage level of the programming pulse can be adjusted using incremental step pulse programming (ISPP) techniques.

[0028] According to another aspect of this disclosure, data can be written to multiple memory cells simultaneously (e.g., using the same set of programming verification cycles). In an example, multiple memory cells share word lines connected to the gate terminals of multiple memory cells, and thus programming pulses can be applied to the gate terminals of multiple memory cells. Based on other biases for the respective memory cells, programming of the respective memory cells can be enabled or disabled. In an example, a relatively low voltage (e.g., 0V) is applied to the bit lines of the memory cells to enable programming, and the programming voltage can inject electrons into the floating gate of the memory cells. In another example, a relatively high voltage (e.g., 10V) is applied to the bit lines of the memory cells to disable programming, and electron injection into the floating gate of the memory cells is disabled in response to the programming pulse.

[0029] According to some aspects of this disclosure, the programming speed of memory cells can vary with various factors. In one example, memory cells sharing the same word line may have slightly different programming speeds, for example, due to voltage distribution of programming pulses above the word line, etc. The distribution of programming speeds for memory cells sharing the same word line can be relatively narrow (e.g., relatively small variance). In another example, memory cells on different word lines within the same memory cell block may have significant programming speed differences, for example, due to differences in programming pulse voltage levels, channel bias voltage differences, etc. The distribution of programming speeds for memory cells associated with different word lines within the same memory cell block can be relatively large (e.g., relatively large variance). In yet another example, memory cells in different memory cell blocks may have significant programming speed differences due to various differences between different memory cell blocks. The distribution of programming speeds for memory cells in different memory cell blocks can be significantly large (e.g., significantly large variance).

[0030] Furthermore, according to aspects of this disclosure, the programming speed of the memory cell may vary. For example, with a large number of program-erase (PE) cycles, the programming speed of the memory cell may then change significantly.

[0031] In some relevant examples, a set of programming verification loops with fixed verification start loops is used to program memory cells in a semiconductor device. In some examples, the earliest programming verification loop (e.g., to verify the memory cell with the fastest programming speed for the state) is used to select the verification start loop for a state, thereby ensuring correct programming in the worst-case scenario (e.g., with the fastest programming speed). In the example, the verification start loop for the first state (S1) is loop 1; the verification start loop for the second state (S2) is loop 2, and the verification start loop for the third state (S3) is loop 3. In the example, selecting the earliest programming verification loop may increase the programming time (tPROG) when most memory cells are programmed to the third state, for example, at a much later programming verification loop. Furthermore, a fixed verification start loop may not be suitable for a changed programming speed.

[0032] Some aspects of this disclosure provide techniques for determining the verification start cycle of a semiconductor memory device during use. The verification start cycle of the semiconductor memory device can be adjusted differently for different segments of the memory cells in the semiconductor memory device, and the verification start cycle of the semiconductor memory device can be adjusted in response to the use of the semiconductor memory device (e.g., PE cycle).

[0033] Figure 1 A block diagram of a semiconductor memory device 100 according to some embodiments of the present disclosure is shown. The semiconductor memory device 100 includes a memory cell array 102 and peripheral circuitry 101 coupled together. In some examples, the memory cell array 102 and the peripheral circuitry 101 are disposed on the same die (chip). In other examples, the memory cell array 102 is disposed on an array die, and the peripheral circuitry 101 is disposed on a different die, such as a die implemented using complementary metal-oxide-semiconductor (CMOS) technology and referred to as a CMOS die. The array die and the CMOS die are suitably bonded and electrically coupled together. Reference will be made to... Figure 3 Examples of coupled array dies and CMOS dies are described.

[0034] In some examples, a CMOS die may be coupled to multiple array dies. In an embodiment, semiconductor memory device 100 is an integrated circuit (IC) package that encapsulates one or more array dies and one or more CMOS dies.

[0035] Semiconductor memory device 100 is configured to store data in memory cell array 102 and perform operations in response to received commands (CMDs). In some examples, semiconductor memory device 100 can receive write commands (also referred to as programming commands in some examples), read commands, erase commands, etc., and perform operations accordingly. In one example, semiconductor memory device 100 receives a write command with an address (ADDR) and data (DATA), and then semiconductor memory device 100 stores the data at the address in memory cell array 102. In another example, semiconductor memory device 100 receives a read command with an address, and then semiconductor memory device 100 accesses memory cell array 102 and outputs the data stored at the address in memory cell array 102. In yet another example, semiconductor memory device 100 receives an erase command with an address, and then semiconductor memory device 100 resets one or more memory cell blocks at the address to an unprogrammed state (also referred to as an erased state), such as a "1" in 1 bit, "11" in 2 bits, "111" in 3 bits, etc., in NAND flash memory storage technology.

[0036] Typically, the memory cell array 102 may include one or more memory planes 160, and each of the memory planes 160 may include multiple memory cell blocks, for example, Figure 1 The diagram shows blocks 1 through N. In some examples, parallel operations may occur at different storage planes 160. In some embodiments, each of the storage blocks 1 through N is the smallest unit for performing an erase operation. Each storage block comprises several pages. In some examples, a page is the smallest unit capable of being programmed. In the examples, the storage units of a page can share a word line.

[0037] In some embodiments, the memory cell array 102 is a flash memory array and is implemented using 3D NAND flash memory technology. Each of the memory cell blocks 1 to N includes a plurality of memory cell strings arranged vertically (e.g., perpendicular to the main surface of the die). Each memory cell string includes a plurality of transistors connected in series. (Refer to...) Figure 3 Describe the details of the storage unit string.

[0038] In some embodiments, the peripheral circuit 101 includes an interface circuit 110 and a controller 120 coupled together.

[0039] Interface circuitry 110 includes suitable circuitry for interfacing with memory cell array 102 or with external components (e.g., host devices) of semiconductor memory device 100. In some examples, interface circuitry 110 includes a first portion, referred to as a host interface, for interfacing with a host device, and a second portion, referred to as an array interface, for interfacing with memory cell array 102. Figure 1 In the example, interface circuit 110 includes, for example, Figure 1 The command decoding circuit 114, address decoding circuit 115, page buffer circuit 112, data input / output (I / O) circuit 111, and voltage generator 113 are shown coupled together.

[0040] In some examples, address decoding circuitry 115 may receive an address (ADDR) from an I / O pin coupled to external circuitry (e.g., a host device) and perform address decoding. In some examples, address decoding circuitry 115 may operate in conjunction with controller 120 to perform address decoding. In some embodiments, the address received from the host device is a file system logical block address. In some examples, address decoding circuitry 115 and controller 120 may perform the functions of a flash translation layer (FTL) to translate the block address used by the file system into the address of a physical cell in memory cell array 102. In examples, the translation from the block address used by the file system to the physical cell in memory cell array 102 may be used to exclude faulty memory cells. In some embodiments, the address of the physical cell is in the form of a row address (R-ADDR) and a column address (C-ADDR). In response to the row address, address decoding circuitry 115 is able to generate word line (WL) signals and select signals, such as one or more top select gate (TSG) signals, one or more bottom select gate (BSG) signals, etc., based on the row address, and provide WL signals and select signals to memory cell array 102. In some examples, during a write operation, address decoding circuit 115 provides a WL signal and a select signal to memory cell array 102 to select the page to be programmed. During a read operation, address decoding circuit 115 can provide a WL signal and a select signal to select the page to be buffered. During an erase operation, address decoding circuit 115 can provide the appropriate WL signal and select signal.

[0041] Page buffer circuitry 112 is coupled to the bit lines (BL) of memory cell array 102 and is configured to buffer data, such as one or more pages of data during read and write operations. In one example, during a write operation, page buffer circuitry 112 may buffer data to be programmed and drive the data to the bit lines of memory cell array 102, thereby writing data into memory cell array 102. In another example, during a read operation, page buffer circuitry 112 may sense data on the bit lines of memory cell array 102 and buffer the sensed data for output.

[0042] In some embodiments, page buffer circuit 112 includes latch circuitry associated with bit lines. Values ​​in the latch circuitry can indicate programming states. For example, during a write operation that writes data to a memory cell in a memory string connected to the bit lines, the latch circuitry associated with the bit lines can switch values, for example, from "0" to "1" in response to the on-statement of the memory cell (e.g., the memory cell being fully programmed) during a verification step of the programming verification cycle, using a programming verification loop. Further programming of the memory cell is prohibited when the latch circuitry has the switched value (e.g., "1"). In some examples, the latch circuitry can hold the switched value (e.g., "1") for the remainder of the write operation. In one example, data (e.g., page data) in page buffer circuit 112 has been written to memory cell array 102 when all latch circuitry has the value "1".

[0043] exist Figure 1 In one example, data I / O circuitry 111 is coupled to page buffer circuitry 112 via a data line (DL). In this example (e.g., during a write operation), data I / O circuitry 111 is configured to receive data from external circuitry (e.g., a host device) of semiconductor memory device 100 and provide the received data to memory cell array 102 via page buffer circuitry 112. In another example (e.g., during a read operation), data I / O circuitry 111 is configured to output data from memory cell array 102 to external circuitry (e.g., a host device) based on column address (C-ADDR).

[0044] Voltage generator 113 is configured to generate appropriate voltage levels for suitable operation of semiconductor memory device 100. For example, during a read operation, voltage generator 113 can generate appropriate voltage levels for source voltage, body voltage, various WL voltages, selection voltage, etc., for the read operation. In some examples, a source voltage as an array common source (ACS) voltage is provided to the source terminals of memory cell array 102 during a read operation; for example, a body voltage is provided to the P-type well (PW) for the body portion of the memory cell string during a read operation. WL voltage and selection voltage are provided to address decoding circuit 115, so that address decoding circuit 115 can output WL signals and selection signals (e.g., TSG signals and BSG signals) at appropriate voltage levels during a read operation.

[0045] In another example, during the erase operation, voltage generator 113 can generate voltages at appropriate levels for the source voltage, body voltage, various WL voltages, select voltage, BL voltage, etc., suitable for the erase operation. In some examples, a source voltage as the ACS voltage is provided to the source terminals of the memory cell array 102 during the erase operation; a PW voltage is provided to the P-type wells that constitute the body portion of the memory cell string during the erase operation. The WL voltage and select voltage are provided to the address decoding circuit 115, so that the address decoding circuit 115 can output the WL signal and the BSG and TSG signals at appropriate voltage levels during the erase operation. The BL voltage is provided to the page buffer circuit 112, so that the page buffer circuit 112 can drive the bit line (BL) at an appropriate voltage level during the erase operation. It should be noted that in some examples, the BL voltage can be applied to the bit line without going through the page buffer circuit 112.

[0046] In another example, during a write operation, voltage generator 113 can generate voltages at appropriate levels for the source voltage, body voltage, various WL voltages, select voltage, BL voltage, verification voltage, reference voltage, etc., suitable for the write operation. In some examples, a source voltage as the ACS voltage is provided to the source terminals of the memory cell array 102 during the write operation; a PW voltage is provided to the P-type wells of the body portion of the memory cell string during the write operation. The WL voltage, select voltage, and verification voltage are provided to address decoding circuit 115, so that address decoding circuit 115 can output the WL signal and BSG and TSG signals at appropriate voltage levels during the write operation. The BL voltage and reference voltage are provided to page buffer circuit 112, so that page buffer circuit 112 can drive the bit line (BL) at appropriate voltage levels during the write operation and can sense the programming state during the verification step during the write operation.

[0047] In some embodiments, for example, the command decoding circuit 114 is configured to receive a command (CMD) from the host device via an I / O pin during a command cycle. In some embodiments, the I / O pin can transmit other information, such as an address in an address cycle or data in a data cycle. In some embodiments, the received command is a command based on some high-level protocol (e.g., the USB protocol).

[0048] In some embodiments, the command decoding circuit 114 and the controller 120 may operate together to decode received commands. In an example, the command decoding circuit 114 performs initial decoding of the received command and provides the decoded command to the controller 120 for further processing. The controller 120 may perform further decoding and then generate control parameters based on the command for controlling other circuits, such as the page buffer circuit 112, the data I / O circuit 111, the voltage generator 113, etc.

[0049] In some embodiments, controller 120 may control voltage generator 113 to generate a voltage of an appropriate level based on a command. Controller 120 may cooperate with other circuitry to provide a signal to memory cell array 102 at the appropriate time and with the appropriate voltage level.

[0050] exist Figure 1 In one example, controller 120 includes read control 121, erase control 122, and write control 123. In this example, in response to a read command, read control 121 can generate control parameters to generate control signals, thereby reading data from memory cell array 102. In another example, in response to a write command, write control 123 can generate control parameters to generate control signals, thereby writing data to memory cell array 102. In yet another example, in response to an erase command, erase control can generate control parameters to generate control signals, thereby erasing one or more memory cell blocks of memory cell array 102.

[0051] Controller 120 can be implemented using any suitable technology.

[0052] In some examples, controller 120 is implemented as a microcontroller unit (MCU) (not shown) and firmware (FW) memory (not shown). The MCU may include one or more processing cores, and the FW memory stores firmware that can be executed by one or more processing cores. For example, the firmware includes a read module, a write module, and an erase module. The MCU can execute the read module to perform the function of read control 121. The MCU can execute the write module to perform the function of write control 123. The MCU can execute the erase module to perform the function of erase control 122.

[0053] It should be noted that any suitable non-volatile memory capable of retaining stored data even when power is lost can be used to implement the FW memory. In this example, a read-only memory (ROM) is used to implement the FW memory. In another example, a programmable ROM is used to implement the FW memory. In yet another example, an erasable programmable ROM is used to implement the FW memory.

[0054] In some embodiments, controller 120 may be implemented using logic circuitry. In some examples, portions of controller 120 or the entire controller 120 may be implemented using logic circuitry that can have a much faster processing speed than firmware-based implementations. In examples, some functions of controller 120 may be implemented using programmable logic units that provide flexible development options and fast processing speeds.

[0055] According to some aspects of this disclosure, write control 123 is configured to determine a verification start loop for a state (e.g., a state for programming multiple bits in a memory cell) based on sensing results from programming one or more word lines in a word line group. The verification start loop for determining the state can be stored as associated with the word line group. Then, for subsequent programming of the word lines in the word line group, write control 123 can use a programming verification loop with the verification start loop for the state.

[0056] In some embodiments, write control 123 includes a group-based verification start loop determination module 130 and memory 140 (or allocated storage space in memory). In an embodiment, the group-based verification start loop determination module 130 is configured to detect a first write to a word line in the word line group (e.g., after power-on of the semiconductor memory device 100), and to perform a first programming verification loop using the default verification start loop of the state (e.g., the earliest verification start loop of the state), and to write data to the word line. Furthermore, the group-based verification start loop determination module 130 can monitor results, such as sensing results, values ​​in the latch circuitry of the page buffer circuit 112, etc., and determine an updated verification start loop of the state. The updated verification start loop of the state can be stored in the memory 140 associated with the word line group (e.g., ...). Figure 1 In the state of the group-based verification start loop 145), the state is updated to execute a programmed verification loop for writing to the word line. Therefore, for subsequent writes to word lines in the word line group (e.g., the same word line as the first write or other word lines), the updated verification start loop of the state can be used to execute a programmed verification loop for writing to the word line.

[0057] The state-updated verification start loop can be determined based on various suitable techniques. In some examples, at each programming verification loop within the first programming verification loop, for example, based on values ​​in the latch circuitry of page buffer circuit 112, the total number of active memory cells (e.g., fully programmed memory cells) for each state pair word line can be counted. At a particular programming verification loop, when the total number of active memory cells for the state increases to equal or greater than a threshold, the particular programming verification loop can be determined to be the state-updated verification start loop.

[0058] According to aspects of this disclosure, word lines with similar programming speeds can form word line groups. Therefore, in the example, when determining the state in a verification start loop based on writing to one word line in the word line group, the state-determining verification start loop can be used for a programming verification loop to write to any word line in the word line group. In some examples, the programming speed of memory cells at different word lines can be characterized by the fabrication of the semiconductor memory device, thus allowing word lines to be grouped based on the programming speed characterization.

[0059] In some examples, word line groups can be defined using the addresses of word lines within the word line group. The definitions of word line groups can be appropriately stored on each of the semiconductor memory devices. In one example, the definitions of word line groups can be stored in a special partition of the memory cell array 102. For example, the memory cell array 102 includes an initialization partition 165. The initialization partition 165 is a portion of the memory cell array 102 that can be loaded into the peripheral circuitry 101 when the semiconductor memory device 100 is powered on. In some examples, upon power-on, information in the initialization partition 165 is loaded into the peripheral circuitry 101 to configure the peripheral circuitry 101. In another example, the definitions of word line groups can be stored in the initialization partition 165 and loaded into the peripheral circuitry 101 upon power-on. In yet another example, the definitions of word line groups are implemented explicitly or implicitly in the firmware. In some embodiments, the definitions of word line groups are stored in a non-volatile form, so that the definitions of word line groups are not lost upon power-off.

[0060] In some examples, word lines can be block-based, and each word line group includes one or more memory cell blocks, for example, Figure 1 One or more BLOCK-1 to BLOCK-N. In some examples, word line groups can be word line-based, and each word line group includes multiple word lines. In another example, word line groups can be single word line-based, and each word line group includes a single word line.

[0061] In some embodiments, the state determination verification start loop can be stored in a volatile form. In one example, memory 140 can be implemented using static random access memory (SRAM). In another example, memory 140 is implemented using suitable register circuitry. Thus, after each power-on, the state verification start loop can be re-determined and stored. Consequently, when the programming speed changes (e.g., due to an increase in the PE cycle), the state verification start loop can be re-determined at each power-on to compensate for the change in programming speed.

[0062] It should be noted that in some examples, the group-based verification start loop determination module 130 is implemented as firmware to be executed by the processor; in some other examples, the group-based verification start loop determination module 130 is implemented using circuitry.

[0063] Figure 2 The illustration shows a programming verification loop used in write operations on word line groups, illustrating some examples. Word line groups consist of word lines with similar programming speeds. Figure 2 In the examples, in response to the first write to a word line in the word line group (e.g., the first write to the word line group after power-on), a set of programming verification loops with predefined verification start loops, as shown in 210, can be used. In some examples, the predefined verification start loops are set as early as possible to ensure correct programming of memory cells with fast programming speeds. For example, the predefined verification start loop of S1 is in the first programming verification loop, as shown in 211; the predefined verification start loop of S2 is in the second programming verification loop, as shown in 212; and the predefined verification start loop of S3 is in the third programming verification loop, as shown in 214.

[0064] In some embodiments, write control (e.g., write control 123) may count the total number of active memory cells for each state during the verification step, compare the total number of active memory cells for each state with a threshold, and accordingly determine the verification start loop for the state for subsequent writing to the word line group. In some examples, the threshold is an appropriate value depending on the error correction capability.

[0065] For example, assuming the threshold is 2. In the first programming verification loop (LOOP1), at verification 211, the total number of active memory cells for S1 is 3, therefore write control 123 determines that the verification start loop for S1 is LOOP1. In the second programming verification loop (LOOP2), at verification 212, the total number of active memory cells for S2 is 0, therefore write control 123 determines that the verification start loop for S2 can be a later loop. In the third programming verification loop (LOOP3), at verification 213, the total number of active memory cells for S2 is 2, therefore write control 123 determines that the verification start loop for S2 is LOOP3.

[0066] Similarly, in the example, in LOOP3, at verification 214, the total number of active memory cells for S3 is 1, so write control 123 determines that the verification start loop for S3 can be a later loop. In the fourth programming verification loop (LOOP4), at verification 215, the total number of active memory cells is 4, so write control 123 determines that the verification start loop for S3 is LOOP4.

[0067] Accordingly, in Figure 2In the example, for the subsequent writing of word lines in the word line group, a programming verification loop with an updated verification start loop, as shown in 220, can be used. For example, the updated verification start loop for S1 is LOOP1, as shown in 221; the updated verification start loop for S2 is LOOP3, as shown in 222; and the updated verification start loop for S3 is LOOP4, as shown in 223. As shown, using the updated verification start loop can reduce the total programming time used for writing word lines.

[0068] It should be pointed out that, Figure 2 The example in the example is used to illustrate that other suitable predefined validation start loops can be used in the first write of a word line group.

[0069] Figure 3 A cross-sectional view of a semiconductor memory device 300 according to some embodiments of the present disclosure is shown. In some examples, the semiconductor memory device 300 may be a semiconductor memory device 100. According to some embodiments of the present disclosure, the semiconductor memory device 300 includes an array die 302 and a CMOS die 301 bonded together.

[0070] It should be noted that, in some embodiments, the semiconductor memory device may include a plurality of array dies and CMOS dies. The plurality of array dies and CMOS dies may be stacked and bonded together. The CMOS dies are respectively coupled to the plurality of array dies and are capable of driving the respective array dies to operate in a manner similar to that of the semiconductor memory device 300.

[0071] The array die 302 includes a substrate 303 and memory cells formed on the substrate 303. The CMOS die 301 includes a substrate 304 and peripheral circuitry formed on the substrate 304. For simplicity, the main surface of the substrate 303 is referred to as the XY plane, and the direction perpendicular to the main surface is referred to as the Z direction.

[0072] Substrates 303 and 304 can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. Substrates 303 and 304 can each comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. Group IV semiconductors can include Si, Ge, or SiGe. Substrates 303 and 304 can each be a bulk wafer or an epitaxial layer.

[0073] Semiconductor memory device 300 includes a memory cell array (e.g., memory cell array 102) and peripheral circuitry (e.g., address decoding circuitry, page buffer circuitry, data I / O circuitry, voltage generator, main controller, etc.). Figure 3In the example, a memory cell array can be formed on the substrate 303 of the array die 302, and peripheral circuitry can be formed on the substrate 304 of the CMOS die 301. The array die 302 and the CMOS die 301 are arranged face-to-face (the surface on which the circuitry is formed is called the face, and the opposite surface is called the back) and bonded together.

[0074] In some examples, a well can be formed in substrate 302 to be used accordingly for the block as the main body portion of the block. Figure 3 In one example, a P-type well 305 is formed in substrate 303, and a block of three-dimensional (3D) NAND memory cell strings can be formed in the P-type well 305. The P-type well 305 can form the body portion for the 3D NAND memory cell strings (e.g., connected to a PW terminal), and a voltage referred to as PW can be applied to the P-type well 305 via the PW terminal. In some examples, a memory cell array as an array of vertical memory cell strings is formed in core region 306. In addition to core region 306 and peripheral region, array die 302 also includes a stepped region 307 (also referred to as a connection region in some examples) to facilitate connections with, for example, the gates of memory cells in the vertical memory cell strings, the gates of select transistors, etc. The gates of memory cells in the vertical memory cell strings correspond to word lines for the NAND memory architecture.

[0075] exist Figure 3 In the example, the vertical storage cell string 380 is shown as an array representing vertical storage cell strings formed in the core region 306. Figure 3 A version of the reference numerals corresponding to the vertical memory cell string 380' is also shown. The vertical memory cell string 380 is formed in a layer stack 390. The layer stack 390 includes alternately stacked gate layers 395 and insulating layers 394. The gate layers 395 and insulating layers 394 are configured to form vertically stacked transistors. In some examples, the stacked layers of transistors include memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors, etc. In some examples, the stacked layers of transistors may include one or more dummy select transistors. The gate layer 395 corresponds to the gate of the transistor. The gate layer 395 is made of a gate stack material such as a high dielectric constant (high k) gate insulator layer and a metal gate (MG) electrode. The insulating layer 394 is made of one or more insulating materials such as silicon nitride, silicon dioxide, etc.

[0076] According to some aspects of this disclosure, a vertical string of memory cells is formed by channel structures 381 extending vertically (in the Z direction) into a layer stack 390. The channel structures 381 may be configured to be spaced apart from each other in the XY plane. In some embodiments, the channel structures 381 are arranged in the form of an array between gate line cut-out structures (not shown). The gate line cut-out structures facilitate the replacement of the sacrificial layer with the gate layer 395 in a post-gate process. The array of channel structures 381 can have any suitable array shape, such as a matrix array shape along the X and Y directions, a sawtooth array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. In some embodiments, each of the channel structures has a circular shape in the XY plane and a cylindrical shape in the XZ and YZ planes. In some embodiments, the number and arrangement of the channel structures between the gate line cut-out structures are not limited.

[0077] In some embodiments, the channel structure 381 has a cylindrical shape extending in the Z direction perpendicular to the main surface of the substrate 303. In embodiments, the channel structure 381 is formed of a circularly shaped material in the XY plane and extends in the Z direction. For example, the channel structure 381 includes functional layers having a circular shape in the XY plane and extending in the Z direction, such as a barrier insulating layer 382 (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) 383, a tunneling insulating layer 384 (e.g., silicon oxide), a semiconductor layer 385, and an insulating layer 386. In an example, the barrier insulating layer 382 (e.g., silicon oxide) is formed on the sidewalls of the holes for the channel structure 381, and then the charge storage layer (e.g., silicon nitride) 383, the tunneling insulating layer 384, the semiconductor layer 385, and the insulating layer 386 are sequentially stacked from the sidewalls. The semiconductor layer 385 can be any suitable semiconductor material, such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material can be undoped or may include p-type or n-type dopants. In some examples, the semiconductor material is undoped intrinsic silicon. However, due to defects, in some examples, the intrinsic silicon material can have approximately 10⁻⁶ ohms. 10 cm –3 The carrier density. The insulating layer 386 is formed of an insulating material such as silicon oxide and / or silicon nitride, and / or may be formed as an air gap.

[0078] According to some aspects of this disclosure, the channel structure 381 and the layer stack 390 together form a memory cell string 380. For example, the semiconductor layer 385 corresponds to the channel portion for transistors in the memory cell string 380, and the gate layer 395 corresponds to the gate of the transistors in the memory cell string 380. Typically, the transistor has a gate controlling the channel and has a drain and a source at each side of the channel. For simplicity, in Figure 3 In the example, Figure 3The upper side of the channel in a transistor is called the drain, and Figure 3 The bottom side of the channel in a transistor is called the source. It should be noted that the drain and source can be switched in certain drive configurations. Figure 3 In the example, semiconductor layer 385 corresponds to the connection channel of the transistor. For a particular transistor, the drain of the particular transistor is connected to the source of the upper transistor above the particular transistor, and the source of the particular transistor is connected to the drain of the lower transistor below the particular transistor. Thus, the transistors in the memory cell string 380 are connected in series.

[0079] The storage cell string 380 includes storage cell transistors (or storage cells). The storage cell transistors can have different threshold voltages based on the number of charge carriers captured in a portion of the charge storage layer 383 corresponding to the floating gate used for the storage cell transistor. For example, when a significant amount of holes are captured (stored) in the floating gate of the storage cell transistor, the threshold voltage of the storage cell transistor is below a predefined value, and the storage cell transistor is in an unprogrammed state (also known as an erased state) corresponding to logic "11" in two binary bits. When holes are expelled from the floating gate (or electrons are captured in the floating gate), the threshold voltage of the storage cell transistor increases, thus allowing the storage cell transistor to be programmed to other suitable states, such as S2, S3, etc.

[0080] The memory cell string 380 includes one or more top select transistors configured to couple / decouple memory cells in the memory cell string 380 from bit lines, and includes one or more bottom select transistors configured to couple / decouple memory cells in the memory cell string 380 from ACS.

[0081] The top-select transistor is controlled by the top-select gate (TSG). For example, when the TSG voltage (the voltage applied to the TSG) is greater than the threshold voltage of the top-select transistor, the top-select transistor is turned on and the memory cell is coupled to the bit line; and when the TSG voltage (the voltage applied to the TSG) is less than the threshold voltage of the top-select transistor, the top-select transistor is turned off and the memory cell is decoupled from the bit line.

[0082] Similarly, the bottom-select transistor is controlled by the bottom-select gate (BSG). For example, when the BSG voltage (the voltage applied to the BSG) is greater than the threshold voltage of the bottom-select transistor, the bottom-select transistor is turned on and the memory cell is coupled to the ACS; and when the BSG voltage (the voltage applied to the BSG) is less than the threshold voltage of the bottom-select transistor, the bottom-select transistor is turned off and the memory cell is decoupled from the ACS.

[0083] According to some aspects of this disclosure, the bottom portion of the semiconductor layer 385 in the channel hole corresponds to the source side of the vertical memory cell string 380, and the bottom portion is designated as 385(S). A common source layer 389 is formed to be electrically connected to the source of the vertical memory cell string 380. The common source layer 389 may include one or more layers. In some examples, the common source layer 389 includes a silicon material, such as intrinsic polysilicon, doped polysilicon (e.g., N-type doped silicon, P-type doped silicon), etc. In some examples, the common source layer 389 may include a metal silicide to improve conductivity. The common source layer 389 is similarly electrically connected to the source of other vertical memory cell strings (not shown), and thus forms an array common source (ACS).

[0084] In some examples, when the vertical memory cell string 380 is configured to be erased by block, the common source layer 389 can extend and cover the core area of ​​the block as well as the step area of ​​the block. In some examples, the common source layer 389 can be appropriately insulated for different blocks that are being erased individually.

[0085] exist Figure 3 In the example, in channel structure 381, semiconductor layer 385 extends vertically upward from the source side of channel structure 381 and forms the top portion corresponding to the drain side of vertical memory cell string 380. The top portion of semiconductor layer 385 is labeled 385(D). It should be noted that the naming of drain side and source side is for ease of description. Drain side and source side may serve functions different from their names.

[0086] exist Figure 3 In the example, connection structures (such as vias 372 with metal lines 373, bonding structures 374, etc.) can be formed to electrically couple the top portion of the semiconductor layer 385(D) to the bit line (BL).

[0087] In addition, Figure 3 In the example, the step region 307 includes steps formed to facilitate word line connections to the gates of transistors (e.g., memory cells, one or more top-select transistors, one or more bottom-select transistors). For example, the word line connection structure 370 includes contact structures 371, via structures 372, and metal lines 373 electrically coupled together. The word line connection structure 370 can electrically couple WL to the gate terminals of transistors in the memory cell string 380.

[0088] exist Figure 3 In the example, array die 302 and CMOS die 301 are positioned face-to-face (circuit side is the front, and substrate side is the back) and bonded together. Typically, peripheral circuitry on the CMOS die interfaces the semiconductor memory device 300 with external circuitry.

[0089] exist Figure 3 In the example, CMOS die 301 and array die 302 each include bonding structures that can be aligned with each other. For example, CMOS die 301 includes bonding structure 334, and array die 302 includes a corresponding bonding structure 374. Array die 302 and CMOS die 301 can be properly aligned such that bonding structure 334 is aligned with bonding structure 374. When array die 302 and CMOS die 301 are bonded together, bonding structure 334 is bonded to and electrically coupled to bonding structure 374, respectively.

[0090] Figure 4 A block diagram of a group-based verification start loop determination circuit 430 according to some embodiments of the present disclosure is shown. The group-based verification start loop determination circuit 430 can be used to replace the group-based verification start loop determination module 130 in the semiconductor memory device 100. For example, the group-based verification start loop determination circuit 430 is coupled to the page buffer circuit 112 and the memory 140, as... Figure 4 As shown in the image.

[0091] The group-based verification start loop determination circuit 430 is configured to detect sensing results during a first programming verification loop performed in response to a first write operation to a first word line in the word line group, and to determine a verification start loop with multiple states based on the sensing results during the first programming verification loop. The verification start loops with multiple states can be stored in memory 140 associated with the word line group. Furthermore, in response to a second write operation to a second word line in the word line group, the group-based verification start loop determination circuit 430 can access memory 140 to retrieve the verification start loops with multiple states associated with the word line group. A second programming verification loop with the retrieved verification start loops with multiple states can then be executed during the second write operation.

[0092] Specifically, in Figure 4 In the example, the group-based verification start loop determination circuit 430 includes a first counter circuit 431, a second counter circuit 432, a comparator circuit 433, and a selection circuit 444 coupled together, such as Figure 4 As shown in the image.

[0093] In some examples, the first counter circuit 431 is coupled to a latch circuit in the page buffer circuit 112. The latch circuit is coupled to a bit line, and the value in the latch circuit can indicate the programming state of the memory cell coupled to the bit line. For example, when the memory cell coupled to the bit line is fully programmed (the threshold voltage is within the range corresponding to the state used to write multiple bit values ​​to the memory cell), the memory cell is turned on during state verification, and the value associated with the bit line in the latch circuit switches, for example, from "0" to "1". The first counter circuit 431 can count the total number of memory cells turned on in each state (referred to as the total number of turned-on memory cells in each state) based on the value in the latch circuit.

[0094] The second counter circuit 432 is configured to count loops in the programming verification loop. The comparator circuit 433 is configured to compare the total number of active memory cells of a state with a threshold. In some examples, the same threshold is used for all states. In other examples, different thresholds may be used for different states. In one example, when the total number of active memory cells is equal to or greater than the threshold, the comparator circuit 433 may cause the loop counted by the second counter circuit 432 to be stored as the verification start loop of the state in the memory 140 associated with the word line group.

[0095] The memory 140 can store the state of the group-based verification start loop in various forms. Figure 5 A table is shown, displaying values ​​stored as associated with state and word line groups. Each value is associated with a state and a word line group. When the state and word line groups are provided, the values ​​associated with those groups can be located and retrieved.

[0096] Re-reference Figure 4 The selection circuit 444 can retrieve the verification start loop associated with the state of the word line group based on state and word line information. For example, the selection circuit 444 can determine the word line group based on the word line information and then locate and retrieve the verification start loop associated with the state and word line group. In some examples, the memory 140 includes registers configured to store verification start loops and indexed based on the state and word line group. The selection circuit 444 includes a multiplexer (MUX) coupled to the registers. Thus, the MUX selects one of the registers based on the state and word line group and outputs the value of the selected register from the selection circuit 444 as the verification start loop.

[0097] In some embodiments, memory 140 is implemented as a volatile memory and a register that may lose stored data in response to power-off (or power failure). In some examples, in response to power-on, the value in memory 140 is reset to one or more default values, such as 0 or the verification start loop with the earliest verification start loop of the state. Then, in order to perform a first write to a first word line in the word line group (the first word line can be any word line in the word line group), selection circuit 444 outputs a default value associated with the state. When the default value is detected, the first write to the first word line in the word line group can be performed using a first programming verification loop with the default verification start loop of the state (e.g., the earliest verification start loop of the state). Group-based verification start loop determination circuit 430 can determine an updated verification start loop of the state based on sensing results during the first programming verification loop, and the updated verification start loop of the state can be stored in memory 140 associated with the word line group. Then, in subsequent writes to word lines in the word line group, the updated verification start loop of the state can be retrieved and used in subsequent programming verification loops.

[0098] Therefore, in some examples, when the programming speed changes, for example, when the PE cycle increases, the verification start loop for the word line group can be reset and redefined in response to power-on.

[0099] In some other embodiments, the reset and re-determination of the verification start loop for the state of the word line group can be triggered by other suitable triggers such as timers, reset commands, etc.

[0100] Word line groups can be defined appropriately. In some examples, word line groups are based on a single word line, so each word line group includes a single word line. In some other examples, word line groups are based on a segment, so each word line group includes multiple word lines. In some still examples, word line groups are based on a memory block, so each word line group includes one or more memory blocks.

[0101] Word lines can be determined and defined using various techniques. In some examples, word lines are determined based on programming speed characteristics.

[0102] Figure 6A flowchart outlining a process 600 for determining and defining word line groups according to some embodiments of the present disclosure is shown. In some examples, process 600 is performed by a semiconductor memory device provider that supplies semiconductor memory devices (e.g., semiconductor memory device 100, semiconductor memory device 300, etc.). In some examples, the semiconductor memory device includes a first die (e.g., an array die) and a second die (e.g., a CMOS die). The first die includes a memory cell array, and the second die includes peripheral circuitry for the memory cell array. The first and second dies are joined together such that the peripheral circuitry is electrically coupled to the memory cell array. Process 400 begins at S601 and proceeds to S610.

[0103] At S610, the word line groups of a semiconductor memory device are determined based on programming speed characterization. In some examples, samples of the semiconductor memory device are tested to determine programming speed characteristics, such as word line programming speed, programming speed variation during PE cycles, etc. Based on the programming speed characterization, word lines can be divided into word line groups. Word line groups can include single word lines, segments of word lines, or blocks of word lines.

[0104] At S620, a word line group is defined in the semiconductor memory device. In some examples, the word line group is defined to implement an algorithm in the firmware. In other examples, the word line group is defined as a configuration stored in the initialization partition 165. The process then proceeds to S699 and terminates.

[0105] Figure 7 A flowchart outlining a process 700 according to some embodiments of the present disclosure is shown. In some examples, process 700 is performed by a write control section (e.g., write control 123). Process 700 begins at S701 and proceeds to S710.

[0106] At S710, write control 123 receives an instruction for a write operation to write data to a page associated with a word line.

[0107] At S720, write control 123 determines whether the write operation is the first write operation to the word line group. If the write operation is the first write operation to the word line group, the process proceeds to S730; otherwise, the process proceeds to S760.

[0108] At S730, the write operation is the first write to the word line group, and write control 123 can cause a first programming verification loop to execute. The first programming verification loop is executed to write data to the page associated with the word line. In some examples, the first programming verification loop uses a default verification start loop for the state, which is designed to perform state verification at the earliest loop to avoid programming errors. Furthermore, write control 123 can monitor the sensing results of the verification during the first programming verification loop. For example, write control 123 can count the total number of active memory cells for each state, which can be increased by loops within the first programming verification loop.

[0109] At S740, write control 123 compares the total number of active memory cells of the state with a threshold to determine the verification start loop of the state. For example, for a state, write control 123 compares the total number of active memory cells of the state (e.g., including memory cells active by previous loops) with a threshold, and determines the loop as the verification start loop when the total number of active memory cells at the loop is equal to or greater than the threshold.

[0110] At S750, for example, write control 123 stores the verification start cycle of the state associated with the word line group in memory 140. Then, the process proceeds to S799, and the write operation is completed.

[0111] At S760, the write operation is not the first write to the word line group, so the write control 123 performs a verification start loop, for example, by retrieving the state associated with the word line group from memory 140.

[0112] At S770, write control 123 executes the second programming verification loop according to the verification start loop of the status, and writes the data to the page associated with the word line. Then, the process proceeds to S799, and the write operation is completed.

[0113] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor memory device, comprising: A storage cell array, the storage cell array comprising storage cell blocks; as well as Peripheral circuitry, coupled to the memory cell array, is configured as follows: In response to a first write operation to a first word line in a word line group comprising one or more word lines, a first programming verification loop is executed, thereby programming the memory cell associated with the first word line into multiple states; The verification start loop for the plurality of states is determined based on the sensing results in the first programming verification loop; and A second programming verification loop with the determined verification start loop having the plurality of states is executed in response to a second write operation to the second word line in the word line group.

2. The semiconductor memory device according to claim 1, wherein, The peripheral circuitry is configured to count the total number of active memory cells of the state during the first programming verification cycle, and to determine the cycle as the verification start cycle of the state when the total number of active memory cells of the state at the cycle meets the requirement.

3. The semiconductor memory device according to claim 2, wherein, The peripheral circuit includes: A first counter circuit is configured to count the total number of on-memory cells in the state. A second counter circuit, configured to count the number of iterations in the first programming verification loop; and A comparison circuit is configured to compare the total number of on-memory cells of the state with a threshold, and to store the loop number as the verification start loop of the state in response to the total number of on-memory cells of the state being equal to or greater than the threshold.

4. The semiconductor memory device according to claim 1, wherein, The peripheral circuit includes: A page buffer circuit having a latch circuit coupled to a bit line, wherein the value in the latch circuit indicates the sensing result in the first programming verification cycle.

5. The semiconductor memory device according to claim 1, wherein, The peripheral circuit includes: A memory configured to store the determined verification start loop of the plurality of states associated with the word line group.

6. The semiconductor memory device according to claim 5, wherein, The memory is a volatile memory that loses the determined verification start loop of the plurality of states in response to a power outage.

7. The semiconductor memory device according to claim 1, wherein, The peripheral circuitry is configured to execute the first programming verification loop in response to the first write operation on the first word line in the word line group after the semiconductor memory device is powered on.

8. The semiconductor memory device according to claim 1, wherein, The word line group is defined as at least one of the following: Including the first character line; Including the first word line and one or more other word lines of the memory cell block; and Includes the aforementioned storage unit block.

9. The semiconductor memory device according to claim 1, wherein, The word line group is defined in the non-volatile portion of the semiconductor memory device.

10. The semiconductor memory device according to claim 1, wherein, The second character line is the first character line or another character line in the character line group.

11. The semiconductor memory device according to claim 1, wherein, The multiple states each represent the value of a multiple binary bit.

12. A method for programming a semiconductor memory device, comprising: A first programming verification loop is executed in response to a first write operation to a first word line in a word line group comprising one or more word lines, the first programming verification loop programming the memory cell associated with the first word line in the word line group into multiple states; Based on the sensing results during the first programming verification loop, the verification start loop for the plurality of states is determined; as well as In response to a second write operation to a second word line in the word line group, a second programming verification loop with the determined verification start loop having the plurality of states is executed.

13. The method according to claim 12, wherein, The verification start loop, which determines the plurality of states based on the sensing results during the first programming verification loop, further includes: Count the total number of active memory cells in the state; and When the total number of active memory cells in the looped state meets the requirement, the loop is determined as the verification start loop for the state.

14. The method of claim 13, further comprising: The total number of active memory cells in the stated state is compared with a threshold. as well as The verification start loop is determined based on the results of the comparison.

15. The method of claim 12, further comprising: The value in the latch circuit coupled to the sensing line indicates the sensing result during the first programming verification cycle.

16. The method of claim 12, further comprising: The determined verification start loop of the plurality of states associated with the word line group is stored in memory.

17. The method according to claim 16, wherein, The memory is a volatile memory that loses the determined verification start loop of the plurality of states in response to a power outage.

18. The method according to claim 12, wherein, Executing the first programming verification loop in response to the first write operation on the first word line in the word line group further includes: After the semiconductor memory device is powered on, the first programming verification loop is executed in response to the first write operation on the first word line in the word line group.

19. The method according to claim 12, wherein, The semiconductor memory includes blocks of memory cells, and the word line group is defined as at least one of the following: Including the first character line; Including the first word line and one or more other word lines of the memory cell block; and Includes the aforementioned storage unit block.

20. The method according to claim 12, wherein, The word line group is defined in the non-volatile portion of the semiconductor memory device.

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