Package including a substrate configured as a heat sink

Abstract

A package includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat sink. The second substrate is configured to have no electrical connection to the integrated device.

Description

[0001] Priority requirements

[0002] This patent application claims priority to U.S. non-patent application number 16 / 789,272, filed February 12, 2020, entitled “PACKAGE COMPRISING ASUBSTRATE CONFIGURED AS A HEAT SPREADER”, which is assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] Various features relate to packages that include integrated devices, but more specifically to a package that includes integrated devices and a substrate configured as a heat spreader. Background Technology

[0004] Figure 1 The illustration shows a package 100 including a substrate 102, an integrated device 104, and an encapsulation layer 106. The substrate 102 includes multiple dielectric layers 120, multiple interconnects 122, and multiple solder interconnects 124. Multiple solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. The encapsulation layer 106 encapsulates the integrated device 104 and the multiple solder interconnects 144. Heat dissipation in the package 100 is always a challenge, which can affect the performance of the package 100. There is a constant need for packages with better performance. Summary of the Invention

[0005] Various features relate to packages that include integrated devices, but more specifically to a package that includes integrated devices and a substrate configured as a heat sink.

[0006] One example provides a package including a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first and second substrates. The second substrate is configured to operate as a heat sink. The second substrate is configured to have no electrical connection to the integrated device.

[0007] Another example provides an apparatus including a first substrate, an integrated device coupled to the substrate, a heat dissipation component coupled to the integrated device, and an encapsulation layer located between the first substrate and the heat dissipation component. The heat dissipation component is configured not to have an electrical connection to the integrated device.

[0008] Another example provides a method for fabricating a package. The method provides a first substrate. The method couples an integrated device to the first substrate. The method couples a second substrate to the integrated device. The second substrate is configured to operate as a heat sink. The second substrate is configured to have no electrical connection to the integrated device. The method forms an encapsulation layer between the first and second substrates. Attached Figure Description

[0009] When taken in conjunction with the accompanying drawings, various features, properties and advantages will become apparent from the detailed description set forth below, wherein the same reference numerals are used to identify them accordingly throughout.

[0010] Figure 1 The illustration shows a cross-sectional view of the package, which includes integrated devices and a substrate.

[0011] Figure 2 The illustration shows a cross-sectional view of a package including a substrate configured as a heat sink.

[0012] Figure 3 The illustration shows a cross-sectional view of a package that includes another substrate configured as a heat sink.

[0013] Figure 4 The illustration shows a cross-sectional view of a package that includes another substrate configured as a heat sink.

[0014] Figure 5 The illustration shows a close-up view of a substrate configured as a heat sink.

[0015] Figure 6 (including) Figures 6A to 6B The illustration shows an exemplary sequence for fabricating a substrate configured as a heat sink.

[0016] Figure 7 An exemplary flowchart of a method for fabricating a substrate configured as a heat sink is illustrated.

[0017] Figure 8 (including) Figures 8A to 8D The illustration shows an exemplary sequence for fabricating a package that includes a substrate configured as a heat sink.

[0018] Figure 9 (including) Figures 9A to 9B The illustration shows an exemplary sequence for fabricating a package that includes a substrate configured as a heat sink.

[0019] Figure 10 An exemplary flowchart of a method for fabricating a package including a substrate configured as a heat sink is illustrated.

[0020] Figure 11 The illustrations depict various electronic devices that can integrate the dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Detailed Implementation

[0021] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, it will be understood by those skilled in the art that various aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring various aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure various aspects of this disclosure.

[0022] This disclosure describes a package including a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first and second substrates. The second substrate is configured to operate as a heat sink. The second substrate is configured to have no electrical connection to the integrated device. The second substrate may have a second coefficient of thermal expansion (CTE) similar to that of the first substrate. Due to the fact that the first and second substrates have similar CTEs, this configuration can provide a package with improved heat dissipation while also reducing, minimizing, and / or eliminating package warpage. In some embodiments, the CTEs of the first and second substrates may be similar to the CTE of the integrated device.

[0023] An exemplary package including a substrate configured as a heat sink

[0024] Figure 2 The illustration shows a cross-sectional view of a package 200 including a substrate configured as a heat sink. The package 200 may be a molded embedded package (MEP). The package 200 is coupled to a board 290 (e.g., a printed circuit board (PCB)) via multiple solder interconnects 250.

[0025] like Figure 2 As shown, package 200 includes a first substrate 202, an integrated device 204, a second substrate 206, an encapsulation layer 208, an underfill 280, and a thermal interface material (TIM) 282. The integrated device 204 is coupled to the first substrate 202. The second substrate 206 is coupled to the integrated device 204. The encapsulation layer 208 is coupled to the first substrate 202 and the second substrate 206 such that the encapsulation layer 208 is located between the first substrate 202 and the second substrate 206. The second substrate 206 is configured to operate as a heat sink. The second substrate 206 can be a heat dissipation component. The second substrate 206 can be an interposer. The second substrate 206 is configured to have no electrical connection to the integrated device 204. For example, the second substrate 206 is configured not to be electrically coupled to the circuitry of the integrated device 204.

[0026] The first substrate 202 may have a first coefficient of thermal expansion (CTE) of approximately 7 to 15 parts per million (ppm / C). The second substrate 206 may have a second coefficient of thermal expansion (CTE) of approximately 7 to 15 parts per million (ppm / C). The second CTE of the second substrate 206 may be similar to (e.g., closely matched) the first CTE of the first substrate 202. Excessive mismatch of CTEs of different components of the package 200 may cause warping of the package 200, which may lead to package failure. When the first CTE of the first substrate 202 and the second CTE of the second substrate 206 are similar (e.g., closely matched), the warping of the package 200 is reduced, minimized, and / or eliminated, thereby providing a more reliable package with a lower probability of failure. Moreover, the first substrate 202 and the second substrate 206 may each have a CTE similar to (e.g., closely matched) the CTE of the integrated device 204. The integrated device 204 may have a CTE of approximately 7 parts per million (ppm / C). The second CTE of the second substrate 206 can be specified by patterning multiple interconnects 262 with a specific design and / or by using a specific type of material for the dielectric layer 260.

[0027] The second substrate 206 offers numerous advantages and benefits. In addition to being configured as a heat sink with a CTE (Coefficient of Thermal Expansion), which can be configured to be similar to the CTE of the first substrate 202 and / or the CTE of the integrated device 204, the second substrate 206 can also be fabricated using inexpensive processes, thus providing an inexpensive component that can be configured as a heat sink. As will be further described below, the second substrate 206 can also be a relatively thin and balanced substrate structure comprising a dielectric layer and multiple interconnects (e.g., vias).

[0028] The first substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226. The plurality of interconnects 222 are located (e.g., formed) in and / or on the at least one dielectric layer 220. The first substrate 202 may be a laminated substrate that includes the aforementioned dielectric layer and interconnects. In some embodiments, the first substrate 202 may include an organic substrate, glass, and / or quartz.

[0029] A first solder resist layer 224 is located on a first surface of the first substrate 202 (e.g., the top surface of a surface-facing integrated device). For example, the first solder resist layer 224 may be formed on at least one dielectric layer 220. A second solder resist layer 226 is located on a second surface of the first substrate 202 (e.g., the bottom surface of a surface-facing plate). For example, the second solder resist layer 226 may be formed on at least one dielectric layer 220. In some embodiments, the first solder resist layer 224 and / or the second solder resist layer 226 may be optional.

[0030] Integrated device 204 is coupled to a first substrate 202 via a plurality of interconnects 240. The plurality of interconnects 240 may be coupled to interconnects from a plurality of interconnects 222. The plurality of interconnects 240 may include pillars, which may be considered part of integrated device 204. In some embodiments, the plurality of interconnects 240 may be coupled to the plurality of interconnects 222 via solder interconnects. Integrated device 204 includes a front side (which may be an active side) and a back side. Integrated device 204 is coupled to a first substrate 202 and a second substrate 206 such that the front side of integrated device 204 faces the first substrate 202 and the back side of integrated device 204 faces the second substrate 206. Underfill 280 may be located between integrated device 204 and the first substrate 202. Underfill 280 may laterally surround the plurality of interconnects 240. Underfill 280 may also be located on the sides of integrated device 204.

[0031] Encapsulation layer 208 is coupled to a first substrate 202 and a second substrate 206 such that encapsulation layer 208 is located between the first substrate 202 and the second substrate 206. Encapsulation layer 208 may be located above a first solder mask layer 224 on the first substrate 202. Encapsulation layer 208 may be coupled to the first substrate 202 and the second substrate 206 such that encapsulation layer 208 at least laterally encapsulates integrated device 204. Encapsulation layer 208 may include a mold, resin, polymer, and / or epoxy resin.

[0032] The second substrate 206 is coupled to the back side of the integrated device 204 via a TIM 282. The TIM 282 can be an adhesive material with high thermal conductivity (e.g., greater than 0.5 W / mK). The TIM 282 may have a CTE of approximately 20 to 200 ppm / C. The TIM 282 can be coupled to the back side of the integrated device 204 and the second substrate 206. The TIM 282 can be used to ensure that there are no voids or very few voids between the integrated device 204 and the second substrate 206. Reducing, minimizing, and / or eliminating voids is important because voids can act as insulators, and therefore voids can reduce the heat dissipation and / or heat dissipation of the second substrate 206. Using the TIM 282 helps to reduce, minimize, and / or eliminate voids, which helps to improve the heat dissipation and / or heat dissipation capabilities of the second substrate 206. The TIM 282 can be coupled to the side of the integrated device 204. In some implementations, the second substrate 206 may contact the integrated device 204 (e.g., touch the back side of the integrated device 204).

[0033] The second substrate 206 includes a dielectric layer 260, a plurality of interconnects 262, and at least one solder mask layer 264. The second substrate 206 may be an interposer. As mentioned above, the second substrate 206 may be configured as a heat sink and / or heat dissipator. The second substrate 206 may be a component for heat dissipation. Specifically, the plurality of interconnects 262 may be configured to operate as a heat sink and / or heat dissipator. The plurality of interconnects 262 are configured to have no electrical connection to the integrated device 204 and / or the first substrate 202 (e.g., no electrical connection to the integrated device 204 when it is in operation). The plurality of interconnects 262 may include vias, traces, and / or pads. The second substrate 206 may include a different number of interconnects (e.g., a different number of vias). In some embodiments, some vias may be fabricated and combined to form larger vias. In some embodiments, the vias of the plurality of interconnects 262 may include vias that are separated from each other, such that two or more vias are not coupled together. In some embodiments, one or more vias of the plurality of interconnects 262 may include vias recessed from the surface (e.g., bottom surface, top surface) of the second substrate (e.g., 206). The dielectric layer 260 may include glass, silicon, quartz, and / or combinations thereof.

[0034] Solder resist layer 264 may be located on the surface of the second substrate 206 facing the integrated device 204 and / or the first substrate 202. Solder resist layer 264 may be configured to provide improved adhesion. Solder resist layer 264 is coupled to dielectric layer 260 and encapsulation layer 208.

[0035] The overall thickness of the package 200, including the second substrate 206, is significantly thinner than other packages with other types of heat sinks. In some embodiments, the package 200 and the second substrate 206 may have a total thickness of about 1 millimeter (mm) or less (e.g., 1000 micrometers (μm) or less). In some embodiments, the plurality of solder interconnects 250 may have a thickness of about 200 micrometers or less, the first substrate 202 may have a thickness of about 400 micrometers or less, the integrated device 204 and the encapsulation layer 208 may each have a thickness of about 200 micrometers or less, and the second substrate 206 may have a thickness of about 200 micrometers or less.

[0036] Figure 2 The illustration shows a second substrate 206 including a via with approximately vertical sidewalls. However, different embodiments may include vias with different shapes and / or configurations.

[0037] Figure 3The illustration shows a package 300 including a substrate configured as a heat sink. Package 300 is similar to package 200 and includes components similar to those in package 200. Package 300 includes a second substrate 306 configured as a heat sink. Package 300 includes a first substrate 202, an integrated device 204, a second substrate 306, an encapsulation layer 208, an underfill 280, and a thermal interface material (TIM) 282. The second substrate 306 may be configured to have no electrical connection to the integrated device 204 and / or the first substrate 202.

[0038] The second substrate 306 is similar to the second substrate 206 of package 200. The second substrate 306 includes a dielectric layer 260, a plurality of interconnects 362, and at least one solder mask layer 264. The second substrate 306 may be an interposer. As mentioned above, the second substrate 306 may be configured as a heat sink and / or heat dissipator. The second substrate 306 may be a component for heat dissipation. Specifically, the plurality of interconnects 362 may be configured to operate as a heat sink and / or heat dissipator. The plurality of interconnects 362 are configured not to have electrical connections to the integrated device 204 and / or the first substrate 202. The plurality of interconnects 362 may include vias, traces, and / or pads.

[0039] like Figure 3 As shown, the vias from multiple interconnects 362 include diagonal sidewalls. Therefore, from Figure 3 Multiple interconnecting vias of 362 can have connections with those from... Figure 2 The vias of the multiple interconnect 262 have different shapes and / or designs. The difference in via shape may be due to the materials used in fabrication. Figure 2 vias and Figure 3 Different manufacturing processes for vias.

[0040] Similar to Figure 2 The second substrate 306 may have a second coefficient of thermal expansion (CTE) of approximately 7 to 15 parts per million (ppm / °C). The second CTE of the second substrate 206 may be similar to (e.g., closely matched) the first CTE of the first substrate 202. Moreover, the first substrate 202 and the second substrate 306 may each have a CTE similar to (e.g., closely matched) the CTE of the integrated device 204.

[0041] Figure 4The illustration shows a package 400 including a substrate configured as a heat sink. Package 400 is similar to package 300 and includes components similar to those in package 300. Package 400 includes a second substrate 406 configured as a heat sink. Package 400 includes a first substrate 202, an integrated device 204, a second substrate 406, an encapsulation layer 208, an underfill 280, and a thermal interface material (TIM) 282. The second substrate 406 may be configured to have no electrical connection to the integrated device 204 and / or the first substrate 202.

[0042] The second substrate 406 is similar to the second substrate 406 of package 300. In some embodiments, the second substrate 406 may be a more detailed representation of the second substrate 306. The second substrate 406 includes a dielectric layer 260, a plurality of interconnects 342, and at least one solder mask layer 264. The second substrate 406 may be an interposer. As mentioned above, the second substrate 406 may be configured as a heat sink and / or heat dissipator. The second substrate 406 may be a component for heat dissipation. Specifically, the plurality of interconnects 462 may be configured to operate as a heat sink and / or heat dissipator. The plurality of interconnects 462 are configured not to have electrical connections to the integrated device 204 and / or the first substrate 202. The plurality of interconnects 462 may include vias, traces, and / or pads.

[0043] Similar to Figure 2 The second substrate 406 may have a second coefficient of thermal expansion (CTE) of approximately 7 to 15 parts per million (ppm / °C). The second CTE of the second substrate 206 may be similar to (e.g., closely matched) the first CTE of the first substrate 202. Moreover, the first substrate 202 and the second substrate 406 may each have a CTE similar to (e.g., closely matched) the CTE of the integrated device 204.

[0044] like Figure 4 As shown, vias from a plurality of interconnects 462 include diagonal sidewalls. One or more interconnects (e.g., vias) from the plurality of interconnects 462 may be defined by one or more metal layers. For example, a via may be defined by a first metal layer 461 (e.g., a first copper layer) and a second metal layer 463 (e.g., a second copper layer).

[0045] Figure 5A close-up view of a second substrate 406 is illustrated. As mentioned above, the second substrate 406 includes a dielectric layer 260, a plurality of interconnects 462, and at least one solder mask layer 264. The plurality of interconnects 462 may be defined by one or more metal layers. For example, interconnects (e.g., vias) from the plurality of interconnects 462 may be defined by a first metal layer 461 and a second metal layer 463. The first metal layer 461 may include a metal layer 461a over a first surface (e.g., a bottom surface) of the dielectric layer 260, a metal layer 461b over a second surface (e.g., a top surface) of the dielectric layer 260, and a metal layer 461c over a side surface of the dielectric layer 260. The first metal layer 461 may be a seed metal layer. The metal layers (461a, 461b, 461c) may be continuous and / or continuous metal layers. In some embodiments, the metal layers (461a, 461b, 461c) may be separate metal layers. In some embodiments, the second substrate 406 may include a metal layer 562 formed over the bottom and / or top sides of the plurality of interconnects 462. The metal layer 562 may include nickel (Ni). A dielectric layer 260 may be formed over the metal layer 562 and / or the plurality of interconnects 462. The metal layer 562 may be implemented in any substrate described in this disclosure (e.g., the second substrate 206).

[0046] Various packages having different substrates configured as heat sinks have been described, and the sequence of substrates used to fabricate the substrates configured as heat sinks will now be described below.

[0047] Exemplary sequence for fabricating a substrate configured as a heat sink

[0048] Figure 6 (including) Figures 6A to 6B The illustration shows an exemplary sequence of materials for providing or fabricating a substrate configured as a heat sink. In some embodiments, Figures 6A to 6B The sequence can be used to provide or create Figure 4 The second substrate 406 or any substrate described in this disclosure.

[0049] It should be noted that Figures 6A to 6B The sequence can be combined with one or more stages to simplify and / or clarify the sequence for providing or fabricating a substrate configured as a heat sink. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of this disclosure.

[0050] like Figure 6A As shown, Stage 1 illustrates the state after substrate 600 is provided. Substrate 600 includes a dielectric layer 260, a metal layer 602, and a metal layer 604. Metal layer 602 and / or metal layer 604 may include copper. Metal layer 602 may correspond to... Figure 4Metal layer 461b. Metal layer 604 can correspond to Figure 4 Metal layer 461a. Metal layers 602 and 604 can be seed layers.

[0051] Stage 2 illustrates the state after cavity 619 is formed in substrate 600. Cavity 619 is formed through metal layer 602, dielectric layer 260, and metal layer 604. Laser processes (e.g., laser ablation) can be used to form cavity 619.

[0052] Stage 3 illustrates the state after a metal layer 620 has been formed on the sidewall of cavity 619. An electroplating process (e.g., an electroless electroplating process) can be used to form the metal layer 620 on the sidewall of cavity 619. The metal layer 620 can correspond to... Figure 4 The metal layer 461c.

[0053] Stage 4 illustrates the state after a photoresist layer is formed on the substrate 600. A first photoresist layer 622 may be formed on the surface of the substrate 600 (e.g., the top surface), and a second photoresist layer 624 may be formed on the surface of the substrate 600 (e.g., the bottom surface).

[0054] like Figure 6B As shown, stage 5 illustrates the state after the second metal layer 463 is formed on the substrate 600. The second metal layer 463 can be formed using an electroplating process. The second metal layer 463 can be formed on metal layers 620, 602, and / or 604. The second metal layer 463 can be located in the cavity 619 and / or on the substrate 600. Stage 5 illustrates a plurality of interconnects 462 defined by the second metal layer 463, metal layer 620, metal layer 602, and / or metal layer 604.

[0055] Phase 6 illustrates the state after the photoresist layer (e.g., 622, 624) has been removed from the substrate 600.

[0056] Phase 7 illustrates the state after portions of metal layer 602 and metal layer 604 have been removed. In some embodiments, any metal layer 602 or any metal layer 604 not covered by the second metal layer 463 is removed.

[0057] Stage 8 illustrates the state after a solder resist layer 264 has been formed over the dielectric layer 260. An electroplating process may be used to form at least one solder resist layer 264. Stage 8 may also illustrate a second substrate 406 including a dielectric layer 260, a plurality of interconnects 462 (which may be defined by a first metal layer 461 and a second metal layer 463), and at least one solder resist layer 264.

[0058] In some embodiments, (e.g., a metal layer (e.g., 562) may be formed over the bottom and / or top sides of the plurality of interconnects 462. (e.g., the metal layer (e.g., 562) may be formed prior to the formation of at least one solder mask layer 264.) The solder mask layer 264 may be formed over the metal layer (e.g., 562). Note that the sequence and processes used to fabricate the second substrate 406 may also be used to fabricate the first substrate 202. In some embodiments, different sequences and / or processes may be used to fabricate the first substrate 202.

[0059] Exemplary flowchart of a method for fabricating a substrate configured as a heat sink

[0060] In some implementations, fabricating a substrate configured as a heat sink includes several processes. Figure 7 An exemplary flowchart of a method 700 for providing or fabricating a substrate configured as a heat sink is illustrated. In some embodiments, Figure 7 Method 700 can be used to provide or make the product described in this disclosure. Figure 4 The second substrate. However, method 700 can be used to provide or manufacture any substrate described in this disclosure.

[0061] It should be noted that, in order to simplify and / or clarify the methods for providing or fabricating a substrate configured as a heat sink, Figure 7 The sequence can combine one or more processes. In some implementations, the order of the processes can be changed or modified.

[0062] The method (at 705) provides a substrate (e.g., 600) comprising a dielectric layer (e.g., 260) and metal layers (e.g., 602, 604). The substrate 600 may be fabricated or supplied by a vendor. Metal layers 602 and / or 604 may comprise copper. Metal layer 602 may correspond to… Figure 4 Metal layer 461b. Metal layer 604 can correspond to Figure 4 Metal layer 461a. Metal layers 602 and 604 can be seed layers. Figure 6A Phase 1 is illustrated and described as an example of a substrate including a metal layer.

[0063] The method (at 710) forms a plurality of cavities (e.g., 619) in a substrate (e.g., 600). Cavities 619 may be formed by a metal layer 602, a dielectric layer 260, and a metal layer 604. A laser process (e.g., laser ablation) may be used to form cavities 619. Figure 6A Stage 2 is illustrated and described as an example of cavity formation.

[0064] The method (at 715) forms a metal layer (e.g., 620) in a cavity (e.g., 619) of a substrate (e.g., 600). The metal layer 620 is formed on the sidewalls of the cavity 619. An electroplating process (e.g., an electroless electroplating process) can be used to form the metal layer 620 on the sidewalls of the cavity 619. The metal layer 620 can correspond to... Figure 4 The metal layer 461c. Figure 6A Stage 3 is illustrated and described as an example of metal formation in the cavity.

[0065] The method (at 720) provides a photoresist layer (e.g., 622, 624) on a substrate 600. A first photoresist layer 622 may be formed on a surface (e.g., top surface) of the substrate 600, and a second photoresist layer 624 may be formed on a surface (e.g., bottom surface) of the substrate 600. Figure 6A Phase 4 is illustrated and described as an example of providing a photoresist layer.

[0066] The method (at 725) forms a second metal layer (e.g., 463) on substrate 600. The second metal layer 463 can be formed using an electroplating process. The second metal layer 463 can be formed on metal layers 620, 602, and / or 604. The second metal layer 463 can be located in cavity 619 and / or on substrate 600. Forming the metal layer can define and / or form a plurality of interconnects 462 (e.g., vias). The plurality of interconnects 462 can be defined by the second metal layer 463, metal layer 620, metal layer 602, and / or metal layer 604. Figure 6B Phase 5 is illustrated and described as an example of providing a second metal layer to define the via.

[0067] This method (at 730) removes the photoresist layer (e.g., 622, 624). Figure 6B Stage 6 is illustrated and described as an example of photoresist layers (e.g., 622, 624) removed from substrate 600.

[0068] The method (at 735) removes one or more metal layers (e.g., 602, 604) from the substrate. In some embodiments, any metal layer 602 or any metal layer 604 not covered by the second metal layer 463 is removed. Metal layers 602 and 604 may be seed layers. Figure 6B Stage 7 is illustrated and described as an example of removing metal (e.g., 602, 604) from substrate 600.

[0069] The method involves forming (at 740) at least one solder resist layer (e.g., 264) on top of the dielectric layer 260. An electroplating process may be used to form at least one solder resist layer 264. Figure 6B Stage 8 illustrates an example of forming at least one solder resist layer 264.

[0070] In some embodiments, a metal layer (e.g., 562) may be formed over the bottom and / or top sides of the plurality of interconnects 462. The metal layer (e.g., 562) may be formed prior to the formation of at least one solder mask layer 264. The metal layer 562 may include nickel (Ni).

[0071] Exemplary sequence for fabricating a package including a substrate configured as a heat sink

[0072] Figure 8 (which includes) Figures 8A to 8D The illustration shows an exemplary sequence of packages for providing or fabricating a substrate configured as a heat sink. In some embodiments, Figures 8A to 8D The sequence can be used to provide or create including Figure 3 The second substrate 306 of the package 300, or any package described in this disclosure.

[0073] It should be noted that, Figures 8A to 8D The sequence of processes can be combined with one or more stages to simplify and / or clarify the sequence of processes for providing or fabricating a package comprising a substrate configured as a heat sink. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of this disclosure. Figures 8A to 8D The sequence can be used to manufacture one package or several packages (as part of a chip) at a time.

[0074] like Figure 8A As shown, Phase 1 illustrates the state after the second substrate 306 has been provided. The second substrate 306 includes a dielectric layer 260, a plurality of interconnects 362, and at least one solder resist layer 264. The second substrate 306 may be provided by a supplier or used by [other suppliers / familiar manufacturers]. Figures 6A to 6B The process described in the text is used to create it.

[0075] Phase 2 illustrates the state after the copper ball 810 is coupled to the second substrate 306. The copper ball 810 may include a copper core ball (CCB). The copper ball 810 may include solder. The copper ball 810 may be coupled to the bottom surface of the second substrate 306. The copper ball 810 may be coupled to at least one solder mask layer 264 of the second substrate 306. The copper ball 810 may be coupled near the edge and / or periphery of the second substrate 306.

[0076] Phase 3 illustrates the state after the first substrate 202 has been provided. The first substrate 202 can be provided by a supplier or manufactured by the supplier. Figures 6A to 6BA process similar to the one shown can be used to fabricate the first substrate 202. However, different embodiments may use different processes to fabricate the first substrate 202. Examples of processes that can be used to fabricate the first substrate 202 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The first substrate 202 may be a laminated substrate. The first substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222.

[0077] like Figure 8B As shown, stage 4 illustrates the state after the integrated device 204 is coupled to the first substrate 202. The integrated device 204 is coupled to the first substrate 202 via a plurality of interconnects 240. The plurality of interconnects 240 can be coupled to interconnects of a plurality of interconnects 222 from the first substrate 202. The plurality of interconnects 240 can be coupled to interconnects of the plurality of interconnects 222 via solder interconnects. The integrated device 204 can be coupled to the first substrate 202 such that the front side (e.g., the active side) of the integrated device 204 faces the first substrate 202.

[0078] Phase 5 illustrates the state after the underfill 280 is formed between the integrated device 204 and the first substrate 202. The underfill 280 can be formed such that the underfill 280 is coupled to the integrated device 204 and the first substrate 202.

[0079] like Figure 8C As shown, Stage 6 illustrates the state after TIM 282 is provided on the integrated device 204. TIM 282 can be provided on the integrated device 204 such that TIM 282 is coupled to the back side of the integrated device 204. Stage 6 also illustrates solder interconnects 820 provided on the first substrate 202. TIM 282 can be a fast-curing TIM.

[0080] Phase 7 illustrates the state after the second substrate 306, having copper balls 810, is coupled to the first substrate 202 and the integrated device 204. The second substrate 306 is coupled to the integrated device 204 via TIM 282. Specifically, the second substrate 206 is coupled to the integrated device 204 such that the back side of the integrated device 204 faces the second substrate 306. The copper balls 810 can be coupled to the first substrate 202 via solder interconnects 820.

[0081] like Figure 8DAs shown, Stage 8 illustrates the state after an encapsulation layer 208 is provided between the first substrate 202 and the second substrate 206, such that the encapsulation layer 208 is coupled to the first substrate 202 and the second substrate 206. The encapsulation layer 208 laterally surrounds the integrated device 204. The encapsulation layer 208 may also encapsulate at least a portion of the copper balls 810. Stage 8 may also illustrate the state after a plurality of solder interconnects 250 are coupled to the first substrate 202. The process of forming and / or setting the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0082] Stage 9 illustrates the state after singulation, where the first substrate 202, encapsulation layer 208, and second substrate 26 are cut (e.g., sliced) to remove portions of the first substrate 202, encapsulation layer 208, copper ball 810, and second substrate 206. Mechanical processes (e.g., sawing) can be used to perform the singulation.

[0083] Phase 9 illustrates package 300, which includes a second substrate 306 configured as a heat sink. As shown in Phase 9, package 300 does not have copper balls 810. Furthermore, the second substrate 306 is configured not to have electrical connections to integrated device 204. Specifically, a plurality of interconnects 362 are configured not to have electrical connections to integrated device 204 and / or first substrate 202.

[0084] The packages described in this disclosure (e.g., 200, 300, 400) can be manufactured one at a time, or they can be manufactured together as part of one or more wafers and then cut into individual packages.

[0085] Figure 9 (including) Figures 9A to 9B The illustration shows an exemplary sequence for providing or fabricating a package including a substrate configured as a heat sink. In some embodiments, the sequence of FIG9 can be used to provide or fabricate a plurality of packages 300 at once, wherein each package includes Figure 3 The second substrate 306. The sequence of FIG9 can be used to fabricate any package described in this disclosure. FIG9 can be used to fabricate a package from one or more wafers comprising several packages. The sequence of FIG9 can be similar to Figures 8A to 8D A sequence, and may contain Figures 8A to 8D Many processes described in the text.

[0086] It should be noted that, in order to simplify and / or clarify the sequence for providing or fabricating a package comprising a substrate configured as a heat sink, the sequence of FIG9 may combine one or more stages. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more processes may be replaced or substituted without departing from the spirit of this disclosure. The sequence of FIG9 may be used to fabricate several packages (as part of a wafer) at once, which are then diced.

[0087] like Figure 9A As shown, Phase 1 illustrates a state including a first wafer 900, which includes a plurality of first substrates 202 and a plurality of integrated devices 204 as described in this disclosure. The first wafer 900 also includes a plurality of solder interconnects 820. Phase 1 of Figure 9 can be similar to... Figure 8C Phase 6.

[0088] Phase 2 illustrates the state after the second wafer 910 is coupled to the first wafer 900 and a plurality of integrated devices 204. The second wafer 910 includes a plurality of second substrates 306, including a dielectric layer 260, a plurality of interconnects 362, and at least one solder resist layer 264. Copper balls 810 may be coupled to the second wafer 910. The copper balls 810 may be coupled to the first wafer 900 via solder interconnects 820. Figure 9A Phase 2 can be similar to Figure 8C Phase 7.

[0089] like Figure 9B As shown, stage 3 illustrates the state after an encapsulation layer 208 is provided between the first wafer 900 and the second wafer 910, such that the encapsulation layer 208 is coupled to the first wafer 900 and the second wafer 910. Figure 9B Phase 3 can be similar to Figure 8D Stage 8.

[0090] Phase 4 illustrates the state after the first wafer 900, encapsulation layer 208, and second wafer 910 have been cut to fabricate several packages 300. Figure 9B Phase 4 can be similar to Phase 9 in Figure 8E.

[0091] Exemplary flowchart of a method for fabricating a package including a substrate configured as a heat sink

[0092] In some embodiments, fabricating a package that includes a substrate configured as a heat sink involves several processes. Figure 10 An exemplary flowchart of a method 1000 for providing or fabricating a package including a substrate configured as a heat sink is illustrated. In some embodiments, Figure 10 Method 1000 can be used to provide or make the product described in this disclosure. Figure 3Package 300. However, method 1000 can be used to provide or manufacture any package described in this disclosure.

[0093] It should be noted that, in order to simplify and / or clarify the methods for providing or fabricating packages including substrates configured as heat sinks, Figure 10 The sequence can combine one or more processes. In some implementations, the order of the processes can be changed or modified.

[0094] The method (at 1005) provides coupling at least one copper ball (e.g., 810) to a second substrate (e.g., 306). The copper ball 810 may include a copper core ball (CCB). The copper ball 810 may include solder. The copper ball 810 may be coupled to the bottom surface of the second substrate 306. The copper ball 810 may be coupled to at least one solder resist layer 264. The copper ball 810 may be coupled near the edge of the second substrate 306. The second substrate 306 may be configured as a heat sink. Figure 8A Phase 2 is illustrated and described as an example of coupling copper balls to a second substrate.

[0095] The method (at 1010) provides a first substrate (e.g., 202). The first substrate 202 may be supplied by a vendor or fabricated. Figures 6A to 6B A process similar to the one shown can be used to fabricate the first substrate 202. However, different embodiments may use different processes to fabricate the first substrate 202. The first substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Figure 8A Phase 3 is illustrated and described as an example of providing a first substrate.

[0096] This method (at 1015) couples an integrated device (e.g., 204) to a first substrate (e.g., 2020). The integrated device 204 can be coupled to the first substrate 202 via a plurality of interconnects 240. The plurality of interconnects 240 can be coupled to interconnects 222 from the first substrate 202. The plurality of interconnects 240 can be coupled to interconnects 222 via solder interconnects. The integrated device 204 can be coupled to the first substrate 202 such that the front side (e.g., the active side) of the integrated device 204 faces the first substrate 202. Figure 8B Phase 4 illustrates and describes an example of an integrated device coupled to a first substrate.

[0097] The method (in 1020) provides an underfill (e.g., 280) between the integrated device (e.g., 204) and the first substrate (e.g., 202). The underfill 280 can be configured such that the underfill 280 is coupled to the integrated device 204 and the first substrate 202. Figure 8BPhase 5 is illustrated and described as an example of the bottom filler disposed between the integrated device and the first substrate.

[0098] The method (in 1025) provides a thermal interface material (TIM) (e.g., 282) on an integrated device (e.g., 204). TIM 282 may be provided on the integrated device 204 such that TIM 282 is coupled to the back side of the integrated device 204. Figure 8C Phase 6 is illustrated and described as an example of a TIM provided on top of an integrated device. The method can also provide solder interconnects (e.g., 820) on top of a first substrate 202, such as... Figure 8C The stage 6 is described and illustrated.

[0099] The method (at 1030) couples a second substrate (e.g., 306) having copper balls (e.g., 810) to a first substrate 202 and an integrated device 204. The second substrate 306 is configured as a heat sink. The second substrate 306 is configured to have no electrical connection to the integrated device 204. The second substrate 306 is coupled to the integrated device 204 via a TIM 282. Specifically, the second substrate 206 is coupled to the integrated device 204 such that the back side of the integrated device 204 faces the second substrate 306. Figure 8C Phase 7 illustrates and describes an example of a second substrate with copper balls coupled to a first substrate and an integrated device.

[0100] The method (at 1035) provides an encapsulation layer (e.g., 208) between a first substrate (e.g., 202) and a second substrate (e.g., 306), such that the encapsulation layer is coupled to both the first and second substrates. The encapsulation layer 208 laterally surrounds the integrated device 204. Figure 8D Phase 8 illustrates and describes an example of an encapsulation layer provided between the first substrate and the second substrate.

[0101] The method (at 1040) cuts a first substrate (e.g., 202), an encapsulation layer (e.g., 208), and a second substrate (e.g., 206) to remove portions of the first substrate 202, the encapsulation layer 208, the copper balls 810, and the second substrate 206. A mechanical process (e.g., sawing) can be used to perform the cutting. After cutting, the result can be a package 300 including a second substrate 306 configured as a heat sink. After cutting, the package 300 does not have the copper balls 810. Moreover, the second substrate 306 is configured to have no electrical connection to the integrated device 204. Specifically, a plurality of interconnects 362 are configured to have no electrical connection to the integrated device 204 and / or the first substrate 202. Figure 8D Stage 9 is illustrated and describes an example of cutting.

[0102] Exemplary electronic devices

[0103] Figure 11 The illustrations depict various electronic devices that can be integrated with any of the devices described above, integrated devices, integrated device (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1102, laptop computer device 1104, fixed-location terminal device 1106, wearable device 1108, or motor vehicle 1110 may include the device 1100 described herein. For example, device 1100 may be any device and / or integrated circuit (IC) package described herein. Figure 11 The devices 1102, 1104, 1106, and 1108 illustrated, as well as vehicle 1110, are merely exemplary. Other electronic devices may also feature device 1100, including but not limited to mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous motor vehicles), or any other device or combination thereof that stores or retrieves data or computer instructions (e.g., electronic devices).

[0104] Figures 2 to 5 One or more components, processes, features, and / or functions illustrated in 6A to 6B, 7, 8A to 8D, 9A to 9B, and / or 10 to 11 may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 2 to 5 6A to 6B, 7, 8A to 8D, 9A to 9B and / or 10 to 11 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some embodiments, Figures 2 to 5 6A to 6B, 7, 8A to 8D, 9A to 9B and / or 10 to 11 and their corresponding descriptions can be used to manufacture, create, provide and / or produce devices and / or integrated devices. In some embodiments, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a heat dissipation device and / or an interposer.

[0105] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be drawn to scale. In some instances, not all components and / or parts may be shown for clarity. In some instances, the location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some embodiments, the various components and / or parts in the drawings may be optional.

[0106] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as being more preferred or advantageous than other aspects of this disclosure. Similarly, the term “aspects” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact with each other. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can propagate or is able to propagate between the two objects. The term “electrically coupled” can mean that two objects are electrically connected. Two electrically coupled objects may or may not have current propagating between the two objects. The term “encapsulation” means that an object can partially or completely encapsulate another object. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component above a second component may mean (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on its surface), and / or (3) the first component is (e.g., embedded in) the second component. The terms “approximately 'value X'” or “approximately value X” as used in this disclosure mean within 10% of 'value X'. For example, a value of approximately 1 or close to 1 would mean a value in the range of 0.9 to 1.1.

[0107] In some embodiments, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., a seed layer + metal layer). In some embodiments, an interconnect includes a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal, ground, or power supply). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different embodiments may use similar or different processes to form interconnects. In some embodiments, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or electroplating processes may be used to form interconnects.

[0108] Furthermore, it should be noted that the various disclosures contained herein can be described as processes, depicted as flowcharts, task diagrams, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations can be executed in parallel or concurrently. Additionally, the order of operations can be rearranged. A process terminates when its operations are completed.

[0109] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of various aspects of this disclosure is intended to be illustrative and not to limit the scope of the claims. Therefore, this teaching can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: First substrate; Integrated devices are coupled to the first substrate; The second substrate is coupled to the integrated device. The second substrate is configured to operate as a heat sink. The second substrate includes a dielectric layer and multiple interconnects. The plurality of interconnects are configured to have no electrical connection to the integrated device. The plurality of interconnects includes a plurality of vias, The vias from the plurality of vias include (i) a first metal layer located on the wall of the cavity of the second substrate, and (ii) a second metal layer located in the cavity of the second substrate; as well as An encapsulation layer is located between the first substrate and the second substrate.

2. The packaging component according to claim 1, The first substrate includes a first coefficient of thermal expansion (CTE) having a value in the range of 7 to 15 parts per million (ppm / C). The second substrate includes a second coefficient of thermal expansion (CTE) having a value in the range of 7 to 15 parts per million (ppm / C).

3. The package of claim 1, further comprising a thermal interface material (TIM) located between the second substrate and the integrated device, wherein the thermal interface material (TIM) is configured to couple the second substrate to the integrated device.

4. The packaging component according to claim 1, The integrated device includes a front side and a back side. The front side of the integrated device faces the first substrate, and The back side of the integrated device faces the second substrate.

5. The package of claim 1, wherein the first substrate comprises a laminated substrate.

6. The package of claim 2, wherein the second coefficient of thermal expansion (CTE) is similar to the first coefficient of thermal expansion (CTE).

7. The package of claim 1, further comprising an underfill material located between the integrated device and the first substrate.

8. The package of claim 1, wherein the package is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

9. The package of claim 1, wherein the dielectric layer of the second substrate comprises glass, silicon, quartz and / or combinations thereof.

10. The package according to claim 1, The packaged components have a thickness of 1000 micrometers or less. The first substrate has a thickness of 400 micrometers or less. The second substrate has a thickness of 200 micrometers or less, and The encapsulation layer has a thickness of 200 micrometers or less.

11. The packaging component according to claim 2, The integrated device described herein includes a coefficient of thermal expansion (CTE) having a value of 7 parts per million (ppm / C), and The CTE of the integrated device, the first CTE of the first substrate, and the second CTE of the second substrate are similar.

12. An apparatus comprising: First substrate; Integrated devices are coupled to the first substrate; Components used for heat dissipation are coupled to the integrated device. The heat dissipation component is configured to have no electrical connection to the integrated device. The heat dissipation component includes a dielectric layer and multiple interconnects configured not to have electrical connections to the integrated device. The plurality of interconnects includes a plurality of vias, and The vias from the plurality of vias include (i) a first metal layer located on the wall of the cavity of the heat dissipation component, and (ii) a second metal layer located in the cavity of the heat dissipation component; as well as An encapsulation layer is located between the first substrate and the heat dissipation component.

13. The apparatus of claim 12, further comprising a thermal interface material (TIM) located between the heat dissipation component and the integrated device, wherein the thermal interface material (TIM) is configured to couple the heat dissipation component to the integrated device.

14. The apparatus according to claim 12, The integrated device includes a front side and a back side. The front side of the integrated device faces the first substrate, and The back side of the integrated device faces the heat dissipation component.

15. The apparatus of claim 12, wherein the first substrate comprises a laminated substrate.

16. The apparatus according to claim 12, The first substrate includes a first coefficient of thermal expansion (CTE), and The heat dissipation component includes a second coefficient of thermal expansion (CTE) similar to the first coefficient of thermal expansion (CTE).

17. The apparatus of claim 12, further comprising an underfill material located between the integrated device and the first substrate.

18. The apparatus of claim 12, wherein the apparatus is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

19. The apparatus according to claim 12, The first substrate has a thickness of 400 micrometers or less. The heat dissipation component described herein has a thickness of 200 micrometers or less, and The encapsulation layer has a thickness of 200 micrometers or less.

20. A method for manufacturing a package, comprising: Provide a first substrate; The integrated device is coupled to the first substrate; The second substrate is coupled to the integrated device. The second substrate is configured to operate as a heat sink. The second substrate includes a dielectric layer and multiple interconnects. The second substrate is configured to have no electrical connection to the integrated device. The plurality of interconnects includes a plurality of vias, The vias from the plurality of vias include (i) a first metal layer located on the wall of the cavity of the second substrate, and (ii) a second metal layer located in the cavity of the second substrate; as well as An encapsulation layer is formed between the first substrate and the second substrate.

21. The method of claim 20, further comprising providing a thermal interface material (TIM) between the second substrate and the integrated device, wherein the thermal interface material (TIM) is configured to couple the second substrate to the integrated device.

22. The method according to claim 20, The integrated device includes a front side and a back side. The front side of the integrated device faces the first substrate, and The back side of the integrated device faces the second substrate.

23. The method of claim 20, wherein the first substrate comprises a laminated substrate.

24. The method according to claim 20, The first substrate includes a first coefficient of thermal expansion (CTE), and The second substrate includes a second coefficient of thermal expansion (CTE) similar to the first coefficient of thermal expansion (CTE).

25. The method of claim 20, further comprising an underfill located between the integrated device and the first substrate.

26. The method of claim 20, wherein the dielectric layer of the second substrate comprises glass, silicon, quartz, and / or combinations thereof.

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