Dual-core lockstep method, device and electronic device

Abstract

The present application relates to the field of chip technology, and discloses a dual-core lockstep method, device and electronic device. The device compares the calculation results obtained by the main computing unit and the slave computing unit based on the same input instruction, and also compares the intermediate data of the main computing unit and the slave computing unit in the process of generating the calculation result, and obtains multiple comparison results, so that the specific reasons for the inconsistency of the calculation results of the main computing unit and the slave computing unit can be determined based on the multiple comparison results, and different processing methods are adopted according to different specific reasons to obtain the calculation result of the input instruction, without having to re-execute the input instruction every time, which is conducive to reducing the number of times the device re-executes the instruction and improving the efficiency of the device in executing instructions.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a dual-core lockstep method, device and electronic device. Background Art

[0002] As users' demand for control safety increases, computing devices (such as processors) using dual core lockstep (DCLS) technology are increasingly widely used, especially in fields with high safety requirements such as automobiles, rail transit, and aerospace. DCLS is a computing unit redundancy technology. Two computing units are set in a computing device, one as a master computing unit and the other as a slave computing unit. The master computing unit and the slave computing unit execute the same instructions and are strictly synchronized, and the calculation results of the two computing units are compared through a comparison circuit to obtain a lockstep signal. Therefore, when the computing device uses the calculation result to control the execution unit (for example, based on the calculation result to control the brakes of the car, adjust the speed of the car, turn the car, etc.), the lockstep signal can be output to the execution unit when the lockstep signal indicates that the results of the two computing units are the same, and the lockstep signal does not output the control signal to the execution unit when the lockstep signal indicates that the results of the two computing units are different. In this way, it can be avoided that when the calculation result of one computing unit is wrong, the wrong calculation result is used to control the execution unit, thereby improving safety.

[0003] However, the current DCLS technology only compares the calculation results of the master computing unit and the slave computing unit, and can only give whether the calculation results of the master computing unit and the slave computing unit are the same, but will not give the reasons for the different calculation results. Regardless of the reasons for the different calculation results of the master computing unit and the slave computing unit, the computing device can only re-execute the instructions, resulting in a low efficiency of the computing device using the DCLS technology in executing instructions. Summary of the invention

[0004] The embodiments of the present application provide a dual-core lockstep method, device and electronic device. By comparing the calculation results of the master computing unit and the slave computing unit at the same time, as well as the intermediate data generated in the process of generating the calculation results, the number of times the master computing unit and the slave computing unit re-execute instructions is reduced, which is conducive to improving the efficiency of the dual-core lockstep device in executing instructions.

[0005] In a first aspect, an embodiment of the present application provides a dual-core lock-step method, the method comprising: obtaining a main computing result generated by a main computing unit of a computing device executing a first instruction and first intermediate data generated in the process of generating the main computing result, and obtaining a slave computing result generated by a slave computing unit of the computing device executing the first instruction and second intermediate data corresponding to the first intermediate data generated in the process of generating the slave computing result; corresponding to the main computing result being different from the slave computing result, generating a computing result of the first instruction based on a comparison result of the first intermediate data and the second intermediate data.

[0006] In an embodiment of the present application, an electronic device that adopts the dual-core lock-step method can, when the main calculation result is different from the slave calculation result, choose to re-execute the first instruction or generate the calculation result of the first instruction by other means based on the comparison result of the first intermediate data and the second intermediate data (for example, the various lock-step results described below), without having to re-execute the first instruction each time, thereby reducing the number of times the electronic device re-executes the first instruction, which is beneficial to improving the efficiency of the electronic device in executing instructions.

[0007] In a possible implementation of the first aspect, the first intermediate data includes at least one of the following data: first cache data generated in the process of the main computing unit generating the main computing result, first input data received in the process of the main computing unit generating the main computing result, first input instruction received in the process of the main computing unit generating the main computing result, first interrupt data received or generated in the process of the main computing unit generating the main computing result, and first tightly coupled memory data generated in the process of the main computing unit generating the main computing result;

[0008] The above-mentioned second intermediate data includes at least one of the following data: second cache data generated from the computing unit in the computing result process, second input data generated from the computing unit and received from the computing result process, second input instructions generated from the computing unit and received from the computing result process, second interrupt data received or generated from the computing unit in the computing result process, and second tightly coupled memory data generated from the computing unit and generated from the computing unit in the computing result process.

[0009] In a possible implementation of the first aspect, generating a calculation result of the first instruction based on a comparison result of the first intermediate data and the second intermediate data includes:

[0010] In the case where the first input data and the second input data are different, and / or the first input instruction and the second input instruction are different, if the first input data and the input data corresponding to the first instruction are the same, and the first input instruction is the same as the first instruction, the main calculation result is used as the calculation result of the first instruction;

[0011] When the first input instruction and the second input instruction are the same, and the first input data and the second input data are the same, if the first cache data and the second cache data are different, or the first interrupt data and the second interrupt data are different, or the first tightly coupled memory data and the second tightly coupled memory data are different, the master computing unit and the slave computing unit are used to re-execute the first instruction to obtain a calculation result of the first instruction.

[0012] In an embodiment of the present application, the electronic device will use the main computing unit and the slave computing unit to re-execute the first instruction to obtain the calculation result of the first instruction only when the first input instruction and the second input instruction are the same and the first input data are the same. This is beneficial to reducing the number of times the electronic device re-executes the first instruction and improving the efficiency of the electronic device in executing instructions.

[0013] In a possible implementation of the first aspect above, the above-mentioned method of generating a calculation result of the first instruction based on the comparison result of the first intermediate data and the second intermediate data includes: determining the error type that causes the main calculation result to be different from the slave calculation result based on the comparison result of the first intermediate data and the second intermediate data, the error type including recoverable errors and unrecoverable errors; based on the error type, obtaining the calculation result of the first instruction through a preset method corresponding to the error type.

[0014] In an embodiment of the present application, the electronic device uses the main computing unit and the slave computing unit to re-execute the first instruction to obtain the calculation result of the first instruction only when the error type that causes the main calculation result to be different from the slave calculation result is an irrecoverable error. This is beneficial to reducing the number of times the electronic device re-executes the first instruction and improving the efficiency of the electronic device in executing instructions.

[0015] In a second aspect, an embodiment of the present application provides a dual-core lock-step device, which includes: a main computing unit, used to execute a first instruction to generate a main computing result, and to generate first intermediate data in the process of generating the main computing result; a slave computing unit, used to execute a first instruction to generate a slave computing result, and to generate second intermediate data in the process of generating the slave computing result; a comparison unit, used to compare the first intermediate data and the second intermediate data, generate and output a first comparison result, wherein the first comparison result can be used to generate a calculation result of the first instruction when the main calculation result and the slave calculation result are different.

[0016] For example, in some embodiments, the comparison unit may include at least one of the comparison circuits C1 to C5 and the comparison circuits C3 - 1 to C3 - 5 described below.

[0017] In an embodiment of the present application, other devices or modules, such as the control unit CT2 / control unit CT3 described below, can generate the calculation result of the first instruction in different ways based on the first comparison result (such as the lock-step results described below) when the main calculation result and the slave calculation result are different, without having to use the main calculation unit and the slave calculation unit to re-execute the first instruction to obtain the calculation result of the first instruction each time, which is beneficial to reducing the number of times the electronic device re-executes the first instruction and improving the efficiency of the electronic device in executing instructions.

[0018] In a possible implementation of the second aspect, the first intermediate data includes at least one of the following data: first cache data generated in the process of the main computing unit generating the main computing result, first input data received in the process of the main computing unit generating the main computing result, first input instruction received in the process of the main computing unit generating the main computing result, first interrupt data received or generated in the process of the main computing unit generating the main computing result, and first tightly coupled memory data generated in the process of the main computing unit generating the main computing result;

[0019] The second intermediate data includes at least one of the following data: second cache data generated from the computing unit in the computing result process, second input data generated from the computing unit and received from the computing result process, second input instructions generated from the computing unit and received from the computing result process, second interrupt data received or generated from the computing unit in the computing result process, and second tightly coupled memory data generated from the computing unit and generated from the computing unit in the computing result process.

[0020] In a possible implementation of the second aspect, the apparatus further includes: a control unit configured to generate a calculation result of the first instruction based on the first comparison result when the master calculation result is different from the slave calculation result.

[0021] For example, in some embodiments, the control unit may include the control unit CT2 and the control unit CT3 described below.

[0022] In a possible implementation of the second aspect, the control unit generates a calculation result of the first instruction based on the first comparison result in the following manner:

[0023] The control unit, when the first comparison result indicates that the first input data and the second input data are different, and / or the first input instruction is the same as the second input instruction, uses the main calculation result as the calculation result of the first instruction if the first input data is the same as the input data corresponding to the first instruction, and the first input instruction is the same as the first instruction;

[0024] The control unit uses the main computing unit and the slave computing unit to re-execute the first instruction to obtain a calculation result of the first instruction when the first comparison result indicates that the first input instruction and the second input instruction are the same, and the first input data and the second input data are the same, if the first cache data and the second cache data are different, or the first interrupt data and the second interrupt data are different, or the first tightly coupled memory data and the second tightly coupled memory data are different.

[0025] In the embodiment of the present application, the dual-core lock-step device will use the main computing unit and the slave computing unit to re-execute the first instruction to obtain the calculation result of the first instruction only when the first input instruction and the second input instruction are the same and the first input data are the same. This is beneficial to reducing the number of times the dual-core lock-step device re-executes the first instruction and improving the efficiency of the dual-core lock-step device in executing instructions.

[0026] In a possible implementation of the second aspect above, the apparatus further includes a classification unit, configured to output an error type to the control unit according to the first comparison result, wherein the error type is used to indicate whether the first instruction needs to be re-executed to obtain a calculation result of the first instruction.

[0027] For example, in some embodiments, the classification unit may include a classification circuit CL1 hereinafter.

[0028] In an embodiment of the present application, the dual-core lock-step device can also directly output the error type, so that other modules can directly use the main computing unit and the slave computing unit to re-execute the first instruction to obtain the calculation result of the first instruction when the received error type is used to indicate that the first instruction needs to be re-executed to obtain the calculation result of the first instruction, which is beneficial to improving the speed at which the dual-core lock-step device responds to errors.

[0029] In a possible implementation of the second aspect above, it also includes: a delay unit, used to adjust the phase of the main calculation result and / or the slave calculation result, and output the main calculation result and the slave calculation result with the same phase to the comparison unit, and used to adjust the phase of the first intermediate data and / or the second intermediate data, and output the first intermediate data and the second intermediate data with the same phase to the comparison unit.

[0030] In a third aspect, an embodiment of the present application provides an electronic device, which includes any dual-core lock-step device provided by the second aspect and various possible implementations of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 According to some embodiments of the present application, a schematic diagram of a scenario of controlling the driving state of a vehicle 01 using a computing device P is shown;

[0032] Figure 2According to some embodiments of the present application, a schematic diagram of the structure of a computing device P1 using the DCLS technology is shown;

[0033] Figure 3 According to some embodiments of the present application, a schematic structural diagram of a dual-core lockstep device P2 is shown;

[0034] Figure 4 According to some embodiments of the present application, a schematic structural diagram of a dual-core lockstep device P2' is shown;

[0035] Figure 5 According to some embodiments of the present application, a schematic structural diagram of a dual-core lockstep device P3 is shown;

[0036] Figure 6 According to some embodiments of the present application, a schematic structural diagram of an electronic device 100 is shown. DETAILED DESCRIPTION

[0037] Illustrative embodiments of the present application include, but are not limited to, dual-core lockstep methods, apparatus, and electronic devices.

[0038] The technical solution of the embodiments of the present application is described below in conjunction with the accompanying drawings.

[0039] It can be understood that the embodiments of the present application are applicable to any scenario that requires dual-core lock-step or multi-core lock-step, including but not limited to industrial control, aircraft control, spacecraft control, intelligent driving, assisted driving, rail transit, etc. For ease of description, the technical solution of the present application is introduced below by taking the scenario of controlling the driving state of a vehicle as an example.

[0040] Figure 1 According to some embodiments of the present application, a schematic diagram of a scenario in which a computing device P is used to control the driving state of a vehicle 01 is shown.

[0041] like Figure 1 As shown, the computing device P is one of the processing chips in the control system of the vehicle 01, and is used to generate control signals for each controller of the vehicle 01 according to the driver's operation of the vehicle 01, the road data on which the vehicle 01 is currently traveling (such as ground type, surrounding obstacle data, road speed limit data, etc.), and the motion data of the vehicle 01 (such as the vehicle's driving speed, driving direction, etc.), thereby controlling the driving state of the vehicle 01.

[0042] For example, after detecting the driver's operation of braking the vehicle 01 or detecting an obstacle ahead, the computing device P generates a brake control signal and sends the brake control signal to the brake controller, which brakes the vehicle P. For another example, when the computing device P detects the driver's steering operation or detects that the direction of the road ahead is inconsistent with the current driving direction of the vehicle 01, it generates a steering control signal and sends the steering control signal to the steering controller, which adjusts the direction of the vehicle 01 according to the steering control signal. For another example, when the computing device P detects the driver's acceleration or deceleration operation or detects the acceleration or deceleration of the vehicle ahead, it generates a motion control signal and sends the motion control signal to the motion controller, which adjusts the speed of the vehicle based on the motion control signal.

[0043] If the computing device P generates an erroneous control signal due to an internal fault, a fault in the occupied hardware resources, etc., the corresponding controller may make an incorrect adjustment to the driving state of the vehicle, causing a safety accident.

[0044] In order to avoid the generation of erroneous control signals due to internal failures of the computing device P, failures of occupied hardware resources, etc., which may cause the corresponding controller to make incorrect adjustments to the vehicle's driving state and cause safety accidents, the computing device P may adopt DCLS technology.

[0045] For example, Figure 2 According to some embodiments of the present application, a schematic diagram of the structure of a computing device P1 using the DCLS technology is shown.

[0046] like Figure 2 The computing device P1 shown includes a master computing unit MP1, a slave computing unit SP1, an input delay circuit ID1, an output delay circuit OD1, an output delay circuit OD2, and a comparison circuit CP1.

[0047] The main calculation unit MP1 is used to receive input instructions to generate main calculation results, and output the main calculation results to the output delay circuit OD1 and the control unit CT1. For example, the main calculation unit MP1 can be used to receive the driver's operation, road data, and vehicle motion data, and generate a control signal based on the received driver's operation, road data, and vehicle motion data, and send the control signal to the delay circuit OD1 and each controller.

[0048] The input delay circuit ID1 is used to receive the same input instruction as the master computing unit MP1 and delay the input instruction before outputting it to the slave computing unit SP1.

[0049] The slave calculation unit SP1 is used to receive an input instruction of the input delay circuit ID1 , generate a slave calculation result based on the received input instruction, and send the slave calculation result to the output delay circuit OD2 .

[0050] The output delay circuit OD1 and the output delay circuit OD2 are used to delay the master calculation result and the slave calculation result respectively, so that the master calculation result and the slave calculation result have the same phase, that is, the master calculation result and the slave calculation result at each moment are obtained based on the same instruction.

[0051] The comparison circuit CP1 is used to compare the master calculation result and the slave calculation result, and output the lock step result to the control unit CT1. The lock step result is true when the master calculation result and the slave calculation result are the same (for example, the lock step result can be a binary number 1), and false when the master calculation result and the slave calculation result are different (for example, the lock step result can be a binary number 0).

[0052] The control unit CT1 is used to output the main calculation result, such as outputting a control signal to each controller, when it detects that the lock-step result is 1 (i.e., the main calculation result and the slave calculation result are the same); when it detects that the lock-step result is 0 (i.e., the main calculation result and the slave calculation result are different), not output the calculation result, and send an interrupt to the main calculation unit MP1 and the slave calculation unit SP1, so that the main calculation unit MP1 and the slave calculation unit SP1 can re-execute the input instruction to obtain the correct calculation result.

[0053] Since the probability of the same error occurring simultaneously in the main computing unit MP1 and the slave computing unit SP1 is low, and the computing device P1 will output an erroneous calculation result only when the same error occurs simultaneously in the main computing unit MP1 and the slave computing unit SP1, the possibility of the computing device P1 outputting an erroneous calculation result can be reduced, thereby improving the safety of the computing device P1 and the control system using the computing device P1.

[0054] However, since the comparison circuit CP2 only compares the output results of the main computing unit MP1 and the slave computing unit SP1, the subsequent circuits (such as the interrupt control unit) can only determine whether the calculation results of the main computing unit MP1 and the slave computing unit SP1 are consistent. No matter what the reason is that the calculation results of the main computing unit MP1 and the slave computing unit SP1 are inconsistent, the input instruction can only be re-executed, which reduces the efficiency of the computing device P1 in executing instructions.

[0055] In view of this, an embodiment of the present application provides a dual-core lock-step device, which compares the calculation results obtained by the main computing unit and the slave computing unit based on the same input instruction, and also compares the intermediate data (such as input data, interrupt data, cache data, tightly coupled memory data, etc.) of the main computing unit and the slave computing unit in the process of generating the calculation result, and obtains multiple comparison results. Therefore, the processor or electronic device using the computing device can determine the specific reasons for the inconsistency of the calculation results of the main computing unit and the slave computing unit based on the multiple comparison results, and adopt different processing methods according to different specific reasons to obtain the calculation result of the input instruction, without having to re-execute the input instruction every time, which is conducive to reducing the number of times the processor or electronic device re-executes the instruction and improving the efficiency of the processor or electronic device in executing the instruction.

[0056] It can be understood that the intermediate data of the main computing unit and the slave computing unit in the process of generating calculation results include but are not limited to input instructions, input data corresponding to the input instructions, interrupt data, cache data, tightly coupled memory data, bus interface data, register data, memory data, etc., which are not limited here.

[0057] Specifically, Figure 3 According to some embodiments of the present application, a schematic structural diagram of a dual-core lockstep device P2 is shown.

[0058] like Figure 3 As shown, the dual-core lockstep device P2 includes: a main computing unit MP2, a slave computing unit SP2, an input delay circuit ID2, an output delay circuit OD3, an output delay circuit OD4, a comparison circuit C1, a comparison circuit C2, a comparison circuit C3, a comparison circuit C4, and a comparison circuit C5.

[0059] The main calculation unit MP2 is used to receive input instructions to generate main calculation results, and output the main calculation results to the output delay circuit OD3 and the control unit CT2. For example, the main calculation unit MP2 can be used to receive the driver's operation, road data, and vehicle motion data, and generate a control signal based on the received driver's operation, road data, and vehicle motion data, and send the control signal to the delay circuit OD3 and each controller.

[0060] It can be understood that, generally, the main computing unit MP2 and the slave computing unit SP2 are computing units with the same structure, and can obtain the same computing result based on the same instructions and using the same computing logic.

[0061] The input delay circuit ID2 is used to receive the same input instruction as the master computing unit MP2 and output the input instruction to the slave computing unit SP2 after delaying the input instruction.

[0062] The slave calculation unit SP2 is used to receive an input instruction of the input delay circuit ID1 , generate a slave calculation result based on the received input instruction, and send the slave calculation result to the output delay circuit OD4 .

[0063] The output delay circuit OD3 and the output delay circuit OD4 are used to delay the main calculation result and the slave calculation result respectively, and transmit the delayed main calculation result and the slave calculation result to the comparison circuit C1, so that the main calculation result and the slave calculation result have the same phase, that is, the main calculation result and the slave calculation result at each moment are obtained based on the same instruction. For example, in the case where the phase of the main calculation result is ahead of the phase of the slave calculation result, the output delay circuit OD3 can delay the phase of the main calculation result; in the case where the phase of the main calculation result lags behind the phase of the slave calculation result, the output delay circuit OD4 can delay the phase of the slave calculation result; or the output delay circuit OD3 and the output delay circuit OD4 are used to delay the main calculation result and the slave calculation result for different lengths of time respectively, so that the phase of the main calculation result and the slave calculation result are the same.

[0064] The comparison circuit C1 is used to compare the master calculation result and the slave calculation result, and output a lock-step result 1. The lock-step result 1 is true (e.g., binary 1) when the master calculation result and the slave calculation result are the same, and false (e.g., binary 0) when the master calculation result and the slave calculation result are different. In some embodiments, the comparison circuit C1 can be implemented as an XOR gate circuit.

[0065] The comparison circuit C2 is used to compare the cache data 2 of the master computing unit MP2 in the process of generating the master computing result and the cache data 2 of the slave computing unit SP2 in the process of generating the slave computing result, and output the lock step result 2. The lock step result 2 is true (e.g., binary 1) when the cache data 1 and the cache data 2 are the same, and false (e.g., binary 0) when the cache data 1 and the cache data 2 are different. In some embodiments, the comparison circuit C2 can be implemented as an XOR gate circuit.

[0066] It can be understood that in some embodiments, a delay circuit can also be set between the comparison circuit C2 and the main processing unit MP2, and / or between the comparison circuit C2 and the slave processing unit SP2, so as to delay the phase of at least one of the cache data 1 and the cache data 2, so that the cache data 1 and the cache data 2 have the same phase, that is, the cache data 1 and the cache data 2 at each moment are obtained based on the same instruction.

[0067] The comparison circuit C3 is used to compare the TCM data 1 of the master computing unit MP2 in the process of generating the master computing result and the TCM data 2 of the slave computing unit SP2 in the process of generating the slave computing result, and output the lock step result 3. The lock step result 3 is true (e.g., binary 1) when the TCM data 1 and the TCM data 2 are the same, and false (e.g., binary 0) when the TCM data 1 and the TCM data 2 are different. In some embodiments, the comparison circuit C3 can be implemented as an XOR gate circuit.

[0068] It can be understood that in some embodiments, a delay circuit can be further provided between the comparison circuit C3 and the main processing unit MP2, and between the comparison circuit C3 and the slave processing unit SP2, so as to delay the phase of at least one of the tightly coupled memory data 1 and the tightly coupled memory data 2, so that the tightly coupled memory data 1 and the tightly coupled memory data 2 have the same phase, that is, the tightly coupled memory data 1 and the tightly coupled memory data 2 at each moment are obtained based on the same instruction.

[0069] The comparison circuit C4 is used to compare the interruption data 1 in the process of generating the main calculation result by the main calculation unit MP2 and the interruption data 2 in the process of generating the slave calculation result by the slave calculation unit SP2, and output the lock step result 4. The lock step result 4 is true (for example, binary 1) when the interruption data 1 and the interruption data 2 are the same, and false (for example, binary 0) when the interruption data 1 and the interruption data 2 are different. In some embodiments, the comparison circuit C4 can be implemented as an exclusive OR gate circuit.

[0070] It can be understood that in some embodiments, a delay circuit can also be set between the comparison circuit C4 and the main processing unit MP2, and between the comparison circuit C4 and the slave processing unit SP2, so as to delay the phase of at least one of the interrupt data 1 and the interrupt data 2, so that the interrupt data 1 and the interrupt data 2 have the same phase, that is, the interrupt data 1 and the interrupt data 2 at each moment are obtained based on the same instruction.

[0071] The comparison circuit C5 is used to compare the input instructions and / or data related to the input instructions received by the main computing unit MP2 and the slave computing unit SP2, and output the lock step result 5. The lock step result 5 is true (e.g., binary 1) when the input instructions and / or data related to the input instructions received by the main computing unit MP2 and the slave computing unit SP2 are the same, and false (e.g., binary 0) when the input instructions and / or data related to the input instructions received by the main computing unit MP2 and the slave computing unit SP2 are different. In some embodiments, the comparison circuit C5 can be implemented as an XOR gate circuit.

[0072] It can be understood that in some embodiments, a delay circuit can also be set between the comparison circuit C5 and the main processing unit MP2, and between the comparison circuit C5 and the slave processing unit SP2, so as to delay the phase of at least one of the interrupt data 1 and the interrupt data 2, so as to delay the phase of at least one of the input instructions and / or data related to the input instructions received by the main processing unit MP2 and the slave processing unit SP2, so that the input instructions and / or data related to the input instructions received by the main processing unit MP2 and the slave processing unit SP2 have the same phase.

[0073] The control unit CT2 may adopt different processing methods based on the data of the lock step results 1 to 5 .

[0074] For example, when the lock-step result 1 and the lock-step result 5 are 0, it means that the input data and / or data related to the input instruction received by the main computing unit MP2 and the slave computing unit SP2 are different, which will naturally produce different results, but the result is not caused by internal errors in the main computing unit MP2 and the slave computing unit SP2. When the input instruction received by the main computing unit MP2 is the same as the instruction to be actually executed, and the data related to the received input instruction is the same as the data of the instruction to be actually executed, the control unit CT2 can directly output the main calculation result as the calculation result without re-executing the instruction, thereby improving the efficiency of the dual-core lock-step device P2 in executing instructions. Specifically, Figure 1 In the scenario shown, assuming that the road data input into the main computing unit MP2 is inconsistent with the road data input into the slave computing unit, and the road data input into the main computing unit MP2 is the same as the actual road data, the control unit CT2 can directly send each control signal in the calculation result generated by the main computing unit to the corresponding controller, thereby adjusting the driving state of the vehicle.

[0075] For another example, when the control unit CT2 detects that the lock step result 5 indicates that the input data or input instruction-related data received by the main computing unit MP2 and the slave computing unit SP2 are different, but the main computing unit MP2 and the slave computing unit SP2 have not generated the corresponding calculation results, an interrupt can be sent to the main computing unit MP2 and the slave computing unit SP2, so that the main computing unit MP2 and the slave computing unit SP2 can terminate the calculation process and re-acquire the input data and / or input instruction-related data to obtain the calculation results, without waiting until the calculation results generated by the main computing unit MP2 and the slave computing unit SP2 are different and then recalculating, thereby improving the speed of the dual-core lock step device P2 to respond to errors. Specifically, in Figure 1In the scenario shown, assuming that the road data input into the main computing unit MP2 is inconsistent with the road data input into the slave computing unit (i.e., the lock-step result 5 is 1), and the main computing unit MP2 and the slave computing unit SP2 have not yet obtained the corresponding calculation results, the control unit CT2 can directly terminate the calculation process of the main computing unit MP2 and the slave computing unit SP2, so that the main computing unit MP2 and the slave computing unit SP2 re-acquire the road data to obtain the corresponding control signal.

[0076] Understandably, Figure 3 The structure of the dual-core lock-step device P2 shown is only an example. In other embodiments, the dual-core lock-step device P2 may also include more or fewer modules. For example, the dual-core lock-step device P2 may have more comparison circuits to compare more data generated by the main computing unit MP2 and the slave computing unit SP2 to generate more lock-step results. The dual-core lock-step device P2 may also merge or split some modules. For example, the dual-core lock-step device P2 may merge the comparison circuit C1, the comparison circuit C2, the comparison circuit C3, the comparison circuit C4, and the comparison circuit C5 into one circuit or use a comparator that can compare multiple data at the same time.

[0077] The embodiment of the present application also provides a dual-core lock-step device. Compared with the aforementioned dual-core lock-step device P2, a classification circuit is added for classifying the reasons causing the difference between the main calculation result and the slave calculation result according to each lock-step result, so that its control unit CT2 can directly take corresponding measures based on the classification result without judging by executing instructions, thereby improving the response speed of the dual-core lock-step device when the main calculation result and the slave calculation result are inconsistent.

[0078] Specifically, Figure 4 According to some embodiments of the present application, a schematic structural diagram of a dual-core lockstep device P2 ′ is shown.

[0079] like Figure 4 As shown, the dual-core lock-step device P2′ includes: a master computing unit MP2, a slave computing unit SP2, an input delay circuit ID2, an output delay circuit OD3, an output delay circuit OD4, a comparison circuit C1, a comparison circuit C2, a comparison circuit C3, a comparison circuit C4, a comparison circuit C5 and a classification circuit CL1. The functions of the master computing unit MP2, the slave computing unit SP2, the input delay circuit ID2, the output delay circuit OD3, the output delay circuit OD4, the comparison circuit C1, the comparison circuit C2, the comparison circuit C3, the comparison circuit C4, and the comparison circuit C5 can refer to the description of the dual-core lock-step device P2, and will not be repeated here.

[0080] The input of the classification circuit CL1 includes lock step result 1, lock step result 2, lock step result 3, lock step result 4, and lock step result 5, which are used to classify the reasons for the inconsistency between the main calculation result generated by the main calculation unit MP2 and the slave result generated by the slave calculation unit SP2.

[0081] For example, in some embodiments, the classification circuit CL1 can lock the causes of the inconsistency between the main computing result generated by the main computing unit MP2 and the slave result generated by the slave computing unit SP2 into recoverable errors (for example, errors caused by input data or data related to input instructions) and unrecoverable errors (for example, cache data errors, TCM data errors, interrupt data errors) based on lock result 1, lock result 2, lock result 3, lock result 4, and lock result 5, and output 1 in the case of an unrecoverable error (output 1 if any one of lock result 2, lock result 3, and lock result 4 is 1), and output 0 in the case of only recoverable errors (for example, output 0 if only lock result 1 and lock result 5 are 1).

[0082] Among them, recoverable errors refer to errors that do not require re-execution of input instructions to obtain correct calculation results; unrecoverable errors refer to errors that require re-execution of input instructions to obtain correct calculation results.

[0083] Therefore, the control unit CT2 can directly send an interrupt to the dual-core lock-step device P2′ when the received error type is 1, so that the dual-core lock-step device P2′ re-executes the input instruction, and does not re-execute the input instruction when the received error type is 1. In this way, the interrupt controller can directly send an interrupt to the dual-core lock-step device P2′ according to the error type, without judging whether an interrupt request needs to be sent by executing instructions, thereby improving the speed at which the dual-core lock-step device P2′ responds to errors.

[0084] The aforementioned dual-core lock-step device P2 and dual-core lock-step device P2′ each have only one slave computing unit, and the technical solution of the present application is also applicable to a dual-core lock-step device including multiple slave computing units.

[0085] For example, Figure 5 According to some embodiments of the present application, a schematic structural diagram of a dual-core lockstep device P3 is shown.

[0086] like Figure 5 As shown, the dual-core lock-step device 3 includes: a main computing unit MP3, a slave computing unit SP3, a slave computing unit SP4, an input delay circuit ID3, an input delay circuit ID4, an output delay circuit OD5, an output delay circuit OD6, an output delay circuit OD7, a comparison circuit C3-1, a comparison circuit C3-2, a comparison circuit C3-3, a comparison circuit C3-4, and a comparison circuit C3-5.

[0087] The main calculation unit MP3 is used to receive input instructions to generate main calculation results, and output the main calculation results to the output delay circuit OD5 and the control unit CT3. For example, the main calculation unit MP3 can be used to receive the driver's operation, road data, and vehicle motion data, and generate a control signal based on the received driver's operation, road data, and vehicle motion data, and send the control signal to the delay circuit OD5 and each controller.

[0088] The input delay circuit ID3 is used to receive the same input instruction as the master computing unit MP3 and output the input instruction to the slave computing unit SP3 after delaying the input instruction.

[0089] The input delay circuit ID4 is used to receive the same input instruction as the main computing unit MP3 and output the input instruction to the slave computing unit SP4 after delaying the input instruction.

[0090] The slave calculation unit SP3 is used to receive an input instruction of the input delay circuit ID4, generate a slave calculation result based on the received input instruction, and send the slave calculation result to the output delay circuit OD7.

[0091] The slave calculation unit SP4 is used to receive an input instruction of the input delay circuit ID3, generate a slave calculation result based on the received input instruction, and send the slave calculation result to the output delay circuit OD6.

[0092] Output delay circuit OD5, output delay circuit OD6 and output delay circuit OD7 are used to delay the main calculation result, the slave calculation result generated by the slave calculation unit SP4 and the slave calculation result generated by the slave calculation unit SP3, respectively, and transmit the delayed main calculation result and the slave calculation result to the comparison circuit C3-1, so that the main calculation result and each slave calculation result have the same phase, that is, the main calculation result and each slave calculation result at each moment are obtained based on the same instruction.

[0093] The comparison circuit C3-1 is used to compare the master calculation result and the slave calculation result, and output a lock step result 1. The lock step result 1 is true (eg, binary 1) when the master calculation result and each slave calculation result are the same, and false (eg, binary 0) otherwise.

[0094] It can be understood that in some embodiments, the lock-step result output by the comparison circuit C3-1 can also be true when the number of identical results in the master calculation result and each slave calculation result is greater than a preset number, otherwise it is false. For example, it is true when at least two calculation results in the master calculation result and each slave calculation result are the same, which is not limited here.

[0095] The comparison circuit C3-2 is used to compare the cache data 3 of the master computing unit MP3 in the process of generating the master computing result, the cache data 4 of the slave computing unit SP3 in the process of generating the slave computing result, and the cache data 5 of the slave computing unit SP4 in the process of generating the slave computing result, and output the lock step result 2. The lock step result 2 is true (for example, binary 1) when the cache data 3, the cache data 4, and the cache data 5 are all the same, otherwise it is false (for example, binary 0).

[0096] It can be understood that in some embodiments, the lock-step result 2 output by the comparison circuit C3-2 can also be true when the number of identical data in cache data 3, cache data 4, and cache data 5 is greater than a preset number, otherwise it is false. For example, it is true when at least 2 of cache data 3, cache data 4, and cache data 5 are identical, otherwise it is false. This is not limited here.

[0097] It can be understood that in some embodiments, a delay circuit can also be set between the comparison circuit C3-2 and the main processing unit MP3, between the comparison circuit C3-2 and the slave processing unit SP3, and between the comparison circuit C3-2 and the slave processing unit SP4, so that the cache data 3, cache data 4 and cache data 5 have the same phase, that is, the cache data 3, cache data 4 and cache data 5 at each moment are obtained based on the same instruction.

[0098] The comparison circuit C3-3 is used to compare the tightly coupled memory data 3 of the master computing unit MP3 in the process of generating the master computing result, the tightly coupled memory data 4 of the slave computing unit SP3 in the process of generating the slave computing result, and the tightly coupled memory data 5 of the slave computing unit SP4 in the process of generating the slave computing result, and output the lock step result 3. The lock step result 3 is true (for example, binary 1) when the tightly coupled memory data 3, the tightly coupled memory data 4 and the tightly coupled memory data 5 are the same, otherwise it is false (for example, binary 0).

[0099] It can be understood that in some embodiments, the lock-step result 3 output by the comparison circuit C3-3 may also be true when the number of identical data among the tightly coupled memory data 3, the tightly coupled memory data 4 and the tightly coupled memory data 5 is greater than a preset number, otherwise it is false. For example, it is true when at least 2 of the tightly coupled memory data 3, the tightly coupled memory data 4 and the tightly coupled memory data 5 are the same, otherwise it is false, and this is not limited here.

[0100] It can be understood that in some embodiments, a delay circuit can also be set between the comparison circuit C3-3 and the main processing unit MP3, between the comparison circuit C3-3 and the slave processing unit SP3, and between the comparison circuit C3-3 and the slave processing unit SP4, so that the tightly coupled memory data 3, the tightly coupled memory data 4 and the tightly coupled memory data 5 have the same phase, that is, the tightly coupled memory data 3, the tightly coupled memory data 4 and the tightly coupled memory data 5 at each moment are obtained based on the same instruction.

[0101] The comparison circuit C3-4 is used to compare the interruption data 3 of the master calculation unit MP3 in the process of generating the master calculation result, the interruption data 4 of the slave calculation unit SP3 in the process of generating the slave calculation result, and the interruption data 5 of the slave calculation unit SP4 in the process of generating the slave calculation result, and output the lock step result 4. The lock step result 4 is true (for example, binary 1) when the interruption data 3, the interruption data 4, and the interruption data 5 are the same, otherwise it is false (for example, binary 0).

[0102] It can be understood that in some embodiments, the lock-step result 4 output by the comparison circuit C3-4 can also be true when the number of identical interrupt data 3, interrupt data 4, and interrupt data 5 is greater than a preset number, otherwise it is false. For example, it is true when at least 2 of the interrupt data 3, interrupt data 4, and interrupt data 5 are the same, otherwise it is false. This is not limited here.

[0103] It can be understood that in some embodiments, a delay circuit can also be set between the comparison circuit C3-4 and the main processing unit MP3, between the comparison circuit C3-4 and the slave processing unit SP3, and between the comparison circuit C3-4 and the slave processing unit SP4, so that the interrupt data 3, interrupt data 4 and interrupt data 5 have the same phase, that is, the interrupt data 3, interrupt data 4 and interrupt data 5 at each moment are obtained based on the same instruction.

[0104] The comparison circuit C3-5 is used to compare the input instructions and / or data related to the input instructions received by the master computing unit MP3 and the slave computing units SP3 and SP4, and output the lock step result 5. The lock step result 5 is true (e.g., binary 1) when the input instructions and / or data related to the input instructions received by the master computing unit MP3 and the slave computing units SP3 and SP4 are the same, and false (e.g., binary 0) otherwise.

[0105] It can be understood that in some embodiments, the lock-step result 5 output by the comparison circuit C3-5 may also be in the input instructions and / or input instruction-related data received by the main computing unit MP3 and the slave computing units SP3 and SP4, and is true when the same number is greater than a preset number, otherwise it is false, and no limitation is made here.

[0106] It can be understood that in some embodiments, a delay circuit can also be set between the comparison circuit C3-5 and the input delay circuit ID3, and between the comparison circuit C3-5 and the input delay circuit ID3, so that the input instructions and / or data related to the input instructions received by the main computing unit MP3 and the slave computing unit SP3, and the slave computing unit SP4 have the same phase.

[0107] Therefore, the control unit CT3 can adopt different processing methods based on the data of the lock step results 1 to 5.

[0108] For example, when the lock step result 1 and the lock step result 5 are 0, it means that the input data and / or the data related to the input instruction received by the main computing unit MP3 and the slave computing unit SP3 and the slave computing unit SP4 are different, and naturally different results will be produced, but the result is not caused by the internal error of the main computing unit MP3, the slave computing unit SP3 and the slave computing unit SP4. The control unit CT3 can directly output the main calculation result as the calculation result without re-executing the instruction when the input instruction received by the main computing unit MP3 is the same as the instruction to be actually executed and the data related to the received input instruction is the same as the data of the instruction to be actually executed, thereby improving the efficiency of the dual-core lock step device P3 in executing instructions.

[0109] For another example, when the control unit CT3 detects that the lock-step result 5 indicates that the input data or data related to the input instruction received by the main computing unit MP3 and the slave computing units SP3, SP4 are different, but the main computing unit MP3 and the slave computing units SP3, SP4 have not yet generated the corresponding calculation results, the control unit CT3 can send an interrupt to the main computing unit MP3 and the slave computing units SP3, SP4, so that the main computing unit MP3 and the slave computing units SP3, SP4 can terminate the calculation process and re-acquire the input data and / or data related to the input instruction to obtain the calculation result, without having to wait for the calculation results generated by the main computing unit MP3 and the slave computing units SP3, SP4 to be different and then recalculate, thereby improving the speed at which the dual-core lock-step device P3 responds to errors.

[0110] An embodiment of the present application further provides a processor, which includes any dual-core lock-step device provided in the aforementioned embodiments, such as the aforementioned dual-core lock-step device P2, dual-core lock-step device P2′, dual-core lock-step device P3, etc.

[0111] The present application also provides an electronic device. Specifically, Figure 6 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device 100 is shown. Figure 6As shown, the electronic device 100 includes one or more processors 101, a system memory 102, a non-volatile memory (NVM) 103, a communication interface 104, an input / output (I / O) device 105, a control unit 107, and a system control logic 106 for coupling the processor 101, the system memory 102, the non-volatile memory 103, the communication interface 104, the input / output (I / O) device 105 and the control unit 107. Among them:

[0112] The processor 101 may include a main computing unit and at least one slave computing unit, and the main computing unit and the slave computing unit may be one or more of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microprocessor (MCU), an artificial intelligence (AI) processor or a programmable logic device (Field Programmable Gate Array, FPGA), and a neural network processor (Neural-network Processing Unit, NPU). The main computing unit and at least one slave processing unit may be used to execute instructions and generate corresponding main computing results or slave computing results.

[0113] The processor 101 may also include a comparison circuit for comparing calculation results generated by a main computing unit and at least one slave computing unit, and for comparing intermediate data in a process in which the main computing unit generates a main calculation result and intermediate data in a process in which the slave computing unit generates a slave calculation result, and obtaining corresponding comparison results (i.e., the lock-step results mentioned above).

[0114] In some embodiments, the processor 101 may include the aforementioned dual-core lock-step device P2 , dual-core lock-step device P2 ′, or dual-core lock-step device P3 .

[0115] The control unit 107 is used to receive the main calculation result and the lock-step result generated by the processor 101, and output the main calculation result or send an interrupt to re-execute the instruction to the processor 101 according to the lock-step result. For details, please refer to the description of the control unit CT2 and the control unit CT3 above, which will not be repeated here.

[0116] The system memory 102 is a volatile memory, such as a random-access memory (RAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc. The system memory is used to temporarily store data and / or instructions. For example, in some embodiments, the system memory 102 can be used for main calculation results.

[0117] The non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 103 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 103 may also be a removable storage medium, such as a secure digital (SD) memory card, etc. In other embodiments, the non-volatile memory 103 may be used to store data or instructions.

[0118] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, and then communicating with any other suitable device through one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104. For example, the electronic device 100 may send calculation results to other electronic devices through the communication interface 104.

[0119] The input / output (I / O) device 105 may include input devices such as a keyboard, a mouse, etc., and output devices such as a display, etc. A user may interact with the electronic device 100 via the input / output (I / O) device 105 .

[0120] The system control logic 106 may include any suitable interface controller to provide any suitable interface with other modules of the electronic device 100. For example, in some embodiments, the system control logic 106 may include one or more memory controllers to provide an interface for the processor to access the system memory 102 and the non-volatile memory 103 through a bus interface.

[0121] In some embodiments, at least one of the processors 101 may be packaged together with the logic of one or more controllers for the system control logic 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101 may also be integrated with the logic of one or more controllers for the system control logic 106 on the same chip to form a system-on-chip (SoC).

[0122] Understandably, Figure 6 The structure of the electronic device 100 shown is only an example. In other embodiments, the electronic device 100 may include more or fewer components than shown, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0123] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device and at least one output device.

[0124] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0125] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0126] It should be noted that in the examples and description of this patent, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises one" does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0127] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A dual-core lockstep method, characterized in that: include: Acquire a main calculation result generated by a main calculation unit of a computing device executing a first instruction and first intermediate data generated in the process of generating the main calculation result, and acquire a secondary calculation result generated by a secondary calculation unit of the computing device executing the first instruction and second intermediate data corresponding to the first intermediate data generated in the process of generating the secondary calculation result; Corresponding to the master calculation result being different from the slave calculation result, generating a calculation result of the first instruction based on a comparison result of the first intermediate data and the second intermediate data; The first intermediate data includes at least one of the following data: first cache data generated in the process of the main computing unit generating the main computing result, first input data received in the process of the main computing unit generating the main computing result, first input instruction received in the process of the main computing unit generating the main computing result, first interrupt data received or generated in the process of the main computing unit generating the main computing result, and first tightly coupled memory data generated in the process of the main computing unit generating the main computing result; The second intermediate data includes at least one of the following data: second cache data generated by the slave computing unit in the slave computing process, second input data received by the slave computing unit in the slave computing process, second input instructions received by the slave computing unit in the slave computing process, second interrupt data received or generated by the slave computing unit in the slave computing process, and second tightly coupled memory data generated by the slave computing unit in the slave computing process; The generating a calculation result of the first instruction based on a comparison result of the first intermediate data and the second intermediate data includes: In the case where the first input data and the second input data are different, and / or the first input instruction and the second input instruction are different, If the first input data is the same as the input data corresponding to the first instruction, the first input instruction is the same as the first instruction, and the main calculation result is used as the calculation result of the first instruction; When the first input instruction is the same as the second input instruction and the first input data is the same as the second input data, If the first cache data and the second cache data are different, or the first interrupt data and the second interrupt data are different, or the first tightly coupled memory data and the second tightly coupled memory data are different, the first instruction is re-executed using the master computing unit and the slave computing unit to obtain a calculation result of the first instruction.

2. A dual-core lockstep device, characterized in that: include: A main computing unit, configured to execute a first instruction to generate a main computing result, and to generate first intermediate data in the process of generating the main computing result; A slave computing unit, configured to execute the first instruction to generate a slave computing result, and to generate second intermediate data in the process of generating the slave computing result; a comparing unit, configured to compare the first intermediate data and the second intermediate data, generate and output a first comparison result, wherein the first comparison result can be used to generate a calculation result of the first instruction when the master calculation result and the slave calculation result are different; a control unit, configured to generate a calculation result of the first instruction based on the first comparison result when the master calculation result is different from the slave calculation result; The first intermediate data includes at least one of the following data: first cache data generated in the process of the main computing unit generating the main computing result, first input data received in the process of the main computing unit generating the main computing result, first input instruction received in the process of the main computing unit generating the main computing result, first interrupt data received or generated in the process of the main computing unit generating the main computing result, and first tightly coupled memory data generated in the process of the main computing unit generating the main computing result; The second intermediate data includes at least one of the following data: second cache data generated by the slave computing unit in the slave computing process, second input data received by the slave computing unit in the slave computing process, second input instructions received by the slave computing unit in the slave computing process, second interrupt data received or generated by the slave computing unit in the slave computing process, and second tightly coupled memory data generated by the slave computing unit in the slave computing process; The control unit generates a calculation result of the first instruction based on the first comparison result in the following manner: When the first comparison result indicates that the first input data is different from the second input data, and / or the first input instruction is different from the second input instruction, the control unit If the first input data is the same as the input data corresponding to the first instruction, the first input instruction is the same as the first instruction, and the main calculation result is used as the calculation result of the first instruction; When the first comparison result indicates that the first input instruction is the same as the second input instruction, and the first input data is the same as the second input data, the control unit If the first cache data and the second cache data are different, or the first interrupt data and the second interrupt data are different, or the first tightly coupled memory data and the second tightly coupled memory data are different, the first instruction is re-executed using the master computing unit and the slave computing unit to obtain a calculation result of the first instruction.

3. The device according to claim 2, characterized in that Also includes: A classification unit is used to output an error type to the control unit according to the first comparison result, and the error type is used to indicate whether it is necessary to re-execute the first instruction to obtain the calculation result of the first instruction.

4. The device according to claim 2, characterized in that Also includes: A delay unit, used for adjusting the phase of the main calculation result and / or the slave calculation result, and outputting the main calculation result and the slave calculation result having the same phase to the comparison unit, and for adjusting the phase of the first intermediate data and / or the second intermediate data, and outputting the first intermediate data and the second intermediate data having the same phase to the comparison unit.

5. An electronic device, characterized in that: The electronic device comprises the dual-core lockstep device according to any one of claims 2 to 4.

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