System for Verifying the DDR Controller of an SOC Chip Based on FPGA

Abstract

The present invention provides a system for verifying the DDR controller of an SOC chip based on an FPGA, including: the DDR controller of the SOC chip to be verified, a DFI-AXI bridge, an FPGA DDR controller, an FPGA DDR PHY, and a DDR particle. The DFI-AXI bridge is connected to the DDR controller of the SOC chip through a DFI interface and to the FPGA DDR controller through an AXI interface. The DFI-AXI bridge is used to perform protocol conversion between DFI and AXI, so as to interact between the DDR controller of the SOC chip and the FPGA DDR controller; the FPGA DDR controller is connected to the FPGA DDR PHY through an FPGA internal bus, and the FPGA DDR PHY is connected to the DDR particle. The present invention realizes the verification of the DDR controller of the SOC chip on the FPGA hardware prototype verification platform, and improves the success rate of chip tape-out.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular, to a system for verifying a DDR controller of an SOC chip based on an FPGA. Background Art

[0002] With the wide application of big data and artificial intelligence, in order to efficiently process massive data, more and more system-on-chip (SOC) chips are integrated with DDR controllers to reduce memory latency. Figure 1 An example of an SOC chip integrated with a DDR controller is shown. The DDR controller integrated with the SOC chip is also called the SOC chip DDR controller. As Figure 1 shown, the SOC chip DDR controller is connected to DDR particles outside the SOC chip through the SOC chip DDR physical layer (DDR PHY), and is used to control the access to the memory, including controlling read / write request signals, address signals, data signals, command signals, etc. Verifying the SOC chip DDR controller is a key link in the entire SOC chip verification process. Currently, the platforms used to verify SOC chips mainly include RTL software simulation verification platforms and FPGA hardware prototype verification platforms. The SOC chip verification can be carried out based on any of these two platforms.

[0003] The solution based on the RTL software simulation verification platform is to integrate the DDR SDRAM memory model into the verification environment, write test stimuli and provide them to the SOC processor. The SOC processor sends stimuli to the DDR through the bus and receives responses, thereby realizing the verification of the SOC chip function. This solution can observe all the signal waveforms inside the SOC chip, so it can discover hardware design problems as early as possible. However, due to the large logic of the SOC chip DDR controller and the large number of test items, the simulation speed on the RTL software simulation verification platform is slow and cannot be quickly iterated, resulting in a longer R & D cycle of the SOC chip.

[0004] The solution based on the FPGA hardware prototype verification platform uses FPGA to piece together an effective process to verify the function of the SOC chip. Since the DDR PHY in the SOC chip is an actual circuit fixed in the SOC chip and cannot be synthesized again, and there may be significant differences between the FPGA DDR PHY and the SOC chip DDR PHY, resulting in incompatibility between the FPGA DDR PHY and the SOC chip DDR controller. Therefore, the current FPGA hardware prototype verification platform usually uses an FPGA DDR controller and an FPGA DDR PHY to replace the SOC chip DDR controller and the SOC chip DDR PHY respectively to perform the verification of the SOC chip (see Figure 2) Obviously, the current FPGA hardware prototype verification platform cannot verify the DDR controller of the SOC chip. On the one hand, there are differences between the DDR controller of the SOC chip and the FPGA DDR controller. Verifying the SOC chip by replacing the DDR controller and the DDR PHY may lead to serious errors in the verification results of the FPGA hardware prototype verification platform, and the DDR types supported by some FPGA hardware prototype verification platforms may be incompatible with the DDR controller of the SOC chip and cannot be used for the verification of the SOC chip; on the other hand, since the FPGA hardware prototype verification platform cannot verify the DDR controller of the SOC chip, the risk of chip tape-out failure is increased. Summary of the Invention

[0005] In order to overcome the defects existing in the above-mentioned prior art, the present invention provides a system for verifying the DDR controller of an SOC chip based on an FPGA. The system includes a DDR controller of the SOC chip to be verified, a DFI-AXI bridge, an FPGA DDR controller, an FPGA DDR PHY, and DDR particles. Among them, the DFI-AXI bridge is connected to the DDR controller of the SOC chip through a DFI interface and connected to the FPGA DDR controller through an AXI interface. The DFI-AXI bridge is used to perform protocol conversion between DFI and AXI to interact between the DDR controller of the SOC chip and the FPGA DDR controller; the FPGA DDR controller is connected to the FPGA DDR PHY through an FPGA internal bus; and, the FPGA DDR PHY is connected to the DDR particles.

[0006] In the above system, the DFI-AXI bridge includes a transmission transaction processing module and a reception transaction processing module. The transmission transaction processing module decodes the write command, write address, and write data from the DDR controller of the SOC chip, performs DFI-to-AXI protocol conversion on the write address and write data according to the write command, and sends the protocol-converted write address and write data to the FPGA DDR controller. The reception transaction processing module decodes the read command and read address from the DDR controller of the SOC chip, performs DFI-to-AXI protocol conversion on the read address according to the read command, and sends the protocol-converted read address to the FPGA DDR controller.

[0007] In the above system, the sending transaction processing module further decodes the write response from the FPGA DDR controller, performs AXI-to-DFI protocol conversion on the write response, and sends the protocol-converted write response to the SOC chip DDR controller. The receiving transaction processing module further decodes the read data from the FPGA DDR controller, performs AXI-to-DFI protocol conversion on the read data, and sends the protocol-converted read data to the SOC chip DDR controller.

[0008] In the above system, the sending transaction processing module includes a write operation control unit and a write sending unit. The write operation control unit decodes the write command, write address, and write data from the SOC chip DDR controller, and writes the write command, write address, and write data into the write command queue, write address queue, and write data queue respectively. The write sending unit obtains the write command from the write command queue, obtains the write address and write data from the write address queue and write data queue respectively according to the write command, performs DFI-to-AXI protocol conversion on the write address and write data, and sends the protocol-converted write address and write data to the FPGA DDR controller. Among them, the write command queue, write address queue, and write data queue respectively implement cross-clock domain operations.

[0009] In the above system, the write sending unit further decodes the write response from the FPGA DDR controller, performs AXI-to-DFI protocol conversion on the write response, and writes the protocol-converted write response into the write response queue; and the write operation control unit further obtains the write response from the write response queue and sends the write response to the SOC chip DDR controller. Among them, the write response queue implements cross-clock domain operations.

[0010] In the above system, the write operation control unit further performs the following controls:

[0011] For the write sending unit in the write idle state, when any one of the write command queue, write address queue, and write data queue is not empty, the write operation control unit controls the write sending unit to enter the write enable state; for the write sending unit in the write enable state, it searches for the corresponding write address and write data in the write address queue and write data queue according to the write command in the write command queue. If found, it controls the write sending unit to enter the write sending state, so that the write sending unit performs the protocol conversion from DFI to AXI on the write address and write data in the write sending state and sends the protocol-converted write address and write data to the FPGA DDR controller. If not found, it controls the write sending unit to enter the write waiting state, and waits until the corresponding write address and write data are found in the write address queue and write data queue, and then controls the write sending unit to enter the write sending state; for the write sending unit in the write sending state, when the write command queue, write address queue, and write data queue are all empty, the write operation control unit controls the write sending unit to enter the write idle state.

[0012] In the above system, the receiving transaction processing module includes a read operation control unit and a read receiving unit. The read operation control unit decodes the read command and read address from the SOC chip DDR controller, and writes the read command and read address into the read command queue and read address queue respectively; the read receiving unit obtains the read command from the read command queue, obtains the read address from the read address queue according to the read command, performs the protocol conversion from DFI to AXI on the read address, and sends the protocol-converted read address to the FPGA DDR controller. Among them, the read command queue and the read address queue respectively implement cross-clock domain operations.

[0013] In the above system, the read receiving unit also decodes the read data from the FPGA DDR controller, performs the protocol conversion from AXI to DFI on the read data, and writes the protocol-converted read data into the read data queue; and, the read operation control unit also obtains the read data from the read data queue and sends the read data to the SOC chip DDR controller. Among them, the read data queue implements cross-clock domain operation.

[0014] In the above system, the read operation control unit also performs the following controls:

[0015] For the read receiving unit in the read idle state, when the read command queue or the read address queue is not empty, the read operation control unit controls the read receiving unit to enter the read enable state; for the read receiving unit in the read enable state, it searches for the corresponding read address in the read address queue according to the read command in the read command queue. If found, it controls the read receiving unit to enter the read receiving state, so that the read receiving unit performs the protocol conversion from DFI to AXI on the read address in the read receiving state and sends the protocol-converted read address to the FPGA DDR controller. If not found, it controls the read receiving unit to enter the read waiting state, and waits until the corresponding read address is found in the read address queue and then controls the read receiving unit to enter the read receiving state; for the read receiving unit in the read receiving state, when both the read command queue and the read address queue are empty, the read operation control unit controls the read receiving unit to enter the read idle state.

[0016] The queues in the above system can adopt asynchronous cross-clock domain FIFO queues.

[0017] The embodiments of the present invention can achieve the following beneficial effects:

[0018] The present invention provides a system for verifying the DDR controller of an SOC chip based on an FPGA, which overcomes the problem that the existing FPGA hardware prototype verification platform cannot verify the DDR controller of the SOC chip, and realizes the verification of the DDR controller of the SOC chip on the FPGA hardware prototype verification platform. Compared with the verification scheme based on the RTL software simulation verification platform, the present invention improves the verification speed of the DDR controller of the SOC chip. Since the verification speed is relatively fast, more test programs can be verified and sufficient verification can be achieved, so the success rate of chip tape-out is also improved. By designing the DFI-AXI bridge, the present invention realizes the protocol conversion between the DDR controller of the SOC chip and the FPGA DDR controller, so that the verification of the DDR controller of the SOC chip does not depend on the specific model of the FPGA and the type of DDR, and has good compatibility.

[0019] It should be understood that the above general description and the following detailed description are only illustrative and explanatory, and are not used to limit the present invention. Brief Description of the Drawings

[0020] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention, wherein:

[0021] Figure 1 Schematically shows a block diagram of an SOC chip integrated with a DDR controller according to an embodiment of the present invention;

[0022] Figure 2Schematically shows a block diagram of an FPGA hardware prototype verification platform according to an embodiment of the present invention;

[0023] Figure 3 Schematically shows a block diagram of a system for verifying a DDR controller of an SOC chip based on an FPGA according to an embodiment of the present invention;

[0024] Figure 4 Schematically shows a block diagram of a DFI-AXI bridge according to an embodiment of the present invention;

[0025] Figure 5 Schematically shows a flowchart of a protocol conversion process between DFI and AXI according to an embodiment of the present invention;

[0026] Figure 6 Schematically shows a state transition diagram of a write sending unit according to an embodiment of the present invention;

[0027] Figure 7 Schematically shows a state transition diagram of a read receiving unit according to an embodiment of the present invention;

[0028] Figure 8 Schematically shows a block diagram of a DFI-AXI bridge according to another embodiment of the present invention. Detailed implementation manners

[0029] To make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below through specific embodiments with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] The inventors found that the reason why the prior art cannot verify the DDR controller of an SOC chip based on an FPGA lies in the interface difference. This problem can be solved by adding a protocol conversion bridge (i.e., a DFI-AXI bridge) between the DDR controller of the SOC chip and the inherent DDR controller of the FPGA. The DFI-AXI bridge is used to implement the protocol conversion between the DFI interface for connecting the DDR PHY in the DDR controller of the SOC chip and the AXI interface in the DDR controller of the FPGA, so as to verify the DDR controller of the SOC chip on the FPGA hardware prototype verification platform.

[0031] The present invention provides a system for verifying the DDR controller of an SOC chip based on an FPGA, which realizes the verification of the DDR controller of the SOC chip on the FPGA hardware prototype verification platform. Generally speaking, the system provides a DFI-AXI bridge and combines with the existing FPGA DDR storage path, where the DFI-AXI bridge is used to perform protocol conversion between the DFI interface of the SOC chip DDR controller and the AXI interface of the FPGA DDR controller. The present invention is not limited by the FPGA DDR storage structure, and the DFI-AXI bridge can be combined with any type of DDR particle and any model of FPGA to realize the verification of the SOC chip DDR controller.

[0032] Figure 3 FIG. schematically shows a block diagram of a system for verifying the DDR controller of an SOC chip based on an FPGA according to an embodiment of the present invention, as Figure 3 shown, the system includes: the DDR controller of the SOC chip to be verified, a DFI-AXI bridge, an FPGA DDR controller, an FPGA DDR PHY, and a DDR particle. Among them, the DFI-AXI bridge is connected to the SOC chip DDR controller through the DFI interface and connected to the FPGA DDR controller through the AXI interface. The DFI-AXI bridge is used to perform protocol conversion between DFI and AXI, so as to perform data interaction between the SOC chip DDR controller and the FPGA DDR controller; in addition, the FPGA DDR controller is connected to the FPGA DDR PHY through the FPGA internal bus, and the FPGA DDR PHY is connected to the DDR particle. The following will refer to Figure 3 - 7 to describe each part of the system separately.

[0033] 1) DDR Controller of SOC Chip

[0034] In the SOC chip, the SOC chip DDR controller is connected to the bus of the SOC chip through the Advanced eXtensible Interface (AXI) interface and connected to the supporting SOC chip DDR PHY through the DDR PHY Interface (DFI) interface. In the system for verifying the DDR controller of the SOC chip based on the FPGA, the DDR controller of the SOC chip to be verified is connected to the bus through the AXI interface, commands and data are transmitted through this bus (such as receiving requests to access memory from this bus, etc.), and is connected to the DFI-AXI bridge through the DFI interface.

[0035] 2) DFI - AXI Bridge

[0036] The DFI-AXI bridge is connected to the DDR controller of the SOC chip to be verified through the DFI interface and to the FPGA DDR controller through the AXI interface. Generally speaking, the DFI-AXI bridge is used to implement the protocol conversion between the SOC chip DDR controller and the FPGA DDR controller (abbreviated as the protocol conversion between DFI and AXI), and at the same time filter out unnecessary commands and data. Figure 4 The structural block diagram of the DFI-AXI bridge is schematically shown as Figure 4 shown. The DFI-AXI bridge includes a transmit transaction processing module and a receive transaction processing module, which will be described separately below.

[0037] - Transmit transaction processing module

[0038] The transmit transaction processing module is used to receive and decode the write command, write address, and write data from the SOC chip DDR controller through the DFI interface, perform DFI-to-AXI protocol conversion on the write address and write data according to the write command, and send the protocol-converted write address and write data to the FPGA DDR controller through the AXI interface. In the opposite direction, the transmit transaction processing module also receives and decodes the write response from the FPGA DDR controller through the AXI interface, performs AXI-to-DFI protocol conversion on the write response, and sends the protocol-converted write response to the SOC chip DDR controller through the DFI interface.

[0039] See Figure 4 , the transmit transaction processing module further includes a write operation control unit and a write sending unit. Now, in combination with Figure 5Describe the protocol conversion process between DFI and AXI cooperated by the write operation control unit and the write sending unit: The write operation control unit in the transmit transaction processing module receives commands and data from the DDR controller of the SOC chip through the DFI interface and decodes them; for the decoded write command, write address, and write data, the write operation control unit writes the write command, write address, and write data into the write command queue, write address queue, and write data queue respectively, where the write command queue, write address queue, and write data queue can be three separate asynchronous cross-clock domain FIFO queues for implementing cross-clock domain operations respectively, and the write command queue, write address queue, and write data queue can be either inside or outside the write sending unit; the write sending unit obtains the write command from the write command queue, obtains the corresponding write address and write data from the write address queue and write data queue respectively according to the write command, performs the protocol conversion from DFI to AXI on the write address and write data, and sends the protocol-converted write address and write data to the FPGA DDR controller through the AXI interface. In the above process, flow control operations can be performed on the write command queue, write address queue, and write data queue to ensure the correctness of the transmit transaction processing. In the opposite direction, the write sending unit receives commands and data from the FPGA DDR controller through the AXI interface and decodes them; for the decoded write response, the write sending unit performs the protocol conversion from AXI to DFI on the write response and writes the protocol-converted write response into the write response queue, where the write response queue can be an asynchronous cross-clock domain FIFO queue for implementing cross-clock domain operations, and the write response queue can be either inside or outside the write sending unit; the write operation control unit obtains the write response from the write response queue and sends the write response to the DDR controller of the SOC chip through the DFI interface.

[0040] The write operation control unit also monitors the status of the write command queue, write address queue, and write data queue, and controls the status of the write sending unit according to the status of these queues. Such as Figure 6As shown, the states of the write transmission unit include four states: write idle, write enable, write wait, and write transmit. When the write command queue, write address queue, and write data queue are all empty, the write transmission unit is in the write idle state, which is the initial state. When the write operation control unit receives and decodes the write command, write address, and write data from the DDR controller of the SOC chip, it will write the decoded write command, write address, and write data into the write command queue, write address queue, and write data queue respectively. When any one of the write command queue, write address queue, and write data queue is not empty, the write operation control unit controls the write transmission unit to enter the write enable state. In the write enable state, when the write command queue is not empty, the write operation control unit controls the write transmission unit to obtain the write command from the write command queue, and find the corresponding write address and write data from the write address queue and write data queue according to the write command; if found, the write operation control unit controls the write transmission unit to enter the write transmit state, so that the write transmission unit performs the protocol conversion from DFI to AXI on the write address and write data in the write transmit state, and sends the protocol-converted write address and write data to the FPGA DDR controller through the AXI interface; if not found (for example, the queue is full but the write address or write data has not arrived yet), the write operation control unit controls the write transmission unit to enter the write wait state, and then controls the write transmission unit to enter the write transmit state after finding the corresponding write address and write data in the write address queue and write data queue. When the write command queue, write address queue, and write data queue are all empty and the empty state lasts for a certain period of time, the write operation control unit controls the write transmission unit to enter the write idle state.

[0041] - Receive transaction processing module

[0042] The receive transaction processing module is used to receive and decode the read command and read address from the DDR controller of the SOC chip through the DFI interface, perform the protocol conversion from DFI to AXI on the read address according to the read command, and send the protocol-converted read address to the FPGA DDR controller through the AXI interface. In the opposite direction, the receive transaction processing module also receives and decodes the read data from the FPGA DDR controller through the AXI interface, performs the protocol conversion from AXI to DFI on the read data, and sends the protocol-converted read data to the SOC chip DDR controller through the DFI interface.

[0043] See Figure 4 As shown, the receive transaction processing module further includes a read operation control unit and a read receive unit. Now, in combination with Figure 5Describe the protocol conversion process between DFI and AXI that the read operation control unit and the read reception unit cooperate to execute: The read operation control unit in the receive transaction processing module receives commands and data from the DDR controller of the SOC chip through the DFI interface and decodes them; for the read commands and read addresses obtained by decoding, the read operation control unit writes the read commands and read addresses into the read command queue and the read address queue respectively, where the read command queue and the read address queue can be two separate asynchronous cross-clock domain FIFO queues for implementing cross-clock domain operations respectively, and they can be located either inside or outside the read reception unit; the read reception unit obtains the read command from the read command queue, obtains the corresponding read address from the read address queue according to the read command, performs the protocol conversion from DFI to AXI on the read address, and sends the read address after protocol conversion to the FPGA DDR controller through the AXI interface. In the above process, traffic control operations can be performed on the read command queue and the read address queue to ensure the correctness of the receive transaction processing. In the opposite direction, the read reception unit receives commands and data from the FPGA DDR controller through the AXI interface and decodes them; for the read data decoded, the read reception unit performs the protocol conversion from AXI to DFI on the read data, and writes the read data after protocol conversion into the read data queue, where the read data queue can be an asynchronous cross-clock domain FIFO queue for implementing cross-clock domain operations, and it can be located either inside or outside the read reception unit; the read operation control unit obtains the read data from the read data queue and sends the read data to the DDR controller of the SOC chip through the DFI interface.

[0044] The read operation control unit also monitors the read command queue and the read address queue and controls the state of the read reception unit according to the states of these queues. For example Figure 7As shown, the states of the read reception unit include read idle, read enable, read wait, and read reception. When both the read command queue and the read address queue are empty, the read reception unit is in the read idle state. After the read operation control unit receives and decodes the read command and read address from the DDR controller of the SOC chip, it writes the decoded read command and read address into the read command queue and the read address queue respectively. When either the read command queue or the read address queue is not empty, the read operation control unit controls the read reception unit to enter the read enable state. In the read enable state, when the read command queue is not empty, the read operation control unit controls the read reception unit to obtain the read command from the read command queue, and searches for the corresponding read address in the read address queue according to this read command; if found, the read operation control unit controls the read reception unit to enter the read reception state, so that the read reception unit performs the protocol conversion from DFI to AXI on the read address in the read reception state, and sends the protocol-converted read address to the FPGA DDR controller through the AXI interface; if not found, the read operation control unit controls the read reception unit to enter the read wait state, and then controls the read reception unit to enter the read reception state after finding the corresponding read address in the read address queue. When both the read command queue and the read address queue are empty and the empty state lasts for a certain period of time, the read operation control unit controls the read reception unit to enter the read idle state.

[0045] 3) DDR Controller of FPGA

[0046] The FPGA DDR controller is an inherent module of the FPGA. It should be understood that a matching FPGA DDR controller can be selected according to the model of the FPGA and the type of the DDR chip. The FPGA DDR controller is connected to the DFI-AXI bridge through the AXI interface, and is connected to the FPGA DDR PHY through the dedicated internal bus of the FPGA. The FPGA DDR controller receives the write address, write data, and / or read address from the DFI-AXI bridge and sends them to the FPGA DDR PHY through the dedicated internal bus of the FPGA, and receives the write response and / or read data from the FPGA DDR PHY and sends them to the DFI-AXI bridge through the AXI interface.

[0047] 4) FPGA DDR PHY

[0048] Similar to the FPGA DDR controller, the FPGA DDR PHY is also an inherent module of the FPGA. Similarly, the appropriate FPGA DDR PHY can be selected according to the FPGA model and the type of DDR memory chip. The FPGA DDR PHY is connected to the FPGA DDR controller through a dedicated internal bus of the FPGA and interacts with the DDR memory chip. The FPGA DDR PHY receives the write address, write data, and / or read address from the FPGA DDR controller and sends them to the DDR memory chip, and receives the write response and / or read data from the DDR memory chip and sends them to the FPGA DDR controller.

[0049] 5) DDR Chip

[0050] The DDR memory chip, that is, the actual DDR memory chip, writes the write data to the corresponding location in the DDR memory chip according to the write address from the FPGA DDR PHY and returns a write response; or, obtains the read data at the corresponding location according to the read address from the FPGA DDR PHY and sends it to the FPGA DDR PHY.

[0051] In the above embodiment, by designing the DFI-AXI bridge, the protocol conversion between the DDR controller of the SOC chip and the FPGA DDR controller is realized, overcoming the problem that the existing FPGA hardware prototype verification platform cannot verify the DDR controller of the SOC chip, and realizing the verification of the DDR controller of the SOC chip on the FPGA hardware prototype verification platform; and making the verification of the DDR controller of the SOC chip independent of the specific FPGA model and the type of DDR memory chip. For example, Xilinx FPGA and DDR4 memory chips can be used, so the compatibility is better. In addition, the inventor found through experiments that it takes about 30 hours to perform DDR read and write of 16MB in size on the RTL software simulation verification platform, while it only takes about 30 seconds in the system provided in the above embodiment. Thus, it can be seen that the present invention also improves the verification speed of the DDR controller of the SOC chip. Due to the fast verification speed, more test programs can be verified and full verification can be achieved, so the success rate of the SOC chip tape-out is improved.

[0052] In the above embodiment, the DFI-AXI bridge is described as including a transmit transaction processing module and a receive transaction processing module. In other embodiments, the DFI-AXI bridge may further include other modules such as a command transaction processing module and an interaction transaction processing module, such as Figure 8As shown. The command transaction processing module is used to perform the startup and initialization operations of the DFI-AXI bridge before executing the DDR read / write transaction, determine whether the initialization operation is completed and whether the clock frequency ratio is correct. When it is determined that the initialization operation has been completed and the clock frequency ratio is correct, the DFI-AXI bridge can start to execute the DDR read / write transaction. The command transaction processing module can also interact with other modules of the DFI-AXI bridge (for example, the interactive transaction processing module). The interactive transaction processing module is used to process operations such as DFI status update, low-power control, and error status control, filter out unnecessary PHY commands and responses, and can interact with other modules in the DFI-AXI bridge to complete the corresponding control.

[0053] It should be understood that although several modules or units of the system are described above, the division method of the modules and units is not limited to this. In fact, the features and functions of the two or more modules or units described above can also be implemented in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and implemented by multiple modules or units.

[0054] It should be noted that some exemplary methods are depicted as flowcharts. Although the flowcharts represent the operations as being executed sequentially, it can be understood that many of the operations can be executed in parallel, simultaneously or synchronously. Additionally, the order of the operations can be rearranged. The processing can terminate when the operations are completed, or it can have additional steps not included in the drawings or embodiments.

[0055] Although the present invention has been described through preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above and shown in the drawings. Those skilled in the art can make various changes and modifications without departing from the scope of the present invention.

Claims

1. A system for verifying the DDR controller of an SOC chip based on FPGA, characterized in that The system includes: an SOC chip DDR controller to be verified, a DFI-AXI bridge, an FPGA DDR controller, an FPGA DDR PHY, and DDR chips; Among them, the DFI-AXI bridge is connected to the SOC chip DDR controller through a DFI interface and to the FPGA DDR controller through an AXI interface. The DFI-AXI bridge is used to perform protocol conversion between DFI and AXI to interact between the SOC chip DDR controller and the FPGA DDR controller. The FPGA DDR controller is connected to the FPGA DDR PHY through an FPGA internal bus. And the FPGA DDR PHY is connected to the DDR chips; Among them, the DFI-AXI bridge includes a transmit transaction processing module and a receive transaction processing module; The transmit transaction processing module includes a write operation control unit and a write transmit unit. Among them, the write operation control unit decodes the write command, write address, and write data from the SOC chip DDR controller, and writes the write command, write address, and write data into a write command queue, a write address queue, and a write data queue respectively. Among them, the write transmit unit obtains the write command from the write command queue, obtains the write address and write data from the write address queue and the write data queue respectively according to the write command, performs DFI-to-AXI protocol conversion on the write address and write data, and sends the protocol-converted write address and write data to the FPGA DDR controller. Among them, the write command queue, the write address queue, and the write data queue respectively implement cross-clock domain operations; Among them, the write operation control unit also performs the following controls: For the write transmit unit in the write idle state, when any one of the write command queue, the write address queue, and the write data queue is not empty, the write operation control unit controls the write transmit unit to enter the write enable state; For the write transmit unit in the write enable state, look for the corresponding write address and write data in the write address queue and the write data queue according to the write command in the write command queue. If found, control the write transmit unit to enter the write transmit state, so that the write transmit unit performs DFI-to-AXI protocol conversion on the write address and write data in the write transmit state and sends the protocol-converted write address and write data to the FPGA DDR controller. If not found, control the write transmit unit to enter the write wait state, and wait until the corresponding write address and write data are found in the write address queue and the write data queue, and then control the write transmit unit to enter the write transmit state; For the write transmit unit in the write transmit state, when the write command queue, the write address queue, and the write data queue are all empty, the write operation control unit controls the write transmit unit to enter the write idle state.

2. The system according to claim 1, wherein The sending transaction processing module decodes the write command, write address, and write data from the DDR controller of the SOC chip, performs protocol conversion from DFI to AXI on the write address and write data according to the write command, and sends the protocol-converted write address and write data to the FPGA DDR controller; Among them, the receiving transaction processing module decodes the read command and read address from the DDR controller of the SOC chip, performs protocol conversion from DFI to AXI on the read address according to the read command, and sends the protocol-converted read address to the FPGA DDR controller.

3. The system according to claim 2, wherein the sending transaction processing module also decodes the write response from the FPGA DDR controller, performs protocol conversion from AXI to DFI on the write response, and sends the protocol-converted write response to the DDR controller of the SOC chip; and the receiving transaction processing module also decodes the read data from the FPGA DDR controller, performs protocol conversion from AXI to DFI on the read data, and sends the protocol-converted read data to the DDR controller of the SOC chip.

4. The system according to claim 3, wherein the write sending unit also decodes the write response from the FPGA DDR controller, performs protocol conversion from AXI to DFI on the write response, and writes the protocol-converted write response into the write response queue; and the write operation control unit also obtains the write response from the write response queue and sends the write response to the DDR controller of the SOC chip; wherein the write response queue implements cross-clock domain operation.

5. The system according to claim 3, wherein The receiving transaction processing module includes a read operation control unit and a read receiving unit; wherein, the read operation control unit decodes the read command and read address from the DDR controller of the SOC chip, and writes the read command and read address into the read command queue and the read address queue respectively; wherein, the read receiving unit obtains the read command from the read command queue, obtains the read address from the read address queue according to the read command, performs protocol conversion from DFI to AXI on the read address, and sends the protocol-converted read address to the FPGA DDR controller; wherein the read command queue and the read address queue respectively implement cross-clock domain operation.

6. The system according to claim 5, wherein the read receiving unit also decodes the read data from the FPGA DDR controller, performs protocol conversion from AXI to DFI on the read data, and writes the protocol-converted read data into the read data queue; and the read operation control unit also obtains the read data from the read data queue and sends the read data to the DDR controller of the SOC chip; wherein the read data queue implements cross-clock domain operation.

7. The system according to claim 5, wherein The read operation control unit also performs the following control: For the read receiving unit in the read idle state, when the read command queue or the read address queue is not empty, the read operation control unit controls the read receiving unit to enter the read enable state; For the read receiving unit in the read enable state, search for the corresponding read address in the read address queue according to the read command in the read command queue. If found, control the read receiving unit to enter the read receiving state, so that the read receiving unit performs the protocol conversion from DFI to AXI on the read address in the read receiving state and sends the protocol-converted read address to the FPGA DDR controller. If not found, control the read receiving unit to enter the read waiting state, and wait until the corresponding read address is found in the read address queue, and then control the read receiving unit to enter the read receiving state; For the read receiving unit in the read receiving state, when both the read command queue and the read address queue are empty, the read operation control unit controls the read receiving unit to enter the read idle state.

8. The system according to any one of claims 3, 4, 5, and 6, characterized in that, The queue adopts an asynchronous cross-clock domain FIFO queue.

Images