Processor, data processing method for processor, and electronic device

Abstract

A processor, a data processing method for the processor, and an electronic device. The processor includes a first-level cache space, a first translation lookaside buffer, and at least one preset cache space. The first-level cache space and the at least one preset cache space are sequentially communicatively connected to form a communication link. The at least one preset cache space includes a target preset cache space. The first translation lookaside buffer and the target preset cache space are arranged at the same path level. The first translation lookaside buffer is communicatively connected to the target preset cache space. The first translation lookaside buffer is configured to cache first-level page table entries. The processor can improve the performance of a data prefetcher, enabling an accelerator to use virtual addresses, thereby greatly simplifying the programming mode of programs using heterogeneous architectures and improving the performance of a near memory page table walker.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a processor, a data processing method for the processor, and an electronic device. Background Art

[0002] In the field of computer technology, memory management is a key function of computer operating systems. In a multi-process operating system, each process has its own virtual address space and can use any virtual address within the system's specified range. The addresses used by the central processing unit (CPU) when executing applications are virtual addresses. When the operating system allocates memory to a process, it must map the virtual addresses used to physical addresses, which are the actual physical memory access addresses. This separation of addresses into virtual and physical addresses simplifies program compilation, allowing the compiler to compile programs based on a continuous and sufficient virtual address space. Virtual addresses for different processes are assigned to different physical addresses, enabling the system to run multiple processes simultaneously, thereby improving overall computer system efficiency. Furthermore, because applications can use but not modify address translations, one process cannot access the memory contents of another, thereby enhancing system security. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a processor, including a first-level cache space, a first translation lookaside buffer, and at least one preset cache space. The first-level cache space and the at least one preset cache space are communicatively connected in sequence to form a communication link. The at least one preset cache space includes a target preset cache space. The first translation lookaside buffer and the target preset cache space are set at the same path level. The first translation lookaside buffer is communicatively connected to the target preset cache space. The first translation lookaside buffer is configured to cache first-level page table entries. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0005] Figure 1 A schematic diagram of an address translation process;

[0006] Figure 2 A schematic diagram of the architecture of a multi-core processor;

[0007] Figure 3 A schematic diagram showing an example of the contents of a TLB entry;

[0008] Figure 4 A schematic diagram of the architecture of a processor provided for at least one embodiment of the present disclosure;

[0009] Figure 5 A schematic diagram of the architecture of another processor provided for at least one embodiment of the present disclosure;

[0010] Figure 6A A schematic diagram showing the contents of a data item in the first-level page table entry buffer;

[0011] Figure 6B A schematic diagram showing the composition structure of the physical address of the first-level page table entry is shown;

[0012] Figure 7 An exemplary schematic diagram illustrating an architecture of a cache in a processor provided by at least one embodiment of the present disclosure is shown;

[0013] Figure 8 A flowchart of a data processing method for a processor provided in some embodiments of the present disclosure;

[0014] Figure 9 A flowchart of another data processing method for a processor provided in some embodiments of the present disclosure;

[0015] Figure 10 A flowchart of another data processing method for a processor provided in some embodiments of the present disclosure;

[0016] Figure 11 A schematic flow chart of another data processing method for a processor provided by at least one embodiment of the present disclosure is shown;

[0017] Figure 12A A schematic diagram of a process of reading cache data is shown;

[0018] Figure 12B A schematic flow chart of data processing using a processor provided by an embodiment of the present disclosure;

[0019] Figure 13 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure; and

[0020] Figure 14 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0022] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0023] When a computer operating system processes a task, it needs to convert the virtual address used by the application into a physical address, so that memory access can be performed based on the physical address to obtain data. The process of converting virtual addresses into physical addresses is called address translation.

[0024] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components. When any component of an embodiment of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0025] Figure 1 This is a schematic diagram of an address translation process, showing the address translation process of the four-level page table. Figure 1As shown, a virtual address is divided into several segments, for example, represented as EXT, OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, OFFSET_lvl1, and OFFSET_pg. In this example, the high-order virtual address segment EXT is not used. The virtual address segments OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, and OFFSET_lvl1 represent the offset values ​​of the four-level page table, that is, the virtual address segment OFFSET_lvl4 represents the offset value of the fourth-level page table, the virtual address segment OFFSET_lvl3 represents the offset value of the third-level page table, the virtual address segment OFFSET_lvl2 represents the offset value of the second-level page table, and the virtual address segment OFFSET_lvl1 represents the offset value of the first-level page table.

[0026] The initial address of the highest-level page table (also known as the fourth-level page table) is stored in the architecture register REG_pt. Its content is set by the operating system and cannot be changed by the application. In the second-level page table, the third-level page table, and the fourth-level page table, the page table entry of each level of the page table stores the starting address of the next-level page table. The first-level page table entry (Page Table Entry, PTE) stores the high bits of the physical address of the corresponding memory page. It is combined with the virtual address offset (OFFSET_pg) of a virtual address to obtain the physical address corresponding to the virtual address. In this way, the starting address of the next-level page table is obtained step by step, and the first-level page table entry (PTE) can be obtained eventually, so as to further obtain the corresponding physical address, thus realizing the translation from virtual address to physical address.

[0027] It should be noted that although Figure 1 A 4-level page table is shown, but the embodiments of the present disclosure are not limited thereto, and any number of multi-level page tables may be used, such as a 2-level page table, a 3-level page table, a 5-level page table, etc. A single-level page table may also be used, which may be determined according to actual needs, and the embodiments of the present disclosure do not impose any restrictions on this. For example, a system may support memory pages of different sizes, and the size of each memory page is represented by the number of bits of the virtual address offset OFFSET_pg. For example, the size of each memory page may be 4K. In the same system, the larger the memory page, the fewer address translation levels are required. It should be noted that any system with any memory page size can be applied. If the system supports multiple memory page sizes, the number of page table levels corresponding to different memory page sizes will also be different, and the present disclosure does not impose any restrictions on this.

[0028] Figure 2 is a schematic diagram of the architecture of a multi-core processor. Figure 2As shown, the processor has four processor cores (CPU Core). At the same time, the processor also has multiple levels of cache, such as the first level cache (L1 Cache), the second level cache (L2 Cache) and the last level cache (Last Level Cache, LLC). In this example, the last level cache is actually the third level cache (L3 Cache). Of course, the embodiments of the present disclosure are not limited to this. The processor can have any number of multi-level caches, so the last level cache can also be a cache of any level, which can be determined according to actual needs.

[0029] For example, in this example, the last-level cache is shared by multiple processor cores, while the second-level cache is private to each processor core. That is, multiple processor cores share a single last-level cache, while each processor core is provided with a dedicated second-level cache. The last-level cache and the second-level cache are used to store instructions and data, and the last-level cache is connected to the memory. It should be noted that in other examples, the second-level cache may also be a shared cache, and the embodiments of the present disclosure are not limited to this.

[0030] For example, a dedicated first-level cache is provided for each processor core, and the first-level cache is located within the processor core. For example, the first-level cache may include a first-level instruction cache (L1I cache) and a first-level data cache (L1D cache), which are used to cache instructions and data, respectively. An electronic device (such as a computer) including this processor also includes memory, and the processor core implements instruction transfer and data access through a multi-level cache and memory data caching mechanism.

[0031] Each of the above-mentioned levels of cache can be selected to be set to one of a variety of architectures, such as fully associative, set associative, directly indexed, etc. During use, the replacement strategy adopted when using recently accessed data to fill multiple items in the cache can also include Least Recently Used (LRU), Least-Frequently Used (LFU), etc., and the embodiments of the present disclosure do not limit this.

[0032] For example, a translation lookaside buffer (TLB) is set up separately for each processor core. The translation lookaside buffer can include a translation lookaside buffer (ITLB) for instructions and a translation lookaside buffer (DTLB) for data. For example, both ITLB and DTLB are set up in the processor core. Address translation is a very time-consuming process. For multi-level page tables, it usually takes multiple memory accesses to obtain the corresponding physical address. Figure 1 Taking the four-level page table shown as an example, it is necessary to access the memory four times to obtain the corresponding physical address. Therefore, in order to save address translation time and improve computer system performance, a TLB (such as an ITLB and a DTLB) can be set in the processor core to store a portion of previously used first-level page table entries (PTEs). When address translation is required, the virtual page number of the virtual address to be translated is first used to query the TLB for the required first-level page table entry. If the query hits in the TLB, the required first-level page table entry can be immediately obtained, and the obtained first-level page table entry is used to offset the corresponding physical address by the address of the translated virtual address. On the other hand, if there is no query hit in the TLB, then it is necessary to use the virtual page number of the virtual address to be translated to perform the page table query as described above (such as a multi-level page table query) to obtain the required first-level page table entry, and the obtained first-level page table entry is used to offset the corresponding physical address by the address of the translated virtual address.

[0033] Similar to the CPU cache architecture, for example, TLB can also have multiple architectures, such as fully associative, set associative, directly indexed, etc. The TLB architecture can also be a multi-level structure, with the lowest level TLB having the smallest size and the fastest speed. When the lowest level TLB does not hit, the next level TLB is searched. The replacement strategy used when filling multiple entries in the TLB can also refer to the replacement strategy in the cache, such as Least Recently Used (LRU) and Least-Frequently Used (LFU). Figure 3 A schematic diagram showing an example of the contents of a TLB entry.

[0034] like Figure 3 As shown, each entry in the TLB (also referred to as a TLB entry or a TLB data entry) corresponds to, for example, a previously used first page table entry (PTE), and includes a valid bit, a virtual address bit, a physical address bit, and an attribute bit. When the valid bit is a valid value, it indicates that the data item is a valid item, and when the valid bit is an invalid value, it indicates that the data item is an invalid item. For example, in some examples, the valid bit is 1 bit, and when its value is 1, it is a valid value, and when its value is 0, it is an invalid value. The virtual address bit stores the virtual address (virtual page number) of the memory page or the hash value of the address, the physical address bit stores the physical address (physical page number) of the memory page, and the attribute bit stores the attributes and status of the memory page. The information of the physical address bit and attribute bit of the TLB entry comes from the corresponding PTE.

[0035] Although the TLB can reduce a lot of address translation latency, it is still unavoidable to access the page table for address translation when a TLB query misses (misses) during the execution of software programs. In order to reduce the time required for translation operations, a hardware page table walker (PTW) is usually set up separately for the processor core to perform the page table browsing process. The hardware page table walker is set up inside the processor core. By using the hardware page table walker, multiple levels of page tables can be traversed to obtain the final physical address of the memory page. For example, the page table walker can be set up inside the processor core or outside the processor core.

[0036] The L1I and L1D caches are accessed using physical addresses (physically indexed, virtually tagged). The second-level cache, last-level cache, and memory are also accessed using physical addresses. Therefore, before data is accessed, address translation must first be performed through the ITLB or DTLB. During the address translation process, when a page table walk is required, the hardware page table walker needs to access the addresses of each level of page table stored in memory to read the corresponding data. The address calculation is then performed on the retrieved data. The process of reading data related to each level of page table is basically the same as the process of reading normal data. In other words, a page table entry read request is basically the same as a data read request. A read request from the hardware page table walker can pass through the first-level cache, the second-level cache, and the last-level cache to reach memory. If the data requested by the hardware page table walker exists in a certain level of cache, the cache returns the data and does not forward the hardware page table walker's request to the next level of cache / memory. Conversely, when the data requested by the hardware page table walker is retrieved from memory, the data is temporarily retained (i.e., cached) in at least one level of memory.

[0037] The inventors of the present disclosure have noticed that Figure 2 The processor shown has the following technical bottlenecks:

[0038] First, data prefetchers are one of the main technologies used to reduce data access latency in processor cores. They can prefetch data based on different data access patterns. However, prefetchers trained to access any level of cache other than the first-level cache can only use physical addresses and cannot issue cross-page prefetch requests, which greatly affects prefetcher performance.

[0039] Second, to further improve the performance of SoCs, including processors, SoCs are increasingly adopting heterogeneous architectures, typically consisting of multiple processor cores and other accelerators. However, accelerators cannot use virtual addresses, which complicates programming using heterogeneous architectures.

[0040] Third, for architectures that place the page table walker inside the processor core, the page table walker accesses memory more frequently. Even for architectures that place the page table walker next to the LLC cache, the page table walker may still access memory more frequently, which still limits its performance.

[0041] At least one embodiment of the present disclosure provides a processor, a data processing method for the processor, and an electronic device. The processor can improve the performance of the data prefetcher, allowing the accelerator to use virtual addresses, which greatly simplifies the programming mode of programs using heterogeneous architectures. Furthermore, for architectures that place the page table walker next to the LLC cache, the processor provided by the embodiment of the present disclosure can further reduce the number of memory accesses by the page table walker, thereby improving the performance of the near memory page table walker.

[0042] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0043] At least one embodiment of the present disclosure provides a processor, including a first-level cache space, a first translation lookaside buffer, and at least one preset cache space. The first-level cache space and the at least one preset cache space are communicatively connected in sequence to form a communication link. The at least one preset cache space includes a target preset cache space. The first translation lookaside buffer and the target preset cache space are set at the same path level. The first translation lookaside buffer is communicatively connected to the target preset cache space. The first translation lookaside buffer is configured to cache first-level page table entries.

[0044] In the above embodiments of the present disclosure, the preset cache space is a cache space different from the first-level cache space (L1 Cache), for example, it can be a second-level cache space (L2 Cache) or a later-level cache space, such as the last-level cache (LLC Cache).

[0045] Figure 4 A schematic diagram of the architecture of a processor provided by at least one embodiment of the present disclosure. Figure 4 As shown, in some embodiments of the present disclosure, the processor includes at least one processor core and a first-level cache space, a first translation lookaside buffer, a second translation lookaside buffer, and at least one preset cache space for the processor core.

[0046] For example, the processor has, for example, four processor cores (CPU Cores). The processor also has multiple levels of cache, such as a first-level cache, a second-level cache, and a last-level cache. In this example, the second-level cache and the last-level cache are preset cache spaces.

[0047] In some examples, the first and second translation lookaside buffers may be examples of the aforementioned translation lookaside buffers (TLBs). Here, the first and second translation lookaside buffers may be examples of the aforementioned TLBs, meaning that they implement similar PTE storage functions and employ similar principles. However, the hardware structure, location, etc. of the first and second translation lookaside buffers may differ from those of the aforementioned TLBs, and the hardware structure, location, etc. of the second and third translation lookaside buffers may also differ from those of the aforementioned TLBs. The embodiments of the present disclosure are not limited thereto.

[0048] and Figure 2 Compared to the scenario shown, in an embodiment of the present disclosure, the first TLB is a newly added TLB, which is arranged at the same path level as any predetermined L1 cache space in all cache levels of the processor except the first-level cache space. Here, the second TLB is located within the processor core, and the first-level cache space is also located within the processor core. The second TLB and the first-level cache space are arranged at the same path level, and the first-level cache space is communicatively connected to the second TLB. It should be noted that the first TLB can have the same size, number of levels, architecture, and replacement strategy as the second TLB, or can have different sizes, numbers of levels, architectures, and replacement strategies.

[0049] For example, the first-level cache space is an L1 cache, located within the processing core. For example, the first-level cache space and the processor core are located at the same path level, the first-level cache space is communicatively connected to the processor core, and the processor core can directly retrieve data or instructions from the first-level cache space. Here, "located at the same path level" means that the physical locations within the chip are adjacent or close, and data can be directly exchanged and transmitted. Therefore, the first-level cache space and the processor core being located at the same path level can mean that the first cache space is located within the processor core, is relatively close to the processor core, and the processor core can directly exchange and transmit data with the first-level cache space. For example, "communication connection" means that data / instructions can be directly transmitted. For example, the second translation lookaside buffer and the first-level cache space are located at the same path level, and the second translation lookaside buffer is communicatively connected to the first-level cache space. The second translation lookaside buffer and the first-level cache space being located at the same path level can mean that the second translation lookaside buffer is located adjacent to the first-level cache space, is relatively close to the first-level cache space, and the first-level cache can directly exchange and transmit data with the second translation lookaside buffer. For another example, the second translation lookaside buffer may be disposed inside the processor core. The second translation lookaside buffer may be logically disposed at the same path level as the processor core, and the second translation lookaside buffer is communicatively connected to the processor core.

[0050] like Figure 4 As shown, in some examples, the first-level cache space includes an L1I cache and an L1D cache, where the L1I cache is used to store instructions and the L1D cache is used to store data. Of course, the embodiments of the present disclosure are not limited to this. In other examples, the L1I cache and the L1D cache may not be distinguished, and only one L1 cache may be provided for storing both data and instructions.

[0051] For example, in some examples, at least one preset cache space includes a second-level cache space to an N-level cache space, where N is an integer greater than 2. The N-level cache space is closest to the memory and farthest from the processor core. Figure 4 In the example shown, at least one preset cache space may include a second-level cache space (L2 cache) and a last-level cache space (LLC), that is, N=3 at this time. Of course, the embodiments of the present disclosure are not limited to this, and N can be any integer greater than 2, such as 4, 5, 6, etc. Correspondingly, the processor is a 4-level cache architecture, a 5-level cache architecture, a 6-level cache architecture, etc. For example, in other examples, at least one preset cache space includes a cache space, that is, only includes a second-level cache space. At this time, the processor is a 2-level cache architecture. It should be noted that in the processor provided in the embodiment of the present disclosure, in addition to the first-level cache space, other levels of cache can be used as examples of preset cache spaces in the present disclosure.

[0052] For example, the first-level cache space and at least one preset cache space are sequentially connected to form a communication link, thereby enabling data retrieval from one level to another. For example, when a processor core needs to retrieve data, it may first query the first-level cache space. If there is no hit, it may continue to query the second-level cache space. If there is still no hit, it may continue to query the last-level cache space. If there is still a miss in the last-level cache space, it may retrieve the data from the main memory.

[0053] For example, in the description of this disclosure, at least one preset cache space includes a target preset cache space as a description target, and the target preset cache space can be any one of a plurality of preset cache spaces. For example, any one of the second-level cache space to the N-level cache space can be used as the target preset cache space.

[0054] For example, the first translation lookaside buffer and the target preset cache space are set at the same path level, the first translation lookaside buffer is communicatively connected to the target preset cache space, and the first translation lookaside buffer is configured to cache first-level page table entries. For example, the first translation lookaside buffer is set outside the processor core.

[0055] For example, in Figure 4In the example, the second-level cache space serves as the target preset cache space, the first translation lookaside buffer and the second-level cache space are set at the same path level, and the first translation lookaside buffer is communicatively connected to the second-level cache space. Therefore, the first translation lookaside buffer and the second-level cache space being set at the same path level can mean that the first translation lookaside buffer is set next to the second-level cache space, is closer to the second-level cache space, and the second-level cache space can directly interact and transmit data with the first translation lookaside buffer. For example, the second-level cache space is a private type or a shared type cache space for the processor core, and the second-level cache space serves as the target preset cache space. That is, in some processor architectures, the second-level cache space is provided separately for each processor core and is of a private type, while in other processor architectures, the second-level cache space is shared by multiple processor cores and is of a shared type. Regardless of whether the second-level cache space is of a private type or a shared type, the second-level cache space can be used as the target preset cache space.

[0056] For example, in some embodiments of the present disclosure, the second-level cache space is a private type of cache space for the processor core, the number of the second-level cache spaces is multiple, the number of the processor cores is multiple, the multiple second-level cache spaces correspond one-to-one to the multiple processor cores, the multiple second-level cache spaces serve as target preset cache spaces and are provided with multiple first translation lookaside buffers, that is, the multiple second-level cache spaces correspond one-to-one to the multiple first translation lookaside buffers, and each second-level cache space corresponds to a first translation lookaside buffer.

[0057] Figure 5 A schematic diagram of the architecture of another processor provided for at least one embodiment of the present disclosure.

[0058] Figure 5 The architecture of the processor and Figure 4 The architecture of the processor in is basically the same, and the processor has, for example, 4 processor cores. The processor also has multiple levels of cache, such as a first-level cache, a second-level cache, and a last-level cache. In this example, the second-level cache and the last-level cache are preset cache spaces. The difference is that in Figure 5 In the example, the last-level cache space serves as the target preset cache space, the first translation lookaside buffer and the last-level cache space are configured at the same path level, and the first translation lookaside buffer and the last-level cache space are communicatively connected. Therefore, configuring the first translation lookaside buffer and the last-level cache space at the same path level may mean that the first translation lookaside buffer is configured adjacent to the last-level cache space, is relatively close to the last-level cache space, and the last-level cache space can directly exchange and transmit data with the first translation lookaside buffer.

[0059] For example, in some embodiments, the N-level cache space is a shared type of cache space for the processor core, that is, multiple processor cores share the same N-level cache space, and the N-level cache space is used as the target preset cache space. This example is Figure 5 The situation shown.

[0060] It should be noted that although Figure 4 It shows that the second-level cache space is used as the target preset cache space and the first translation lookaside buffer is set next to the second-level cache space. Figure 5 The last level cache space is shown as the target preset cache space and the first translation lookaside buffer is set next to the last level cache space, but this does not constitute a limitation of the embodiments of the present disclosure. In some examples, when the processor includes more levels of cache, any other level cache space other than the first level cache space can be used as the target preset cache space, thereby adjusting the setting position of the first translation lookaside buffer accordingly. It should be noted that the first translation lookaside buffer is not set in the processor core, or the first translation lookaside buffer is not set next to the first level cache space.

[0061] In an embodiment of the present disclosure, by setting the first translation lookaside buffer at the same path level as the target preset cache space (for example, setting it next to other cache spaces other than the first-level cache space, for example, setting it outside the processor core), the obstacle of the data prefetcher not being able to use virtual addresses can be overcome, and the obstacle of the data prefetcher not being able to send cross-page prefetch requests can be overcome, which can improve the performance of the data prefetcher. Moreover, since the first translation lookaside buffer is set, virtual addresses can be used for any component set outside the processor core, which greatly improves convenience. For example, an accelerator set next to any level cache space other than the first-level cache space can also use virtual addresses, which greatly simplifies the program programming mode using heterogeneous architectures. Moreover, for an architecture that places a page table walker outside the processor core (for example, an architecture that places a page table walker next to an LLC), the processor provided by the embodiment of the present disclosure can further reduce the number of times the page table walker accesses memory, thereby improving the performance of the page table walker.

[0062] For example, the first-level cache space and at least one preset cache space are sequentially connected to form a communication link. For example, when a processor core needs to retrieve data, it may first query the first-level cache space. If there is no hit, it will send a data read request to the lower-level cache space until the memory obtains the required data.

[0063] For example, the first translation lookaside buffer stores at least part of the page table entry data from the first-level page table to the M-th-level page table, where M is an integer greater than 1. That is, the first translation lookaside buffer can store any recently used page table entry data.

[0064] For example, in some embodiments of the present disclosure, the processor core is configured to generate a first-level page table entry read request in response to the need to perform a page table browse in response to the absence of first-level page table entry data required for address translation in the first translation lookaside buffer or the second translation lookaside buffer.

[0065] For example, when the processor core needs to perform address translation, it first queries the first translation lookaside buffer or the second translation lookaside buffer to see if there is a required PTE. If there is no hit, a page table browse is required, and the page table walker generates a first-level page table entry read request, and sends the first-level page table entry read request to each level of cache in turn until the memory reads the data. Therefore, the first-level page table entry read request is passed down in the multi-level cache structure. When the target preset cache space as the description object receives the first-level page table entry read request, it queries the static random access memory (as described in detail later) in the target preset cache space to see if there is a required PTE. If there is a hit, the PTE obtained by the query is returned. If there is no hit, the page table walker continues to query the lower-level cache space or memory of the target preset cache space in order to try to obtain the PTE.

[0066] For example, the first-level page table entry read request includes the virtual address of the corresponding memory page. In some examples, the first-level page table entry read request also includes a translation bit. The virtual address of the corresponding memory page is the virtual page number in the virtual address that needs to be translated.

[0067] For example, the memory page size is X=2 Y Bytes (e.g. 4096 = 2 12 ), and the memory page is always X-byte aligned, so the low Y bits of the physical address and virtual address of the memory page are always 0, so the virtual address of the memory page can not save the low Y bits of the address to save hardware resources.

[0068] Many high-performance CPUs support virtual machine mode, where a single physical machine (stand-alone or server) runs multiple virtual machines, each with its own operating system. In the example where a first-level page table entry read request also includes a translation bit, one or more virtual machines are running in the computer system. Each virtual machine uses a virtual address. When translating a virtual address in the virtual machine's system, the virtual address must first be translated into a guest physical address. This guest physical address is still a virtual address in the computer system, not a real physical address. The guest physical address is then translated into a system physical address, which is a real physical address. In other words, in virtual machine mode, each address translation requires a guest virtual address to a guest physical address and then a guest physical address to a system physical address. In a four-level page table architecture, a guest virtual address to system physical address translation may require up to 24 memory accesses. To minimize the number of address translations in virtual machine mode, a translation bit is added to distinguish between system physical address PTEs and guest physical address PTEs. When the translation bit is a valid value (for example, "1"), it indicates that a translation from a guest physical address (also called an intermediate physical address (IPA)) to a system physical address is provided. When the translation bit is an invalid value (for example, "0"), it indicates that a translation from a guest virtual address directly to a system physical address is provided, or that the current system is not in virtual machine mode.

[0069] For example, the first-level page table entry read request also includes the physical address of the corresponding first-level page table entry and the physical address of the first-level page table entry itself in the memory. The size of the first-level page table entry is N=2 M Bytes, the lower M bits of the physical address of the first-level page table entry are always 0, so the physical address of the first-level page table entry can not save the lower M bits of the physical address to save hardware resources.

[0070] Typically, data read and write requests include data read requests (data will not be overwritten), data write requests (data will be overwritten), and instruction read requests (data is an executable instruction), that is, it can be one of the three. The first-level page table entry read request contains the information described above, and its type is different from the usual data read request. For example, when performing a query in the cache, the first-level page table entry read request and the usual data read request are stored in different miss status holding registers (Miss Status Handling Registers, MSHR). In an embodiment of the present disclosure, when the second-level cache space to the N-th level cache space receives a data read request, it is necessary to determine whether the request is a first-level page table entry read request.

[0071] A typical cache space, such as a second-level cache, includes control logic, memory (such as static random access memory (SRAM)), and a fill buffer. The control logic is the control module of the cache space and is used to control the operation of the cache space. The memory is used to store cached data (including operation data or instruction data). The fill buffer is used to temporarily store a data read request when the cache space is queried by a data read request and misses, thereby monitoring the execution status of the data read request. When the target data of the data read request is read from the lower-level cache or memory into the cache space, the data read request is deleted from the fill buffer. For example, the read target data is also written to the memory of the cache space for subsequent use.

[0072] In an embodiment of the present disclosure, a first-level page table entry buffer is added to the preset cache space. The first-level page table entry buffer is configured to store information carried by a first-level page table entry read request. For example, the preset cache space includes control logic, a memory (e.g., a static random access memory), a first-level page table entry buffer, and a fill buffer. The first-level page table entry buffer is used to cache the first-level page table entry read request in the event of a query miss, while the fill buffer caches normal data read requests in the event of a query miss as described above.

[0073] Figure 6A A schematic diagram showing the contents of a data item in the first-level page table entry buffer.

[0074] like Figure 6A As shown, for example, each data item in the first-level page table entry buffer is used to store information of the cached requested first-level page table entry, and the content of this information includes the valid bit, translation bit, virtual address and physical address of the memory page corresponding to the requested first-level page table entry. When the valid bit is a valid value (for example, "1"), it indicates that the data item is a valid item; when the valid bit is an invalid value (for example, "0"), it indicates that the data item is an invalid item. When the translation bit is a valid value (for example, "1"), it indicates that the data item is used to provide translation from guest physical address to system physical address; when the translation bit is an invalid value (for example, "0"), it indicates that the data item is used to provide translation from guest virtual address to system physical address, or indicates that it is not in virtual machine mode.

[0075] The size of data stored in the cache and transferred between caches is fixed, for example, 64 bytes. Such a piece of data is called a cache line. However, the data of a first-level page table entry is often much smaller, for example, 8 bytes, and only occupies a part of the cache line. Therefore, the physical address of the cached first-level page table entry needs to have enough bits to obtain the correct first-level page table entry data from the cache line read. For example, in one example, Figure 6B As shown, the physical address of the corresponding first-level page table entry includes a cache row address and a cache row offset value. The cache row address is used to compare with the address of the returned data corresponding to the first-level page table entry read request to determine whether the data includes the first-level page table entry data. The cache row offset value represents the offset value of the corresponding first-level page table entry data in the cache row.

[0076] The size of the first-level page table entry buffer can be determined based on actual needs. If the first-level page table entry buffer is not large enough, a new first-level page table entry read request may arrive while the first-level page table entry buffer is full. To avoid this, the cache needs to notify the processor core or upper-level cache through a mechanism such as a token to suspend sending new first-level page table entry read requests. Token technology is a well-known method and can be referenced by conventional designs, so it will not be detailed here.

[0077] Figure 7 An exemplary schematic diagram of a cache architecture in a processor provided by at least one embodiment of the present disclosure is shown. The processor is, for example, Figure 4 or Figure 5 Processor shown.

[0078] like Figure 7 As shown, the processor includes an upper-level cache space 701, a target preset cache space 702, and a lower-level cache space / memory 703 that are sequentially connected to form a communication link. Similarly, the target preset cache space 702 is the preset cache space to be described currently. For example, the upper-level cache space 701 refers to the cache space above the target preset cache space 702. For example, when the target preset cache space is a second-level cache space, the upper-level cache space is a first-level cache space. When the target preset cache space is a third-level cache space (or LLC cache), the upper-level cache space is a second-level cache space. The lower-level cache space 703 refers to the cache space below the target preset cache space 702. When the target preset cache space is a second-level cache space, the lower-level cache space is a third-level cache space (or the aforementioned LLC). The first translation backup buffer 704 and the target preset cache space 702 are set at the same path level.

[0079] The target preset cache space 702 includes a control logic 705, a static random access memory 706, a first-level page table entry buffer 707, and a fill buffer 708. The static random access memory 706 is an example of a storage medium for storing cached data and tags. The control logic 705 is used to control the operation of the target preset cache space 702, which includes comparing the data read request with the tags of each cache line currently cached when receiving a data read request to determine whether the requested data is in the cache. If the requested data is in the cache, the corresponding data is returned. If the data requested by the query does not hit the cache (i.e., it is not in the cache), the data read request is filled into the fill buffer 708. For example, the fill buffer 708 passes the data read request to the lower-level cache space / memory 703 and waits for the return of the requested data. Similarly, when the control logic 705 receives a first-level page table item read request, if the requested first-level page table item data is in the cache, the corresponding data is returned; if the requested first-level page table item data does not hit the cache, the first-level page table item read request is filled into the first-level page table item buffer 707, and the information carried by the first-level page table item read request is saved. The first-level page table item buffer 707 passes the first-level page table item read request to the lower-level cache space / memory 703 and waits for the return of the requested first-level page table item data.

[0080] It should be noted that in the embodiments of the present disclosure, the processor can be a single-core architecture or a multi-core architecture, and the embodiments of the present disclosure do not limit this. The number or level of cache and the setting method are also not limited, which can be determined according to actual needs. The processor is not limited to Figure 4 and Figure 5 The structure shown may include more or fewer components, and the connection method between the components is not limited.

[0081] At least one embodiment of the present disclosure further provides a data processing method for a processor. The data processing method includes caching first-level page table entries for address translation in a first translation lookaside buffer. In at least one embodiment, the method can improve the performance of a data prefetcher, enable an accelerator to use virtual addresses, thereby greatly simplifying the programming model of programs using heterogeneous architectures, and improve the performance of a near memory page table walker.

[0082] As described above, in at least one embodiment of the present disclosure, the processor includes a first-level cache space, a first translation lookaside buffer, and at least one preset cache space, the first-level cache space and the at least one preset cache space are sequentially communicatively connected to form a communication link, the at least one preset cache space includes a target preset cache space, the first translation lookaside buffer and the target preset cache space are set at the same path level, and the first translation lookaside buffer is communicatively connected to the target preset cache space. For example, the processor may be Figure 4 or Figure 5 The processor shown. For details about the processor, please refer to the above content and will not be repeated here.

[0083] like Figure 8 As shown, in some embodiments, the method includes steps S11 to S13. Figure 8 The method shown is used, for example, on the target preset cache space side.

[0084] Step S11 : In response to receiving a read request generated by a processor core, determining whether the read request is a first-level page table entry read request.

[0085] As can be seen from the above, when the target preset cache space receives a data read request, it needs to determine whether the request is a first-level page table entry read request or a data read request involving normal data being processed. Therefore, in order to support the first translation lookaside buffer, the target preset cache space needs to be able to identify PTE read operations. For example, as described above, the target preset cache space includes a first-level page table entry buffer for temporarily storing a first-level page table entry read request when a query cache miss occurs. When the requested corresponding PTE is obtained from the current level, lower level cache space, or memory, the corresponding PTE can be identified using the temporarily stored first-level page table entry read request.

[0086] Step S12: In response to the read request being a first-level page table entry read request, the first-level page table entry corresponding to the first-level page table entry read request is returned, and the corresponding first-level page table entry and the virtual address and translation bit of the memory page in the first-level page table entry read request are written into the first translation backup buffer.

[0087] As described above, when the requested corresponding PTE is obtained from the lower-level cache space or memory and the PTE is identified, the PTE may be saved in the first translation lookaside buffer.

[0088] like Figure 9 As shown, in some embodiments, step S12 may include steps S210 - S220 .

[0089] Step S210: In response to the first-level page table entry read request hitting the first translation lookaside buffer, the corresponding first-level page table entry obtained from the target preset cache space is returned, and the corresponding first-level page table entry and the virtual address and translation bit of the memory page in the first-level page table entry read request are written into the first translation lookaside buffer.

[0090] For example, when a first-level page table entry read request hits the target preset cache space, the target preset cache space has the required first-level page table entry cached therein, and the corresponding first-level page table entry can be obtained immediately.

[0091] For example, when the first-level page table entry corresponding to the first-level page table entry read request hits in the target preset cache space, the first-level page table entry is a used first-level page table entry, and the first translation backup buffer can store the used first-level page table entry for use by devices such as a data prefetcher.

[0092] Step S220: In response to a first-level page table entry read request not hitting the target preset cache space, return the corresponding first-level page table entry obtained from the lower-level cache or memory of the target preset cache space, and write the corresponding first-level page table entry and the virtual address and translation bit of the memory page in the first-level page table entry read request into the first translation backup buffer.

[0093] For example, if a first-level page table entry read request does not hit the target preset cache space, the target preset cache space is then further searched for the required first-level page table entry in a lower-level cache or memory, for example, by using a level-by-level query to obtain the required first-level page table entry. To maintain consistency in the first translation lookaside buffer, the corresponding first-level page table entry and the virtual address and translation bits of the memory page in the first-level page table entry read request need to be written to the first translation lookaside buffer.

[0094] Return to Figure 8 In some examples, the method may further include step S13.

[0095] Step S13: In response to the read request not being a first-level page table entry read request, returning data corresponding to the read request obtained from the target preset cache space, a lower-level cache of the target preset cache space, or a memory.

[0096] For example, when the read request is a common data read request type, corresponding data is obtained from the target preset cache space, a lower-level cache of the target preset cache space, or a memory.

[0097] like Figure 10 As shown, in other embodiments, for Figure 9 The illustrated step S220 may include steps S110 - S120 . Figure 10The method shown is also used on the target preset cache space side, for example.

[0098] Step S110: In response to the first-level page table entry corresponding to the first-level page table entry read request not being in the target preset cache space, the first-level page table entry read request is inserted into the first-level page table entry buffer, the first-level page table entry corresponding to the first-level page table entry read request is returned from the lower-level cache or memory of the target preset cache space, and the physical address of the returned corresponding first-level page table entry is compared with the physical address in the valid entry of the first-level page table entry buffer.

[0099] For example, Figure 7 The static random access memory 706 shown is used to store cached data and tags. The control logic 705 is used to compare the tag information included in a request with the tag information of the cache line in the cache to determine whether the requested data is in the cache. When the tag information included in the first-level page table entry read request is not equal to the tag information of the cache line in the target preset cache space, the first page table entry data corresponding to the first-level page table entry read request is not in the target preset cache space, and the first-level page table entry read request is inserted into the first-level page table entry buffer.

[0100] For example, if the first page table item data corresponding to the first-level page table item read request does not hit in the target preset cache space, the requested first page table item data is returned from the lower-level cache or memory, and the physical address of the returned first page table item data is compared with the physical address of the valid item in the first-level page table item buffer to determine whether the first-level page table item read request corresponding to the returned first page table item data is a first-level page table item read request that did not hit before.

[0101] Step S120: In response to the physical address of the corresponding first-level page table entry being the same as the physical address in at least one valid entry in the first-level page table entry buffer, the corresponding first-level page table entry and the virtual address and translation bit of the memory page in the first-level page table entry read request are written into the first translation backup buffer, and the valid entry corresponding to the first-level page table entry read request in the first-level page table entry buffer is deleted.

[0102] For example, if the physical address of the returned data is the same as the physical address of a valid entry in the first-level page table entry buffer, it means that the first-level page table entry read request corresponding to the returned first-level page table entry data is a first-level page table entry read request that was previously missed. Therefore, the requested first-level page table entry, the virtual address of the memory page, and the translation bit are extracted from the returned first-level page table entry data and filled into the first translation lookaside buffer for subsequent address translation. In addition, in order to maintain the consistency of the TLB data items in each translation lookaside buffer, other translation lookaside buffers (such as the second translation lookaside buffer) except the first translation lookaside buffer may also be synchronously updated.

[0103] For another example, in some examples, the method may further include: in response to one or more contents in the second translation lookaside buffer being cleared, clearing the corresponding one or more contents in the first translation lookaside buffer to maintain consistency between the first translation lookaside buffer and the second translation lookaside buffer.

[0104] For example, in some cases (e.g., a process switch or a translation lookaside buffer entry is modified by the operating system), one or more items in the second translation lookaside buffer need to be cleared. In this case, to ensure cache coherence of the translation lookaside buffer, the corresponding one or more items in the first translation lookaside buffer also need to be cleared.

[0105] For example, Figure 8 and Figure 9 as well as Figure 10 The methods shown cooperate with each other, and the execution order of each step can be adjusted and changed, which is not limited by the embodiments of the present disclosure.

[0106] It should be noted that in the embodiments of the present disclosure, the data processing method is not limited to the steps described above, and may also include more or fewer steps. The execution order of each step is not limited, which can be determined according to actual needs.

[0107] Figure 11 A schematic flow chart of another data processing method for a processor provided by at least one embodiment of the present disclosure is shown. Similarly, the processor includes a first-level cache space, a first translation lookaside buffer, and at least one preset cache space. The first-level cache space and the at least one preset cache space are sequentially connected to form a communication link. The at least one preset cache space includes a target preset cache space. The first translation lookaside buffer and the target preset cache space are set at the same path level. The first translation lookaside buffer is connected to the target preset cache space. The data processing method of this embodiment involves the process of using the first translation lookaside buffer to perform address translation.

[0108] like Figure 11 As shown, the data processing method includes the following steps S111 to S112.

[0109] Step S111: according to the address translation request, query whether a first-level page table entry corresponding to the address translation request is cached in the first translation lookaside buffer.

[0110] Step S112: in response to a query in the first translation lookaside buffer finding a first-level page table entry corresponding to the address translation request, performing address translation using the corresponding first-level page table entry.

[0111] For example, in order to save address translation time and improve computer system performance, the first-level page table entries (PTEs) used before can be stored in a first translation lookaside buffer that is not at the same path level as the first-level cache. When address translation is required, the first translation lookaside buffer is queried based on the address translation request to see if there is the required PTE. If a hit is found, the corresponding PTE can be immediately obtained for calculating the physical address. Unlike the second translation lookaside buffer at the same path level as the first-level cache, when the first translation lookaside buffer is set outside the processor core, it can also be used for scenarios such as off-core prefetching. For example, a data prefetcher generates an address translation request, queries the first-level page table entries it needs in the first translation lookaside buffer outside the processor core, and performs data prefetching based on the query result. In this way, the data prefetching operation does not need to be performed in the processor core, thereby improving the performance of the processor.

[0112] For example, in some examples, such as Figure 11 As shown, the method may further include step S113.

[0113] Step S113: Based on the target address obtained by performing address translation using the corresponding first-level page table entry, data corresponding to the target address is read into at least a target preset cache space.

[0114] For example, the data corresponding to the target address may be used later, so the data is read into the target preset cache in advance to reduce the processing time when it is read when it is used later, avoiding the need to further read from the memory.

[0115] Figure 12A A schematic diagram of a process of reading cache data is shown.

[0116] Figure 12A The cache data reading process shown corresponds to Figure 2 The processor shown does not support TLBs other than the intra-core TLB, that is, it does not support the first translation lookaside buffer in the processor provided by the embodiment of the present disclosure that is not at the same path level as the first-level cache.

[0117] like Figure 12AAs shown, first, a current cache space (such as the second-level cache or the last-level cache) receives a data read request generated by the processor core. Then, the preset cache space is queried to see if the requested data exists. If the requested data exists in the cache space, the requested data is obtained from the storage unit (such as static random access memory) in the cache space. If the requested data does not exist in the cache space, the read request is written to the fill buffer, and the query and read operation continues from the lower-level cache space / memory to obtain the requested data. The requested data is returned to the current cache space, the data / tag cached in the cache space is updated, and the previously cached data read request is deleted from the fill buffer (thus no longer monitoring the data read request).

[0118] Figure 12B A schematic flowchart of data processing using a processor provided by at least one embodiment of the present disclosure.

[0119] The following combination Figure 7 The processor architecture shown provides a detailed description of the data processing method provided by the embodiment of the present disclosure.

[0120] like Figure 12B As shown, first, the target preset cache space 702 receives a data read request generated by the processor core, and then determines whether the data read request hits the target preset cache space 702 .

[0121] In response to the data read request hitting the target preset cache space 702, the corresponding data is obtained from the static random access memory 706 of the target preset cache space. Then, it is determined whether the data read request is a PTE read request. If it is a PTE read request, the data obtained according to the PTE read request (i.e., the PTE), the virtual address of the memory page, and the translation bits are written to the first translation lookaside buffer 704 for use in subsequent address translation, and the requested data is returned to the upper-level cache space 701. If it is not a PTE read request, the requested data is directly returned to the upper-level cache space 701.

[0122] In response to the data read request not hitting the target preset cache space 702, the data read request is written into the fill buffer 708 of the target preset cache space, and then a determination is made as to whether the data read request is a PTE read request. In response to the data read request being a PTE read request, the PTE read request is written into the PTE buffer 707, and then the requested data is obtained from the lower-level cache space / memory 703. Alternatively, in response to the data read request not being a PTE request, the requested data is directly obtained from the lower-level cache space / memory 703. Then, in both of the above cases, the requested data obtained from the lower-level cache space / memory 703 is used to update the data / tag of the static random access memory 706 for subsequent use.

[0123] Next, the obtained physical address of the requested data is compared with the physical address of the valid item in the PTE buffer 707. If they are equal, it means that the requested data is PTE data, then the requested PTE, the virtual address of the memory page and the translation bit are extracted from the requested data, the matching data item is deleted from the PTE buffer 707, the obtained requested PTE, the virtual address of the memory page and the translation bit are written to the first translation lookaside buffer (704) for subsequent use, and the requested data (i.e., PTE) is returned to the upper-level cache space 701. If the address of the requested data is not equal to the physical address of the valid item in the PTE buffer (707), it means that the requested data is not PTE data, then it is processed as ordinary data, that is, the requested data is directly returned to the upper-level cache space 701.

[0124] It should be noted that the data processing methods provided in various embodiments of the present disclosure can be used in the processor provided in any embodiment of the present disclosure, and the processor can implement one or more steps of the data processing methods provided in the embodiments of the present disclosure.

[0125] At least one embodiment of the present disclosure further provides an electronic device, which includes the processor provided by at least one embodiment of the present disclosure.

[0126] Figure 13 1 is a schematic block diagram of an electronic device 1300 provided in some embodiments of the present disclosure. Figure 13 As shown, the electronic device 1300 includes a processor 1310. The processor 1310 is, for example, the processor provided by any embodiment of the present disclosure, and the processor can execute one or more steps in the data processing method described above.

[0127] For example, the processor 1310 may be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86, ARM, or RISC-V architecture. The processor 1310 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 1300 to perform desired functions.

[0128] Figure 14 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 1400 is suitable for implementing the data processing method provided in the embodiments of the present disclosure. The electronic device 1400 can be a terminal device or a computer system. It should be noted that Figure 14 The electronic device 1400 shown is merely an example and does not limit the functions and scope of use of the embodiments of the present disclosure.

[0129] like Figure 14 As shown, the electronic device 1400 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1410, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1420 or a program loaded from a storage device 1480 into a random access memory (RAM) 1430. The processing device 1410 is, for example, a processor provided in any embodiment of the present disclosure. Various programs and data required for the operation of the electronic device 1400 are also stored in the RAM 1430. The processing device 1410, the ROM 1420, and the RAM 1430 are connected to each other via a bus 1440. An input / output (I / O) interface 1450 is also connected to the bus 1440.

[0130] Typically, the following devices may be connected to the I / O interface 1450: an input device 1460 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1470 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1480 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1490. The communication device 1490 may allow the electronic device 1400 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 14 The electronic device 1400 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 1400 may alternatively implement or possess more or fewer devices.

[0131] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 1300 / 1400 can be referred to the above description of the processor and the data processing method, which will not be repeated here.

[0132] There are a few points to note:

[0133] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0134] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0135] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A processor comprising a processor core, a first-level cache space, a first translation lookaside buffer, and at least one preset cache space, in, The first-level cache space and the at least one preset cache space are sequentially connected to form a communication link. The at least one preset cache space includes a target preset cache space, the first translation lookaside buffer and the target preset cache space are set at the same path level, and the first translation lookaside buffer is communicatively connected to the target preset cache space, The first translation lookaside buffer is configured to cache first-level page table entries, and the first translation lookaside buffer is disposed outside the processor core; The first-level cache space is located in the processor core, and the target preset cache space is configured as follows: In response to receiving a read request generated by the processor core, determining whether the read request is a first-level page table entry read request; In response to the read request being the first-level page table entry read request, returning the obtained first-level page table entry corresponding to the first-level page table entry read request, and writing the corresponding first-level page table entry and the virtual address and translation bits of the memory page in the first-level page table entry read request into the first translation lookaside buffer; or In response to the read request not being the first-level page table entry read request, data corresponding to the read request obtained from the target preset cache space, a lower-level cache of the target preset cache space, or a memory is returned.

2. The processor according to claim 1, wherein: Returning the obtained first-level page table entry corresponding to the first-level page table entry read request, and writing the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request into the first translation lookaside buffer, comprising: In response to the first-level page table entry read request hitting the target preset cache space, returning the corresponding first-level page table entry obtained from the target preset cache space, and writing the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request into the first translation lookaside buffer; In response to the first-level page table entry read request not hitting in the target preset cache space, the corresponding first-level page table entry obtained from the lower-level cache or memory of the target preset cache space is returned, and the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request are written into the first translation backup buffer.

3. The processor according to claim 2, wherein: The target preset cache space includes a first-level page table entry buffer, and the first-level page table entry buffer is configured to store information carried by the first-level page table entry read request, The content of each data item in the first-level page table entry buffer includes a valid bit, a translation bit, a virtual address and a physical address of a memory page corresponding to the requested first-level page table entry, When the valid bit is a valid value, it indicates that the data item is a valid item; when the valid bit is an invalid value, it indicates that the data item is an invalid item. When the translation bit is a valid value, it indicates that the data item is used to provide translation from a guest physical address to a system physical address. When the translation bit is an invalid value, it indicates that the data item is used to provide translation from a guest virtual address to the system physical address.

4. The processor according to claim 3, wherein: In response to a first-level page table entry read request not hitting the target preset cache space, returning the corresponding first-level page table entry obtained from a lower-level cache or memory of the target preset cache space, and writing the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request into the first translation lookaside buffer, comprising: In response to the first-level page table entry corresponding to the first-level page table entry read request not being in the target preset cache space, inserting the first-level page table entry read request into the first-level page table entry buffer, returning the first-level page table entry corresponding to the first-level page table entry read request from a lower-level cache or memory of the target preset cache space, and comparing the physical address of the returned corresponding first-level page table entry with the physical address in the valid entry of the first-level page table entry buffer; In response to the physical address of the corresponding first-level page table entry being the same as the physical address in at least one valid entry in the first-level page table entry buffer, the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request are written into the first translation lookaside buffer, and the valid entry corresponding to the first-level page table entry read request in the first-level page table entry buffer is deleted.

5. The processor according to claim 3, wherein: The first-level page table entry read request includes the virtual address of the corresponding memory page, The virtual address of the corresponding memory page is the virtual page number in the virtual address that needs to be translated. The processor according to claim 5 , wherein: The first-level page table entry read request also includes the physical address of the corresponding first-level page table entry, The physical address of the corresponding first-level page table entry includes a cache row address and a cache row offset value. The cache row address is used to compare with the address of the returned data corresponding to the first-level page table entry read request to determine whether the data includes first-level page table entry data. The cache row offset value represents the offset value of the corresponding first-level page table entry data in the corresponding cache row.

7. The processor according to claim 1, wherein: The at least one preset cache space includes a second-level cache space to an N-th-level cache space, where N is an integer greater than 2. The N-level cache space is closest to the memory and farthest from the processor core, and any one-level cache space from the second-level cache space to the N-level cache space serves as the target preset cache space.

8. The processor according to claim 7, wherein: The second-level cache space is a private or shared cache space for the processor core, and the second-level cache space serves as the target preset cache space.

9. The processor according to claim 7, wherein: The N-th level cache space is a shared type cache space for the processor core, and the N-th level cache space serves as the target preset cache space.

10. The processor according to claim 7, wherein: The first-level cache space to the N-th-level cache space store at least part of the page table entry data of the first-level page table to the page table entry data of the M-th-level page table, where M is an integer greater than 1.

11. The processor of claim 1 , further comprising a second translation lookaside buffer, wherein The second translation lookaside buffer is located in the processor core, The second translation lookaside buffer and the first level cache space are arranged at the same path level, and the first level cache space is communicatively connected with the second translation lookaside buffer. The processor core is configured to generate a first-level page table entry read request in response to the absence of first-level page table entry data required for address translation in the first translation lookaside buffer or the second translation lookaside buffer.

12. The processor according to claim 11, wherein: The first translation lookaside buffer is further configured to clear the corresponding one or more contents in the first translation lookaside buffer in response to one or more contents in the second translation lookaside buffer being cleared, so as to maintain consistency between the first translation lookaside buffer and the second translation lookaside buffer.

13. A data processing method for a processor, wherein: The processor includes a processor core, a first-level cache space, a first translation lookaside buffer, and at least one preset cache space, the first-level cache space and the at least one preset cache space being communicatively connected in sequence to form a communication link, the at least one preset cache space including a target preset cache space, the first translation lookaside buffer and the target preset cache space being arranged at the same path level, the first translation lookaside buffer being communicatively connected to the target preset cache space, and the first translation lookaside buffer being arranged outside the processor core, The data processing method includes: caching first-level page table entries for address translation in the first translation lookaside buffer; the data processing method further comprises: In response to receiving a read request generated by the processor core, determining whether the read request is a first-level page table entry read request; In response to the read request being a first-level page table entry read request, returning the obtained first-level page table entry corresponding to the first-level page table entry read request, and writing the corresponding first-level page table entry and the virtual address and translation bits of the memory page in the first-level page table entry read request into the first translation lookaside buffer; In response to the read request not being the first-level page table entry read request, data corresponding to the read request obtained from the target preset cache space, a lower-level cache of the target preset cache space, or a memory is returned.

14. The data processing method according to claim 13, wherein: Returning the obtained first-level page table entry corresponding to the first-level page table entry read request, and writing the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request into the first translation lookaside buffer, comprising: In response to the first-level page table entry read request hitting the target preset cache space, returning the corresponding first-level page table entry obtained from the target preset cache space, and writing the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request into the first translation lookaside buffer; In response to the first-level page table entry read request not hitting in the target preset cache space, the corresponding first-level page table entry obtained from the lower-level cache or memory of the target preset cache space is returned, and the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request are written into the first translation backup buffer.

15. The data processing method according to claim 14, wherein: The target preset cache space includes a first-level page table entry buffer, and the first-level page table entry buffer is configured to store information carried by the first-level page table entry read request, The content of each data item in the first-level page table entry buffer includes a valid bit, a translation bit, a virtual address and a physical address of a memory page corresponding to the requested first-level page table entry, When the valid bit is a valid value, it indicates that the data item is a valid item; when the valid bit is an invalid value, it indicates that the data item is an invalid item. When the translation bit is a valid value, it indicates that the data item is used to provide a translation from a guest physical address to a system physical address; when the translation bit is an invalid value, it indicates that the data item is used to provide a translation from a guest virtual address to the system physical address. In response to a first-level page table entry read request not hitting the target preset cache space, returning the corresponding first-level page table entry obtained from a lower-level cache or memory of the target preset cache space, and writing the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request into the first translation lookaside buffer, comprising: In response to the first-level page table entry corresponding to the first-level page table entry read request not being in the target preset cache space, inserting the first-level page table entry read request into the first-level page table entry buffer, returning the first-level page table entry corresponding to the first-level page table entry read request from a lower-level cache or memory of the target preset cache space, and comparing the physical address of the returned corresponding first-level page table entry with the physical address in the valid entry of the first-level page table entry buffer; In response to the physical address of the corresponding first-level page table entry being the same as the physical address in at least one valid entry in the first-level page table entry buffer, the corresponding first-level page table entry and the virtual address of the memory page and the translation bit in the first-level page table entry read request are written into the first translation lookaside buffer, and the valid entry corresponding to the first-level page table entry read request in the first-level page table entry buffer is deleted.

16. The data processing method according to claim 13, wherein: The processor further includes a second translation lookaside buffer, the second translation lookaside buffer being located within the processor core, the second translation lookaside buffer being arranged at the same path level as the first level cache space, and the first level cache space being communicatively connected to the second translation lookaside buffer, The data processing method further includes: In response to the absence of first-level page table entry data required for address translation in the first translation lookaside buffer or the second translation lookaside buffer, a first-level page table entry read request is generated.

17. The data processing method according to claim 16, further comprising: In response to one or more contents in the second translation lookaside buffer being cleared, corresponding one or more contents in the first translation lookaside buffer are cleared to maintain consistency between the first translation lookaside buffer and the second translation lookaside buffer.

18. A data processing method for a processor, wherein: The processor includes a processor core, a first-level cache space, a first translation lookaside buffer, and at least one preset cache space, the first-level cache space and the at least one preset cache space being communicatively connected in sequence to form a communication link, the at least one preset cache space including a target preset cache space, the first translation lookaside buffer and the target preset cache space being arranged at the same path level, the first translation lookaside buffer being communicatively connected to the target preset cache space, and the first translation lookaside buffer being arranged outside the processor core, The data processing method includes: querying, in accordance with the address translation request, whether a first-level page table entry corresponding to the address translation request is cached in the first translation lookaside buffer; In response to finding a first-level page table entry corresponding to the address translation request in the first translation lookaside buffer, performing address translation using the corresponding first-level page table entry; The data processing method further includes: In response to receiving a read request generated by the processor core, determining whether the read request is a first-level page table entry read request; In response to the read request being a first-level page table entry read request, returning the obtained first-level page table entry corresponding to the first-level page table entry read request, and writing the corresponding first-level page table entry and the virtual address and translation bits of the memory page in the first-level page table entry read request into the first translation lookaside buffer; In response to the read request not being the first-level page table entry read request, data corresponding to the read request obtained from the target preset cache space, a lower-level cache of the target preset cache space, or a memory is returned.

19. The data processing method according to claim 18, further comprising: Based on a target address obtained by performing address translation using the corresponding first-level page table entry, data corresponding to the target address is read into at least the target preset cache space.

20. An electronic device comprising the processor according to any one of claims 1 to 12.

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