Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a display area and a non-display area; the display area comprises a plurality of data lines and a plurality of connection lines, and the non-display area comprises a plurality of pads; the data lines extend in a first direction, one end of the connection lines is coupled to the data lines, and the other end of the connection lines is coupled to the pads; the display area comprises a first boundary close to one side of the pads; the connection lines comprise a first segment; in the first direction, the first segment extends from the first boundary into the display area; the length of the first segment in the first direction in at least one connection line is D1, and the length of the display area in the first direction is D0, wherein D1>D0 / 2. The present application can improve the problem of uneven screen-off picture.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In existing technologies, fan-out lines are provided on the bottom bezel of the display panel. One end of the fan-out line connects to the display driver chip, and the other end connects to a data line located in the display area. However, the fan-out line occupies a significant amount of space on the bottom bezel, resulting in a wider bottom bezel and affecting aesthetics. One current design solution is to place some of the fan-out lines within the display area to reduce the width of the bottom bezel. However, placing some of the fan-out lines within the display area results in a certain reflectivity to ambient light. This causes a difference in reflectivity between the area where the fan-out lines are located and other display areas without fan-out lines, leading to uneven screen display when the screen is off. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the problem of uneven screen display in the prior art when the screen is off.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a display area and a non-display area;

[0005] The display area includes multiple data lines and multiple connection lines, and the non-display area includes multiple pads; the data lines extend in a first direction, one end of the connection lines is coupled to the data lines, and the other end of the connection lines is coupled to the pads; the display area includes a first boundary near the pads.

[0006] The connecting line includes a first line segment; in a first direction, the first line segment extends from a first boundary into the display area;

[0007] In at least one connecting line, the length of the first segment in the first direction is D1, and the length of the display area in the first direction is D0, where D1>D0 / 2.

[0008] Secondly, based on the same inventive concept, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention.

[0009] The display panel and display device provided in this embodiment of the invention have the following beneficial effects: Connecting lines are provided within the display area, and at least a portion of the data lines are coupled to pads via these connecting lines. This allows some fan-out lines, which would otherwise need to be located in the non-display area, to be placed within the display area, saving wiring space in the non-display area and facilitating narrowing of the non-display area. Furthermore, the connecting lines are elongated along the data line extension direction, extending at least a portion of the connecting lines from the lower display area to the upper display area. This ensures that connecting lines are provided at multiple locations within the display area along the data line extension direction, preventing abrupt changes in the graphic density of the connecting lines along the first direction within the display area. This reduces the difference in ambient light reflectivity between the upper and lower display areas within the display area, improving the problem of uneven screen display when the screen is off. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a display panel in the prior art;

[0012] Figure 2 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0013] Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0014] Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0015] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0016] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0018] Figure 8 for Figure 7 A schematic diagram of a cross-section at the position of the tangent line A-A';

[0019] Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0020] Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0023] Figure 13 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0024] Figure 14 This is a schematic diagram of the film layer of another display panel provided in an embodiment of the present invention;

[0025] Figure 15 This is a pixel circuit diagram in a display panel provided in an embodiment of the present invention;

[0026] Figure 16 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0027] Figure 17 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0028] Figure 18 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0031] Fan-out lines are typically provided in the non-display area of ​​a conventional display panel. These fan-out lines are the connection lines between the data lines within the display area and the driver chip within the non-display area. Because the spacing between data lines within the display area is greater than the spacing between adjacent pins on the driver chip, fan-out lines are provided in the non-display area to achieve the connection between the data lines in the display area and the pins of the driver chip. Furthermore, the spacing between the fan-out lines gradually decreases from the display area towards the driver chip. In other words, multiple fan-out lines originate from the boundary between the display area and the non-display area, gradually converge, and then connect to the corresponding pads. This convergence process requires a certain amount of space. To reduce the space occupied by the fan-out lines in the non-display area, existing technologies place some of the fan-out lines within the display area. Figure 1 This is a schematic diagram of a display panel in the prior art, such as... Figure 1 As shown, fan-out line 001 located within display area AA is coupled to data line 002. Fan-out line 001 within display area AA is primarily coupled to the corresponding data line 002 at the lower part of display area AA, resulting in display area AA being divided into upper and lower regions. Graphical fan-out lines 001 are provided in the first region Q1, while no fan-out lines 001 are provided in the second region Q2, leading to a significant difference in graphic density between the two regions. Furthermore, the graphic fan-out lines 001 within display area AA have a certain reflectivity to ambient light, causing a significant difference in the reflectivity of the area containing fan-out lines 001 compared to other display areas without fan-out lines 001, resulting in uneven screen display when the screen is off.

[0032] To address the problems existing in the prior art, this invention provides a display panel with connecting lines (or fan-out lines located in the display area) arranged within the display area. At least a portion of the data lines are coupled to pads via the connecting lines, and the connecting lines are extended along the extension direction of the data lines, such that at least a portion of the connecting lines are extended above the vertical center line of the display area, or in other words, at least a portion of the connecting lines are extended from the lower display area to the upper display area of ​​the display area. This ensures that connecting lines are arranged at multiple locations within the display area along the extension direction of the data lines, thereby avoiding abrupt changes in the density of the connecting line pattern within the display area, reducing the difference in ambient light reflectivity at different locations within the display area, and improving the problem of uneven screen display when the screen is off.

[0033] Figure 2 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 2As shown, the display panel includes a display area AA and a non-display area NA; the display area AA includes multiple data lines 10 and multiple connection lines 20, and the non-display area NA includes multiple pads 30; the data lines 10 extend in a first direction x, one end of the connection line 20 is coupled to the data line 10, and the other end of the connection line 20 is coupled to the pad 30. The pads 30 are used for bonding and connecting with a driving structure, wherein the driving structure can be a driving chip or a flexible circuit board on which the driving chip is fixed.

[0034] The display area AA includes a first boundary 40 on the side near the pad 30; the first boundary 40 is the boundary between the display area AA and the non-display area AA on the side near the pad 30. The connecting line 20 includes a first line segment X1; in the first direction x, the first line segment X1 extends from the first boundary 40 into the display area AA. The first line segment X is the initial line segment in the connecting line 20 that extends into the display area AA starting from the position of the first boundary 40, and the extension direction of the first line segment X1 is the same as the extension direction of the data line 10. The first direction x is the routing direction or extension direction of the first line segment X1, indicating that the first line segment X1 has a certain length in the first direction x. Figure 2 The diagram only uses the first line segment X1 as a straight line. In some embodiments, the first line segment X1 can also be a broken line composed of multiple line segments.

[0035] In at least one connecting line 20, the length of the first line segment X1 in the first direction x is D1, and the length of the display area AA in the first direction x is D0, where D1 > D0 / 2. That is, the length of the first line segment X1 in at least a portion of the connecting lines 20 in the first direction x is not less than half the length of the display area AA in the first direction x. Specifically, a portion of the first line segment X1 extends from the first boundary 40 along the first direction x into the display area AA, extending above the longitudinal center line 50 of the display area AA. The longitudinal center line 50 divides the display area AA into an upper display area and a lower display area adjacent to each other in the first direction x. The upper and lower display areas are symmetrical about the longitudinal center line 50, with the area closer to the first boundary 40 being the lower display area and the area farther from the first boundary 40 being the upper display area. The longitudinal center line 50 extends along the second direction y, which intersects the first direction x. Optionally, the second direction y is perpendicular to the first direction x. In the first direction x, the distance from the longitudinal center line 50 to the first boundary 40 is D. z , where D z =D0 / 2.

[0036] In this embodiment of the invention, a connecting line 20 is provided within the display area AA. At least a portion of the data lines 10 are coupled to the pads 30 via the connecting line 20. This allows some fan-out lines that would otherwise need to be located in the non-display area NA to be placed within the display area AA, saving wiring space in the non-display area NA and facilitating the narrowing of the non-display area NA. Furthermore, the connecting line 20 is elongated along the extension direction of the data lines 10, so that at least a portion of the connecting line 20 extends from the lower display area of ​​the display area AA to the upper display area of ​​the display area AA. This ensures that connecting lines 20 are provided at multiple locations within the display area AA along the extension direction of the data lines 10. This avoids abrupt changes in the graphic density of the connecting lines 10 along the first direction x within the display area AA, reduces the difference in ambient light reflectivity between the upper and lower display areas within the display area AA, and improves the problem of uneven screen display when the screen is off.

[0037] In some embodiments, D1>2D0 / 3. In some embodiments, the longest first segment X1 in the connecting line 20 basically runs through the display area AA in the first direction x. In other words, the longest first segment X1 in the connecting line 20 extends to the top of the upper display area of ​​the display area AA in the first direction x, which is equivalent to stretching the first segment X1 to fill the entire display area AA in the first direction x, so that the graphic of the first segment X1 exists at various positions in the display area AA along the first direction x. This can avoid the graphic density of the connecting line 10 in the display area AA changing drastically along the first direction x, reduce the difference in ambient light reflectivity between the upper and lower display areas in the display area AA, and improve the problem of uneven screen-off display.

[0038] like Figure 2 As shown, the display area AA includes a symmetry axis 60 extending along a first direction x; on one side of the symmetry axis 60: in the second direction y, from the edge of the display area AA towards the symmetry axis 60, the lengths of multiple first line segments X1 gradually increase. For example... Figure 2 As shown, the connecting line 20 also includes a second line segment X2 extending along the second direction y. One end of the second line segment X2 is coupled to the first line segment X1, and the other end of the second line segment X2 is coupled to the data line 10. The connecting line 20 located in the display area AA extends from the position of the first boundary 40 within the display area AA. The initial position of the connecting line 20 on the first boundary 40 is a certain distance away from the data line 10 to which the connecting line 20 is to be coupled. Therefore, the connecting line 20 needs to first run along the first direction x (e.g., setting the first line segment X1) and then run along the second direction y (e.g., setting the second line segment X2) to connect to the corresponding data line 10. In this embodiment of the invention, on one side of the axis of symmetry 60, the length of multiple first line segments X1 gradually increases along the direction close to the axis of symmetry 60. Therefore, when routing multiple connecting lines 20, the connecting lines 20 will not cross and short-circuit with each other, which simplifies the routing method of the connecting lines 20.

[0039] It should be noted that, Figure 2 The diagram only uses the second line segment X2 as a straight line. The direction of the second line segment X2 is the second direction y. In some embodiments, the second line segment X2 can also be a broken line composed of multiple line segments.

[0040] Figure 3 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 3 As shown, the display area AA includes a first display area AA1 and two second display areas AA2; in the second direction y, the two second display areas AA2 are located on both sides of the first display area AA1; the display area AA has a symmetry axis 60 extending in the first direction x, and the symmetry axis 60 is located in the first display area AA1; the data line 10 includes multiple intermediate data lines 10b and multiple edge data lines 10a, the intermediate data lines 10b are located in the first display area AA1, and the edge data lines 10a are located in the edge display areas AA2; at least a portion of the connecting line 20 is located in the second display area AA2, and the connecting line 20 is coupled to the edge data lines 10a.

[0041] The non-display area NA includes leads, specifically the lines connected to pad 30 within the non-display area NA. These leads include a first lead 31a and a second lead 31b. The intermediate data line 10b is directly coupled to the pad 30 via the second lead 31b. The edge data line 10a is coupled to the pad 30 via a connecting line 20. In fact, the connecting line 20 also needs to be connected to the pad 30 via the first lead 31a located in the non-display area NA. Figure 3 The position circled in the middle is where the first lead 31a and the second lead 31b intersect. Optionally, the first lead 31a and the second lead 31b are located in different metal layers at least at their intersection to ensure that they are insulated from each other.

[0042] In this embodiment of the invention, the fan-out lines that would normally be located in the non-display area NA are introduced into the display area AA. The data line 10 and the pad 30 are coupled using the connecting lines 20 within the display area AA. This reduces the width occupied by multiple fan-out lines in the second direction y, thereby saving wiring space in the non-display area NA and facilitating a narrower non-display area NA. Furthermore, the intermediate data line 10b is still directly coupled to the pad 30 via the second lead 31b, which reduces the number of connecting lines 20 within the display area AA, simplifies the wiring within the display area AA, and also reduces the likelihood of ambient light reflection from the connecting lines 20 within the display area AA.

[0043] In some embodiments, on one side of the axis of symmetry 60: in the second direction y, from the edge of the display area AA to the axis of symmetry 60, the length difference between two adjacent first line segments X1 is a constant value. Figure 4 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 4 As shown, on the right side of the axis of symmetry 60, the connecting lines arranged along the direction close to the axis of symmetry 60 are: connecting line 20-1, connecting line 20-2, connecting line 20-3, and connecting line 20-4. The length of the first line segment X1 in connecting lines 20-1, 20-2, 20-3, and 20-4 gradually increases, and the difference between the first line segment X1 in connecting lines 20-2 and 20-1 is d, the difference between the first line segment X1 in connecting lines 20-3 and 20-2 is d, and the difference between the first line segment X1 in connecting lines 20-4 and 20-3 is d. In this embodiment, at least a portion of the connecting lines 20 extend from the lower display area of ​​the display area AA to the upper display area of ​​the display area AA, so that the graphics of the connecting lines 20 are provided at multiple positions in the first direction x within the display area AA, which can avoid abrupt changes in the graphic density of the connecting lines 10 along the first direction x within the display area AA. Meanwhile, the lengths of multiple first line segments X1 are set to vary arithmetically along the direction close to the axis of symmetry 60, which can further improve the uniformity of the graphic density change of the connecting line 10 along the first direction x, and make the reflectivity of each region along the first direction x gradually change to improve the unevenness of the screen-off image.

[0044] In addition, in this embodiment of the invention, the data lines 10 connected to connecting lines 20-1, 20-2, 20-3, and 20-4 are arranged sequentially. The length of the connecting line 20 affects the load on the data line 10, and the load on the data line 10 affects the charging and discharging speed of the data line 10, thereby affecting the brightness of the light-emitting device coupled to the data line 10. When the lengths of the multiple connecting lines 20 coupled to the sequentially arranged data lines 10 differ significantly, it may cause uneven display due to alternating bright and dark stripes. In this embodiment of the invention, the lengths of the multiple first line segments X1 are arranged in an arithmetic progression along a direction close to the axis of symmetry 60. This also helps to balance the abrupt changes in the total length of the multiple connecting lines 20, making the total length of the sequentially arranged connecting lines 20 also approximately arithmetic progression. This allows the brightness of the area where the multiple data lines 10 coupled to the multiple connecting lines 20 gradually change, thus avoiding alternating bright and dark stripes during display.

[0045] In some embodiments, Figure 2To the left of the axis of symmetry 60: Connecting line 20 includes a first connecting line 1-20 and a second connecting line 2-20; the point where the first connecting line 1-20 and data line 10 are coupled is the first point W1, and the point where the second connecting line 2-20 and data line 10 are coupled is the second point W2. In the second direction y, the distance of the first segment X1 of the first connecting line 1-20 from the axis of symmetry 60 is greater than the distance of the first segment X1 of the second connecting line 2-20 from the axis of symmetry 60; in the first direction x, the distance of the first point W1 from the first boundary 40 is less than the distance of the second point W2 from the first boundary 40. That is, on one side of the axis of symmetry 60, the farther the first segment X1 is from the axis of symmetry 60, the smaller the length of the first segment X1 in the first direction x, and the closer the point where the connecting line 20 containing the first segment X1 is coupled to the data line 10 is to the first boundary 40. In other words, the longer the first line segment X1 is in the first direction x, the farther the point where the connecting line 20 containing the first line segment X1 is coupled to the data line 10 is from the axis of symmetry 60. Extending at least a portion of the connecting line 20 along the first direction x from the lower display area of ​​the display area AA to the upper display area of ​​the display area AA avoids abrupt changes in the graphic density of the connecting line 10 along the first direction x within the display area AA, reduces the difference in ambient light reflectivity between the upper and lower display areas within the display area AA, and improves the problem of uneven screen display when the screen is off. Furthermore, since the point where the connecting line 20 is coupled to the data line 10 varies with the length of the first line segment X1, no additional winding is required when the connecting line 20 is coupled to the corresponding data line 10, simplifying the wiring method of the connecting line 20.

[0046] In some embodiments, such as Figure 2 As shown, on the left side of the axis of symmetry 60: the data line 10 includes a first data line 1-10 and a second data line 2-10. It can be seen that in the second direction y, the distance of the first data line 1-10 from the axis of symmetry 60 is greater than the distance of the second data line 2-10 from the axis of symmetry 60. Specifically, the first connecting line 1-20 is coupled to the first data line 1-10, and the second connecting line 2-20 is coupled to the second data line 2-10. In this embodiment, on one side of the axis of symmetry 60: the data line 10 farther from the axis of symmetry 60 in the second direction y is coupled to the connecting line 20 with a shorter first line segment X1, and the data line 10 closer to the axis of symmetry 60 in the second direction y is coupled to the connecting line 20 with a longer first line segment X1. This arrangement reduces the length difference between different connecting lines 20, thereby reducing the load difference on the data lines 10 coupled to the connecting lines 20, which in turn reduces the difference in charging and discharging speeds between different data lines 10, thus improving the brightness uniformity of the light-emitting devices coupled to the data lines 10 and enhancing the display effect.

[0047] In addition, with Figure 2Taking the left side of the central axis of symmetry 60 as an example, this embodiment of the invention enables the first pad 30 from left to right in the non-display area NA to be coupled to the first data line 10 from left to right in the display area AA, and the second pad 30 from left to right to be coupled to the second data line 10 from left to right in the display area AA. In other words, the data lines 10 in the display area AA and the pads 30 in the non-display area NA are connected sequentially in a one-to-one correspondence. With this configuration, no adjustments to the output pin positions of the driver chip are required, and the display panel provided by this embodiment of the invention is applicable to most existing driver chips.

[0048] In some embodiments, Figure 5 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 5 As shown, the connecting line 20 includes a first segment X1 extending along a first direction x, a second segment X2 extending along a second direction y, and a third segment X3 extending along the first direction x. The second segment X2 is coupled to the data line 10 through the third segment X3. To the left of the axis of symmetry 60: the connecting line 20 includes a first connecting line 1-20 and a second connecting line 2-20; in the second direction y, the distance of the first segment X1 of the first connecting line 1-20 from the axis of symmetry 60 is greater than the distance of the first segment X1 of the second connecting line 2-20 from the axis of symmetry; the data line 10 includes a third data line 3-10 and a fourth data line 4-10; in the second direction y, the distance of the third data line 3-10 from the axis of symmetry 60 is greater than the distance of the fourth data line 4-10 from the axis of symmetry 60; wherein, the first connecting line 1-20 is coupled to the fourth data line 4-10, and the second connecting line 2-20 is coupled to the third data line 3-10. In this embodiment, the connecting line 20 includes a first line segment X1, a second line segment X2, and a third line segment X3 connected sequentially. The shape of the connecting line 20 is approximately an inverted U-shape. Combined with the design in this embodiment of the invention that extends the first line segment X of the connecting line 20 to the upper display area of ​​the display area AA, it can be seen that within the display area where the connecting line 20 is located, the graphic density of the connecting line 20 is more uniform in both the first direction x and the second direction y, which can further improve the problem of uneven screen display when the screen is off. Moreover... Figure 5 The embodiment enables each connecting line 20 to be coupled to the data line 10 at a position close to the first boundary 40 within the display area AA. It also enables the points where each connecting line 20 is coupled to the data line 10 to be at approximately the same distance from the non-display area NA in the first direction x, so that the charging and discharging positions of each data line 10 are at approximately the same distance from the first boundary 40.

[0049] In some embodiments, Figure 6 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 6As shown, the display area AA includes a virtual line 70, and the virtual line 70 includes a first virtual line 71; at least one first virtual line 71 is provided between two adjacent connecting lines 20, and the routing direction of the first virtual line 71 is the same as the routing direction of the connecting line 20. In this embodiment of the invention, the connecting line 20 includes at least a first line segment X1 extending in the first direction x and a second line segment X2 extending in the second direction y, wherein the extension direction of the second line segment X2 intersects with the extension direction of the data line 10 in the display area AA, so the second line segment X2 may overlap with multiple data lines 10 insulatedly within the display area AA (e.g., Figure 6 (Illustration of the area circled in region Z1). This results in severe signal crosstalk on the connecting line 20, and also between adjacent connecting lines 20. In this embodiment of the invention, a first virtual line 71 is provided between adjacent connecting lines 20, and the routing direction of the first virtual line 71 is the same as that of the connecting line 20. The first virtual line 71 can be used to improve the signal crosstalk problem and ensure the stability of the data signal transmitted on the connecting line 20.

[0050] In addition, the setting of the first virtual line 71 can further improve the uniformity of graphic density in the display area AA, further reduce the difference in ambient light reflectivity between different areas in the display area AA, and improve the problem of uneven screen display when the screen is off.

[0051] Figure 6 The diagram only illustrates the presence of a first virtual line 71 between two adjacent connecting lines 20. In some embodiments, two or more first virtual lines 71 are provided between two adjacent connecting lines 20, which will not be shown in the diagram here.

[0052] In some embodiments, the first virtual line 71 and the connecting line 20 are on the same layer and made of the same material. For example... Figure 6 As shown, the first virtual line 71 includes a first virtual line segment 711 extending in the first direction x and a second virtual line segment 712 extending in the second direction y, and the first virtual line segment 711 and the second virtual line segment 712 are connected. Both the first virtual line segment 711 and the second virtual line segment 712 are manufactured in the same layer and with the same material as the connecting line 20. In this embodiment, the first virtual line 71 and the connecting line 20 can be manufactured simultaneously in the same process, simplifying the manufacturing process. Furthermore, placing the first virtual line 71 and the connecting line 20 in the same layer significantly enhances their effectiveness in preventing signal crosstalk between adjacent connecting lines 20.

[0053] like Figure 6As shown, the first virtual line 71 includes a first virtual line segment 711 extending in the first direction x, and the first virtual line segment 711 is located between two adjacent first line segments X1. That is, the first virtual line segment 711 between two adjacent first line segments X1 has the same extension direction as the first line segment X1. When the first virtual line 71 and the connecting line 20 are in the same layer and made of the same material, setting the extension direction of the first virtual line segment 711 to be the same as that of the first line segment X1 is beneficial to simplify the design of the mask. However, if the virtual line segment located between adjacent first line segments X1 intersects with the extension direction of the first line segment X1, it will increase the complexity of the mask design.

[0054] In some embodiments, Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 8 for Figure 7 A schematic diagram of a cross-section at the position of the midtangent line A-A'. (Example) Figure 7 As shown, the connecting line 20 also includes a first segment X1 extending along a first direction x and a second segment X2 extending along a second direction y. The first segment X1 and the second segment X2 are electrically connected to each other. The first virtual line 71 includes a first virtual segment 711 extending along the first direction x and a second virtual segment 712 extending along the second direction y. The first virtual segment 711 is located between two adjacent first segments X1, and the second virtual segment 712 is located between two adjacent second segments X2.

[0055] like Figure 8 As shown, the display panel includes a substrate 010, and the virtual lines, connecting lines, and data lines are all located on the same side of the substrate 010. The first virtual line segment 711 and the first line segment X1 are in the same layer and made of the same material, while the second virtual line segment 712 and the second line segment X2 are in the same layer and made of the same material, but the first virtual line segment 711 and the second virtual line segment 712 are located in different layers. In this embodiment, the first line segment X1 and the second line segment X2 in the connecting line 20 are located in different layers; that is, the connecting line 20 is made using two metal layers, and the lines in the connecting line 20 with different extension directions are located in different layers. The first line segment X1 and the second line segment X2 are in... Figure 7 The area Z2 in the middle region is connected by a through-hole that penetrates the insulation layer.

[0056] Depend on Figure 8It can be seen that the connecting line 20 and the first virtual line 71 are both located on the side of the data line 10 away from the substrate 010. The second line segment X2 and the second virtual line segment 712 are located in the same layer and on the side of the first virtual line segment 711 and the first line segment X1 away from the substrate 010. A first insulating layer 011 is provided between the film layers containing the data line 10 and the first line segment X1, and a second insulating layer 012 is provided between the film layers containing the second line segment X2 and the first line segment X1. Therefore, in the direction e perpendicular to the plane containing the substrate 010, the space between the second line segment X2 and the data line 10 includes at least the first insulating layer 011 and the second insulating layer 012. In this embodiment of the invention, the first line segment X1 and the second line segment X2 are located on different layers, and the second line segment X2 is located on the side of the first line segment X1 away from the data line 10. This can increase the distance between the second line segment X2 and the data line 10 in the direction e perpendicular to the plane where the substrate 010 is located. This can reduce the crosstalk caused by the overlap of the second line segment X2 and multiple data lines 10, and ensure the stability of the data signal transmitted on the connection line 20.

[0057] Furthermore, by setting the first virtual line segment 711 and the first line segment X1 to extend in the same direction and be located on the same layer, the first virtual line segment 711 can provide excellent shielding and prevent signal crosstalk between two adjacent first line segments X1. Similarly, by setting the second virtual line segment 712 and the second line segment X2 to extend in the same direction and be located on the same layer, the second virtual line segment 712 can provide excellent shielding and prevent signal crosstalk between two adjacent second line segments X2.

[0058] Figure 7 The diagram illustrates that the first virtual line segment 7111 and the second virtual line segment 712 are not connected. In other embodiments, the first virtual line segment 7111 and the second virtual line segment 712, located in different metal layers, are connected through a via penetrating the insulating layer.

[0059] In some embodiments, Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 9 The diagram only shows a portion of the display panel. To clearly illustrate the relationship between the first line segment X1, data line 10, and the first virtual line segment 711 in the display panel, Figure 9 Only these line segments are shown in the diagram; the structure of other circuits and light-emitting devices is not shown. For example... Figure 9 As shown, at least one data line 10 is spaced between at least two partially adjacent first line segments X1. Figure 9This is a top view of the display panel. It can be understood that the top view direction is parallel to the plane perpendicular to the substrate 010. In the plane perpendicular to the substrate 010, the first virtual line segment 711 and the data line 10 at least partially overlap. The first line segment X1 extends from the first boundary 40 into the display area AA along the first direction x. In order to save space in the non-display area NA, multiple connecting lines 20 need to be arranged on one side of the axis of symmetry 60. All of the multiple connecting lines 20 are drawn from the first boundary 40 into the display area AA.

[0060] In designing this embodiment, various factors were considered, including the number of connecting lines 20 within the display area AA, the density of the first line segment X1 within the display area AA, and the saving of space in the non-display area NA. Furthermore, after the connecting lines 20 are installed within the display area AA, the connecting lines 20 need to pass through the first lead 31a (refer to...). Figure 3 (As shown in the diagram) Coupled to pad 30, the routing method of the first lead 31a also needs to be considered. The spacing between adjacent first leads 31a also needs to be designed to adapt to the spacing between adjacent pads 30. In this embodiment of the invention, at least one data line 10 is spaced between two adjacent first segments X1 within the display area AA, so that the spacing between two adjacent first segments X1 arranged within the display area AA is approximately the same as the spacing between two adjacent data lines 10. This facilitates the routing of the first leads 31a in the non-display area NA. The spacing between adjacent first leads 31a can be designed with reference to the spacing between adjacent second leads 31b. In other words, the spacing between adjacent first leads 31a can be designed with reference to the spacing between fan-out lines in the prior art, which simplifies the routing design of the first leads 31a.

[0061] In addition, since both the first virtual line segment 711 and the data line 10 are made of metal, both the first virtual line segment 711 and the data line 10 will reflect ambient light. In this embodiment of the invention, the first virtual line segment 711 and the data line 10 are set to overlap at least partially, so that the first virtual line segment 711 can block part of the data line 10, thereby reducing the overall reflectivity and improving the display effect.

[0062] In some embodiments, Figure 10 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 10As shown, the virtual line 70 includes a first virtual line 71 and a second virtual line 72. The first virtual line 71 is located between adjacent connecting lines 20, and the extension direction of the first virtual line 71 is the same as the extension direction of the connecting line 20. The second virtual line 72 extends along the second direction y. Optionally, at least a portion of the second virtual line 72 passes through the display area AA in the second direction y. At least one second virtual line 72 intersects at least one first line segment X1, and the second virtual line 72 breaks at the intersection with the first line segment X1. The details of the second virtual line 72 breaking at the intersection with the first line segment X1 can be found in [reference needed]. Figure 10 A schematic diagram of region Z3. At least one second virtual line 72 intersects with at least one first virtual line 71, and the second virtual line 72 and the first virtual line 71 are coupled at the intersection. For details regarding the coupling of the second virtual line 72 and the first virtual line 71 at the intersection, please refer to... Figure 10 A schematic diagram of the central region Z4. The second virtual line 72 provided in this embodiment of the invention can further improve the overall uniformity of graphic density within the display area AA, thus mitigating the problem of uneven screen display when the screen is off.

[0063] In this embodiment of the invention, the second virtual line 72 can be located on the same layer as the first line segment X1, or the second virtual line 72 and the first line segment X1 can be located on different layers. When the second virtual line 72 and the first line segment X1 are located on the same metal layer, the second virtual line 72 is set to break at the intersection with the first line segment X1. In this case, the second virtual line 72 will not affect the signal transmission of the first line segment X1 and will not increase the load on the connecting line 20. When the second virtual line 72 and the first line segment X1 are located on different layers, assuming the second virtual line 72 is located on the side of the first line segment X1 closer to the substrate 010, the patterned second virtual line 72 is fabricated first, then an insulating layer is fabricated on the second virtual line 72, and then the first line segment X1 is fabricated. Since the second virtual line 72 is set to break at the intersection with the first line segment X1, the break point of the second virtual line 72 is equivalent to forming a groove, and the part of the first line segment X1 fabricated subsequently is fabricated in the groove. This setting can improve the flatness of the module after the first line segment X1 process.

[0064] In this embodiment of the invention, the extension direction of the first virtual line segment 711 in the first virtual line 71 is the same as the extension direction of the first line segment X1. Figure 10It can be seen that the second virtual line 72 and the first virtual line segment 711 are coupled at their intersection. The first virtual line segment 711 can be located on the same layer as the first line segment X1 or on a different layer. That is, the second virtual line 72 can be on the same layer as the first virtual line segment 711 or on a different layer. When the second virtual line 72 and the first virtual line segment 711 are on the same layer, they are directly connected at their intersection. When the second virtual line 72 and the first virtual line segment 711 are on different layers, they are connected at their intersection through a via in the insulating layer. In this embodiment of the invention, the second virtual line 72 and the first virtual line 71 are coupled. When a constant voltage signal is applied to the first virtual line 71 and the second virtual line 72, such as a power signal (either a positive or negative power signal) to drive the pixel circuit, it helps to reduce the voltage drop of the power signal and improve the uniformity of the power signal within the display area AA. When the reset signal for driving the pixel circuit is connected on the first virtual line 71 and the second virtual line 72, it helps to reduce the voltage drop of the reset signal and improve the uniformity of the reset signal in the display area AA.

[0065] In some embodiments, Figure 11 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 11 As shown, the virtual line 70 includes a third virtual line 73 extending along a first direction x; at least one third virtual line 73 intersects at least one second line segment X2, and the third virtual line 73 breaks at the intersection with the second line segment X2; at least one third virtual line 73 intersects at least one first virtual line 71, and the third virtual line 73 is coupled to the first virtual line 71 at the intersection. Figure 11 As illustrated, a portion of the third virtual line 73 extends through the display area AA in the first direction x. It should be noted that, since the third virtual line 73 extends in the same direction as the data line 10, this is done to clearly distinguish the two types of lines. Figure 11 The third virtual line 73 is indicated by a thick black line. The thick black line does not imply that the line width of the third virtual line 73 is large.

[0066] A connecting line 20 is set within the display area AA. The connecting line includes a first line segment X1. At least a portion of the first line segment X1 extends to the upper display area of ​​the display area AA, while a portion of the first line segment X1 is shorter and only extends to the lower display area of ​​the display area AA. This addresses the issue of uneven distribution of the first line segment X1 in the second direction y within the display area AA, which can be addressed by referring to the above... Figure 6 To understand, Figure 6The left and right positions of the central display area AA basically lack the first line segment X1. To further improve the uniformity of graphic density within the display area AA, a third virtual line 73 is provided in this embodiment of the invention. The extension direction of the third virtual line 73 is the same as the extension direction of the first line segment X1. The addition of the third virtual line 73 helps to balance the differences in trace density extending along the first direction x at different positions.

[0067] In this embodiment of the invention, the third virtual line 73 can be located on the same layer as the second line segment X2, or on different layers. When the third virtual line 73 and the second line segment X2 are on the same layer, the third virtual line 73 is broken at the intersection with the second line segment X2. In this case, the third virtual line 73 will not affect the signal transmission of the second line segment X2 and will not increase the load on the connecting line 20. When the third virtual line 73 and the second line segment X2 are on different layers, assuming the third virtual line 73 is located on the side of the second line segment X2 closer to the substrate 010, the patterned third virtual line 73 is fabricated first, then an insulating layer is fabricated on the third virtual line 73, and then the second line segment X2 is fabricated. Since the third virtual line 73 is broken at the intersection with the second line segment X2, the break point of the third virtual line 73 is equivalent to forming a groove, and the part of the second line segment X2 fabricated subsequently is fabricated in the groove. This setting can improve the flatness of the module after the second line segment X2 process.

[0068] In this embodiment of the invention, the extension direction of the second virtual line segment 712 in the first virtual line 71 is the same as the extension direction of the second line segment X2. Figure 11 It can be seen that the third virtual line 73 and the second virtual line segment 712 are coupled at their intersection. The second virtual line segment 712 can be located on the same layer as the second line segment X2 or on a different layer. That is, the third virtual line 73 can be on the same layer as the second virtual line segment 712 or on a different layer. When the third virtual line 73 and the second virtual line segment 712 are on the same layer, they are directly connected at their intersection. When the third virtual line 73 and the second virtual line segment 712 are on different layers, they are connected at their intersection through a via in the insulating layer. In this embodiment of the invention, the third virtual line 73 is coupled to the first virtual line 71. When a constant voltage signal is applied to the first virtual line 71 and the third virtual line 73, such as a power signal (either a positive or negative power signal) to drive the pixel circuit, it helps to reduce the voltage drop of the power signal and improve the uniformity of the power signal within the display area AA. When the reset signal for driving the pixel circuit is connected on the first virtual line 71 and the third virtual line 73, it helps to reduce the voltage drop of the reset signal and improve the uniformity of the reset signal in the display area AA.

[0069] In some embodiments, Figure 12 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 12 As shown, the virtual line 70 includes a fourth virtual line 74 extending along the first direction x, and the fourth virtual line 74 does not intersect with the connecting line 20. The fourth virtual line 74 passes through the display area AA in the first direction x. It should be noted that, since the fourth virtual line 74 extends in the same direction as the data line 10, to clearly distinguish the two types of lines, Figure 12 The fourth virtual line 74 is indicated by a bold black line, but the bold black line does not imply a larger line width for the fourth virtual line 74. For example... Figure 12 As illustrated, the connecting lines 20 are basically set on the left and right sides of the display area AA, and no connecting lines 20 are set in the middle area of ​​the display area AA. Therefore, in this embodiment of the invention, a fourth virtual line 74 extending along the first direction x is set to increase the graphic density difference between the middle area and the left and right side areas of the display area AA, thereby further improving the uniformity of graphic density in the display area AA and improving the unevenness of the screen-off image.

[0070] Figure 12 The schematic virtual line 70 includes a first virtual line 71 with the same routing direction as the connecting line 20, a third virtual line 73 extending along the first direction x, and a fourth virtual line 74.

[0071] In some embodiments, the first virtual line segment 711 and the second virtual line segment 712 in the first virtual line 71 are located on the same layer, and the fourth virtual line 74 is located on the same layer as the first virtual line 71.

[0072] In another embodiment, the first virtual line segment 711 and the second virtual line segment 712 in the first virtual line 71 are located on different layers, and the fourth virtual line 74 and the first virtual line segment 711 with the same extension direction are located on the same layer.

[0073] In some embodiments, Figure 13 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 13 As shown, the display area AA includes a first virtual line 71, a second virtual line 72, a third virtual line 73, and a fourth virtual line 74. (As...) Figure 13 As illustrated in region Z7, the second virtual line 72 and the third virtual line 73 intersect and are coupled at the intersection. For example... Figure 13As illustrated in region Z8, the second virtual line 72 and the fourth virtual line 74 intersect and are coupled at the intersection. It can be seen that in embodiments including four types of virtual lines, the intersecting virtual lines 70 are coupled to each other, forming an approximate grid structure within the entire display area AA. This arrangement improves the uniformity of graphic density within the display area AA. Furthermore, when a constant voltage is applied to the virtual lines 70, it also reduces the overall impedance and improves the uniformity of the constant voltage within the surface.

[0074] In embodiments that include four types of virtual lines, optionally, two metal layers are used to fabricate the virtual lines. Virtual lines extending along a first direction x are located on one layer, while virtual lines extending along a second direction y are located on another layer. For example, the first virtual line segment 711, the third virtual line 73, and the fourth virtual line 74 of the first virtual line 71 extending along the first direction x are located on the same layer, and the second virtual line 72 extending along the second direction y and the second virtual line segment 712 of the first virtual line 71 are located on the same layer. Two virtual lines whose extension directions intersect are connected at their intersection points via vias penetrating the insulating layer.

[0075] In some embodiments, the first segment X1 and the second segment X2 in the connecting line 20 are located in different layers. The first segment X1 is located in the same layer as a virtual line extending along a first direction x, and the second segment X2 is located in the same layer as a virtual line extending along a second direction y. The film layer containing the second segment X2 is located on the side of the film layer containing the first segment X1 that is furthest from the substrate 010. This arrangement increases the distance between the second segment X2 and the data line 10 in a direction perpendicular to the plane of the substrate 010, thereby reducing signal crosstalk caused by the intersection of the second segment X2 and the data line 10.

[0076] In some embodiments, such as Figure 13 As shown, the non-display area NA includes a first non-display area NA1, and multiple pads 30 are located in the first non-display area NA1. Each pad 30 includes a constant voltage signal terminal 30h, which is used to provide a constant voltage signal. The first non-display area NA1 includes a first constant voltage bus 80, and a virtual line 70 is coupled to the constant voltage signal terminal 30h through the first constant voltage bus 80. In this embodiment of the invention, the virtual line 70 is coupled to the constant voltage signal terminal 30h, so a constant voltage signal is transmitted on the virtual line 70. The constant voltage signal can be, for example, a power supply signal or a reset signal that drives the pixel circuit.

[0077] Figure 13The diagram illustrates that the first virtual line 71 extends to the first non-display area NA1 and is coupled to the first constant voltage bus 80; a portion of the second virtual line 72 extends to the first non-display area NA1 and is coupled to the first constant voltage bus 80; and a fourth virtual line 74 extends to the first non-display area NA1 and is coupled to the first constant voltage bus 80. This arrangement allows the first constant voltage bus 80 to be coupled to the virtual lines 70 within the display area AA at multiple points, thereby improving the uniformity of the constant voltage signal at various locations and enhancing the brightness uniformity of the display area.

[0078] Figure 14 This is a schematic diagram of the film layer of another display panel provided in an embodiment of the present invention. Figure 15 This is a pixel circuit diagram in a display panel provided in an embodiment of the present invention. Figure 14 As shown, the display panel includes a substrate 010, an array layer 020 located on one side of the substrate 010, and a device layer 030; the array layer 020 includes multiple pixel circuits 021, and the device layer 030 includes multiple light-emitting devices P; the light-emitting device P includes a stacked first electrode 031, a light-emitting layer 032, and a second electrode 033. Figure 14 Only one transistor in pixel circuit 021 is shown in the diagram. (Combined with...) Figure 15 To understand this, the first electrode 031 is coupled to the first power signal line Pvdd through the pixel circuit 021, and the second electrode 033 is coupled to the second power signal line Pvee.

[0079] like Figure 15As shown, the pixel circuit includes a driving transistor Tm, a gate reset transistor T1, an electrode reset transistor T2, a data write transistor T3, a threshold compensation transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst. The gate reset transistor T1 is used to reset the gate of the driving transistor Tm, and the electrode reset transistor T2 is used to reset the light-emitting device P. The first electrode of the gate reset transistor T1 is coupled to the reset signal line Ref, which provides the reset signal. The second electrode of the gate reset transistor T1 is coupled to the first node N1, the gate of the driving transistor Tm is coupled to the first node N1, the first electrode of the driving transistor Tm is coupled to the second node N2, and the second electrode of the driving transistor Tm is coupled to the third node N3. The driving transistor Tm is connected in series between the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The first electrode of the data write transistor T3 is coupled to the data line 10, and the second electrode of the data write transistor T3 is coupled to the second node N2. The threshold compensation transistor T4 is connected in series between the first node N1 and the third node N3. The first plate of the storage capacitor Cst and the first electrode of the first light-emitting control transistor T5 are both coupled to the first power supply signal line Pvdd. The first electrode of the electrode reset transistor T2 is coupled to the reset signal line Ref, and the second electrode of the electrode reset transistor T2 and the first electrode of the light-emitting device P are coupled to the fourth node N4. The second electrode of the light-emitting device P is coupled to the second power supply signal line Pvee. The first power supply signal line Pvdd is the positive power supply line, and the second power supply signal line Pvee is the negative power supply line. The gate of the data write transistor T3 and the gate of the threshold compensation transistor T4 are coupled to the first scan line Sc1, the gate of the gate reset transistor T1 and the gate of the electrode reset transistor T2 are coupled to the second scan line Sc2, and the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are coupled to the light-emitting control line E. It should be noted that... Figure 15 The diagram only shows a pixel circuit with 7 transistors and 1 capacitor, and is not intended to limit the invention.

[0080] In one embodiment, the constant voltage signal terminal 30h includes a first power supply terminal, and a virtual line 70 is coupled to the first power supply terminal. The virtual line 70 is multiplexed as a first power signal line Pvdd. Since the first power signal line Pvdd is a positive power line, the first constant voltage bus 80 is a positive power bus, and the virtual line 70 within the display area AA can provide a positive power signal to the pixel circuit. In some embodiments, multiplexing the virtual line 70 as the first power signal line Pvdd eliminates the need for a conventional first power signal line within the display area AA, saving space occupied by the pixel circuit and increasing the number of pixel circuits. In other embodiments, multiplexing the virtual line 70 as the first power signal line Pvdd and connecting it in parallel with a conventional first power signal line within the display area AA reduces the voltage drop during transmission of the first power signal, improves the uniformity of the power signal within the display area AA, and thus improves brightness uniformity.

[0081] In another embodiment, the constant voltage signal terminal 30h includes a second power supply terminal, and a virtual line 70 is coupled to the second power supply terminal. The virtual line 70 is multiplexed as a second power signal line Pvee. Since the second power signal line Pvee is a negative power line, the first constant voltage bus 80 is a negative power bus, and the virtual line 70 within the display area AA can provide a negative power signal to the pixel circuit. In conventional display panels, a negative power bus needs to be set around the left, right, and top borders of the display area AA, resulting in the negative power bus occupying a large space in the non-display area NA. However, with the design of this embodiment, the negative power buses on the left, right, and top borders of the display area AA can be removed, and the negative power bus is only set in the first non-display area NA1. This reduces the voltage drop of the transmitted negative power signal, improves the uniformity of the negative power signal within the entire display area AA, and also reduces the bezel size and increases the screen-to-body ratio.

[0082] In another embodiment, the display panel includes a reset signal line Ref, and the pixel circuit 021 includes a reset port coupled to the reset signal line Ref; referring to the above. Figure 15 To understand this, the first terminal of gate reset transistor T1 and the first terminal of electrode reset transistor T2 are the reset ports of pixel circuit 021. The constant voltage signal terminal 30h includes a reset signal terminal, and virtual line 70 is coupled to the reset signal terminal. Virtual line 70 is multiplexed as the reset signal line Ref, meaning the first constant voltage bus 80 is the reset bus. Virtual line 70 within display area AA can provide a reset signal to the pixel circuit. For example... Figure 13 The virtual lines 70 shown in the diagram form an approximate grid structure within the entire display area AA. This configuration improves the uniformity of graphic density within the display area AA. Furthermore, by using the virtual lines 70 to connect the reset signal, the overall impedance of the reset signal line can be reduced, and the uniformity of the in-plane reset signal can be improved, thereby enhancing the brightness uniformity within the display area AA.

[0083] Figure 15 The diagram illustrates the coupling of gate reset transistor T1 and electrode reset transistor T2 to the same reset signal line Ref.

[0084] In some embodiments, Figure 16 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 16 As shown, the first terminal of gate reset transistor T1 is coupled to the first reset signal line Ref1, and the first terminal of electrode reset transistor T2 is coupled to the second reset signal line Ref2. The first reset signal line Ref1 provides the first reset signal, and the second reset signal line Ref2 provides the second reset signal. The voltage values ​​of the first and second reset signals are different. The gate of gate reset transistor T1 is coupled to the second scan line Sc2, and the gate of electrode reset transistor T2 is coupled to the first scan line Sc1.

[0085] Figure 16 In this embodiment, the reset port includes a first reset port and a second reset port; the first electrode of the gate reset transistor T1 is the first reset port of the pixel circuit 021, and the first reset signal line Ref1 is coupled to the first reset port. The first electrode reset transistor T2 is the second reset port of the pixel circuit 021, and the second reset signal line Ref2 is coupled to the second reset port.

[0086] In one embodiment, virtual line 70 is configured to transmit a first reset signal, i.e., virtual line 70 is multiplexed as a first reset signal line Ref1. In another embodiment, virtual line 70 is configured to transmit a second reset signal, i.e., virtual line 70 is multiplexed as a second reset signal line Ref2.

[0087] In another embodiment, a portion of the virtual line 70 is multiplexed as the first reset signal line Ref1, and the remaining portion of the virtual line 70 is multiplexed as the second reset signal line Ref2. This configuration allows for the reduction of the voltage drop during transmission of the first reset signal using a portion of the virtual line 70, while simultaneously reducing the voltage drop during transmission of the second reset signal using the remaining portion of the virtual line 70. This improves the uniformity of the reset signal within the display area AA.

[0088] In one embodiment, the display panel includes a first reset signal line A extending along a first direction x and a first reset signal line B extending along a second direction y. The first reset signal line A and the first reset signal line B intersect and are coupled to each other at the intersection. Both the first reset signal line A and the first reset signal line B transmit a first reset signal. This arrangement causes the first reset signal line A and the first reset signal line B to intersect and form a grid structure, which can reduce the voltage drop of the transmitted first reset signal. In this embodiment of the invention, a portion of the virtual line 70 is multiplexed as the first reset signal line Ref1, which can further reduce the voltage drop of the transmitted first reset signal and improve the uniformity of the transmitted first reset signal in the plane. In this embodiment of the invention, multiple light-emitting devices P are arranged in a pixel column in the first direction x within the display area AA. Optionally, the light-emitting devices P in two adjacent pixel columns are coupled to the same first reset signal line A. This not only achieves the intersecting and grid-like structure of the first reset signal line A and the first reset signal line B, but also reduces the number of first reset signal lines A, thereby saving wiring space in the display panel.

[0089] In another embodiment, the display panel includes a second reset signal line A extending along a first direction x and a second reset signal line B extending along a second direction y. The second reset signal line A and the second reset signal line B intersect and are coupled to each other at the intersection. Both the second reset signal line A and the second reset signal line B transmit a second reset signal. This arrangement causes the second reset signal line A and the second reset signal line B to intersect and form a grid structure, which can reduce the voltage drop of the transmitted second reset signal. In this embodiment of the invention, a portion of the virtual line 70 is multiplexed as the second reset signal line Ref2, which can further reduce the voltage drop of the transmitted second reset signal and improve the uniformity of the transmitted second reset signal in the plane. In this embodiment of the invention, multiple light-emitting devices P are arranged in a pixel column in the first direction x within the display area AA. Optionally, the light-emitting devices P in two adjacent pixel columns are coupled to the same second reset signal line A. This not only achieves the intersecting and grid-like structure of the second reset signal line A and the second reset signal line B, but also reduces the number of second reset signal lines A, thereby saving wiring space in the display panel.

[0090] In one embodiment, Figure 17 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 17 As shown, the light-emitting device P includes a red light-emitting device Pr, a green light-emitting device Pg, and a blue light-emitting device Pb; Figure 17 The arrangement of the light-emitting devices P is for illustrative purposes only and is not intended to limit the scope of the invention. Figure 17As can be seen, in the direction perpendicular to the plane of substrate 010, the coupling points of connection line 20-12 and data line 10 overlap with the red light-emitting device Pr, and the coupling points of connection line 20-11 and data line 10 overlap with the blue light-emitting device Pb. That is, the vias coupling the connection lines to data line 10 overlap with the red light-emitting device Pr, or the vias coupling the connection lines to data line 10 overlap with the blue light-emitting device Pb. However, the vias coupling the connection lines to data line 10 do not overlap with the green light-emitting device Pg. In this embodiment, the design of the connection position between connection line 20 and data line 10 vias does not need to avoid the red light-emitting device Pr and the blue light-emitting device Pb, which simplifies the wiring method of connection line 20. Furthermore, by ensuring that the vias coupling the connection lines to data line 10 do not overlap with the green light-emitting device Pg, the vias can be prevented from affecting the uniform light emission of the green light-emitting device Pg in all directions, thus reducing the impact on display color shift.

[0091] In some embodiments, as described above Figure 10 In the embodiment, the second virtual line 72, which intersects with the first line segment X1, is broken at the intersection. It is positioned perpendicular to the plane of the substrate 010. The break point of the second virtual line 72 does not overlap with the green light-emitting device Pg, but it can overlap with either the red light-emitting device Pr or the blue light-emitting device Pb. This configuration reduces the impact of the break point of the second virtual line 72 on the displayed color shift.

[0092] in addition, Figure 12 In the embodiment, the overlap between the break point of the third virtual line 73 and the light-emitting device P can be set with reference to the overlap between the break point of the second virtual line 72 and the light-emitting device P.

[0093] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 18 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 18 As shown, the display device includes the display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention includes, for example, any device with display function such as a mobile phone, tablet computer, laptop computer, or television set.

[0094] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area; the display area includes multiple data lines and multiple connecting lines, and the non-display area includes multiple pads; the data lines extend in a first direction, one end of each connecting line is coupled to the data line, and the other end of each connecting line is coupled to the pads; the display area includes a first boundary near the pads. The connecting line includes a first line segment; in the first direction, the first line segment extends from the first boundary into the display area; In at least one of the connecting lines, the length of the first line segment in the first direction is D1, and the length of the display area in the first direction is D0, wherein D1>D0 / 2; The display area includes virtual lines, and the virtual lines include a first virtual line; at least one first virtual line is disposed between two adjacent connecting lines, and the routing direction of the first virtual line is the same as the routing direction of the connecting lines; the connecting lines also include a second line segment extending along a second direction, which intersects the first direction; wherein... The virtual line includes a second virtual line extending along the second direction; at least one second virtual line intersects at least one first line segment, and the second virtual line is broken at the intersection with the first line segment; at least one second virtual line intersects at least one first virtual line, and the second virtual line is coupled to the first virtual line at the intersection. Alternatively, the virtual line may include a third virtual line extending along the first direction; at least one of the third virtual lines may intersect at least one of the second line segments, and the third virtual line may be broken at the intersection with the second line segment; at least one of the third virtual lines may intersect at least one of the first virtual lines, and the third virtual line may be coupled to the first virtual line at the intersection.

2. The display panel according to claim 1, characterized in that, The display area includes an axis of symmetry extending along the first direction; On one side of the axis of symmetry: in a second direction from the edge of the display area toward the axis of symmetry, the lengths of the plurality of first line segments gradually increase, and the second direction intersects the first direction.

3. The display panel according to claim 2, characterized in that, On one side of the axis of symmetry: in the second direction, from the edge of the display area to the axis of symmetry, the length difference between two adjacent first line segments is a constant value.

4. The display panel according to claim 2, characterized in that, On one side of the axis of symmetry: The connecting line includes a first connecting line and a second connecting line; the point where the first connecting line and the data line are coupled is the first point, and the point where the second connecting line and the data line are coupled is the second point; In the second direction, the distance of the first segment of the first connecting line from the axis of symmetry is greater than the distance of the first segment of the second connecting line from the axis of symmetry; in the first direction, the distance of the first point from the first boundary is less than the distance of the second point from the first boundary.

5. The display panel according to claim 2, characterized in that, On one side of the axis of symmetry: The connecting line includes a first connecting line and a second connecting line; in the second direction, the distance of the first segment of the first connecting line from the axis of symmetry is greater than the distance of the first segment of the second connecting line from the axis of symmetry. The data line includes a first data line and a second data line; in the second direction, the distance of the first data line from the axis of symmetry is greater than the distance of the second data line from the axis of symmetry. The first connecting line is coupled to the first data line, and the second connecting line is coupled to the second data line.

6. The display panel according to claim 1, characterized in that, The connecting line further includes a second line segment extending along a second direction, which intersects the first direction; one end of the second line segment is coupled to the first line segment, and the other end of the second line segment is coupled to the data line.

7. The display panel according to claim 6, characterized in that, The connecting line further includes a third segment extending along the first direction, and the second segment is coupled to the data line through the third segment; The display area includes an axis of symmetry extending along the first direction; on one side of the axis of symmetry: The connecting line includes a first connecting line and a second connecting line; in the second direction, the distance of the first segment of the first connecting line from the axis of symmetry is greater than the distance of the first segment of the second connecting line from the axis of symmetry. The data line includes a third data line and a fourth data line; in the second direction, the distance of the third data line from the axis of symmetry is greater than the distance of the fourth data line from the axis of symmetry. The first connecting line is coupled to the fourth data line, and the second connecting line is coupled to the third data line.

8. The display panel according to claim 1, characterized in that, The first virtual line and the connecting line are in the same layer and made of the same material.

9. The display panel according to claim 1, characterized in that, The first virtual line includes a first virtual line segment extending in the first direction, the first virtual line segment being located between two adjacent first line segments.

10. The display panel according to claim 9, characterized in that, The first virtual line includes a second virtual line segment extending in the second direction, the second virtual line segment being located between two adjacent second line segments; The first virtual line segment and the second virtual line segment are in the same layer and made of the same material, and the first virtual line segment and the second virtual line segment are in the same layer and made of the same material, but the first virtual line segment and the second virtual line segment are located in different layers.

11. The display panel according to claim 9, characterized in that, At least one data line is spaced between at least two partially adjacent first line segments; The display panel includes a substrate; in a plane perpendicular to the substrate, the first virtual line segment and the data line at least partially overlap.

12. The display panel according to claim 1, characterized in that, The virtual line includes a fourth virtual line extending along the first direction, and the fourth virtual line does not intersect the connecting line.

13. The display panel according to claim 1, characterized in that, The display panel includes a constant voltage signal terminal, which is used to provide a constant voltage signal; the virtual line is coupled to the constant voltage signal terminal.

14. The display panel according to claim 13, characterized in that, The non-display area includes a first non-display area, and the plurality of pads are located in the first non-display area; The first non-display area includes a first constant voltage bus, and the virtual line is coupled to the constant voltage signal terminal through the first constant voltage bus.

15. The display panel according to claim 13, characterized in that, The display panel includes a substrate, an array layer located on one side of the substrate, and a device layer; the array layer includes multiple pixel circuits, and the device layer includes multiple light-emitting devices; the light-emitting devices include a stacked first electrode, a light-emitting layer, and a second electrode; The first electrode is coupled to a first power signal line via the pixel circuit, and the second electrode is coupled to a second power signal line; wherein... The constant voltage signal terminal includes a first power supply terminal, and the virtual line is coupled to the first power supply terminal and the virtual line is multiplexed as the first power signal line; or, the constant voltage signal terminal includes a second power supply terminal, and the virtual line is coupled to the second power supply terminal and the virtual line is multiplexed as the second power signal line.

16. The display panel according to claim 13, characterized in that, The display panel includes a substrate, an array layer located on one side of the substrate, and a device layer; the array layer includes multiple pixel circuits, and the device layer includes multiple light-emitting devices; The display panel includes a reset signal line, and the pixel circuit includes a reset port, which is coupled to the reset signal line. The constant voltage signal terminal includes a reset signal terminal, and the virtual line is coupled to the reset signal terminal. The virtual line is multiplexed as the reset signal line.

17. The display panel according to claim 16, characterized in that, The reset signal line includes a first reset signal line and a second reset signal line, and the reset port includes a first reset port and a second reset port; the first reset signal line is coupled to the first reset port, and the second reset signal line is coupled to the second reset port; The pixel circuit includes a gate reset transistor, an electrode reset transistor, and a driving transistor. The gate reset transistor is used to reset the gate of the driving transistor, and the electrode reset transistor is used to reset the light-emitting device. The first electrode of the gate reset transistor is the first reset terminal, and the first electrode reset transistor is the second reset terminal. Some of the virtual lines are multiplexed as the first reset signal line, and some of the virtual lines are multiplexed as the second reset signal line.

18. The display panel according to claim 1, characterized in that, The display panel includes a substrate and a plurality of light-emitting devices located on one side of the substrate; the light-emitting devices include red light-emitting devices, green light-emitting devices and blue light-emitting devices; In a direction perpendicular to the plane of the substrate, the points where the connecting line and the data line are coupled overlap with the red light-emitting device, or the points where the connecting line and the data line are coupled overlap with the blue light-emitting device.

19. The display panel according to claim 1, characterized in that, The display area includes a first display area and two second display areas; in the second direction, the two second display areas are respectively located on both sides of the first display area; the display area has an axis of symmetry extending in the first direction, and the axis of symmetry is located in the first display area; The data lines include multiple intermediate data lines and multiple edge data lines. The intermediate data lines are located in the first display area, and the edge data lines are located in the edge display area. The non-display area includes leads, and the intermediate data lines are coupled to the pads through the leads. At least a portion of the connecting line is located in the second display area, and the connecting line is coupled to the edge data line.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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