Semiconductor package structure and method of forming the same

Abstract

A semiconductor package structure and a method of forming the same. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a cap, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The cap is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the cap and the semiconductor device. A first recess is formed on a lower surface of the cap facing the semiconductor device, and the first recess overlaps the semiconductor device in a top-down view.

Description

Technical Field

[0001] This disclosure relates to a semiconductor packaging structure, and more particularly to a semiconductor packaging structure including a cover and a recess. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then patterning these material layers using photolithography and etching processes to form circuit components and elements. Many integrated circuits (ICs) are typically fabricated on a single semiconductor wafer, and the individual dies on the chip are singulated by sawing along scribe lines between the ICs. The individual dies are usually individually packaged, for example, in multi-chip modules or other types of packages.

[0003] Packaging (structure) not only protects semiconductor devices from environmental contamination but also provides an interface for the semiconductor devices encapsulated within. Smaller packaging structures with less area or lower height have been developed for packaging semiconductor devices.

[0004] While existing packaging structures and methods for manufacturing them are generally sufficient to meet their intended purpose, they are not entirely satisfactory in all respects. Summary of the Invention

[0005] This disclosure provides a semiconductor packaging structure according to several embodiments. The semiconductor packaging structure includes a carrier substrate, an interposer substrate, a semiconductor device, a cover, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The cover is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the cover and the semiconductor device. A first recess is formed on a lower surface of the cover facing the semiconductor device, and in a top view, the first recess overlaps with the semiconductor device.

[0006] Other embodiments of this disclosure provide a semiconductor package structure. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a cover, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate, wherein the interposer substrate is disposed between the carrier substrate and the semiconductor device. The cover is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the cover and the semiconductor device. A first recess is formed on a lower surface of the cover, and a portion of the thermal interface material is accommodated in the first recess.

[0007] Some embodiments of this disclosure also provide a method for forming a semiconductor package structure, including: providing a first semiconductor device on an interposer substrate; disposing the interposer substrate on a carrier substrate, wherein the interposer substrate is disposed between the carrier substrate and the first semiconductor device; providing a thermal interface material on the first semiconductor device; and providing a cover on the carrier substrate to cover the first semiconductor device, wherein the cover contacts the thermal interface material, the cover includes a lower surface facing the first semiconductor device, a first recess is formed on the lower surface of the cover, and a portion of the thermal interface material is accommodated in the first recess. Attached Figure Description

[0008] The form of this disclosure can be best understood from the following detailed description and the accompanying drawings. It should be emphasized that, in accordance with the general practice of the industry, the various features are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration.

[0009] Figures 1A to 1I This illustrates the manufacturing process of a semiconductor package structure according to some embodiments.

[0010] Figure 2A This is a top view of a semiconductor package structure according to some embodiments.

[0011] Figure 2B This is a top view of a semiconductor package structure according to some embodiments.

[0012] Figure 2C This is a top view of a semiconductor package structure according to some embodiments.

[0013] Figure 3A This is a cross-sectional view of a semiconductor package structure according to some embodiments.

[0014] Figure 3B This is a top view of a semiconductor package structure according to some embodiments.

[0015] Figure 4 This is a cross-sectional view of a semiconductor package structure according to some embodiments.

[0016] Figure 5A This is a cross-sectional view of the cover according to some embodiments.

[0017] Figure 5B This is a cross-sectional view of the cover according to some embodiments.

[0018] Figure 5C This is a cross-sectional view of the cover according to some embodiments.

[0019] Figure 6 This diagram shows a flowchart of a method for forming a semiconductor package structure according to some embodiments.

[0020] The attached figures are labeled as follows:

[0021] 10: Carrier substrate

[0022] 10A: Edge

[0023] 10B: Central Part

[0024] 10C: Lower surface

[0025] 11: Boundary

[0026] 12: Conductive structure

[0027] 14: Bottom filler layer

[0028] 20: Intermediate layer substrate

[0029] 20A: Middle section

[0030] 20B: Edge portion

[0031] 21: Parts

[0032] 22: Semiconductor devices

[0033] 22A: First point (first semiconductor device)

[0034] 22B: Second point (second semiconductor device)

[0035] 22C: Third Semiconductor Device

[0036] 22D: Semiconductor device

[0037] 23, 24: Conductive structure

[0038] 26: Bottom filler layer

[0039] 28: Molding layer

[0040] 30, 30A, 30B, 30C, 30D, 30E, 30F: Covers

[0041] 31: Next component

[0042] 32: Lower surface

[0043] 33: concave part

[0044] 33A: First recess

[0045] 33B: Second concave portion

[0046] 33C: The third concave part

[0047] 33D, 33E, 33F, 33G, 33H: concave part

[0048] 34, 34A, 34B: Bottom surface

[0049] 34C: Sidewall

[0050] 35: Top surface

[0051] 36: Inner surface

[0052] 40: Thermal interface materials

[0053] 100, 100A, 100B, 200A, 200B: Semiconductor package structure

[0054] 200: Method

[0055] 202,204,206,208,210,212: Steps

[0056] C: Centerline

[0057] D1, D2, D3, D4, D5, D6, D7, D8: Distance

[0058] DR1: First Direction

[0059] DR2: Second Direction

[0060] T1, T2: Thickness Detailed Implementation

[0061] The following disclosure provides numerous different embodiments or examples to implement various features of the invention. The following disclosure describes specific examples of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where additional features are formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of brevity and clarity and is not in itself intended to specify the relationship between the various embodiments and / or configurations discussed.

[0062] Furthermore, spatially related terms, such as "below," "below," "lower," "above," "above," and similar terms, are used to facilitate the description of the relationship between one element or feature and another element(s) in the accompanying drawings. In addition to the orientations shown in the drawings, these spatially related terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way.

[0063] The use of the term "substantially" in the specification, such as "substantially flat" or "substantially coplanar," is to be understood by those skilled in the art. In some embodiments, the adjective "substantially" may be removed. Where applicable, the term "substantially" may also include embodiments having "completely," "entirely," "all," etc. Where applicable, the term "substantially" may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, including 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" will be interpreted as not excluding insignificant deviations from the specified configuration and may include, for example, deviations up to 10°. The word "substantially" does not exclude "completely," for example, a composition "substantially free of" Y may be completely free of Y.

[0064] Terms such as “about” used in conjunction with a specific distance or size will be interpreted as not excluding insignificant deviations from the specific distance or size, and may include, for example, deviations of up to 10%. The term “about” related to the numerical value x may mean x ± 5 or 10%. The term “each” in the specification should be interpreted as not excluding variations between units and not excluding the omission of some units.

[0065] Embodiments will be described with reference to a specific context, namely packaging techniques for having an interposer substrate or other active chips in a two-dimensional half-integrated circuit (2.5DIC) structure or a three-dimensional integrated circuit (3DIC) structure. The embodiments discussed herein are intended to provide examples for implementing the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. Although the method embodiments discussed below may be performed in a specific order, other method embodiments are contemplated to have the steps performed in any logical order.

[0066] Embodiments of this disclosure relate to three-dimensional packaging or three-dimensional integrated circuit devices. Other features and processes may also be included. For example, test structures may be included to assist in verification testing of the three-dimensional package or three-dimensional integrated circuit device. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, allowing testing of the three-dimensional package or three-dimensional integrated circuit, the use of probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methodologies that combine intermediate verification of known good dies to improve yield and reduce costs.

[0067] A semiconductor package structure and a method of forming the same are provided according to various embodiments. Variations of the embodiments are discussed. Similar element symbols are used to denote similar elements in the various views and illustrative embodiments. According to some embodiments of this disclosure, a semiconductor package structure includes a cover element (stress relief structure), such as a cap structure, for controlling the warpage of a package substrate. In some embodiments, a recess is formed on the surface of the cap facing the semiconductor device. A thermal interface material is sandwiched or filled between the cap and the semiconductor device and in the recess of the cap. The recess of the cap prevents or reduces gaps between the cap and the semiconductor package structure and allows for better contact between the thermal interface material and the cap. Therefore, the reliability and heat dissipation of the semiconductor package structure are improved.

[0068] Figures 1A to 1I This illustrates the manufacturing process of a semiconductor package structure according to some embodiments. In some embodiments, such as... Figure 1A As shown, a semiconductor device 22 is disposed above an interposer substrate 20. In some embodiments, the interposer substrate 20 is supported by a first intermediate substrate. In some embodiments, the interposer substrate 20 includes a plate 21 and a plurality of conductive structures 23. The conductive structures 23 may be made of copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or combinations thereof, or may include the aforementioned materials. The plate 21 may be made of a polymer material, a ceramic material, a metallic material, a semiconductor material, one or more other suitable materials, or combinations thereof, or may include the aforementioned materials. For example, the plate 21 includes resin, prepreg, glass, and / or ceramic. When the plate 21 is made of a metallic or semiconductor material, a plurality of dielectric layers may be formed between the plate 21 and the conductive structures 23 to prevent short circuits.

[0069] When plate 21 is made of or includes a polymer material, plate 21 may also include filler dispersed in the polymer material. The polymer material may be made of or include an epoxy-based resin, a polyimide-based resin, one or more other suitable polymer materials, or a combination thereof. Examples of fillers may include optical fibers (e.g., silica optical fibers and / or carbon-containing optical fibers), particles (e.g., silica particles and / or carbon-containing particles), or a combination thereof.

[0070] In some embodiments, the semiconductor device 22 is a functional integrated circuit (IC) die, such as a semiconductor die, an electronic die, a micro-electro-mechanical systems (MEMS) die, or a combination thereof. The functional integrated circuit die may include one or more application processors, logic circuits, memory devices, power management integrated circuits, analog circuits, digital circuits, mixed-signal circuits, one or more other suitable functional integrated circuits, or a combination thereof, depending on the specific requirements. In some alternative embodiments, the semiconductor device 22 is a package module having one or more semiconductor dies and an interposer substrate carrying such semiconductor dies. Such structures of the semiconductor device 22 are well known in the art and will not be described herein. The semiconductor device 22 can be manufactured using various processes, such as deposition, etching, implantation, photolithography, annealing, and / or other suitable processes.

[0071] According to some embodiments of the present disclosure, in some embodiments, the semiconductor device 22 is bonded to a plurality of conductive structures 24. The conductive structures 24 may include conductive pillars, solder bumps, one or more other suitable bonding structures, or combinations thereof. According to some embodiments of the present disclosure, the conductive structures 24 are made of a solder material, such as tin and silver or another suitable conductive material (e.g., gold). According to some embodiments, the conductive structures 24 are solder balls. According to some embodiments of the present disclosure, a reflow process (not shown) may be performed to create a metallurgical connection between the semiconductor device 22, the conductive structures 24, and the interposer substrate 20.

[0072] In some embodiments, such as Figure 1B As shown, an underfill layer 26 is dispensed (e.g., via a dispenser (not shown)) into the space between each semiconductor device 22 and the interposer substrate 20, and into the space between adjacent conductive structures 24, and then cured (e.g., ultraviolet (UV) or thermal curing) to harden. According to some embodiments of this disclosure, the underfill layer 26 may be configured to provide strong mechanical connections and thermal bridges between the semiconductor device 22 and the interposer substrate 20, reducing cracking in the conductive structures 24 due to thermal expansion misalignment between the semiconductor device 22 and the interposer substrate 20, and protecting the connections from contamination, thereby improving the quality of the manufactured semiconductor package structure 100. Figure 1I The reliability of the bottom filler layer 26 is ensured. In some embodiments, the bottom filler layer 26 includes liquid epoxy resin, deformable colloid, silicone rubber, etc.

[0073] According to some embodiments, such as Figure 1CAs shown, a molding layer 28 is formed over the semiconductor device 22, the underfill layer 26, and the interposer substrate 20 to encapsulate the aforementioned components. According to some embodiments, the molding layer 28 fills the gaps between the semiconductor devices 22. According to some embodiments, the molding layer 28 surrounds the semiconductor device 22 within the gaps. According to some embodiments of this disclosure, the molding layer 28 may be configured to provide package rigidity, protective or hermetically sealed shielding, and / or provide a thermal path to prevent chip overheating. According to some embodiments of this disclosure, the molding layer 28 may be formed by spin coating, injection molding, or the like.

[0074] According to some embodiments, the molding layer 28 comprises a polymer material. Here, according to some embodiments, the term "polymer" may represent a thermosetting polymer, a thermoplastic polymer, or any mixture thereof. For example, the polymer material may include, for instance, plastic materials, epoxy resins, polyimides, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethyl methacrylate (PMMA), polymer components doped with specific fillers (including optical fibers, clay, ceramics, inorganic particles), or any combination thereof. According to some embodiments, in other embodiments, the molding layer 28 may be made of an epoxy resin, such as epoxy cresol novolac (ECN), biphenyl epoxy resin, multifunctional liquid epoxy resin, or any combination thereof. In further embodiments, the molding layer 28 may be made of an epoxy resin, selectively including one or more fillers to provide a composition having any desired properties. According to some embodiments, examples of fillers may be aluminum, titanium dioxide, carbon black, calcium carbonate, silicon dioxide, or any combination thereof. According to some embodiments of this disclosure, a heating process is performed on the molding layer 28 to cure the molding layer 28.

[0075] According to some embodiments, such as Figure 1D As shown, an upper portion of the molding layer 28 is removed to expose the top surface of the semiconductor device 22. According to some embodiments, after the removal process, the top surface of the molding layer 28 is substantially coplanar with or aligned with the top surface of the semiconductor device 22. According to some embodiments, the removal process includes chemical mechanical polishing (CMP) or other suitable polishing or etching processes.

[0076] like Figure 1EAs shown, a plurality of conductive structures 12 are provided on the interposer substrate 20. In some embodiments, the conductive structure 12 may include conductive pillars, solder bumps, one or more other suitable bonding structures, or combinations thereof. According to some embodiments, the conductive structure 12 is made of a solder material, such as tin and silver or another suitable conductive material (e.g., gold). According to some embodiments, the conductive structure 12 is a solder ball. In embodiments where the interposer substrate 20 is provided on a first intermediate substrate, a second substrate is provided on a molding layer 28, and then the first intermediate substrate is removed to allow the conductive structure 12 to be disposed on the interposer substrate 20.

[0077] like Figure 1F As shown, a cutting process is performed to cut the above structure into multiple pieces. In some embodiments, the sidewalls of the interposer substrate 20 are aligned with the sidewalls of the molding layer 28.

[0078] exist Figure 1G In this embodiment, the interposer substrate 20 is disposed on the carrier substrate 10 via the conductive structure 12. In some embodiments of this disclosure, the carrier substrate 10 includes an edge 10A and a central portion 10B surrounded by the edge 10A. In some embodiments, the carrier substrate 10 is a semiconductor substrate. For example, the material of the carrier substrate 10 may include elemental semiconductors such as silicon or germanium; composite semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide; or combinations thereof. Alternatively, the carrier substrate 10 may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some other embodiments, the carrier substrate 10 is a printed circuit board (PCB), a ceramic substrate, or another suitable packaging substrate. According to some embodiments, the carrier substrate 10 may be a core-based or coreless substrate. According to some embodiments of this disclosure, a reflow process (not shown) may be performed to create a metallurgical connection between the carrier substrate 10, the conductive structure 12, and the interposer substrate 20. In some embodiments, after the interlayer substrate 20 is disposed on the carrier substrate 10, the second intermediate substrate is removed.

[0079] In some embodiments of this disclosure, the carrier substrate 10 has various device elements (not shown). Examples of device elements formed on or in the carrier substrate 10 may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-passage and / or n-passage field-effect transistors (PFETs / NFETs), etc.), diodes, resistors, capacitors, inductors, and / or other suitable device elements. Various processes can be performed to form the device elements, such as deposition, etching, implantation, photolithography, annealing, and / or other suitable processes. The carrier substrate 10 may also have one or more circuit layers (not shown) for electrically connecting sequentially attached device elements and semiconductor devices.

[0080] In a top view, the carrier substrate 10 has a generally rectangular (or square) shape, depending on design requirements, but other shapes may also be used. Furthermore, the carrier substrate 10 has opposing surfaces, which may be substantially parallel to each other. The upper surface can be used to receive and integrate other package components. Several electrical connectors (not shown) may be provided on the lower surface to allow electrical connection between the carrier substrate 10 and an external electronic device, such as a printed circuit board (not shown). According to some embodiments of this disclosure, the electrical connectors may be or include solder balls, such as tin-containing solder balls.

[0081] In some embodiments, an underfill layer 14 is dispensed (e.g., via a dispenser (not shown)) into the space between the interposer substrate 20 and the carrier substrate 10, and into the space between adjacent conductive structures 12, and then cured (e.g., by ultraviolet (UV) or thermal curing) to harden. The underfill layer 14 may be configured to provide strong mechanical connections and thermal bridges between the interposer substrate 20 and the carrier substrate 10, reducing cracking in the conductive structures 12 due to thermal expansion misalignment between the interposer substrate 20 and the carrier substrate 10, and protecting the connections from contamination, thereby improving the quality of the manufactured semiconductor package structure 100. Figure 1I The reliability of the bottom filler layer 14 is ensured. In some embodiments, the bottom filler layer 14 includes liquid epoxy resin, deformable colloid, silicone rubber, etc.

[0082] According to some embodiments of this disclosure, such as Figure 1H As shown, a thermal interface material (TIM) 40 is provided on the semiconductor device 22 and the molding layer 28. In some embodiments, the thermal interface material 40 can be used to fill or reduce the gap between the semiconductor device 22 and the cover 30 (described later) to facilitate thermal conduction between the components.

[0083] In some embodiments, the thermal interface material 40 may have a higher thermal transfer coefficient than a typical adhesive material. In some embodiments, the thermal interface material 40 has a thermal transfer coefficient between about 3 W / mK and 8 W / mK, but its thermal transfer coefficient may also be slightly higher or slightly lower. The thermal interface material 40 may include organic materials and may also serve as an adhesive. In some embodiments, the thermal interface material 40 includes a polymer matrix, a phase change polymer, a polysiloxane-based substrate, substrate additives (fluxes), filler materials (a metal core containing an organic solderability retention coating), etc. According to some embodiments of this disclosure, the thermal interface material 40 may be dispensed in a high-viscosity liquid form.

[0084] According to some embodiments of this disclosure, in Figure 1H In this embodiment, a cover 30 is provided on the carrier substrate 10 to cover the semiconductor device 22, and the cover 30 contacts the thermal interface material 40. According to some embodiments of this disclosure, a next element 31 is provided between the carrier substrate 10 and the cover 30. The next element 31 can be configured to bond the cover 30 to the carrier substrate 10.

[0085] In some embodiments, the cover 30 is used to restrict the carrier substrate 10 to mitigate its warping and / or enhance the stability of the carrier substrate 10. In some embodiments, the material of the cover 30 may include metals, such as copper, stainless steel, stainless steel / nickel, etc., but is not limited thereto. In some embodiments, the cover 30 is used for heat dissipation, allowing the heat generated by the semiconductor device 22 to be released.

[0086] In some embodiments, the bonding element 31 may be applied to the carrier substrate 10 before being mounted onto the carrier substrate 10. Examples of materials for the bonding element 31 may include organic bonding materials, such as epoxy resin, polyimide (PI), polybenzoxazole (PBO), benzo-cyclo-butene (BCB), but are not limited thereto.

[0087] According to some embodiments of the present disclosure, a recess 33 is formed on the lower surface 32 of the cover 30, facing the semiconductor device 22. In some embodiments, the recess 33 can be formed by a mechanical drilling process using Computerized Numerical Control (CNC). In this embodiment, material is removed by mechanical drilling, wherein the drilling position is controlled by a computer or controller. Removal can also be achieved by other processes, such as laser cutting, laser drilling, etc. In some embodiments, the recess 33 has a bottom surface 34 facing the semiconductor device 22, and a thermal interface material 40 contacts the bottom surface 34 of the recess 33 and the semiconductor device 22 to fill the gaps between the components. According to some embodiments of the present disclosure, the recess 33 allows the lower surface of the cover 30 to more conform to the top surface of the package to reduce the bond line thickness (BLT) difference between the package center and corners. Therefore, according to some embodiments of the present disclosure, the heat dissipation capability and reliability of the semiconductor package structure 100 are enhanced.

[0088] In some embodiments, the central portion 10B is surrounded by an edge 10A. In some embodiments, a boundary 11 between the edge 10A and the central portion 10B is aligned with the inner surface 36 of the cover in a direction perpendicular to the top surface 35 of the cover 30.

[0089] According to some embodiments of this disclosure, such as Figure 1I As shown, a heating process is performed on a semiconductor package structure 100 used for packaging components. The various packaging components and substrate materials used in the semiconductor package structure 100 may have different coefficients of thermal expansion (CTEs). Therefore, when the package undergoes thermal cycling during packaging assembly, reliability testing, and field operation, the packaging components and substrate materials may expand at different rates, causing the carrier substrate 10 and interposer substrate 20 to tend to warp. Such deformation can cause the thermal interface material 40 at package corners or edges to peel off, affecting heat dissipation performance. In some embodiments of this disclosure, the above problem can be solved by forming recesses 33 on the cover 30.

[0090] In some embodiments of this disclosure, a distance D1 between the edge 10A of the carrier substrate 10 and the top surface 35 of the cover 30 is different from a distance D2 between the central portion 10B of the carrier substrate 10 and the top surface 35 of the cover 30. According to some embodiments of this disclosure, for example, the distance D1 between the edge 10A of the carrier substrate 10 and the top surface 35 of the cover 30 is greater than the distance D2 between the central portion 10B of the carrier substrate 10 and the top surface 35 of the cover 30. In some embodiments, the carrier substrate 10 includes a lower surface 10C that is recessed toward the cover 30 after a heating process.

[0091] In some embodiments of this disclosure, the semiconductor device 22 includes a first point 22A and a second point 22B, which are separate from each other. According to some embodiments of this disclosure, in a direction perpendicular to the top surface 35 of the cover 30, a distance D3 between the top surface 35 of the cover 30 and the first point 22A is different from a distance D4 between the top surface 35 of the cover 30 and the second point 22B. For example, in some embodiments, a centerline C passes through the center of the semiconductor package structure 100, the first point 22A is closer to the centerline C of the semiconductor package structure 100, and the second point 22B is farther away from the centerline C of the semiconductor package structure 100. Therefore, according to some embodiments of this disclosure, when the carrier substrate 10 and the interposer substrate 20 deform during a heating process, the first point 22A becomes closer to the top surface 35 of the cover 30, and the second point 22B becomes farther away from the top surface 35 of the cover 30. Therefore, according to some embodiments of this disclosure, the distance D3 between the first point 22A of the semiconductor device 22 and the top surface 35 of the cover 30 is less than the distance D4 between the second point 22B of the semiconductor device 22 and the top surface 35 of the cover 30. In some embodiments, the top surface 35 of the cover 30 and the top surface of the semiconductor device 22 face different directions.

[0092] In some embodiments, the interposer substrate 20 includes a central portion 20A and an edge portion 20B surrounding the central portion 20A. According to some embodiments of this disclosure, in a direction perpendicular to the top surface 35 of the cover member 30, a distance D5 is located between the top surface 35 of the cover member 30 and the edge portion 20B of the interposer substrate 20, and a distance D6 is located between the top surface 35 of the cover member 30 and the central portion 20A of the interposer substrate 20, and the distance D5 may be greater than the distance D6.

[0093] In some embodiments of this disclosure, the depth of the recess 33 of the cover 30 can be measured from a boundary point of the recess 33 to a bottom point of the recess 33 along a normal direction perpendicular to the top surface 35 of the cover 30. For example, the depth of the recess 33 of the cover 30 can be measured along a direction perpendicular to the top surface 35 of the cover 30 as the maximum thickness of the cover 30 minus the minimum thickness of the cover 30. For example, such as... Figure 1I As shown, the cover has a maximum thickness T1 (i.e., the maximum distance between the top surface 35 of the cover 30 and the thermal interface material 40) and a minimum thickness T2 (i.e., the minimum distance between the top surface 35 of the cover 30 and the thermal interface material 40). In some embodiments, the difference between thickness T1 and thickness T2 (i.e., thickness T1 - thickness T2) is between 0.02 mm and 0.1 mm. In other words, according to some embodiments of this disclosure, the depth of the recess 33 is between 0.02 mm and 0.1 mm.

[0094] Figure 2A A top view of a semiconductor package structure 100 according to some embodiments of the present disclosure. According to some embodiments, in... Figure 2A In this embodiment, two semiconductor devices 22 are housed in recesses 33 of the cover 30. In some embodiments, the area of ​​the recesses 33 is greater than the total area of ​​the semiconductor devices 22. According to some embodiments of this disclosure, the area of ​​the recesses 33 is smaller than the area of ​​the interposer substrate 20. According to some embodiments of this disclosure, this configuration reduces the gap between the cover 30 and the thermal interface material 40, thus allowing heat generated by the semiconductor devices 22 to dissipate more effectively.

[0095] Figure 2B This is a top view of a semiconductor package structure 100A according to some embodiments of the present disclosure. According to some embodiments of the present disclosure, the semiconductor package structure 100A includes a semiconductor device 22. In some embodiments, in a top view, the semiconductor device 22 is received in a recess 33 of a cover member 30A. In other words, in a top view, the area of ​​the semiconductor device is smaller than the area of ​​the recess 33. According to some embodiments of the present disclosure, in a top view of the semiconductor package structure 100A, the recess 33 of the cover member 30A is received in an interposer substrate 20. In some embodiments, the area of ​​the recess 33 is smaller than the area of ​​the interposer substrate 20. For example, the ratio of the area of ​​the recess 33 to the area of ​​the interposer substrate 20 is between 0.3 and 0.9, so that in a top view, the recess 33 is received within the interposer substrate 20.

[0096] Figure 2CThis is a top view of a semiconductor package structure 100B according to some embodiments of the present disclosure. In some embodiments, the semiconductor package structure 100B includes a first semiconductor device 22A, a second semiconductor device 22B, and a third semiconductor device 22C. According to some embodiments of the present disclosure, the cover 30B of the semiconductor package structure 100B includes a first recess 33A, a second recess 33B, and a third recess 33C, wherein the first recess 33A, the second recess 33B, and the third recess 33C are separated from each other.

[0097] In some embodiments, from a top-view perspective, the first semiconductor device 22A, the second semiconductor device 22B, and the third semiconductor device 22C are each located within a first recess 33A, a second recess 33B, and a third recess 33C, respectively. In some embodiments, the area of ​​the first semiconductor device 22A is smaller than the area of ​​the first recess 33A, the area of ​​the second semiconductor device 22B is smaller than the area of ​​the second recess 33B, and the area of ​​the third semiconductor device 22C is smaller than the area of ​​the third recess 33C. In some embodiments, the first recess 33A and the second recess 33B are arranged along a first direction DR1. In some embodiments, the first recess 33A and the third recess 33C are arranged along a first direction DR1. In some embodiments, the second recess 33B and the third recess 33C are arranged along a second direction DR2, wherein the first direction DR1 is different from the second direction DR2. For example, in some embodiments, the first direction DR1 is perpendicular to the second direction DR2. In some embodiments, the areas of the first recess 33A, the second recess 33B, and the third recess 33C are all different. In some embodiments, the depths of the first recess 33A, the second recess 33B, and the third recess 33C may be the same or different, depending on design requirements.

[0098] Figure 3A This is a cross-sectional view of a semiconductor package structure 200A according to some embodiments of the present disclosure. The semiconductor package structure 200A includes a cover member 30C. In some embodiments, the cover member 30C includes a recess 33D formed on a lower surface 32 of the cover member 30C, and the cover member 30C further includes a recess 33E formed in the recess 33D. In some embodiments, the depth of the recess 33D is less than the depth of the recess 33E. For example, such as Figure 3A As shown, a distance D7 between the bottom surface 34A of the recess 33D and the top surface of the semiconductor device 22D is smaller than a distance D8 between the bottom surface 34B of the recess 33E and the top surface of the semiconductor device 22D. In some embodiments, the recess 33D includes a sidewall 34C, and the thermal interface material 40 contacts the sidewall 34C.

[0099] Figure 3B A top view of a semiconductor package structure 200A according to some embodiments of this disclosure. Figure 3B As shown, the size of the semiconductor device 22D is smaller than the area of ​​the recess 33D, but larger than the area of ​​the recess 33E. In some embodiments, in a top view, the recess 33E is within the semiconductor device 22D, and the semiconductor device 22D is within the recess 33D.

[0100] Figure 4 A cross-sectional view of a semiconductor package structure 200B according to some embodiments of this disclosure. Figure 4 In some embodiments of this disclosure, the thermal interface material 40 of the semiconductor package structure 200B is separated from a portion of the sidewall 34C of the cover 30C. In some embodiments, a portion of the bottom surface 34A of the cover 30C is exposed from the thermal interface material 40.

[0101] According to some embodiments of this disclosure Figure 5A This is a cross-sectional view of the cover part, 30D. Figure 5B This is a cross-sectional view of cover part 30E. Figure 5C This is a cross-sectional view of cover 30F. In some embodiments, cover 30, cover 30A, cover 30B, and cover 30C may be replaced by cover 30D, cover 30E, or cover 30F, depending on design requirements. In some embodiments, such as Figure 5A As shown, the cover 30D has a recess 33F on its lower surface. In the cross-sectional view, the recess 33F has a curved concave shape. In some embodiments, such as Figure 5B As shown, the cover 30E has a recess 33G on its lower surface. In the cross-sectional view, the recess 33G has a beveled edge. In some embodiments, such as Figure 5C As shown, the cover 30F has a recess 33H on its lower surface. In the cross-sectional view, the recess 33H has rounded edges. According to some embodiments of this disclosure, various shapes of the recess enhance design flexibility.

[0102] Figure 6This diagram shows a flowchart of a method 200 for forming a semiconductor package structure according to some embodiments. Method 200 begins at step 202, wherein in some embodiments of this disclosure, a carrier substrate is provided. Method 200 continues to step 204, wherein in some embodiments of this disclosure, an interposer substrate is disposed on the carrier substrate. Method 200 continues to step 206, wherein in some embodiments of this disclosure, a semiconductor device is provided on the interposer substrate. Method 200 continues to step 208, wherein in some embodiments of this disclosure, a molding layer is provided to surround the semiconductor device. Method 200 continues to step 210, wherein in some embodiments of this disclosure, a thermal interface material is provided on the semiconductor device and the molding layer. Method 200 continues to step 212, wherein in some embodiments of this disclosure, a cover is provided over the thermal interface material and the carrier substrate. In some embodiments of this disclosure, the cover has a recess formed on a lower surface of the cover facing the semiconductor device, and a portion of the thermal interface material is accommodated in the recess.

[0103] In some embodiments of this disclosure, the semiconductor package structure includes a cover disposed on a semiconductor device and a recess formed on the lower surface of the cover facing the semiconductor device. This design enhances the heat dissipation and reliability of the semiconductor package structure after it has been heated and deformed during the manufacturing process.

[0104] This disclosure provides a semiconductor packaging structure according to several embodiments. The semiconductor packaging structure includes a carrier substrate, an interposer substrate, a semiconductor device, a cover, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The cover is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the cover and the semiconductor device. A first recess is formed on a lower surface of the cover facing the semiconductor device, and in a top view, the first recess overlaps with the semiconductor device.

[0105] In some embodiments, a distance between an edge of the carrier substrate and a top surface of the cover is greater than a distance between a central portion of the carrier substrate and the top surface of the cover. In some embodiments, the first recess has a concave shape, an oblique shape, or a rounded edge. In some embodiments, a second recess is formed on the lower surface, and the second recess is separate from the first recess. In some embodiments, the area of ​​the first recess is different from the area of ​​the second recess. In some embodiments, a third recess is formed on the lower surface, the first and second recesses are arranged in a first direction, the first and third recesses are arranged in a first direction, the second and third recesses are arranged in a second direction, and the first direction is different from the second direction. In some embodiments, a fourth recess is formed on a bottom surface of the first recess, and the distance between the bottom surface of the first recess and a top surface of the semiconductor device is less than the distance between the bottom surface of the fourth recess and the top surface of the semiconductor device. In some embodiments, the first recess includes a sidewall, and a thermal interface material is separated from a portion of the sidewall. In some embodiments, in a top view, the area of ​​the first recess is greater than the area of ​​the semiconductor device, and the area of ​​the fourth recess is smaller than the area of ​​the semiconductor device.

[0106] Other embodiments of this disclosure provide a semiconductor package structure. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a cover, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate, wherein the interposer substrate is disposed between the carrier substrate and the semiconductor device. The cover is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the cover and the semiconductor device. A first recess is formed on a lower surface of the cover, and a portion of the thermal interface material is accommodated in the first recess.

[0107] In some embodiments, in a top view, the area of ​​the first recess is smaller than the area of ​​the interposer substrate. In some embodiments, in a top view, the ratio of the area of ​​the first recess to the area of ​​the interposer substrate is between 0.3 and 0.9. In some embodiments, a second recess is formed on the lower surface of the cover, the second recess being separate from the first recess, and the areas of the first recess and the second recess are different. In some embodiments, the semiconductor device includes a first point and a second point, the first point and the second point being separate from each other, and the distance between the top surface of the cover and the first point is different from the distance between the top surface of the cover and the second point in a direction perpendicular to a top surface of the cover.

[0108] Some embodiments of this disclosure also provide a method for forming a semiconductor package structure, including: providing a first semiconductor device on an interposer substrate; disposing the interposer substrate on a carrier substrate, wherein the interposer substrate is disposed between the carrier substrate and the first semiconductor device; providing a thermal interface material on the first semiconductor device; and providing a cover on the carrier substrate to cover the first semiconductor device, wherein the cover contacts the thermal interface material, the cover includes a lower surface facing the first semiconductor device, a first recess is formed on the lower surface of the cover, and a portion of the thermal interface material is accommodated in the first recess.

[0109] In some embodiments, in a top view, a first semiconductor device is accommodated in a first recess. In some embodiments, the method of forming a semiconductor package structure further includes: providing a second semiconductor device on an interposer substrate; and forming a second recess on a lower surface of a cover member, wherein the first recess is separate from the second recess, and in a top view, the second semiconductor device is accommodated in the second recess. In some embodiments, the first recess includes a bottom surface, and the method of forming a semiconductor package structure further includes forming a third recess on the bottom surface of the first recess. In some embodiments, the method of forming a semiconductor package structure further includes performing a heating process on the semiconductor package structure, wherein a carrier substrate includes a lower surface, and after the heating process, the lower surface is recessed toward the cover member. In some embodiments, the cover member includes a top surface, the interposer substrate includes a middle portion and an edge portion, the edge portion surrounds the middle portion, and in a direction perpendicular to the top surface of the cover member, there is a first distance between the top surface of the cover member and the edge portion, and a second distance between the top surface of the cover member and the middle portion, and the first distance is greater than the second distance.

[0110] The foregoing outlines features of numerous embodiments to enable those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. A semiconductor package structure, comprising: A carrier substrate; An intermediate layer substrate is disposed on the carrier substrate; A semiconductor device is disposed on the interposer substrate; A cover is disposed on the carrier substrate to cover the semiconductor device; as well as A thermal interface material is disposed between the cover and the semiconductor device, wherein a first recess is formed on a lower surface of the cover facing the semiconductor device, and in a top view, the first recess overlaps with the semiconductor device, the first recess includes a sidewall, and the thermal interface material is separated from a portion of the sidewall. A fourth recess is formed on a bottom surface of the first recess, and the distance between the bottom surface of the first recess and a top surface of the semiconductor device is less than the distance between the bottom surface of the fourth recess and the top surface of the semiconductor device. From a top-down view, the fourth recess is within the semiconductor device, and the semiconductor device is within the first recess.

2. The semiconductor packaging structure of claim 1, wherein a distance between an edge of the carrier substrate and a top surface of the cover is greater than a distance between a central portion of the carrier substrate and the top surface of the cover.

3. The semiconductor packaging structure of claim 1, wherein the first recess has a concave shape, an oblique shape, or a rounded edge.

4. The semiconductor package structure of claim 1, wherein a second recess is formed on the lower surface and the second recess is separate from the first recess.

5. The semiconductor packaging structure of claim 4, wherein the area of ​​the first recess is different from the area of ​​the second recess.

6. The semiconductor package structure of claim 4, wherein a third recess is formed on the lower surface, the first recess and the second recess are arranged in a first direction, the first recess and the third recess are arranged in the first direction, the second recess and the third recess are arranged in a second direction, and the first direction is different from the second direction.

7. The semiconductor package structure of claim 3, wherein, in a top view, the area of ​​the first recess is larger than the area of ​​the semiconductor device, and the area of ​​the fourth recess is smaller than the area of ​​the semiconductor device.

8. A semiconductor package structure, comprising: A carrier substrate; An intermediate layer substrate is disposed on the carrier substrate; A semiconductor device is disposed on the interposer substrate, wherein the interposer substrate is disposed between the carrier substrate and the semiconductor device; A cover is disposed on the carrier substrate to cover the semiconductor device; as well as A thermal interface material is disposed between the cover and the semiconductor device, wherein a first recess is formed on a lower surface of the cover, and a portion of the thermal interface material is accommodated in the first recess, the first recess including a sidewall, and the thermal interface material is separated from a portion of the sidewall.

9. The semiconductor packaging structure of claim 8, wherein, in a top view, the area of ​​the first recess is smaller than the area of ​​the interposer substrate.

10. The semiconductor package structure of claim 9, wherein, in a top view, the ratio of the area of ​​the first recess to the area of ​​the interposer substrate is between 0.3 and 0.

9.

11. The semiconductor package structure of claim 8, wherein a second recess is formed on the lower surface of the cover, the second recess being separate from the first recess, and the area of ​​the first recess being different from the area of ​​the second recess.

12. The semiconductor package structure of claim 8, wherein the semiconductor device includes a first point and a second point, the first point and the second point being separate from each other, and the distance between the top surface of the cover and the first point being different from the distance between the top surface of the cover and the second point in a direction perpendicular to a top surface of the cover.

13. A method for forming a semiconductor package structure, comprising: A first semiconductor device is provided on an interlayer substrate; The intermediate layer substrate is disposed on a carrier substrate, wherein the intermediate layer substrate is disposed between the carrier substrate and the first semiconductor device; A thermal interface material is provided on the first semiconductor device; as well as A cover is provided on the carrier substrate to cover the first semiconductor device, wherein the cover contacts the thermal interface material, the cover includes a lower surface facing the first semiconductor device, a first recess is formed on the lower surface of the cover, and a portion of the thermal interface material is accommodated in the first recess, the first recess includes a sidewall, and the thermal interface material is separated from a portion of the sidewall.

14. The method of forming a semiconductor package structure as claimed in claim 13, wherein, in a top view, the first semiconductor device is accommodated in the first recess.

15. The method of forming a semiconductor package structure as described in claim 14, further comprising: A second semiconductor device is provided on the interposer substrate; as well as A second recess is formed on the lower surface of the cover, wherein the first recess is separate from the second recess, and the second semiconductor device is accommodated in the second recess in a top view.

16. The method of forming a semiconductor package structure as claimed in claim 13, wherein the first recess includes a bottom surface, and the method further includes forming a third recess on the bottom surface of the first recess.

17. The method of forming a semiconductor package structure as claimed in claim 13, further comprising performing a heating process on the semiconductor package structure, wherein the carrier substrate includes a lower surface that is recessed toward the cover after the heating process.

18. The method of forming a semiconductor package structure as claimed in claim 17, wherein the cover includes a top surface, the interposer substrate includes a middle portion and an edge portion, the edge portion surrounds the middle portion, and in a direction perpendicular to the top surface of the cover, the top surface of the cover and the edge portion have a first distance, the top surface of the cover and the middle portion have a second distance, and the first distance is greater than the second distance.

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