Display panel and display device

Abstract

The present invention discloses a display panel and a display device, belonging to the field of display technology. The display panel includes a substrate, a display area includes a plurality of first sub-pixels, and a first pixel circuit of the first sub-pixel includes at least a first type of dual-gate transistor, wherein the first gate of the first type of dual-gate transistor is connected to a first control line, and the second gate is connected to a second control line; the first control line and the second control line are arranged in different layers, and the film layer where the second control line is located is located on the side of the film layer where the first control line is located away from the substrate; the orthographic projection of the first control line corresponding to at least some of the first type of dual-gate transistors on the substrate overlaps at least partially with the orthographic projection of the second control line on the substrate; the display panel also includes a second detection line, and the second detection line has the same width as the second control line. The display device includes the above-mentioned display panel. The present invention can monitor the wiring width in real time, improve the monitoring accuracy, and is conducive to ensuring the display quality, and the monitoring method is simple and easy to operate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is one of the hot topics in the current research field of flat panel displays. Compared with liquid crystal displays, OLED has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. At present, in the field of flat panel displays such as mobile phones, PDAs, and digital cameras, OLED has begun to replace traditional liquid crystal displays (LCD). Among them, the design of the driving circuit is a key technology to realize the display function. The driving circuit can generally include a scanning driving circuit, a light control circuit, a data driving circuit, a pixel circuit, etc., among which the pixel circuit design is the core technical content of the OLED display and has important research significance. As a current driving device, the OLED display screen controls the luminous brightness of the pixel unit by controlling the current flowing into the OLED device in each pixel unit. In the production process of the OLED display screen, it is often necessary to make a pixel circuit on the substrate to provide driving current for the OLED device in each pixel unit.

[0003] To ensure the driving performance of pixel circuits, prior art requires monitoring the line widths of various film layers during the circuit fabrication process. This ensures that the signal lines meet the required line widths and achieve their signal transmission function. Current methods for monitoring line widths primarily utilize specialized machines. After completing the circuit fabrication of a film layer, a photograph of the line to be monitored is taken. Using the grayscale differences in the image, the machine automatically identifies the boundaries of the line width pattern, and the required line width information is obtained using the machine's selected measurement mode and algorithm.

[0004] However, with the development of display technology, pixel circuits are becoming more and more complex, with more film layer structures and more signal lines connected to them. It is often the case that multiple signal lines connected to the pixel circuits are overlapped between different film layers of the substrate. When there are no other signal lines overlapping above the signal line, it is relatively easy to automatically distinguish the boundaries of the line width graphics in the photographed photo through the machine; when there are other signal lines overlapping below a certain upper-layer signal line, the boundaries of the line width graphics of the upper-layer signal line in the photographed photo are easily interfered with by the boundaries of the signal lines of the lower layer, making it difficult to accurately identify the boundaries of the line width graphics of the upper-layer signal line, resulting in the difficulty in accurately measuring the line width of the upper layer. The line width changes of the signal lines in the pixel circuit are likely to affect the signal transmission effect, resulting in a decrease in the quality of the displayed image.

[0005] Therefore, providing a display panel and display device that can monitor the trace width in real time, improve monitoring accuracy, and help ensure display quality, and has a simple and easy-to-operate monitoring method, is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a display panel and a display device to solve the problems in the prior art of inaccurate line width monitoring of signal lines in display panels, which easily leads to a decrease in the quality of the displayed image, and the monitoring process is complex and difficult.

[0007] The present invention discloses a display panel, comprising: a display area and a non-display area; the display panel comprises a substrate, on which: the display area comprises a plurality of first sub-pixels, the first sub-pixels comprise an electrically connected first pixel circuit and a light-emitting element; the first pixel circuit comprises at least a first type of dual-gate transistor, the first gate of the first type of dual-gate transistor being connected to a first control line, and the second gate of the first type of dual-gate transistor being connected to a second control line; in the display area, the first control line and the second control line are arranged in different layers, and the film layer where the second control line is located is located on the side of the film layer where the first control line is located away from the substrate; the orthographic projections of the first control lines corresponding to at least some of the first type of dual-gate transistors on the substrate at least partially overlap with the orthographic projections of the second control lines on the substrate; the display panel further comprises a second detection line, and the second detection line has the same width as the second control line.

[0008] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-mentioned display panel.

[0009] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0010] The display area of ​​the display panel provided by the present invention may include a plurality of first sub-pixels. The first sub-pixels may be understood as sub-pixels used for display in the display panel. The first pixel circuit in the first sub-pixel includes at least a first-class dual-gate transistor. Compared with a single-gate transistor, the dual-gate transistor can effectively improve the carrier mobility of the first-class dual-gate transistor, which is beneficial to further improve the resolution of the display panel. The first pixel circuit in the present invention includes a first-class dual-gate transistor. By utilizing the characteristic of the higher mobility of the dual-gate transistor, its driving capability can be improved, making the first pixel circuit more suitable for large-size, high-resolution display panels. The first gate of the first-class dual-gate transistor in the present invention is connected to a first control line, and the second gate of the first-class dual-gate transistor is connected to a second control line, that is, the two gates of the same first-class dual-gate transistor are respectively fed with control signals by two control lines to realize the conduction or cutoff of the first-class dual-gate transistor. The display panel of the present invention also includes a second detection line. The second detection line has the same width as the second control line, so that the second detection line and the second control line have the same width. The line width of the second control line is obtained by monitoring the line width of the second detection line. Since the second detection line is located away from the area overlapping with the first control line, that is, there are no other interfering lines overlapping with the second detection line below the second detection line. Therefore, the machine can automatically distinguish the boundary of the line width pattern of the second detection line in the photograph of the substrate including the second detection line, and then accurately obtain the line width of the second detection line and synchronously obtain the line width of the second control line. The display panel provided by the present invention can monitor the width of the signal line in the display panel in real time through the provision of the second detection line. Not only is the monitoring method simple and easy to operate, but it can also improve monitoring accuracy, which is conducive to ensuring the display quality of the completed display panel.

[0011] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0012] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] Figure 1 is a schematic diagram of the planar structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 yes Figure 1 A schematic diagram of the electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel;

[0016] Figure 3 yes Figure 1 Schematic diagram of the local planar structure of the Q1 region on the substrate;

[0017] Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure along the A-A' direction;

[0018] Figure 5 yes Figure 1 A schematic diagram of another electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel;

[0019] Figure 6 yes Figure 1 A schematic diagram of another electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel;

[0020] Figure 7 yes Figure 1 A schematic diagram of another electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel;

[0021] Figure 8 yes Figure 1 A schematic diagram of another electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel;

[0022] Figure 9 yes Figure 1 A schematic diagram of another electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel;

[0023] Figure 10 yes Figure 9 Schematic diagram of the specific circuit connection structure;

[0024] Figure 11 yes Figure 10 A layout structure of a circuit connection structure produced on a substrate;

[0025] Figure 12 yes Figure 1 Schematic diagram of another local layout structure of the Q1 region on the substrate;

[0026] Figure 13 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0027] Figure 14 yes Figure 13 Schematic diagram of the local layout structure of the Q2 region on the substrate;

[0028] Figure 15 yes Figure 10 Another layout structure in which the circuit connection structure is made on a substrate;

[0029] Figure 16is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0030] Figure 17 yes Figure 16 Schematic diagram of the local layout structure of the Q3 area on the substrate;

[0031] Figure 18 yes Figure 10 Another layout structure in which the circuit connection structure is made on a substrate;

[0032] Figure 19 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0033] Figure 20 yes Figure 19 Schematic diagram of the local layout structure of the Q4 area on the substrate;

[0034] Figure 21 yes Figure 10 Another layout structure in which the circuit connection structure is made on a substrate;

[0035] Figure 22 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0036] Figure 23 yes Figure 22 Schematic diagram of the local layout structure of the Q5 area on the substrate;

[0037] Figure 24 yes Figure 10 Another layout structure in which the circuit connection structure is made on a substrate;

[0038] Figure 25 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0039] Figure 26 yes Figure 25 Schematic diagram of the local layout structure of the first sub-pixel on the substrate;

[0040] Figure 27 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate;

[0041] Figure 28 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate;

[0042] Figure 29 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate;

[0043] Figure 30 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate;

[0044] Figure 31 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate;

[0045] Figure 32 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate;

[0046] Figure 33 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0047] Figure 34 yes Figure 33 Schematic diagram of the layout structure in which the local structure is made on the substrate;

[0048] Figure 35 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0049] Figure 36 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0050] Figure 37 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0051] Figure 38 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0052] Figure 39 It is a schematic diagram of the planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention.

[0054] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0055] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0056] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0057] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0058] Please refer to Figures 1-4 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 yes Figure 1 A schematic diagram of the electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel, Figure 3 yes Figure 1 Schematic diagram of the local planar structure of the Q1 region on the substrate, Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along the A-A' direction (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 1 and Figure 3 The display panel 000 provided in this embodiment includes: a display area AA and a non-display area NA;

[0059] The display panel 000 includes a substrate 00 (not filled in the figure), on which:

[0060] The display area AA includes a plurality of first sub-pixels P, each of which includes an electrically connected first pixel circuit 10 and a light-emitting element 20. The first pixel circuit 10 includes at least a first-type dual-gate transistor T1, wherein a first gate T1G1 of the first-type dual-gate transistor T1 is connected to a first control line L1, and a second gate T1G2 of the first-type dual-gate transistor T1 is connected to a second control line L2. In the display area AA, the first control line L1 and the second control line L2 are arranged in different layers, and the film layer where the second control line L2 is located is located on a side of the film layer where the first control line L1 is located away from the substrate 00. The orthographic projections of the first control lines L1 corresponding to at least some of the first-type dual-gate transistors T1 on the substrate 00 at least partially overlap with the orthographic projections of the second control lines L2 on the substrate 00.

[0061] The display panel 000 further includes a second detection line J2 , and the second detection line J2 has the same width as the second control line L2 .

[0062] Specifically, the display panel 000 provided in this embodiment may be an organic light emitting diode (OLED) display panel. The display area AA of the display panel 000 may include a plurality of first sub-pixels P. The first sub-pixels P may be understood as sub-pixels used for display in the display panel 000. Optionally, the plurality of first sub-pixels P may include a plurality of different colors ( Figure 1 (represented by different filling patterns in the figure), such as at least including red sub-pixels, green sub-pixels, blue sub-pixels, and may also include white sub-pixels, etc.; a plurality of first sub-pixels P may be arranged in an array on the display panel 000, or may be arranged in other ways. In this embodiment, Figure 1 Only the arrangement of a plurality of first sub-pixels P in an array is used as an example for illustration. It can be understood that the embodiment of the present invention Figure 1 In the figure, a strip shape is used as an example in which the orthographic projection shape of a first sub-pixel P onto the light-emitting surface of the display panel 000 is shown. In a specific implementation, the shape of the first sub-pixel P includes but is not limited to this shape and can be designed according to actual needs.

[0063] like Figure 2 As shown, the first sub-pixel P of this embodiment includes an electrically connected first pixel circuit 10 and a light-emitting element 20. The first pixel circuit 10 and the light-emitting element 20 are both fabricated on a substrate 00, that is, the substrate 00 in this embodiment can be used as a carrier substrate of the display panel 000. The light-emitting element 20 in this embodiment can be an organic light-emitting diode (OLED), but is not limited to an organic light-emitting diode. It can also be a micro light-emitting diode, such as a Mini LED and a Micro LED. The first pixel circuit 10 in this embodiment is used to transmit a light-emitting driving current to the light-emitting element 20 under the action of a signal from a driving signal line (such as a first control line L1, a second control line L2, a scanning line, a data line, a voltage signal line, etc., not shown in the figure) on the display panel 000, thereby providing a driving current to the light-emitting element 20 to cause it to emit light.

[0064] The first pixel circuit 10 of this embodiment at least includes a first type of dual-gate transistor T1, such as Figure 4 As shown, compared with the single-gate transistor, the induced charge generated by the potentials of the first gate T1G1 and the second gate T1G2 of the first type of dual-gate transistor T1 is no longer limited to the bottom interface region or the top interface region of the active portion of the first type of dual-gate transistor T1. Figure 4As shown, the active portion of the first-type dual-gate transistor T1 can be understood as the active portion T1P located between the first gate T1G1 and the second gate T1G2. The material of the active portion T1P can be a semiconductor or a metal oxide, etc. This is not limited in this embodiment. Instead, the induced charge generated by the potentials of the first gate T1G1 and the second gate T1G2 of the first-type dual-gate transistor T1 can extend to the entire area of ​​the active portion in the thickness direction (because the first gate T1G1 and the second gate T1G2 overlap on both the upper and lower surfaces of the active portion). This can increase the carrier concentration in the first-type dual-gate transistor T1, thereby effectively improving the carrier mobility of the first-type dual-gate transistor T1, which is conducive to further improving the resolution of the display panel. In this embodiment, the first pixel circuit 10 includes the first-type dual-gate transistor T1. The higher mobility of the dual-gate transistor can be utilized to improve its driving capability. Therefore, the use of the first-type dual-gate transistor T1 in the first pixel circuit 10 can make the first pixel circuit 10 more suitable for large-size, high-resolution display panels.

[0065] Optional, such as Figure 3 and Figure 4 As shown, in this embodiment, an active layer 01 is provided between the film layer where the first control line L1 and the film layer where the second control line L2 are located. The active portion T1P of the first type dual-gate transistor T1 is located in the active layer 01. At least a portion of the orthographic projection of the first control line L1 on the substrate 00 overlaps with the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00, and at least a portion of the orthographic projection of the second control line L2 on the substrate 00 overlaps with the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00. This embodiment explains that during the manufacturing process of the display panel 000, an active layer 01 is further provided between the film layer where the first control line L1 and the film layer where the second control line L2 are located. The active layer 01 is insulated from both the film layer where the first control line L1 and the film layer where the second control line L2 are located. By patterning the active layer 01, the active portion T1P of the first type dual-gate transistor T1 can be located in the active layer 01, and at least a portion of the orthographic projection of the first control line L1 on the substrate 00 overlaps with the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00, and at least a portion of the orthographic projection of the second control line L2 on the substrate 00 overlaps with the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00. That is, the active portion T1P is provided between the first control line L1 and the second control line L2 in some areas, forming a dual-gate structure of the first type dual-gate transistor T1 including a bottom-gate first gate T1G1 and a top-gate second gate T1G2.

[0066] It is understandable that the Figure 2In the figure, only the structure of the first pixel circuit 10 other than the first type dual-gate transistor T1 is represented by a block diagram. This embodiment does not limit other specific structures in the first pixel circuit 10. During specific implementation, the first pixel circuit 10 includes but is not limited to the structure of this embodiment. The first pixel circuit 10 may also include other structures that can enable the light-emitting element 20 to emit light, such as a reset module, a driving module, a data signal writing module, a light-emitting module, etc. This embodiment will not be described in detail here. For details, please refer to the structure of the pixel circuit in the relevant technology for understanding.

[0067] It can be understood that the first pixel circuit 10 for providing a driving current to the light-emitting element 20 to drive it to emit light may include multiple transistors. The first type of dual-gate transistor T1 in this embodiment may be one or two or more of the multiple transistors included in the first pixel circuit 10. This embodiment does not specifically limit which module in the first pixel circuit 10 the first type of dual-gate transistor T1 is a transistor in. It only requires that the first pixel circuit 10 at least includes the first type of dual-gate transistor T1. For example, the reset module in the first pixel circuit 10 may include the first type of dual-gate transistor T1, or the driving module in the first pixel circuit 10 may include the first type of dual-gate transistor T1, or the threshold compensation module in the first pixel circuit 10 may include the first type of dual-gate transistor T1. This embodiment does not limit this.

[0068] In this embodiment, the first gate T1G1 of the first type dual-gate transistor T1 is connected to the first control line L1, and the second gate T1G2 of the first type dual-gate transistor T1 is connected to the second control line L2. Optionally, the first gate T1G1 and the first control line L1 can be arranged on the same layer and connected to each other, and the second gate T1G2 and the second control line L2 can be arranged on the same layer and connected to each other. That is, the two gates of the same first type dual-gate transistor T1 are respectively fed with control signals by two control lines. The first control signal can be fed to the first gate T1G1 via the first control line L1, and the second control signal can be fed to the second gate T1G2 via the second control line L2, thereby realizing the conduction or cutoff of the first type dual-gate transistor T1. The first control line L1 and the second control line L2 can be two of the multiple signal lines in the display panel 000. The first control line L1 and the second control line L2 are arranged in different layers in the display area AA, wherein the film layer where the second control line L2 is located is located on the side of the film layer where the first control line L1 is located away from the substrate 00, that is, the film layer where the first control line L1 is located is closer to the substrate 00 than the film layer where the second control line L2 is located. Among the first control line L1 and the second control line L2, the first control line L1 can be understood as the signal line of the lower layer, and the second control line L2 can be understood as the signal line of the upper layer. During the manufacturing process of the display panel 000, the first control line L1 is manufactured first and the second control line L2 is manufactured later. In this embodiment, the orthographic projections of the first control lines L1 corresponding to at least some of the first-type dual-gate transistors T1 on the substrate 00 are arranged to at least partially overlap with the orthographic projections of the second control lines L2 on the substrate 00, thereby reducing the space occupied by the first control lines L1 and the second control lines L2 in the display area AA, and avoiding the situation where the orthographic projections of all the first control lines L1 on the substrate 00 and the orthographic projections of the second control lines L2 on the substrate 00 do not overlap at all, occupying too much space in the display area AA and affecting the transmittance of the display panel 000.

[0069] In the manufacturing process of the display panel 000 of this embodiment, after the first control line L1 is produced on the substrate 00, the line width of the first control line L1 needs to be monitored to ensure the signal transmission effect of the first control line L1. This can not only avoid line breakage caused by a too small line width, but also avoid excessive load on the first control line L1 caused by an excessive line width that affects signal transmission. When monitoring the line width, if there is no other signal line overlapping with the first control line L1 and the substrate 00, the boundary of the line width pattern of the first control line L1 in the photograph of the substrate 00 including the first control line L1 can be automatically identified by the machine, thereby realizing line width monitoring of the first control line L1. After the second control line L2 is produced, since the orthographic projection of the first control line L1 on the substrate 00 and the orthographic projection of the second control line L2 on the substrate 00 at least partially overlap, that is, in the photograph of the substrate 00 including the first control line L1 and the second control line L2 taken by the machine, when distinguishing the boundary of the line width graphic, the boundary of the line width graphic of the second control line L2 is easily interfered with by the boundary of the line width graphic of the first control line L1, so it is difficult to accurately identify the boundary of the line width graphic of the second control line L2, resulting in the line width of the second control line L2 being difficult to accurately measure.

[0070] It should be noted that in this embodiment, the overall length extension direction of the first control line L1 is defined as the first length direction, and the line width of the first control line L1 can be understood as the width of the first control line L1 perpendicular to its first length direction. The overall length extension direction of the second control line L2 is defined as the second length direction, and the line width of the second control line L2 can be understood as the width of the second control line L2 perpendicular to its second length direction. Optionally, the first length direction of the first control line L1 and the second length direction of the second control line L2 are in the same direction, that is, in this embodiment, the overall extension directions of the first control line L1 and the second control line L2 are substantially the same, extending in the same direction.

[0071] In order to solve the above problem, the present embodiment sets the display panel 000 to further include a second detection line J2. The second detection line J2 has the same width as the second control line L2, so that the second detection line J2 and the second control line L2 can have the same width. The present embodiment does not specifically limit the setting position of the second detection line J2 in the display panel 000. Optionally, the second detection line J2 can be located in the display area AA or in the non-display area NA. When located in the display area AA, it can be set in any free space in the display area AA, or some floating signal lines in the display area AA can be reused as detection lines for monitoring line width. It is only necessary to meet the requirement that the second detection line J2 has the same width as the second control line L2. It can be understood that the present embodiment Figure 1The example in which the second inspection line J2 is located in the non-display area NA is used for illustration only. In specific implementations, the second inspection line J2 can be located elsewhere in the display panel 000. By providing a second inspection line J2 with the same width as the second control line L2 in the display panel 000, the width of the second control line L2 can be determined by monitoring the line width of the second inspection line J2. Since the second inspection line J2 is located away from the area where it overlaps with the first control line L1, i.e., there are no other interfering lines below the second inspection line J2 that overlap with the second inspection line J2, the machine can automatically identify the boundary of the line width pattern of the second inspection line J2 in a photograph of the substrate 00 including the second inspection line J2, thereby accurately determining the line width of the second inspection line J2 and simultaneously determining the line width of the second control line L2. The display panel 000 provided by this embodiment, through the provision of the second inspection line J2, can monitor the width of the signal lines in the display panel 000 in real time. This not only makes the monitoring method simple and easy to operate, but also improves monitoring accuracy, thereby facilitating the display quality of the completed display panel 000.

[0072] It is understood that this embodiment is merely an example of the connection structure included in the first pixel circuit 10. In specific implementations, the structure of the first pixel circuit 10 includes but is not limited to this. The first pixel circuit 10 may also include other electrically connected module structures for realizing the light emitting element 20 to emit light ( Figure 2 The first type of dual-gate transistor T1 is an N-type dual-gate transistor. In the embodiment, the first type of dual-gate transistor T1 can also be a P-type dual-gate transistor.

[0073] It should be noted that the structure of the display panel 000 of this embodiment includes but is not limited to the above-mentioned structure. During specific implementation, the display panel 000 may also include other structures that can realize the display function. This embodiment will not be described in detail here. For specific understanding, please refer to the structure of the organic light emitting diode display panel in the relevant technology.

[0074] Optional, please continue to combine reference Figures 1-4 In this embodiment, the second detection line J2 and the second control line L2 can be provided on the same layer ( Figure 3The same filling pattern is used to indicate the same film layer structure), that is, the second detection line J2 and the second control line L2 of the display area AA can not only have the same line width, but also the second detection line J2 and the second control line L2 of the required monitoring line width can be made of the same film layer, thereby avoiding the need to set up a separate film layer for making the second detection line J2 in the display panel, which is beneficial to reducing the overall thickness of the panel. At the same time, the second detection line J2 and the second control line L2 can be made with the same film layer, process and steps during the manufacturing process of the display panel 000, which is beneficial to improving the process efficiency.

[0075] Optional, such as Figure 1 and Figure 5 As shown, Figure 5 yes Figure 1 Another electrical connection structure diagram of the first pixel circuit and the light-emitting element in the first sub-pixel, the first pixel circuit 10 in this embodiment can also include a reset module 101, a driving transistor DT and a data writing module 102, the control end of the driving transistor DT can be electrically connected to the reset module 101, the first electrode of the driving transistor DT can be electrically connected to the data writing module 102, the second electrode of the driving transistor DT can be electrically connected to the anode of the light-emitting element 20, the driving transistor DT is used to generate a driving current in response to the voltage at its control end to drive the light-emitting element 20 to emit light, the data writing module 102 is used to write the data voltage signal to the control end of the driving transistor, and the reset module 101 is used to initialize the control end of the driving transistor DT before the light-emitting element 20 emits light. Figure 5 In the first pixel circuit 10 shown, the reset module 101 may include a first type of dual-gate transistor T1. Since the leakage current of the dual-gate transistor is much smaller than the leakage current of the single-gate transistor, the first type of dual-gate transistor T1 is used in the reset module 101. At the end of the reset phase, after the first type of dual-gate transistor T1 in the reset module 101 is turned off, the potential of the control end of the driving transistor DT can remain stable, thereby avoiding the luminous brightness of the light-emitting element 20 being affected by the decrease in the potential of the control end of the driving transistor DT, which is beneficial to improving the low grayscale color shift phenomenon.

[0076] Optionally, in this embodiment Figure 5 The example in the figure is only to illustrate that the driving transistor DT is a P-type low-temperature polysilicon transistor. In a specific implementation, the driving transistor DT includes but is not limited to a P-type low-temperature polysilicon transistor, and can also be other types of transistors. The driving transistor DT is a P-type low-temperature polysilicon transistor, so that the high mobility and high driving speed characteristics of the low-temperature polysilicon transistor can be utilized, so that when the data writing module 102 writes the data voltage signal, the driving transistor DT has a faster response speed, and the data voltage signal can be written quickly, avoiding the phenomenon of insufficient charging caused by the long opening time of the driving transistor DT. Optionally, as Figure 5As shown, the first type of dual-gate transistor T1 in the reset module 101 in this embodiment can be an N-type oxide transistor, such as an N-type IGZO (indium gallium zinc oxide) transistor, which is turned on when the first control line L1 inputs a high-level control signal to the first gate T1G1 and the second control line L2 inputs a high-level control signal to the second gate T1G2. Since the leakage current of the IGZO single-gate transistor is smaller than that of the low-temperature polysilicon transistor, when the reset module 101 is electrically connected to the control end of the driving transistor DT, the charge at the control end of the driving transistor DT can be prevented from leaking during low-frequency driving, effectively solving the leakage current problem during low-frequency driving. As a result, the design of the first pixel circuit 10 in this embodiment is also suitable for low-frequency driving, which is beneficial to reducing the power consumption of the display panel. Although the low leakage current characteristic of the IGZO single-gate transistor can effectively solve the leakage current problem during low-frequency driving, the IGZO single-gate transistor has a low mobility, while the organic light-emitting diode, as a current-driven device, requires a large mobility. Therefore, in this embodiment, the N-type IGZO single-gate transistor of the reset module 101 is designed as an N-type IGZO dual-gate transistor. The high mobility of the dual-gate transistor can be used to improve its own driving capability, thereby solving the leakage current problem during low-frequency driving and also using the high mobility characteristic of the dual-gate transistor to meet the high mobility requirement of the current-driven device.

[0077] Optionally, if other modules in this embodiment, such as the data writing module 102, include transistors, the transistors in these modules can still be designed as low-temperature polysilicon transistors. Thus, by using low-temperature polysilicon transistors, the pixel circuit can maintain a strong driving capability. It is only necessary to use IGZO dual-gate transistors in the leakage-prone portion of the first pixel circuit 10 (such as the portion connected to the control terminal of the drive transistor DT). The first pixel circuit 10 of this embodiment combines both low-temperature polysilicon and indium gallium zinc oxide thin-film transistors, enabling the display panel 000 using this first pixel circuit 10 to have both strong driving capability and low power consumption, making it suitable for both high-frequency and low-frequency displays.

[0078] It should be noted that this embodiment merely illustrates that the reset module 101 in the first pixel circuit 10 may include the first type dual-gate transistor T1 of this embodiment. Of the control lines to which the two gates of the first type dual-gate transistor T1 are connected, the line width of the upper second control line L2 can be monitored using the second detection line J2 in the above embodiment. In specific implementations, dual-gate transistors may also be used in other modules of the first pixel circuit 10, and this embodiment does not limit this.

[0079] It is understood that the electrical connection between the structures in this embodiment can be understood as a variety of ways to achieve electrical connection between the two. For example, if no other structure is included between the two structures, a direct connection can achieve electrical connection. If other structures are included between the two structures, electrical connection can also be achieved by providing other conductive structures between the two structures. This embodiment does not limit the specific configuration structure of the electrical connection. During specific implementation, it can be understood based on the actual design structure of the pixel circuit. For example, in this embodiment, the second electrode of the driving transistor is electrically connected to the anode of the light-emitting element 20. It can also be understood that the first pixel circuit 10 can also include a light-emitting control transistor connected to the anode of the light-emitting element 20. In this case, when the light-emitting control transistor is turned on, the second electrode of the driving transistor can also be electrically connected to the anode of the light-emitting element 20.

[0080] In some optional embodiments, please refer to Figure 1 and Figure 6 , Figure 6 yes Figure 1 Another electrical connection structure diagram of the first pixel circuit and the light-emitting element in the first sub-pixel in FIG. 1 is shown. In this embodiment, the first pixel circuit 10 includes an electrically connected driving transistor DT, a data writing module 102, a compensation module 103, a first light-emitting control module 104, a second light-emitting control module 105, a first reset module 101 (i.e. Figure 5 a reset module connected to the control terminal of the driving transistor DT) and a second reset module 106;

[0081] A first terminal of the first light emitting control module 104 is connected to the first power signal Vpvdd, and a second terminal of the first light emitting control module 104 is connected to the first electrode of the driving transistor DT;

[0082] A first terminal of the data writing module 102 is connected to the data voltage signal Vdata, and a second terminal of the data writing module 102 is connected to the first electrode of the driving transistor DT;

[0083] A first terminal of the compensation module 103 is connected to the gate of the driving transistor DT (ie, the control terminal of the driving transistor DT), and a second terminal of the compensation module 103 is connected to the second electrode of the driving transistor DT;

[0084] A first terminal of the first reset module 101 is connected to the first reset signal Vref1 , and a second terminal of the first reset module 101 is connected to the gate of the driving transistor DT;

[0085] A first terminal of the second reset module 106 is connected to the second reset signal Vref2 , and a second terminal of the second reset module 106 is connected to the anode of the light emitting element 20 ;

[0086] The first end of the second light emitting control module 105 is connected to the second electrode of the driving transistor DT, the second end of the second light emitting control module 105 is connected to the anode of the light emitting element 20, and the cathode of the light emitting element 20 is connected to the second power signal Vpvee

[0087] This embodiment illustrates that the first pixel circuit 10 includes a driving transistor DT, a data writing module 102, and a first reset module 101, and further includes an electrically connected compensation module 103, a first light-emitting control module 104, a second light-emitting control module 105, and a second reset module 106. The first light-emitting control module 104 is connected in series between the first power supply signal Vpvdd and the first electrode of the driving transistor DT, and the second light-emitting control module 105 is connected in series between the anode of the light-emitting element 20 and the second electrode of the driving transistor DT. The first light-emitting control module 104 and the second light-emitting control module 105 are configured to provide light-emitting control signals to the light-emitting element 20 during the light-emitting phase of the light-emitting element 20. Optionally, the first light-emitting control module 104 and the second light-emitting control module 105 of this embodiment may also be connected to a first light-emitting control signal EM1 and a second light-emitting control signal EM2, respectively, to control whether the light-emitting control modules are turned on or off. Specifically, the first terminal of the first light-emitting control module 104 can be connected to the first power signal Vpvdd. When the first light-emitting control signal EM1 is an active signal, turning on the first light-emitting control module 104, the first power signal Vpvdd is transmitted to the first terminal of the driving transistor DT. Furthermore, optionally, the first light-emitting control signal EM1 can be connected to a first light-emitting control signal line (not shown) in the display panel 000, and the second light-emitting control signal EM2 can be connected to a second light-emitting control signal line (not shown) in the display panel 000. A first terminal of the second light-emitting control module 105 is connected to the second terminal of the driving transistor DT, and a second terminal of the second light-emitting control module 105 is connected to the anode of the light-emitting element 20. When the second light-emitting control signal EM2 is an active signal, turning on the second light-emitting control module 105, the driving current generated by the driving transistor DT can drive the light-emitting element 20 to emit light. The other terminal of the second light-emitting control module 105 is connected to the anode of the light-emitting element 20, thereby establishing a path between the first power signal Vpvdd, the first light-emitting control module 104, the driving transistor DT, the second light-emitting control module 105, the light-emitting element 20, and the second power signal Vpvee.

[0088] In this embodiment, the first light emitting control signal EM1 and the second light emitting control signal EM2 are controlled so that the first light emitting control module 104 and the second light emitting control module 105 can be turned on during the light emitting phase of the light emitting element 20, providing a current path for the light emitting element 20 so that the light emitting element 20 emits light. In other phases (such as a reset phase or a data writing phase), the first light emitting control module 104 and the second light emitting control module 105 are controlled to be turned off to prevent the light emitting element 20 from accidentally emitting light during the non-light emitting phase. Optionally, Figure 6 As shown, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be connected together to provide the light-emitting control signals of the two light-emitting control modules by the same light-emitting control signal line, that is, the first light-emitting control module 104 and the second light-emitting control module 105 can receive the same light-emitting control signal EM, and the first light-emitting control signal EM1 used to turn on the first light-emitting control module 104 and the second light-emitting control signal EM2 used to turn on the second light-emitting control module 105 can be shared, which is beneficial to reducing the number of signal lines in the display panel 000 using the first pixel circuit 10, improving the transmittance of the display panel or increasing the wiring space of the display panel.

[0089] The first end of the compensation module 103 of this embodiment is connected to the gate of the driving transistor DT (the first node N1), and the second end of the compensation module 103 is connected to the second electrode of the driving transistor DT. The compensation module 103 is used to compensate for the threshold voltage of the driving transistor DT. When the compensation module 103 is in the on state, the gate and the second electrode of the driving transistor DT can be short-circuited, and a voltage difference is generated between the gate and the first electrode of the driving transistor DT through the threshold voltage of the driving transistor DT. At this time, the driving transistor DT is turned on, and the data writing module 102 inputs the data voltage signal Vdata to the second node N2. The data voltage signal Vdata includes the threshold voltage to be compensated and is transmitted to the gate of the driving transistor DT, thereby compensating for the threshold voltage deviation of the driving transistor DT.

[0090] In this embodiment, a first terminal of the first reset module 101 is connected to a first reset signal Vref1, and a second terminal of the first reset module 101 is connected to the gate of the driving transistor DT. The first reset module 101 is configured to reset the gate of the driving transistor DT. Optionally, the first reset signal Vref1 may be provided by a first reference voltage signal line in the display panel 000. When in the on state, the first reset module 101 may connect the first reset signal Vref1 to the gate of the driving transistor DT, and utilize its low-level potential to reset the gate of the driving transistor DT, thereby facilitating the conduction of the driving transistor DT after the reset operation is completed.

[0091] In this embodiment, a first end of the second reset module 106 is connected to the second reset signal Vref2, and a second end of the second reset module 106 is connected to the anode of the light-emitting element 20, so as to provide the second reset signal Vref2 to the light-emitting element 20 when the second reset module 106 is turned on. Optionally, the second reset signal Vref2 can be provided by the second reference voltage signal line in the display panel 000. The second reset signal Vref2 can use its low-level potential to reset the anode of the light-emitting element 20, so that the anode of the light-emitting element 20 is initialized, thereby improving the residual of the data signal of the previous frame, improving the afterimage phenomenon, and enhancing the display effect of the display panel.

[0092] It is understandable that the Figure 6 The first reset module 101, the data writing module 102, the first light-emitting control module 104, the second light-emitting control module 105, the compensation module 103, and the second reset module 106 are all illustrated in block diagrams, but do not represent their actual structures. During specific implementation, the connection structure of the first reset module 101, the data writing module 102, the first light-emitting control module 104, the second light-emitting control module 105, the compensation module 103, and the second reset module 106 itself may include an electrically connected structure such as a transistor. The conduction of the transistor in each module is controlled by an enable signal of the transistor gate to achieve connectivity between the module and the driving transistor DT. This embodiment does not limit the specific internal electrical connection structure of each module. During specific implementation, reference may also be made to the light-emitting control module and the compensation module of the pixel circuit in the related art for understanding, which will not be elaborated in this embodiment.

[0093] Optional, such as Figure 1 、 Figure 7 、 Figure 8 and Figure 9 As shown, Figure 7 yes Figure 1 A schematic diagram of another electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel, Figure 8 yes Figure 1 A schematic diagram of another electrical connection structure between the first pixel circuit and the light-emitting element in the first sub-pixel, Figure 9 yes Figure 1 Another electrical connection structure diagram of the first pixel circuit and the light emitting element in the first sub-pixel is shown in FIG. Figure 7 As shown, the first reset module 101 includes a first type of dual-gate transistor T1; or Figure 8 As shown, the compensation module 103 includes a first type of dual-gate transistor T1; or Figure 9As shown, the compensation module 103 and the first reset module 101 both include a first-type dual-gate transistor T1. At this time, the two gates of the first-type dual-gate transistor T1 in the first reset module 101 can be connected to the first control line L1 and the second control line L2. The two gates of the first-type dual-gate transistor T1 in the compensation module 103 can be connected to the third control line L3 and the fourth control line L4. The setting structure and the method of monitoring the line width of the third control line L3 and the fourth control line L4 can be the same as those of the first control line L1 and the second control line L2, and are not described in detail in this embodiment.

[0094] This embodiment explains that the first reset module 101 and / or the compensation module 103 connected to the gate of the driving transistor DT may include a first-type dual-gate transistor T1. Since the leakage current of the dual-gate transistor is much smaller than the leakage current of the single-gate transistor, the first-type dual-gate transistor T1 is used in the first reset module 101. At the end of the reset phase, after the first-type dual-gate transistor T1 in the first reset module 101 is turned off, the potential of the gate of the driving transistor DT can remain stable, thereby avoiding the luminance of the light-emitting element 20 being affected by the decrease in the gate potential of the driving transistor DT, thereby facilitating improvement of the low-grayscale color shift phenomenon. During the light-emitting stage, there are two paths for the gate of the driving transistor DT to leak electricity. One leakage path is through the first reset module 101, and the other leakage path is through the compensation module 103. Since the first reset module 101 uses the first type of dual-gate transistor T1, and / or the compensation module 103 uses the first type of dual-gate transistor T1, its leakage current is relatively small. Therefore, the leakage of the driving transistor DT can be effectively reduced, and the potential of the gate of the driving transistor DT can be kept stable, so that the driving current generated by the driving transistor DT will not vary within a large range, thereby improving the problem of brightness and color deviation when the light-emitting element 20 emits light.

[0095] It is understandable that this embodiment does not limit the placement position of the first type dual-gate transistor T1 in the first pixel circuit 10. Figure 7-Figure 9 Only the first reset module 101 includes the first type of dual-gate transistor T1, and / or the compensation module 103 includes the first type of dual-gate transistor T1. In specific implementation, the first pixel circuit 10 may further include other modules connected to the gate of the driving transistor DT. In this embodiment, the other modules connected to the gate of the driving transistor DT may also include the first type of dual-gate transistor T1, which is beneficial to improving the display quality of the display panel.

[0096] In some optional embodiments, please refer to Figure 1 、 Figure 9 、 Figure 10 and Figure 11 , Figure 10 yes Figure 9 Schematic diagram of the specific circuit connection structure, Figure 11 yes Figure 10 The circuit connection structure is made on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 11 Transparency is filled), in this embodiment, the first light control module 104 includes a first transistor T01, a gate of the first transistor T01 is connected to the first light control signal EM1, a first electrode of the first transistor T01 is connected to the first power supply signal Vpvdd, and a second electrode of the first transistor T01 is connected to the first electrode of the driving transistor DT;

[0097] The data writing module 102 includes a second transistor T02, a gate of the second transistor T02 is connected to the first scanning signal SP1, a first electrode of the second transistor T02 is connected to the data voltage signal Vdata, and a second electrode of the second transistor T02 is connected to the first electrode of the driving transistor DT;

[0098] The compensation module 103 includes a third transistor T03, which is a first-type dual-gate transistor T1. A first gate T03G1 of the third transistor T03 is connected to the second scan signal SN2, a second gate T03G2 of the third transistor T03 is connected to the second scan signal SN2, a first electrode of the third transistor T03 is connected to the gate of the driving transistor DT, and a second electrode of the third transistor T03 is connected to the second electrode of the driving transistor DT. The first gate T03G1 of the third transistor T03 can be connected to a third control line L3 to provide the second scan signal SN2, and the second gate T03G2 of the third transistor T03 can be connected to a fourth control line L4 to provide the second scan signal SN2.

[0099] The first reset module 101 includes a fourth transistor T04, which is a first-type dual-gate transistor T1. A first gate T04G1 of the fourth transistor T04 is connected to the third scan signal SN3, a second gate T04G2 of the fourth transistor T04 is connected to the third scan signal SN3, a first electrode of the fourth transistor T04 is connected to the first reset signal Vref1, and a second electrode of the fourth transistor T04 is connected to the gate of the driving transistor DT. The first gate T04G1 of the fourth transistor T04 can be connected to the first control line L1 to input the third scan signal SN3, and the second gate T04G2 of the fourth transistor T04 can be connected to the second control line L2 to input the third scan signal SN3.

[0100] The second light emitting control module 105 includes a fifth transistor T05, a gate of the fifth transistor T05 is connected to the second light emitting control signal EM2, a first electrode of the fifth transistor T05 is connected to the second electrode of the driving transistor DT, and a second electrode of the fifth transistor T05 is connected to the anode of the light emitting element 20;

[0101] The second reset module 106 includes a sixth transistor T06 , a gate of which is connected to the fourth scan signal SP4 , a first electrode of which is connected to the second electrode of the driving transistor DT, and a second electrode of which is connected to the anode of the light emitting element 20 .

[0102] This embodiment explains that the data writing module 102 includes a second transistor T02, the gate of which is connected to a first scan signal SP1, which can be connected to a first scan signal line in the display panel. The first electrode of the second transistor T02 is connected to the data voltage signal Vdata, and the second electrode of the second transistor T02 is connected to the first electrode of the driving transistor DT. The first scan signal SP1 controls the conduction and cutoff of the second transistor T02 to enable the data voltage signal Vdata to be written. The second reset module 106 includes a sixth transistor T06, the gate of which is connected to a fourth scan signal SP4. The gates of the second transistor T02 and the sixth transistor T06 can be connected to a common scan signal line, that is, the fourth scan signal SP4 and the first scan signal SP1 can be connected to the same first scan signal line in the display panel. The first electrode of the sixth transistor T06 is connected to the second electrode of the driving transistor DT, and the second electrode of the sixth transistor T06 is connected to the anode of the light-emitting element 20. The fourth scan signal SP4 controls the conduction and cutoff of the sixth transistor T06, providing a second reset signal Vref2 to the anode of the light-emitting element 20 to initialize the anode of the light-emitting element 20. The first light-emitting control module 104 includes a first transistor T01, a gate of the first transistor T01 is connected to a first light-emitting control signal EM1, a first electrode of the first transistor T01 is connected to a first power supply signal Vpvdd, and a second electrode of the first transistor T01 is connected to a first electrode of a driving transistor DT; the second light-emitting control module 105 includes a fifth transistor T05, a gate of the fifth transistor T05 is connected to a second light-emitting control signal EM2, a first electrode of the fifth transistor T05 is connected to a second electrode of the driving transistor DT, and a second electrode of the fifth transistor T05 is connected to an anode of the light-emitting element 20; the gate of the first transistor T01 and the gate of the fifth transistor T05 can be connected to the same light-emitting control signal EM. Optionally, the gate of the first transistor T01 and the gate of the fifth transistor T05 can be connected to the same light-emitting control signal line in the display panel, that is, when the gate of the first transistor T01 and the gate of the fifth transistor T05 jointly respond to the light-emitting control signal EM, the first transistor T01 and the fifth transistor T05 are in an on state, and a path is formed between the first power supply signal Vpvdd, the driving transistor DT, the light-emitting element 20, and the second power supply signal Vpvee. The compensation module 103 includes a third transistor T03 . The third transistor T03 is a first-type dual-gate transistor T1 , and has a relatively small leakage current. Therefore, the potential of the gate of the driving transistor DT connected thereto can be kept stable.The third transistor T03 is turned on or off under the control of the second scan signal SN2. The second scan signal SN2 can be input from two control lines. When the third transistor T03 is turned on, it can short-circuit the gate and the second electrode of the driving transistor DT. The threshold voltage of the driving transistor DT generates a voltage difference between the gate and the first electrode of the driving transistor DT. At this time, the driving transistor DT is turned on, and the second transistor T02 is turned on and inputs the data voltage signal Vdata to the second node N2. This data voltage signal Vdata includes the threshold voltage to be compensated and is transmitted to the gate of the driving transistor DT, thereby compensating for the threshold voltage deviation of the driving transistor DT. The first gate T03G1 of the third transistor T03 can be connected to the third control line L3 to provide the second scan signal SN2. The second gate T03G2 of the third transistor T03 can be connected to the fourth control line L4 to provide the second scan signal SN2. The configuration structure and line width monitoring method of the third control line L3 and the fourth control line L4 can be the same as those of the first control line L1 and the second control line L2 in the above embodiment. The first reset module 101 includes a fourth transistor T04. The fourth transistor T04 is a first-class dual-gate transistor T1 with a low leakage current, thereby maintaining a stable potential at the gate of the drive transistor DT connected thereto. The fourth transistor T04 is turned on or off under the control of a third scan signal SN3. The third scan signal SN3 can be input via two control lines. When the fourth transistor T04 is turned on, the gate of the drive transistor DT can be reset. In this embodiment, the first gate T04G1 of the fourth transistor T04 can be connected to the first control line L1 to receive the third scan signal SN3, and the second gate T04G2 of the fourth transistor T04 can be connected to the second control line L2 to receive the third scan signal SN3. For details, please refer to the configuration structure of the first control line L1 and the second control line L2 and the method for monitoring the line width in the above-mentioned embodiment, which will not be described in detail in this embodiment.

[0103] In this embodiment, the compensation module 103 includes a third transistor T03, which is a first-type dual-gate transistor T1. The first reset module 101 includes a fourth transistor T04, which is a first-type dual-gate transistor T1. Since the dual-gate transistor has a small leakage current, it can improve the instability of the gate potential of the driving transistor DT, avoid the low grayscale color shift of the light-emitting element 20 due to insufficient light emission, and is conducive to improving the display effect.

[0104] The layout of the first pixel circuit 10 is as follows: Figure 11For example, the first control line L1 and the second control line L2 providing the third scan signal SN3 at least partially overlap in a direction perpendicular to the plane of the substrate 00. In this case, in order to monitor the line width of the second control line L2, a second detection line J2 can be set in a vacant position in the display area AA or in the non-display area NA of the display panel 000. The second detection line J2 and the second control line L2 are in the same layer and have the same width. That is, the second detection line J2 and the second control line L2 of the required monitored line width are manufactured using the same film layer, the same process, and the same steps, so that the second detection line J2 and the second control line L2 are in the same layer and have the same width. The width of the second control line L2 is obtained by monitoring the line width of the second inspection line J2. Since the second inspection line J2 is located away from the area where it overlaps with the first control line L1, that is, there are no other interfering lines below the second inspection line J2 that overlap with the second inspection line J2. Therefore, the machine can automatically identify the boundary of the line width pattern of the second inspection line J2 in the photograph of the substrate 00 including the second inspection line J2, and thus accurately obtain the line width of the second inspection line J2. If the second inspection line J2 and the second control line L2 are on the same layer and have the same width, the line width of the second control line L2 can be obtained synchronously. The display panel 000 provided in this embodiment can monitor the width of the signal lines in the display panel 000 in real time by setting the second inspection line J2. Not only is the monitoring method simple and easy to operate, but it also improves monitoring accuracy, which helps to ensure the display quality of the completed display panel 000.

[0105] It is understandable that the Figure 10 and Figure 11 In the description, the first transistor T01 , the second transistor T02 , the fifth transistor T05 , the sixth transistor T06 , and the driving transistor DT are P-type low-temperature polysilicon transistors, and the third transistor T03 and the fourth transistor T04 are N-type oxide double-gate transistors.

[0106] Optionally, the first pixel circuit 10 in this embodiment further includes a storage capacitor Cst. A first electrode of the storage capacitor Cst is connected to the gate of the driving transistor DT (the first node N1), and a second electrode of the storage capacitor Cst is connected to the first power signal Vpvdd. In this embodiment, the first electrode of the storage capacitor Cst is connected to the gate of the driving transistor DT via the first node N1, and the second electrode of the storage capacitor Cst is connected to the first power signal Vpvdd. The storage capacitor Cst is configured to store the data voltage signal Vdata after it is transmitted to the first node N1, thereby facilitating stability of the entire circuit.

[0107] In some optional embodiments, please continue to refer to Figure 1 、 Figures 9-11 In this embodiment, the first pixel circuit 10 further includes a plurality of thin film transistors, such as Figure 10 and Figure 11The first transistor T01, the second transistor T02, the fifth transistor T05, the sixth transistor T06, and the driving transistor DT are shown in FIG. 3 , and the thin film transistors are P-type low temperature polysilicon transistors, such as Figure 10 and Figure 11 The third transistor T03 and the fourth transistor T04 shown in FIG are first-type dual-gate transistors T1, and the first-type dual-gate transistor T1 is an N-type oxide transistor;

[0108] The display panel 000 includes at least a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 stacked in sequence on one side of the substrate 00; optionally, an insulating layer ( Figure 11 not shown);

[0109] Thin film transistors (such as Figure 10 and Figure 11 The gates of the first transistor T01, the second transistor T02, the fifth transistor T05, the sixth transistor T06, and the driving transistor DT) are located in the first metal layer M1. Optionally, the material of the first metal layer M1 can be a metal molybdenum (Mo) material. The first control line L1 and the first gate T1G1 of the first type dual-gate transistor T1 are located in the second metal layer M2. The third control line L3 can also be located in the second metal layer M2. Optionally, the material of the second metal layer M2 can be the same as that of the first metal layer M1, both of which are metal molybdenum (Mo) materials. The second control line L2 and the first The second gate T1G2 of the quasi-dual-gate transistor T1 is located in the third metal layer M3, the second detection line J2 can be located in the third metal layer M3, and the fourth control line L4 can also be located in the third metal layer M3. Optionally, the manufacturing material of the third metal layer M3 can be a composite material of metal titanium (Ti) and metal molybdenum (Mo). Since when the first type of dual-gate transistor T1 is an N-type oxide transistor, the oxide transistor is sensitive to hydrogen ions, and hydrogen ions will affect the electrical performance, metal titanium is added to the third metal layer M3. Metal titanium is more dense and is conducive to blocking hydrogen ions, playing a role in shielding hydrogen ions. The thin film transistor (such as Figure 10 and Figure 11 The source and drain of the first transistor T01, the second transistor T02, the fifth transistor T05, the sixth transistor T06, and the driving transistor DT) shown in FIG, the first type of dual-gate transistor T1 (such as Figure 10 and Figure 11 The source and drain of the third transistor T03 and the fourth transistor T04 shown in FIG are located in the fourth metal layer M4. Optionally, the fourth metal layer M4 may be made of a composite material of titanium (Ti), aluminum (Al) and titanium (Ti).

[0110] The active layer TM1 of the thin-film transistor in this embodiment can be located on the side of the first metal layer M1 closest to the substrate 00. The active layer TM1 of the thin-film transistor can be made of polysilicon, such as poly. The active layer of the first-type dual-gate transistor T1 can be located between the second metal layer M2 and the third metal layer M3. The active layer TM2 of the first-type dual-gate transistor T1 can be made of a metal oxide material, such as IGZO. The first metal layer M1 in this embodiment can also be used to form a first scan signal line, a light-emission control signal line, and a second reference voltage signal line. The gates of the second transistor T02 and the sixth transistor T06 can be connected to a common scan signal line, i.e., the first scan signal line for providing the fourth scan signal SP4 and the first scan signal SP1. The gates of the first transistor T01 and the fifth transistor T05 can be connected to a common light-emission control signal line, i.e., the light-emission control signal line for providing the first light-emission control signal EM1 and the second light-emission control signal EM2. The second metal layer M2 in this embodiment can also be used to form a first reference voltage signal line, one plate of the storage capacitor Cst, i.e., the first reference voltage signal line for providing the first reset signal Vref1. The fourth metal layer M4 of this embodiment can also be used to form a second reference voltage signal line, which is used to provide a second reset signal Vref2. The fourth metal layer M4 on the substrate 00 of this embodiment may also include a fifth metal layer M5 (not filled in the figure) on the side facing away from the substrate 00. The fifth metal layer M5 is used to form a data line (providing a data voltage signal Vdata), a first power signal line (providing a first power signal Vpvdd), a second power signal line (providing a second power signal Vpvee), and the other plate of the storage capacitor Cst on the display panel 000.

[0111] It should be noted that this embodiment is for Figure 9 The working process and working principle of the first pixel circuit 10 are not described in detail. For details, please refer to the working principle of the pixel circuit in the relevant technology. The technical point of this embodiment is that the second detection line J2 is set to the same layer and width as the second control line L2, and both are set in the third metal layer M3, so that even if the first control line L1 and the second control line L2 at least partially overlap, the line width of the second control line L2 can be monitored through the second detection line J2, which can improve the monitoring accuracy and is conducive to ensuring the display quality of the completed display panel 000.

[0112] In some optional embodiments, please refer to Figure 1 、 Figure 10 、 Figure 11 and Figure 12 , Figure 12 yes Figure 1 Schematic diagram of another local layout structure of the Q1 region on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 12 The layout design of the first pixel circuit 10 on the substrate 00 in this embodiment is as follows: Figure 11 For example, the second detection line J2 is located in the non-display area NA.

[0113] This embodiment explains that the display area AA of the display panel 000 includes a plurality of first pixel circuits 10. The layout structure of the first pixel circuits 10 fabricated on the substrate 00 can be as follows: Figure 11 As shown, the second detection line J2 can be set within the non-display area NA, and it is only necessary that the second detection line J2 and the second control line L2 are in the same layer and have the same width. Setting the second detection line J2 in the non-display area NA can prevent the second detection line L2 from occupying the normal display space of the first sub-pixel P, thereby improving the transmittance of the entire display area AA. Figure 12 As shown, the second detection line J2 and the second control line L2 in this embodiment can both be located in the third metal layer M3, and the second detection line J2 and the second control line L2 can be manufactured synchronously, that is, when the third metal layer M3 is patterned, the line located in the display area AA can be defined as the second control line L2, and the line located in the non-display area NA can be defined as the second detection line J2, thereby achieving the purpose of monitoring the line width of the second control line L2 in the display area AA through the second detection line J2 in the non-display area NA.

[0114] In some optional embodiments, please refer to Figure 10 、 Figure 11 、 Figure 13 and Figure 14 , Figure 13 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 14 yes Figure 13 Schematic diagram of the local layout structure of the Q2 region on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 13 and Figure 14 Transparency filling is performed), in this embodiment, the non-display area NA of the display panel 000 includes at least one first virtual sub-pixel PD1, the first virtual sub-pixel PD1 includes a second pixel circuit 10P1; the second pixel circuit 10P1 includes at least a second type of transistor T2, and the second detection line J2 is arranged on the same layer as the gate of the second type of transistor T2.

[0115] This embodiment explains that the display panel 000 may also include at least one first virtual sub-pixel PD1. Optionally, the first virtual sub-pixel PD1 may be disposed in the non-display area NA, and the first virtual sub-pixel PD1 may be disposed around the non-display area NA near the display area AA. The first virtual sub-pixel PD1 in this embodiment may be manufactured using the same process as the first sub-pixel P in the display area AA. The first virtual sub-pixel PD1 includes a second pixel circuit 10P1, and the second pixel circuit 10P1 includes at least a second type of transistor T2. The second type of transistor T2 may have the same structure as any transistor in the first pixel circuit 10 and be manufactured using the same process, which is beneficial to improving process efficiency. The first virtual sub-pixel PD1 in this embodiment does not emit light and is not used for display. The first virtual sub-pixel PD1 may be used to prevent electrostatic discharge (ESD) from damaging the first sub-pixel P in the display area AA. Optionally, the cathode of the virtual light-emitting element in the first virtual sub-pixel PD1 can be electrically connected to the positive power signal line, and the anode of the virtual light-emitting element can be connected to the cathode of the light-emitting element 20 in the first sub-pixel P, so that the virtual light-emitting element becomes a reverse-connected light-emitting diode. Specifically, the anode of the light-emitting element 20 in the normally displaying first sub-pixel P can be connected to the driving transistor, and then connected to the first power signal Vpvdd through the driving transistor, and the light-emitting element 20 can be connected to the second power signal Vpvee, so that it can emit light normally. The anode of the virtual light-emitting element in the first virtual sub-pixel PD1 is connected to the cathode of the light-emitting element 20 in the normally displaying first sub-pixel P, which is equivalent to being connected to the second power signal Vpvee, and the cathode of the virtual light-emitting element in the first virtual sub-pixel PD1 is connected to the first power signal Vpvdd. In this way, the virtual light-emitting element in the first virtual sub-pixel PD1 becomes a reverse-connected light-emitting diode. Since light-emitting diodes have the characteristics of forward conduction and reverse blocking, the virtual light-emitting element in the first virtual sub-pixel PD1 cannot emit light normally after being reverse-connected, forming an electrostatic protector, performing an electrostatic protection function, and reducing electrostatic damage to the display panel. It can be understood that the anti-static working principle of the first virtual sub-pixel PD1 in this embodiment is only an example for illustration. When it is implemented specifically, it includes but is not limited to the above-mentioned anti-static structure. For specific understanding, please refer to the technical solution for electrostatic protection of virtual pixels in related technologies. This embodiment does not make any specific limitations here.

[0116] In this embodiment, the second pixel circuit 10P1 in the first virtual sub-pixel PD1 includes at least a second-type transistor T2, and the second detection line J2 for monitoring the second control line L2 is arranged on the same layer as the gate of the second-type transistor T2. The structure of the first virtual sub-pixel PD1 in the display panel 000 can be utilized, so that the second detection line J2 reuses the structure of the first virtual sub-pixel PD1 in the display panel 000 and is arranged on the same layer as the gate of the second-type transistor T2. That is, the second detection line J2 is jointly manufactured when manufacturing the gate of the second-type transistor T2 of the first virtual sub-pixel PD1 in the non-display area NA. There is no need to set up a separate wiring in the non-display area NA of the display panel 000 for use as the monitoring line width, which is beneficial to saving space in the non-display area NA.

[0117] Optionally, the second-type transistor T2 in the first virtual sub-pixel PD1 in this embodiment is a dual-gate transistor, that is, the second-type transistor T2 and the first-type dual-gate transistor T1 may be of the same type, the first gate T2G1 of the second-type transistor T2 and the first gate T1G1 of the first-type dual-gate transistor T1 are manufactured on the same layer and process, the second gate T2G2 of the second-type transistor T2 and the second gate T1G2 of the first-type dual-gate transistor T1 are manufactured on the same layer and process, and the source and drain of the second-type transistor T2 and the source and drain of the first-type dual-gate transistor T1 are manufactured on the same layer and process;

[0118] The second gate T2G2 of the second type transistor T2 is disposed on the same layer as the second detection line J2.

[0119] This embodiment explains that at least part of the structure of the first virtual sub-pixel PD1 for electrostatic protection provided in the non-display area NA can be the same as that of the first sub-pixel P, that is, the structure of the first pixel circuit 10 can be substantially the same as that of the second pixel circuit 10P1, that is, the second pixel circuit 10P1 can also include Figure 10 The circuit connection structure shown in FIG. Figure 15 As shown, Figure 15 yes Figure 10 Another layout structure of the circuit connection structure in the substrate is made (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 15Transparency is filled), the second-type transistor T2 in the first virtual sub-pixel PD1 can also be a dual-gate transistor and can be manufactured using the same structure and process as the first-type dual-gate transistor T1 in the display area AA. When the second-type transistor T2 is the same type as the first-type dual-gate transistor T1, the second detection line J2 in the non-display area NA can be manufactured on the same layer and process as the second gate T2G2 in the second-type transistor T2 in the non-display area NA. The second-type transistor T2 is the same type as the first-type dual-gate transistor T1, the first gate T2G1 of the second-type transistor T2 is manufactured on the same layer and process as the first gate T1G1 of the first-type dual-gate transistor T1, the second gate T2G2 of the second-type transistor T2 is manufactured on the same layer and process as the second gate T1G2 of the first-type dual-gate transistor T1, and the source and drain of the second-type transistor T2 are manufactured on the same layer and process as the source and drain of the first-type dual-gate transistor T1. The second detection line J2 can be manufactured in the same layer and with the same process as the second gate T1G2 of the first type dual-gate transistor T1, so that the second gate T1G2 of the first type dual-gate transistor T1 is connected to the second control line L2 in the same layer. Then, the second detection line J2 in the non-display area NA and the second control line L2 in the display area AA can be made of not only the same layer and material, but also the same layer and width. By monitoring the line width of the second detection line J2 in the non-display area NA, the line width of the second control line L2 in the display area AA can be obtained. Furthermore, under the premise that no additional signal line is set in the non-display area NA, the monitoring accuracy of the line width of the display area AA can be improved, which is beneficial to ensuring the display quality of the completed display panel 000.

[0120] In some optional embodiments, please refer to Figure 10 、 Figure 11 、 Figure 16-18 , Figure 16 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 17 yes Figure 16 Schematic diagram of the local layout structure of the Q3 area on the substrate, Figure 18 yes Figure 10 Another layout structure of the circuit connection structure in the substrate is made (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 16-18 Transparency filling is performed), in this embodiment, the second control line L2 of the display area AA is connected to the second detection line J2 of the non-display area NA in the non-display area NA, and the second gate T2G2 of the second type transistor T2 is connected to the second detection line J2 in the non-display area NA.

[0121] This embodiment illustrates that the second detection line J2 and the second control line L2 can both be located in the third metal layer M3. The second detection line J2 and the second control line L2 can be fabricated simultaneously, forming an integrally connected structure. Specifically, when patterning the third metal layer M3, the line located within the display area AA can be defined as the second control line L2, while the line located within the non-display area NA can be defined as the second detection line J2. This allows the width of the second control line L2 within the display area AA to be monitored via the second detection line J2 within the non-display area NA. Furthermore, when providing the third scan signal SN3 to the first pixel circuit 10 via the second control line L2, it can be provided via a peripheral wiring around the display area AA. In this case, the peripheral wiring can be reused as the second detection line J2. Furthermore, since the first virtual sub-pixel PD1 is located in the non-display area NA, the scan signal line connected to the second gate of the second-type transistor T2 of the second pixel circuit 10P1 can also function as the second detection line J2. In this embodiment, the second control line L2 of the display area AA and the second detection line J2 of the non-display area NA are connected together in the non-display area NA. The second detection line J2 is also connected to the third scanning signal SN3. Not only can the scanning signal line connected to the second gate of the second type transistor T2 of the second pixel circuit 10P1 in the first virtual sub-pixel PD1 be reused as the second detection line J2, but the outer surrounding line of the display area AA2 can also be reused as the second detection line J2. The third scanning signal SN3 can be provided to the second control line L2 of the display area AA through the second detection line J2. There is no need to set up a separate signal line in the non-display area NA to monitor the line width, which is conducive to achieving accurate line width monitoring effect while saving wiring space in the non-display area NA.

[0122] In some optional embodiments, please refer to Figure 10 、 Figure 11 、 Figures 19-21 , Figure 19 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 20 yes Figure 19 Schematic diagram of the local layout structure of the Q4 area on the substrate, Figure 21 yes Figure 10 Another layout structure of the circuit connection structure in the substrate is made (it can be understood that in order to clearly illustrate the structure of this embodiment, Figures 19-21 Transparency filling is performed), in this embodiment, the non-display area NA of the display panel 000 includes at least one second virtual sub-pixel PD2, and the second virtual sub-pixel PD2 includes a third pixel circuit 10P2;

[0123] The third pixel circuit 10P2 includes at least a third type of dual-gate transistor T3, wherein a first gate T3G1 of the third type of dual-gate transistor T3 is manufactured on the same layer and process as the first gate T1G1 of the first type of dual-gate transistor T1, a second gate T3G2 of the third type of dual-gate transistor T3 is manufactured on the same layer and process as the second gate T1G2 of the first type of dual-gate transistor T1, and a source and drain of the third type of dual-gate transistor T3 is manufactured on the same layer and process as the source and drain of the first type of dual-gate transistor T1.

[0124] The non-display area NA includes at least one first detection line J1. The first gate T3G1 of the third type dual-gate transistor T3 is connected to the first detection line J1 in the non-display area NA. The first detection line J1 is connected to the first control line L1. The first detection line J1 and the first control line L1 have the same layer and width.

[0125] This embodiment illustrates that the display panel 000 may also include at least one second dummy sub-pixel PD2. Optionally, the second dummy sub-pixel PD2 may be disposed within the non-display area NA, and the second dummy sub-pixel PD2 may be disposed near the periphery of the non-display area NA near the display area AA. The second dummy sub-pixel PD1 in this embodiment may be manufactured using the same process as the first sub-pixel P in the display area AA. The second dummy sub-pixel PD2 includes a third pixel circuit 10P2, which includes at least a third-type dual-gate transistor T3. The third-type dual-gate transistor T3 may have the same structure and be manufactured using the same process as the first-type dual-gate transistor T1 in the first pixel circuit 10, thereby improving process efficiency. The second dummy sub-pixel PD2 in this embodiment does not emit light and is not used for display. It functions similarly to the first dummy sub-pixel PD1, both of which can be used to prevent electrostatic discharge (ESD) from damaging the first sub-pixel P in the display area AA. It can be understood that this embodiment does not elaborate on the anti-static working principle of the second virtual sub-pixel PD2. For details, please refer to the technical solution for electrostatic protection of virtual pixels in related technologies or refer to the anti-static principle of the first virtual sub-pixel PD1 in the above embodiment for understanding. This embodiment does not make any specific limitations here.

[0126] In this embodiment, the third pixel circuit 10P2 in the second virtual sub-pixel PD2 includes at least a third type of dual-gate transistor T3, that is, the third type of dual-gate transistor T3 and the first type of dual-gate transistor T1 can be of the same type, and at least part of the structure of the second virtual sub-pixel PD2 for electrostatic protection provided in the non-display area NA can be the same as the structure of the first sub-pixel P, that is, the structure of the first pixel circuit 10 and the structure of the third pixel circuit 10P2 can be basically the same, that is, the third pixel circuit 10P2 can also include Figure 10 The circuit connection structure shown in FIG. Figure 21As shown, the first gate T3G1 of the third type of dual-gate transistor T3 is manufactured in the same layer and process as the first gate T1G1 of the first type of dual-gate transistor T1, the second gate T3G2 of the third type of dual-gate transistor T3 is manufactured in the same layer and process as the second gate T1G2 of the first type of dual-gate transistor T1, and the source and drain of the third type of dual-gate transistor T3 is manufactured in the same layer and process as the source and drain of the first type of dual-gate transistor T1, so that the structure of the second virtual sub-pixel PD2 is manufactured together with the structure of the first sub-pixel P of the display area AA, which is conducive to improving process efficiency.

[0127] In this embodiment, the non-display area NA includes at least one first detection line J1, and the first detection line J1 and the first control line L1 are in the same layer and have the same width, that is, the first detection line J1 and the first control line L1 are located in the same film layer and are manufactured using the same process to obtain the same line width. Then, the first detection line J1 can be used to monitor the line width of the first control line L1, that is, the line width of the first control line L1 located in the lower layer in the display area AA can also be monitored by the first detection line J1 in the non-display area NA. There is no need to consider the overlapping position relationship between the first control line L1 and the second control line L2 in the display area AA. It is only necessary to include a first detection line J1 in the same layer and width as the first control line L1 in the non-display area NA to achieve accurate monitoring of the line width of the first control line L1, which is beneficial to improving the flexibility and freedom of control line layout in the display area AA.

[0128] In this embodiment, the first gate T3G1 of the third type dual-gate transistor T3 is connected to the first detection line J1 in the non-display area NA, and the first detection line J1 is connected to the first control line L1, that is, the first detection line J1 reuses the film layer where the first gate T3G1 of the third type dual-gate transistor T3 is located. For example, the first detection line J1, the first control line L1, the first gate T1G1 of the first type dual-gate transistor T1, and the first gate T3G1 of the third type dual-gate transistor T3 are all arranged in the second metal layer M2, so that the film layer existing in the display panel 000 can be reused. The first detection line J1 can be produced using a layer structure. The first detection line J1 and the first control line L1 can be produced simultaneously. The first detection line J1 is connected to the first control line L1, so the first detection line J1 and the first control line L1 are integrally connected. That is, when patterning the second metal layer M2, the line located in the display area AA can be defined as the first control line L1, and the line located in the non-display area NA can be defined as the first detection line J1. This achieves the purpose of monitoring the line width of the first control line L1 in the display area AA through the first detection line J1 in the non-display area NA. Furthermore, when providing the third scan signal SN3 to the first pixel circuit 10 via the first control line L1, it can be provided via the outer surrounding line of the display area AA. In this case, the outer surrounding line can be reused as the first detection line J1. Moreover, since the second virtual sub-pixel PD2 is located in the non-display area NA, the scan signal line connected to the first gate of the third type dual-gate transistor T3 of the third pixel circuit 10P2 can also be used as the first detection line J1. In this embodiment, the first control line L1 of the display area AA and the first detection line J1 of the non-display area NA are connected together in the non-display area NA. The first detection line J1 is also connected to the third scanning signal SN3. Not only can the scanning signal line connected to the first gate of the third type dual-gate transistor T3 of the third pixel circuit 10P2 in the second virtual sub-pixel PD2 be reused as the first detection line J1, but the outer surrounding line of the display area AA2 can also be reused as the first detection line J1. The third scanning signal SN3 can be provided to the first control line L1 of the display area AA through the first detection line J1, and there is no need to set up a separate signal line in the non-display area NA to monitor the line width. This is conducive to achieving accurate line width monitoring effect while saving wiring space in the non-display area NA.

[0129] In some optional embodiments, please refer to Figure 10 、 Figure 11 、 Figure 22-Figure 24 , Figure 22 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 23 yes Figure 22 Schematic diagram of the local layout structure of the Q5 area on the substrate, Figure 24 yes Figure 10Another layout structure of the circuit connection structure in the substrate is made (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 22-Figure 24 Transparency filling is performed), in this embodiment, the non-display area NA of the display panel 000 includes at least one third virtual sub-pixel PD3, and the third virtual sub-pixel PD3 includes a fourth pixel circuit 10P3;

[0130] The fourth pixel circuit 10P3 includes at least a fourth type of dual-gate transistor T4. The first gate T4G1 of the fourth type of dual-gate transistor T4 is manufactured on the same layer and process as the first gate T1G1 of the first type of dual-gate transistor T1. The second gate T4G2 of the fourth type of dual-gate transistor T4 is manufactured on the same layer and process as the second gate T1G2 of the first type of dual-gate transistor T1. The source and drain of the fourth type of dual-gate transistor T4 are manufactured on the same layer and process as the source and drain of the first type of dual-gate transistor T1.

[0131] The non-display area NA includes at least one first detection line J1, the first gate T4G1 of the fourth type of dual-gate transistor T4 is connected to the first detection line J1 in the non-display area NA, the second gate T4G2 of the fourth type of dual-gate transistor T4 is connected to the second detection line J2 in the non-display area NA, the line width of the first detection line J1 is greater than the line width of the first control line L1, the line width of the first detection line J1 is greater than the line width of the second detection line J2, and the orthographic projection of the first detection line J1 on the substrate 00 covers the orthographic projection of the second detection line J2 on the substrate 00.

[0132] This embodiment illustrates that the display panel 000 may also include at least one third dummy sub-pixel PD3. Optionally, the third dummy sub-pixel PD3 may be disposed within the non-display area NA and may be disposed near the periphery of the non-display area NA near the display area AA. The third dummy sub-pixel PD3 in this embodiment may be fabricated using the same process as the first sub-pixel P in the display area AA. The third dummy sub-pixel PD3 includes a fourth pixel circuit 10P3, which includes at least a fourth-type dual-gate transistor T4. The fourth-type dual-gate transistor T4 may have the same structure and be fabricated using the same process as the first-type dual-gate transistor T1 in the first pixel circuit 10, thereby improving process efficiency. The third dummy sub-pixel PD3 in this embodiment does not emit light and is not used for display. It functions similarly to the first dummy sub-pixel PD1, both of which can be used to prevent electrostatic discharge (ESD) from damaging the first sub-pixel P in the display area AA. It can be understood that this embodiment does not elaborate on the anti-static working principle of the third virtual sub-pixel PD3. For details, please refer to the technical solution for electrostatic protection of virtual pixels in related technologies or refer to the anti-static principle of the first virtual sub-pixel PD1 in the above embodiment. This embodiment does not make any specific limitations here.

[0133] In this embodiment, the fourth pixel circuit 10P3 in the third virtual sub-pixel PD3 includes at least a fourth type of dual-gate transistor T4, that is, the fourth type of dual-gate transistor T4 and the first type of dual-gate transistor T1 can be of the same type, and at least part of the structure of the third virtual sub-pixel PD3 for electrostatic protection provided in the non-display area NA can be the same as the structure of the first sub-pixel P, that is, the structure of the first pixel circuit 10 can be substantially the same as the structure of the fourth pixel circuit 10P3, that is, the fourth pixel circuit 10P3 can also include Figure 10 The circuit connection structure shown in FIG. Figure 24 As shown, the first gate T4G1 of the fourth type of dual-gate transistor T4 is manufactured in the same layer and process as the first gate T1G1 of the first type of dual-gate transistor T1, the second gate T4G2 of the fourth type of dual-gate transistor T4 is manufactured in the same layer and process as the second gate T1G2 of the first type of dual-gate transistor T1, and the source and drain of the fourth type of dual-gate transistor T4 is manufactured in the same layer and process as the source and drain of the first type of dual-gate transistor T1, so that the structure of the third virtual sub-pixel PD3 is manufactured together with the structure of the first sub-pixel P of the display area AA, which is beneficial to improving process efficiency.

[0134] In this embodiment, the non-display area NA includes at least one first detection line J1. The first gate T4G1 of the fourth-type dual-gate transistor T4 is connected to the first detection line J1 in the non-display area NA. The line width of the first detection line J1 is greater than the line width of the first control line L1. This means that the first detection line J1 is not used to monitor the line width of the first control line L1. The line width of the first control line L1 is monitored in the display area AA, where the line width of the first control line L1 itself is obtained by monitoring the line width of the first control line L1. The first gate T4G1 of the fourth-type dual-gate transistor T4 is connected to the first detection line J1 in the non-display area NA. This means that the first detection line J1, the first gate T4G1 of the fourth-type dual-gate transistor T4, and the first control line L1 in the display area AA can be fabricated from the same film layer and can be interconnected. The third scanning signal SN3 is provided to the first pixel circuit 10 in the display area AA via the first detection line J1. In this embodiment, the second gate electrode T4G2 of the fourth type dual-gate transistor T4 is connected to the second detection line J2 in the non-display area NA. The line width of the first detection line J1 is greater than that of the second detection line J2. The orthographic projection of the first detection line J1 on the substrate 00 overlaps the orthographic projection of the second detection line J2 on the substrate 00. That is, when the second detection line J2 is formed above the first detection line J1, its line width is smaller than the line width of the first detection line J1 below it. This ensures that the orthographic projection of the second detection line J2 on the substrate 00 completely falls within the orthographic projection of the first detection line J1 on the substrate 00. At this time, since the boundaries of the line width pattern of the second detection line J2 are all within the boundaries of the line width pattern of the first detection line J1, the boundaries of the line width pattern of the second detection line J2 can be clearly determined, and the line width of the second detection line J2 can be measured and obtained. In addition, since the second detection line J2 and the second control line L2 are on the same layer and have the same width, the line width of the second control line L2 can be accurately determined. In this embodiment, the first detection line J1 is used as the scanning line of the third virtual sub-pixel PD3 and can be connected to the first control line L1 in the display area AA as an integrated structure. The second detection line J2 is used as the scanning line of the third virtual sub-pixel PD3 and can be connected to the second control line L2 in the display area AA as an integrated structure. The line width of the first detection line J2 is greater than the line width of the first control line L1. Therefore, the line width of the first control line L1 is still obtained by monitoring itself in the display area AA (before the first control line L1 is manufactured and other metal lines are not stacked on it), and the second detection line J2 is used as the scanning line of the third virtual sub-pixel PD3 and can be connected to the second control line L2 in the display area AA as an integrated structure. Line J2 can be used as a scanning line to provide the third scanning signal SN3 for the first pixel circuit 10, and can also be reused as the outer surrounding line of the display area AA. The second detection line J2 and the second control line L2 are on the same layer and have the same width. The positive projection of the second detection line J2 on the substrate 00 completely falls within the positive projection range of the first detection line J1 on the substrate 00. Therefore, the second detection line J2 can be used to monitor the line width of the second control line L2. There is no need to set up a separate signal line in the non-display area NA to monitor the line width. This is conducive to achieving accurate line width monitoring effects while saving wiring space in the non-display area NA.In this embodiment, when the second control line L2 is produced in the display area AA, there is no need to consider the overlapping positional relationship between the first control line L1 and the second control line L2 in the display area AA. It is only necessary to include a second detection line J2 with the same layer and width as the second control line L2 in the non-display area NA to achieve accurate monitoring of the line width of the second control line L2, which is beneficial to improving the flexibility and freedom of control line layout in the display area AA.

[0135] In some alternative embodiments, please refer to Figure 10 、 Figure 11 、 Figure 25 and Figure 26 , Figure 25 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 26 yes Figure 25 Schematic diagram of the local layout structure of the first sub-pixel on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 25 and Figure 26 Transparency filling is performed), in this embodiment, the second detection line J2 is located in the display area AA.

[0136] This embodiment explains that the second detection line J2 for monitoring the line width of the second control line L2 can be set within the display area AA. When manufacturing the second control line L2, the second detection line J2 with the same width as the second control line L2 can be manufactured on the same layer. Optionally, the second detection line J2 in this embodiment can be set at any position within the display area AA. It is only necessary that when monitoring the line width of the second detection line J2, there is no other metal trace in the lower film layer to interfere with the boundary of the line width graph of the second detection line J2, and the boundary of the line width graph of the second detection line J2 can be clearly identified. Figure 25 and Figure 26 As shown, the second detection line J2 can be set in an empty position in the display area AA to avoid interfering with the transmission of the driving signal of the display panel 000. In this embodiment, the second detection line J2 is set in the display area AA, which is beneficial to reducing the number of wirings in the non-display area NA, thereby facilitating the realization of a narrow frame effect.

[0137] It can be understood that the line width monitoring of the first control line L1 in this embodiment can be performed by photographing its own line width pattern to identify the line width of the first control line L1 because other metal traces are not covered above the first control line L1 when monitoring the line width of the first control line L1.

[0138] Optional, such as Figure 26As shown, the second detection line J2 and the second control line L2 in this embodiment can both be located in the third metal layer M3, and the second detection line J2 and the second control line L2 can be manufactured synchronously, that is, when the third metal layer M3 is patterned, the structure of the patterned portion of the third metal layer M3 can be defined as the second control line L2, and the structure of the patterned portion of the third metal layer M3 can be defined as the second detection line J2, thereby achieving the purpose of monitoring the line width of the second control line L2 in the display area AA through the second detection line J2 in the display area NA, and the second detection line J2 can also not affect the signal transmission of various types of signal lines in the display area AA.

[0139] Optional, such as Figure 26 As shown, no metal structure is included between the second detection line J2 and the substrate 00 in a direction perpendicular to the plane of the display panel 000. This embodiment explains that when the second detection line J2 is disposed on the substrate 00 within the display area AA, no metal structure is included between the second detection line J2 and the substrate 00 in a direction perpendicular to the plane of the display panel 000. When the second detection line J2 is formed, no other metal line is formed at the position of the second detection line J2 on the substrate 00 to overlap with it. Therefore, when capturing the line width pattern of the second detection line J2, the boundary of the line width pattern of the second detection line J2 can be clearly identified, thereby avoiding interference from the boundary of other metal traces below the second detection line J2 that affects monitoring accuracy.

[0140] In some alternative embodiments, please refer to Figure 10 、 Figure 11 、 Figure 25 、 Figure 26 and Figure 27 , Figure 27 yes Figure 25 Schematic diagram of another partial layout structure of the first sub-pixel on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 27 In this embodiment, the second detection line J2 is floated; or, the second detection line J2 is connected to a fixed potential.

[0141] This embodiment explains that when the second detection line J2 is set in the display area AA, the second detection line J2 can be in a floating state, and the second detection line J2 is not connected to any signal, such as Figure 26As shown, it is only used to monitor the line width of the second control line L2. Alternatively, the second detection line J2 set in the display area AA can not only be used to monitor the line width of the second control line L2, but also can be connected to a fixed potential, such as electrically connecting the second detection line J2 located in the third metal layer M3 to the first power signal line (used to provide the first power signal Vpvdd, not filled in the figure). Optional different metal film layers can be electrically connected through vias, which can not only stabilize the signal of the second detection line J2, but also reduce the impedance of the first power signal line in the display area AA, which is equivalent to the first power signal line of the display panel of this embodiment being connected in parallel by two metal traces of different layers (the original first power signal line of the fifth metal layer M5 and the second detection line J2 of the third metal layer M3), thereby reducing the impedance of the first power signal line in the entire display panel 000 and improving the signal transmission effect of the display panel.

[0142] In some optional embodiments, please continue to refer to Figure 10 、 Figure 11 and Figure 25 In this embodiment, the first control line L1 includes a first sub-segment L11 and a second sub-segment L12, and the second control line L2 includes a third sub-segment L21 and a fourth sub-segment L22;

[0143] The orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00 overlaps with the orthographic projection of the first sub-segment L11 on the substrate 00 , and the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00 overlaps with the orthographic projection of the third sub-segment L21 on the substrate 00 ;

[0144] The line width W11 of the first sub-segment L11 is greater than the line width W21 of the second sub-segment L21 , and the line width W21 of the third sub-segment L21 is greater than the line width W22 of the fourth sub-segment L22 .

[0145] This embodiment explains that the first control line L1 includes a first sub-segment L11 and a second sub-segment L12, and the second control line L2 includes a third sub-segment L21 and a fourth sub-segment L22, wherein the first sub-segment L11 and the second sub-segment L12 only represent the first control line L1 in different regions, and the first sub-segment L11 and the second sub-segment L12 still constitute the overall structure of the first control line L1, and the third sub-segment L21 and the fourth sub-segment L22 only represent the second control line L2 in different regions, and the third sub-segment L21 and the fourth sub-segment L22 still constitute the overall structure of the second control line L2. In this embodiment, the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00 overlaps with the orthographic projection of the first sub-segment L11 on the substrate 00, and the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00 overlaps with the orthographic projection of the third sub-segment L21 on the substrate 00. The material of the active portion T1P of the first type dual-gate transistor T1 can be a metal oxide, such as IGZO, thereby forming a bottom-gate and top-gate dual-gate structure transistor of the first type dual-gate transistor T1. The first sub-segment L11 overlapping with the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00 is the first gate T1G1 of the first type dual-gate transistor T1, and the third sub-segment L21 overlapping with the orthographic projection of the active portion T1P of the first type dual-gate transistor T1 on the substrate 00 is the second gate T1G2 of the first type dual-gate transistor T1. In this embodiment, the line width of the first subsegment L11 is set to be greater than the line width of the second subsegment L12, and the line width of the third subsegment L21 is set to be greater than the line width of the fourth subsegment L22. Since the performance of the metal oxide transistor is proportional to the channel width-to-length ratio of the transistor itself, that is, in this embodiment, the line width of the first subsegment L11 is set to be greater than the line width of the second subsegment L12, and the line width of the third subsegment L21 is set to be greater than the line width of the fourth subsegment L22. This is conducive to improving the channel width-to-length ratio of the first type dual-gate transistor T1, thereby further improving the driving capability of the first type dual-gate transistor T1.

[0146] In some optional embodiments, please continue to refer to Figure 10 、 Figure 11 、 Figure 25 and Figure 28 , Figure 28 yes Figure 25 Schematic diagram of another partial layout structure of the first sub-pixel on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 28 Transparency filling is performed). In this embodiment, the orthographic projection of the second sub-segment L12 on the substrate 00 does not overlap with the orthographic projection of the fourth sub-segment L22 on the substrate 00;

[0147] The fourth sub-segment L22 is multiplexed as the second detection line J2.

[0148] This embodiment explains that when the second detection line J2 is located in the display area AA, the original signal line in the display area AA can be reused as a routing line for monitoring the line width. Specifically, the orthographic projection of the second subsegment L12 of the first control line L1 on the substrate 00 does not overlap with the orthographic projection of the fourth subsegment L22 of the second control line L2 on the substrate 00. That is, the second subsegment L12 of the first control line L1 in the area excluding the first-type dual-gate transistor T1 and the fourth subsegment L22 of the second control line L2 in the area excluding the first-type dual-gate transistor T1 are staggered and do not overlap at all. At this time, the fourth subsegment L22 and the substrate 00 are not interfered with by the second subsegment L12. Therefore, the fourth subsegment L22 can be reused as the second detection line J2 for monitoring the line width of the entire second control line L2. This embodiment reuses part of the sub-segment of the second control line L2 originally present in the display panel 000 to monitor its line width. This not only enables accurate monitoring of the second control line L2, but also avoids setting up a separate detection line in the display area AA for monitoring the line width, which is beneficial to ensuring the display quality of the first sub-pixel P.

[0149] It can be understood that, in this embodiment, the line width W21 of the third sub-segment L21 of the second control line L2 is greater than the line width W22 of the fourth sub-segment L22. Therefore, when monitoring the line width of the second control line L2, it is only necessary to monitor the line width of the thinner part of the fourth sub-segment L22, without monitoring twice. It is only necessary to ensure that the line width of the thinner part meets the design requirements to avoid the risk of broken wires in the thinner parts.

[0150] In some optional embodiments, please continue to refer to Figure 10 、 Figure 11 、 Figure 25 and Figure 29 、 Figure 30 , Figure 29 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate, Figure 30 yes Figure 25 Schematic diagram of another partial layout structure of the first sub-pixel on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 29 and Figure 30 Transparency filling is performed). In this embodiment, in a direction perpendicular to the plane where the display panel 000 is located, the orthographic projection of the second sub-segment L12 on the substrate 00 covers the orthographic projection of the fourth sub-segment L22 on the substrate 00;

[0151] The fourth sub-segment L22 is multiplexed as the second detection line J2.

[0152] This embodiment explains that when the second detection line J2 is located in the display area AA, the original signal line in the display area AA can be reused as a line for monitoring the line width. Specifically, the orthographic projection of the second sub-segment L12 on the substrate 00 covers the orthographic projection of the fourth sub-segment L22 on the substrate 00. Figure 29 The line width W12 of the second sub-segment L12 is equal to the line width W22 of the fourth sub-segment L22, and the orthographic projection of the second sub-segment L12 on the substrate 00 coincides with the orthographic projection of the fourth sub-segment L22 on the substrate 00, or as shown in FIG. Figure 30 The line width W12 of the second sub-segment L12 shown is greater than the line width W22 of the fourth sub-segment L22, and the orthographic projection of the second sub-segment L12 on the substrate 00 covers the orthographic projection of the fourth sub-segment L22 on the substrate 00. Since the orthographic projection of the second sub-segment L12 on the substrate 00 coincides with the orthographic projection of the fourth sub-segment L22 on the substrate 00, or the orthographic projection of the second sub-segment L12 on the substrate 00 covers the orthographic projection of the fourth sub-segment L22 on the substrate 00, the fourth sub-segment L22 can be multiplexed as the second detection line J2 for monitoring the line width of the entire second control line L2. There will be no line width boundary interference of the second sub-segment L12 below the fourth sub-segment L22, and the line width of the second control line L2 can be obtained by monitoring the line width of the fourth sub-segment L22. This embodiment reuses part of the sub-segment of the second control line L2 originally present in the display panel 000 to monitor its line width. This not only enables accurate monitoring of the second control line L2, but also avoids setting up a separate detection line in the display area AA for monitoring the line width, which is beneficial to ensuring the display quality of the first sub-pixel P.

[0153] It can be understood that, in this embodiment, the line width W21 of the third sub-segment L21 of the second control line L2 is greater than the line width W22 of the fourth sub-segment L22. Therefore, when monitoring the line width of the second control line L2, it is only necessary to monitor the line width of the thinner part of the fourth sub-segment L22, without monitoring twice. It is only necessary to ensure that the line width of the thinner part meets the design requirements to avoid the risk of broken wires in the thinner parts.

[0154] Optionally, in this embodiment, the orthographic projection of the second subsegment L12 on the substrate 00 overlaps the orthographic projection of the fourth subsegment L22 on the substrate 00 in a direction perpendicular to the plane of the display panel 000. This can also prevent the orthographic projection of the fourth subsegment L22 on the substrate 00 from overlapping the orthographic projection of the second subsegment L12 on the substrate 00. Since the fourth subsegment L22 is located above the second subsegment L12, if the line width of the fourth subsegment L22 is wider than the line width of the second subsegment L12, portions of the fourth subsegment L22 may easily sag or slope on either side of the second subsegment L12. This can further lead to inaccurate line width monitoring when the fourth subsegment L22 is reused as the second detection line J2. Therefore, in this embodiment, the orthographic projection of the second subsegment L12 on the substrate 00 overlaps the orthographic projection of the fourth subsegment L22 on the substrate 00 in a direction perpendicular to the plane of the display panel 000. This allows for line width monitoring of the second control line L2 by reusing the fourth subsegment L22, while also further improving monitoring accuracy.

[0155] Optional, such as Figure 29 As shown, the line width W12 of the second subsegment L12 is equal to the line width W22 of the fourth subsegment L22, and the orthographic projection of the second subsegment L12 on the substrate 00 coincides with the orthographic projection of the fourth subsegment L22 on the substrate 00. This not only allows the fourth subsegment L22 to be reused to monitor the line width of the second control line L2, but also further improves the transmittance of the display area AA.

[0156] In some optional embodiments, please continue to refer to Figure 10 、 Figure 11 、 Figure 25 and Figure 31 、 Figure 32 , Figure 31 yes Figure 25 Schematic diagram of another local layout structure of the first sub-pixel on the substrate, Figure 32 yes Figure 25 Schematic diagram of another partial layout structure of the first sub-pixel on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 31 and Figure 32 In this embodiment, in a direction perpendicular to the plane of the display panel 000 , the orthographic projection of the first subsegment L11 on the substrate 00 covers the orthographic projection of the third subsegment L21 on the substrate 00 .

[0157] This embodiment explains that the orthographic projection of the active portion T1P of the first type of double-gate transistor T1 on the substrate 00 overlaps with the orthographic projection of the first sub-segment L11 on the substrate 00, and the orthographic projection of the active portion T1P of the first type of double-gate transistor T1 on the substrate 00 overlaps with the orthographic projection of the third sub-segment L21 on the substrate 00. The material of the active portion T1P of the first type of double-gate transistor T1 can be a metal oxide, such as IGZO, thereby forming a double-gate structure transistor with a bottom gate and a top gate of the first type of double-gate transistor T1, wherein the orthographic projection of the active portion T1P of the first type of double-gate transistor T1 on the substrate 00 overlaps with the orthographic projection of the third sub-segment L21 on the substrate 00. When the first sub-segment L11 on which the orthographic projection of the active portion T1P of the first-type dual-gate transistor T1 overlaps with the orthographic projection on the substrate 00 is the first gate T1G1 of the first-type dual-gate transistor T1, and the third sub-segment L21 on which the orthographic projection of the active portion T1P of the first-type dual-gate transistor T1 overlaps with the orthographic projection on the substrate 00 is the second gate T1G2 of the first-type dual-gate transistor T1, they can be arranged in a direction perpendicular to the plane where the display panel 000 is located, and the orthographic projection of the first sub-segment L11 on the substrate 00 covers the orthographic projection of the third sub-segment L21 on the substrate 00, as shown in FIG. Figure 31 As shown, the orthographic projection of the first sub-segment L11 on the substrate 00 can overlap with the orthographic projection of the third sub-segment L21 on the substrate 00, thereby facilitating the improvement of the transmittance of the display area AA, or, as shown in FIG. Figure 32 As shown, the orthographic projection of the third subsegment L21 on the substrate 00 can be completely located within the orthographic projection range of the first subsegment L11 on the substrate 00. The first gate T1G1 of the first type dual-gate transistor T1 is made larger in area, which plays a role in shielding hydrogen ions. This can prevent hydrogen ions in the film layer below the first gate T1G1 from diffusing into the active portion T1P of the IGZO during the high-temperature process, thereby avoiding affecting the driving performance of the first type dual-gate transistor T1.

[0158] Optional, such as Figure 10 、 Figure 11 、 Figure 25 and Figure 31 、 Figure 32 As shown, when the orthographic projection of the first subsegment L11 on the substrate 00 covers the orthographic projection of the third subsegment L21 on the substrate 00 in a direction perpendicular to the plane of the display panel 000, the third subsegment L21 is multiplexed as the second detection line J2.

[0159] This embodiment explains that when the second detection line J2 is located in the display area AA, the original signal line in the display area AA can be reused as a line for monitoring the line width. Specifically, in a direction perpendicular to the plane of the display panel 000, the orthographic projection of the first sub-segment L11 on the substrate 00 covers the orthographic projection of the third sub-segment L21 on the substrate 00, as shown in FIG. Figure 31The line width W11 of the first sub-segment L11 is equal to the line width W21 of the third sub-segment L21, and the orthographic projection of the first sub-segment L11 on the substrate 00 coincides with the orthographic projection of the third sub-segment L21 on the substrate 00, or as shown in FIG. Figure 32 The line width W11 of the first subsegment L11 shown is greater than the line width W21 of the third subsegment L21, and the orthographic projection of the first subsegment L11 on the substrate 00 covers the orthographic projection of the third subsegment L21 on the substrate 00. Since the orthographic projection of the first subsegment L11 on the substrate 00 coincides with the orthographic projection of the third subsegment L21 on the substrate 00, or the orthographic projection of the first subsegment L11 on the substrate 00 covers the orthographic projection of the third subsegment L21 on the substrate 00, the third subsegment L21 can be multiplexed as the second detection line J2 for monitoring the line width of the entire second control line L2. There will be no line width boundary interference of the first subsegment L11 below the third subsegment L21, and the line width of the second control line L2 can be obtained by monitoring the line width of the third subsegment L21. This embodiment reuses part of the sub-segment of the second control line L2 originally present in the display panel 000 to monitor its line width. This not only enables accurate monitoring of the second control line L2, but also avoids setting up a separate detection line in the display area AA for monitoring the line width, which is beneficial to ensuring the display quality of the first sub-pixel P.

[0160] In some optional embodiments, please refer to Figure 33 and Figure 34 , Figure 33 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 34 yes Figure 33 Schematic diagram of the layout structure of the local structure made on the substrate (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 33 and Figure 34 Transparency filling is performed), in this embodiment, the non-display area NA further includes a first transmission line LS;

[0161] In the non-display area NA, the first control line L1 and the second control line L2 are electrically connected through a via K;

[0162] The first control line L1 is connected to the first transmission line LS; or the second control line L2 is connected to the first transmission line LS.

[0163] This embodiment explains that the first control line L1 connected to the first gate T1G1 of the first type of dual-gate transistor T1 in the first pixel circuit 10 and the second control line L2 connected to the second gate T1G2 of the first type of dual-gate transistor T1 both need to be connected to the third scanning signal SN3. Therefore, the first control line L1 and the second control line L2 set in different layers can be electrically connected in the non-display area NA through the via K, so that the setting area of ​​the via K can avoid the display area AA, which is beneficial to reduce the number of vias opened in the display area AA and avoid the excessive number of vias K in the display area AA affecting the display quality. The non-display area NA of this embodiment is also provided with a first transmission line LS. The first transmission line LS can be understood as the outer surrounding wire of the display panel 000. One end of the first transmission line LS can be connected to the first control line L1 (such as Figure 34 as shown); alternatively, one end of the first transmission line LS can be connected to the second control line L2 (not shown in the figure), the first transmission line LS is at least partially arranged around the display area AA, and is connected to the conductive pad in the binding area (not shown in the figure) of the display panel 000, and the third scan signal SN3 is transmitted to the first control line L1 and the second control line L2 of the display area AA through the first transmission line LS through the driving chip or flexible circuit board subsequently bound in the binding area, thereby realizing the driving function and display effect of the display panel.

[0164] Optionally, in this embodiment, the first transmission line LS in the non-display area NA may be provided in the same layer as the first control line L1, or the first transmission line LS in the non-display area NA may be provided in the same layer as the second control line L2, or the first transmission line LS in the non-display area NA may be provided in different layers from the first control line L1 and the second control line L2 (e.g., Figure 34 As shown, at this time, the first transmission lines LS of different layers can also be electrically connected to the first control line L1 by opening vias). This embodiment does not limit this. Any conductive film layer can be used to make the first transmission line LS, as long as it avoids affecting the wiring structure of the non-display area NA and avoids short circuits between the lines.

[0165] In some alternative embodiments, please refer to Figure 35 , Figure 35 is another schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 35 Transparency filling is performed), in this embodiment, the non-display area NA includes a first non-display area NA1 and a second non-display area NA2, and the first non-display area NA1 and the second non-display area NA2 are respectively located on opposite sides of the display area AA;

[0166] The first dummy sub-pixel PD1 is located in the first non-display area NA1 , and the first control line L1 is electrically connected to the second control line L2 through a via K in the second non-display area NA2 .

[0167] This embodiment explains that the display panel 00 may include a first non-display area NA1 and a second non-display area NA2 respectively located on opposite sides of the display area AA, and the first virtual sub-pixel PD1 for electrostatic protection is set in the first non-display area NA1, and the first control line L1 and the second control line L2 are electrically connected in the second non-display area NA2 through the via K. This can avoid the first virtual sub-pixel PD1 and the via K being set in the non-display area NA on the same side of the display area AA and occupying too much space, resulting in uneven space between the first non-display area NA1 and the second non-display area NA2 on opposite sides of the display area AA, and the via K connecting the first control line L1 and the second control line L2 is set in the second non-display area NA2, which can also avoid the opening of the via K causing static electricity to leak along the via hole, affecting the electrostatic protection effect of the first virtual sub-pixel PD1.

[0168] It is understandable that this embodiment does not elaborate on the setting structure and principle of the first virtual sub-pixel PD1, nor does it elaborate on the embodiment in which the second detection line J2 can reuse part of the structure within the first virtual sub-pixel PD1. For details, please refer to the description of the above embodiments.

[0169] In some alternative embodiments, please refer to Figure 36 , Figure 36 is another schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 36 In this embodiment, the non-display area NA includes a plurality of first virtual sub-pixels PD1, and the plurality of first virtual sub-pixels PD1 are at least partially arranged around the display area AA;

[0170] A plurality of first sub-pixels P are arranged along a first direction X to form a first sub-pixel row PH, and a plurality of first sub-pixel rows PH are arranged along a second direction Y, wherein the first direction X and the second direction Y intersect;

[0171] A plurality of first sub-pixels P in a first sub-pixel row PH are electrically connected to the same first control line L1, and a plurality of first sub-pixels P in a first sub-pixel row PH are electrically connected to the same second control line L2;

[0172] At least one first sub-pixel row PH corresponds to a first virtual sub-pixel PD1.

[0173] This embodiment explains that the first sub-pixels P in the display area AA of the display panel 000 can be arranged in an array, with multiple first sub-pixels P arranged along a first direction X to form a first sub-pixel row PH, and multiple first sub-pixel rows PH arranged along a second direction Y, wherein the first direction X and the second direction Y intersect. Optionally, this embodiment is described by taking the first direction X and the second direction Y as being perpendicular to each other in a direction parallel to the plane of the display panel 000 as an example. In this embodiment, multiple first sub-pixels P in a first sub-pixel row PH are electrically connected to the same first control line L1, and multiple first sub-pixels P in a first sub-pixel row PH are electrically connected to the same second control line L2, so that the multiple first sub-pixels P in the entire first sub-pixel row PH can be controlled by the first control line L1, so that the first gates of the first-type dual-gate transistors T1 in the multiple first sub-pixels P in the first sub-pixel row PH are all turned on by signals, and the multiple first sub-pixels P in the entire first sub-pixel row PH can be controlled by the second control line L2, so that the second gates of the first-type dual-gate transistors T1 in the multiple first sub-pixels P in the first sub-pixel row PH are all turned on by signals, thereby achieving the simultaneous turning on and off of the first-type dual-gate transistors T1 in the same first pixel row PH and inputting scan drive signals. In this embodiment, at least one first sub-pixel row PH corresponds to a first virtual sub-pixel PD1, so that multiple first virtual sub-pixels PD1 can be arranged around the display area AA, which is beneficial for providing electrostatic protection for the first sub-pixels P in each first sub-pixel row PH, thereby preventing static electricity from damaging the first sub-pixels P in a first sub-pixel row PH when no first virtual sub-pixel PD1 is arranged around the periphery of the first sub-pixel row PH, thereby further improving the anti-static effect of the entire display panel 000.

[0174] Optionally, at least one first sub-pixel row PH corresponds to a first virtual sub-pixel PD1, and each second control line L2 corresponding to the first sub-pixel row PH can also correspond to a first virtual sub-pixel PD1. The structure in the corresponding first virtual sub-pixel PD1 can be reused as the line width monitoring line of the second control line L2, that is, multiplexed as the second detection line J2, so that the display panel 000 can include multiple second detection lines J2, and at least one second control line L2 is set to correspond to a second detection line J2, so as to better realize the monitoring of the line width of all second control lines L2 in the display panel 000.

[0175] Optionally, the first dummy sub-pixels PD1 corresponding to different first sub-pixel rows PH are all located on the same side of the display area AA in the first direction X. This embodiment explains that the multiple first dummy sub-pixels PD1 included in the non-display area NA can be located on the same side of the display area AA in the first direction X, that is, the first dummy sub-pixels PD1 corresponding to different first sub-pixel rows PH can all be set at the same end of the first sub-pixel row PH. This structure allows multiple first dummy sub-pixels PD1 to be manufactured on the substrate 00 on the same side of the display area AA, which helps reduce process difficulty and improve process efficiency.

[0176] In some alternative embodiments, please refer to Figure 37 , Figure 37 is another schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 37 Transparency filling is performed). In this embodiment, in the first direction X, the two sides of the display area AA1 include a first area NA11 and a second area NA21 that are oppositely arranged. The first area NA11 and the second area NA21 are both located in the non-display area NA. Optionally, the first area NA11 can be understood as a portion of the first non-display area NA1 of the non-display area NA close to the display area AA, and the second area NA21 can be understood as a portion of the second non-display area NA1 of the non-display area NA close to the display area AA.

[0177] At least some of the first dummy sub-pixels PD1 corresponding to the first sub-pixel rows PH are located in the first area NA11 , and at least some of the first dummy sub-pixels PD1 corresponding to the first sub-pixel rows PH are located in the second area NA21 .

[0178] This embodiment explains that the first virtual sub-pixels PD1 corresponding to different first sub-pixel rows PH can be located on different sides of the display area AA in the first direction X, that is, the multiple first virtual sub-pixels PD1 included in the non-display area NA can be located on different sides of the display area AA in the first direction X, at least some of the first virtual sub-pixels PD1 corresponding to the first sub-pixel rows PH are located in the first area NA11, and at least some of the first virtual sub-pixels PD1 corresponding to the first sub-pixel rows PH are located in the second area NA21. This allows the multiple first virtual sub-pixels PD1 to be evenly arranged on both sides of the display area AA, which is beneficial for making the border widths of the first non-display area NA1 and the second non-display area NA2 as equal as possible, thereby avoiding the border at one edge of the display panel 000 being too large to affect the user's visual effect.

[0179] Optional, please refer to Figure 38 , Figure 38 is another schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 38In this embodiment, in two adjacent first sub-pixel rows PH, the first virtual sub-pixel PD1 corresponding to one first sub-pixel row PH is located in the first area NA11, and the first virtual sub-pixel PD1 corresponding to the other first sub-pixel row PH is located in the second area NA21.

[0180] This embodiment explains that when the first virtual sub-pixels PD1 corresponding to different first sub-pixel rows PH are located on different sides of the display area AA in the first direction X, the two first virtual sub-pixels PD1 corresponding to two adjacent first sub-pixel rows PH are respectively located on opposite sides of the display area AA, that is, in the two adjacent first sub-pixel rows PH, the first virtual sub-pixel PD1 corresponding to one first sub-pixel row PH is located in the first area NA11, and the first virtual sub-pixel PD1 corresponding to the other first pixel row PH is located in the second area NA21. This can make the first virtual sub-pixels PD1 arranged at both ends of the area where the two adjacent first pixel rows PH are located more uniform, and can also make the number of first virtual sub-pixels PD1 in the first area NA11 and the number of first virtual sub-pixels PD1 in the second area NA21 as consistent as possible. The multiple first virtual sub-pixels PD1 in the first non-display area NA1 and the multiple first virtual sub-pixels PD1 in the second non-display area NA2 are used to better protect the entire display panel from electrostatic damage, thereby further improving the anti-static effect of the display panel 000.

[0181] In some alternative embodiments, please refer to Figure 39 , Figure 39 1 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 39 This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in the embodiment of the present invention can be a computer, a television, an in-vehicle display device, or other display device 111 having a display function, and the present invention does not impose any specific limitations thereon. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, please refer to the detailed description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0182] It can be seen from the above embodiments that the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0183] The display area of ​​the display panel provided by the present invention may include a plurality of first sub-pixels. The first sub-pixels may be understood as sub-pixels used for display in the display panel. The first pixel circuit in the first sub-pixel includes at least a first-class dual-gate transistor. Compared with a single-gate transistor, the dual-gate transistor can effectively improve the carrier mobility of the first-class dual-gate transistor, which is beneficial to further improve the resolution of the display panel. The first pixel circuit in the present invention includes a first-class dual-gate transistor. By utilizing the characteristic of the higher mobility of the dual-gate transistor, its driving capability can be improved, making the first pixel circuit more suitable for large-size, high-resolution display panels. The first gate of the first-class dual-gate transistor in the present invention is connected to a first control line, and the second gate of the first-class dual-gate transistor is connected to a second control line, that is, the two gates of the same first-class dual-gate transistor are respectively fed with control signals by two control lines to realize the conduction or cutoff of the first-class dual-gate transistor. The display panel of the present invention also includes a second detection line. The second detection line has the same width as the second control line, so that the second detection line and the second control line are in the same layer and have the same width. The line width of the second control line is obtained by monitoring the line width of the second detection line. Since the second detection line is located away from the area overlapping with the first control line, that is, there are no other interfering lines overlapping with the second detection line below the second detection line. Therefore, the machine can automatically distinguish the boundary of the line width pattern of the second detection line in the photograph of the substrate including the second detection line, and then accurately obtain the line width of the second detection line and the line width of the second control line simultaneously. The display panel provided by the present invention can monitor the width of the signal line in the display panel in real time through the provision of the second detection line. Not only is the monitoring method simple and easy to operate, but it can also improve monitoring accuracy, which is conducive to ensuring the display quality of the completed display panel.

[0184] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: Display area and non-display area; The display panel includes a substrate, on which: The display area includes a plurality of first sub-pixels, each of which includes an electrically connected first pixel circuit and a light-emitting element; the first pixel circuit includes at least a first-type dual-gate transistor, a first gate of the first-type dual-gate transistor being connected to a first control line, and a second gate of the first-type dual-gate transistor being connected to a second control line; in the display area, the first control line and the second control line are arranged in different layers, and the film layer where the second control line is located is located on a side of the film layer where the first control line is located away from the substrate; and the orthographic projections of the first control lines corresponding to at least some of the first-type dual-gate transistors on the substrate at least partially overlap with the orthographic projections of the second control lines on the substrate; The display panel further includes a second detection line. The second detection line has the same width as the second control line, and the second detection line is located away from an area overlapping with the first control line.

2. The display panel according to claim 1, wherein: The second detection line and the second control line are arranged on the same layer.

3. The display panel according to claim 1, wherein: An active layer is included between the film layer where the first control line is located and the film layer where the second control line is located, and the active portion of the first type of dual-gate transistor is located in the active layer; At least part of the orthographic projection of the first control line on the substrate overlaps with the orthographic projection of the active portion of the first type of dual-gate transistor on the substrate, and at least part of the orthographic projection of the second control line on the substrate overlaps with the orthographic projection of the active portion of the first type of dual-gate transistor on the substrate.

4. The display panel according to any one of claims 1 or 3, characterized in that: The second detection line is located in the non-display area.

5. The display panel according to claim 4, wherein: The non-display area includes at least one first virtual sub-pixel, the first virtual sub-pixel includes a second pixel circuit; the second pixel circuit includes at least a second type of transistor, and the second detection line is arranged in the same layer as the gate of the second type of transistor.

6. The display panel according to claim 5, wherein: The second type of transistor is a dual-gate transistor, wherein a first gate of the second type of transistor is manufactured in the same layer and process as the first gate of the first type of dual-gate transistor, a second gate of the second type of transistor is manufactured in the same layer and process as the second gate of the first type of dual-gate transistor, and a source and drain of the second type of transistor is manufactured in the same layer and process as the source and drain of the first type of dual-gate transistor; The second gate of the second type transistor is arranged in the same layer as the second detection line.

7. The display panel according to claim 4, wherein: The second control line and the second detection line are connected in the non-display area.

8. The display panel according to claim 4, wherein: The non-display area includes at least one second virtual sub-pixel, and the second virtual sub-pixel includes a third pixel circuit; The third pixel circuit at least includes a third type of dual-gate transistor, wherein the first gate of the third type of dual-gate transistor is manufactured in the same layer and process as the first gate of the first type of dual-gate transistor, the second gate of the third type of dual-gate transistor is manufactured in the same layer and process as the second gate of the first type of dual-gate transistor, and the source and drain of the third type of dual-gate transistor are manufactured in the same layer and process as the source and drain of the first type of dual-gate transistor; The non-display area includes at least one first detection line, the first gate of the third type dual-gate transistor is connected to the first detection line in the non-display area, the first detection line is connected to the first control line, and the first detection line and the first control line have the same layer and width.

9. The display panel according to claim 4, wherein: The non-display area includes at least one third virtual sub-pixel, and the third virtual sub-pixel includes a fourth pixel circuit; The fourth pixel circuit at least includes a fourth type of dual-gate transistor, wherein the first gate of the fourth type of dual-gate transistor is manufactured in the same layer and process as the first gate of the first type of dual-gate transistor, the second gate of the fourth type of dual-gate transistor is manufactured in the same layer and process as the second gate of the first type of dual-gate transistor, and the source and drain of the fourth type of dual-gate transistor are manufactured in the same layer and process as the source and drain of the first type of dual-gate transistor; The non-display area includes at least one first detection line, the first gate of the fourth type dual-gate transistor is connected to the first detection line in the non-display area, the line width of the first detection line is greater than the line width of the first control line, the line width of the first detection line is greater than the line width of the second detection line, and the orthographic projection of the first detection line on the substrate covers the orthographic projection of the second detection line on the substrate.

10. The display panel according to claim 3, wherein: The second detection line is located in the display area.

11. The display panel according to claim 10, wherein: In a direction perpendicular to the plane where the display panel is located, no metal structure is included between the second detection line and the substrate.

12. The display panel according to claim 11, wherein: The second detection line is floating; or, the second detection line is connected to a fixed potential.

13. The display panel according to claim 10, wherein: The first control line includes a first sub-segment and a second sub-segment, and the second control line includes a third sub-segment and a fourth sub-segment; An orthographic projection of the active portion of the first type of dual-gate transistor on the substrate overlaps with an orthographic projection of the first subsegment on the substrate, and an orthographic projection of the active portion of the first type of dual-gate transistor on the substrate overlaps with an orthographic projection of the third subsegment on the substrate; The line width of the first subsegment is greater than the line width of the second subsegment, and the line width of the third subsegment is greater than the line width of the fourth subsegment.

14. The display panel according to claim 13, wherein: The orthographic projection of the second subsegment on the substrate does not overlap with the orthographic projection of the fourth subsegment on the substrate; The fourth sub-segment is multiplexed as the second detection line.

15. The display panel according to claim 13, wherein: In a direction perpendicular to the plane where the display panel is located, the orthographic projection of the second subsegment on the substrate covers the orthographic projection of the fourth subsegment on the substrate; The fourth sub-segment is multiplexed as the second detection line.

16. The display panel according to claim 13, wherein: In a direction perpendicular to the plane where the display panel is located, the orthographic projection of the first subsegment on the substrate covers the orthographic projection of the third subsegment on the substrate.

17. The display panel according to claim 16, wherein: The third sub-segment is multiplexed as the second detection line.

18. The display panel according to claim 1, wherein The non-display area further includes a first transmission line; In the non-display area, the first control line and the second control line are electrically connected through a via hole; The first control line is connected to the first transmission line; or the second control line is connected to the first transmission line.

19. The display panel according to claim 5, wherein: The non-display area includes a first non-display area and a second non-display area, wherein the first non-display area and the second non-display area are respectively located on two opposite sides of the display area; The first virtual sub-pixel is located in the first non-display area, and the first control line is electrically connected to the second control line through a via hole in the second non-display area.

20. The display panel according to claim 5, wherein The non-display area includes a plurality of the first virtual sub-pixels, and the plurality of the first virtual sub-pixels are arranged around the display area; A plurality of the first sub-pixels are arranged along a first direction to form a first sub-pixel row, and a plurality of the first sub-pixel rows are arranged along a second direction, wherein the first direction and the second direction intersect; A plurality of first sub-pixels in one first sub-pixel row are electrically connected to the same first control line, and a plurality of first sub-pixels in one first sub-pixel row are electrically connected to the same second control line; At least one first sub-pixel row corresponds to one first virtual sub-pixel.

21. The display panel according to claim 20, wherein: The first virtual sub-pixels corresponding to different first sub-pixel rows are all located on the same side of the display area in the first direction.

22. The display panel according to claim 20, wherein: In the first direction, both sides of the display area include a first area and a second area that are oppositely arranged, and the first area and the second area are both located in the non-display area; At least some of the first virtual sub-pixels corresponding to the first sub-pixel rows are located in the first area, and at least some of the first virtual sub-pixels corresponding to the first sub-pixel rows are located in the second area.

23. The display panel according to claim 22, wherein: In two adjacent first sub-pixel rows, the first virtual sub-pixels corresponding to one of the first sub-pixel rows are located in the first area, and the first virtual sub-pixels corresponding to the other of the first sub-pixel rows are located in the second area.

24. The display panel according to claim 1, wherein The first pixel circuit further includes a plurality of thin film transistors, wherein the thin film transistors are P-type low temperature polysilicon transistors, and the first type of dual-gate transistors are N-type oxide transistors; The display panel further comprises at least a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer located on one side of the substrate; The gate of the thin film transistor is located in the first metal layer, the first control line and the first gate of the first type of dual-gate transistor are located in the second metal layer, the second control line and the second gate of the first type of dual-gate transistor are located in the third metal layer, and the source and drain of the thin film transistor and the source and drain of the first type of dual-gate transistor are located in the fourth metal layer.

25. The display panel according to claim 1, wherein The first pixel circuit includes a driving transistor, a data writing module, a compensation module, a first light emitting control module, a second light emitting control module, a first reset module and a second reset module that are electrically connected; A first end of the first light emitting control module is connected to a first power supply signal, and a second end of the first light emitting control module is connected to a first electrode of the driving transistor; A first end of the data writing module is connected to a data voltage signal, and a second end of the data writing module is connected to a first electrode of the driving transistor; A first end of the compensation module is connected to the gate electrode of the driving transistor, and a second end of the compensation module is connected to the second electrode of the driving transistor; A first end of the first reset module is connected to a first reset signal, and a second end of the first reset module is connected to the gate of the driving transistor; A first end of the second reset module is connected to a second reset signal, and a second end of the second reset module is connected to the anode of the light emitting element; A first end of the second light emitting control module is connected to the second electrode of the driving transistor, a second end of the second light emitting control module is connected to the anode of the light emitting element, and a cathode of the light emitting element is connected to a second power signal; The compensation module and / or the first reset module include the first type of dual-gate transistors.

26. The display panel according to claim 25, wherein: The first light emitting control module includes a first transistor, a gate of the first transistor is connected to a first light emitting control signal, a first electrode of the first transistor is connected to the first power supply signal, and a second electrode of the first transistor is connected to the first electrode of the driving transistor; The data writing module includes a second transistor, a gate of the second transistor is connected to the first scanning signal, a first electrode of the second transistor is connected to the data voltage signal, and a second electrode of the second transistor is connected to the first electrode of the driving transistor; The compensation module includes a third transistor, which is a dual-gate transistor of the first type, wherein a first gate of the third transistor is connected to a second scanning signal, a second gate of the third transistor is connected to the second scanning signal, a first electrode of the third transistor is connected to the gate of the driving transistor, and a second electrode of the third transistor is connected to the second electrode of the driving transistor; The first reset module includes a fourth transistor, the fourth transistor being a first-type dual-gate transistor, a first gate of the fourth transistor being connected to a third scan signal, a second gate of the fourth transistor being connected to the third scan signal, a first electrode of the fourth transistor being connected to the first reset signal, and a second electrode of the fourth transistor being connected to the gate of the driving transistor; The second light emitting control module includes a fifth transistor, a gate of the fifth transistor is connected to the second light emitting control signal, a first electrode of the fifth transistor is connected to the second electrode of the driving transistor, and a second electrode of the fifth transistor is connected to the anode of the light emitting element; The second reset module includes a sixth transistor, a gate of the sixth transistor is connected to a fourth scanning signal, a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the anode of the light emitting element.

27. A display device, characterized in that: A display panel comprising any one of claims 1-26.

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