Signal line pre-charge circuit, SOC chip, electronic device and pre-charge method

Abstract

The application relates to a signal line pre-charging circuit, an SOC chip, an electronic device and a pre-charging method, and belongs to the technical field of integrated circuits. The circuit comprises a first signal line, a second signal line, a first pre-charging transistor, a second pre-charging transistor, a first balancing tube and a second balancing tube. The first signal line is electrically connected with a power supply through the first pre-charging transistor, and the second signal line is electrically connected with the power supply through the second pre-charging transistor. The first balancing tube and the second balancing tube are respectively electrically connected with the first signal line and the second signal line. The first pre-charging transistor and the first balancing tube are simultaneously turned on or turned off, and the second pre-charging transistor and the second balancing tube are simultaneously turned on or turned off. When the first signal line and the second signal line do not have a specified operation for more than a preset time length, the first pre-charging transistor and the second pre-charging transistor are alternately turned on. The circuit makes any pre-charging transistor and balancing tube not always in the on state, thereby achieving the purpose of circuit anti-aging.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, specifically relating to a signal line pre-charging circuit, a SOC chip, an electronic device, and a pre-charging method. Background Technology

[0002] In chip design, chip aging is an unavoidable issue. Chip aging refers to the gradual degradation of the performance of the metal traces and components within a chip over time, leading to a significant decline in characteristics such as frequency and power consumption. After a few years of operation, the chip may fail to meet its performance specifications or even cease to function. Furthermore, as process nodes advance, chip aging becomes more pronounced with advanced processes. Therefore, it is essential to optimize and protect against chip aging during the chip design process, aiming to delay or mitigate aging and extend the chip's stable operational lifespan. Summary of the Invention

[0003] Therefore, the purpose of this application is to provide a signal line pre-charging circuit, a SOC chip, an electronic device, and a pre-charging method to delay or mitigate circuit aging and extend the lifespan of stable circuit operation.

[0004] The embodiments of this application are implemented as follows:

[0005] In a first aspect, embodiments of this application provide a signal line pre-charging circuit, comprising: a first signal line, a second signal line, a first pre-charging transistor, a second pre-charging transistor, a first balancing transistor, and a second balancing transistor; the first signal line is electrically connected to a power supply via the first pre-charging transistor, and the second signal line is electrically connected to a power supply via the second pre-charging transistor; when the first pre-charging transistor is turned on, the power supply charges the first signal line, and when the second pre-charging transistor is turned on, the power supply charges the second signal line; the first balancing transistor and the second balancing transistor are respectively electrically connected to the first signal line and the second signal line, and both the first balancing transistor and the second balancing transistor are used to balance the voltage on the first signal line and the voltage on the second signal line; wherein, the first pre-charging transistor and the first balancing transistor are simultaneously turned on or simultaneously turned off, and the second pre-charging transistor and the second balancing transistor are simultaneously turned on or simultaneously turned off; when the first signal line and the second signal line have not been operated for a preset time, the first pre-charging transistor and the second pre-charging transistor are alternately turned on.

[0006] In this embodiment, since the first precharge transistor and the second precharge transistor are alternately turned on, similarly, the first balanced transistor and the second balanced transistor are also alternately turned on. Thus, when the signal line precharge circuit is in standby mode for a long time or has no access operation for a long time, neither the precharge transistor nor the balanced transistor will be continuously turned on. The first precharge transistor, the first balanced transistor, and the second precharge transistor, the second balanced transistor are all in a state of being off for half the time. This significantly reduces the impact of NBTI (Negative Bias Temperature Instability) or PBTI (Positive Bias Temperature Instability) effects on device threshold characteristics, achieving the purpose of circuit anti-aging, thereby enabling the signal line precharge circuit to operate stably for a longer period.

[0007] In one possible implementation of the first aspect embodiment, the signal line pre-charging circuit further includes: a control module, specifically a first output terminal and a second output terminal, wherein the first output terminal is electrically connected to the first pre-charging transistor and the first balancing transistor, and the second output terminal is electrically connected to the second pre-charging transistor and the second balancing transistor, respectively; when the first signal line and the second signal line have not been operated for a preset time, the control module is used to alternately control the first pre-charging transistor and the second pre-charging transistor to be turned on.

[0008] In this embodiment, a control module is introduced to control the first pre-charge transistor, the first balance transistor, the second pre-charge transistor, and the second balance transistor, thereby eliminating the need for external devices or components for control. This makes it easier to control the pre-charge transistor and the balance transistor, thereby improving the applicability and control stability of the signal line pre-charge circuit.

[0009] In one possible implementation of the first aspect embodiment, the control module further includes a first input terminal, a second input terminal, and a third input terminal; the first input terminal is used to receive a first square wave signal, the second input terminal is used to receive a second square wave signal, and the third input terminal is used to receive a third square wave signal; the control module is used to alternately control the first precharge transistor and the second precharge transistor to be turned on according to the first square wave signal, the second square wave signal, and the third square wave signal.

[0010] In this embodiment, the first square wave signal, the second square wave signal, and the third square wave signal are used to alternately control the conduction of the first precharge transistor and the second precharge transistor. Since the control signal controlling the first precharge transistor and the second precharge transistor is constrained by the first square wave signal, the second square wave signal, and the third square wave signal, the control module is more convenient to control.

[0011] In one possible implementation of the first aspect embodiment, the control module includes: a first inverter, a first selection unit, a second inverter, and a second selection unit; the input terminal of the first inverter is used to receive the first square wave signal, the output terminal of the first inverter is connected to the first input terminal of the first selection unit and the first input terminal of the second selection unit respectively, the output terminal of the first selection unit is electrically connected to the first precharge transistor and the first balancing transistor respectively, the third input terminal of the first selection unit is used to receive the third square wave signal, and the input terminal of the second inverter is used to receive the second square wave signal; the output terminal of the second inverter is connected to the second input terminal of the first selection unit, and the second input terminal of the second selection unit is used to receive the second square wave signal; or, the output terminal of the second inverter is connected to the second input terminal of the second selection unit, and the second input terminal of the first selection unit is used to receive the second square wave signal; the output terminal of the second selection unit is connected to the second precharge transistor and the first balancing transistor respectively. The second balanced transistor is electrically connected, and the third input terminal of the second selection unit is used to receive the third square wave signal; when the first signal line and the second signal line have not been operated for a preset time, the first selection unit is used to selectively output the inverted signal of the second square wave signal according to the third square wave signal, and the second selection unit is used to selectively output the second square wave signal according to the third square wave signal; wherein, the input terminal of the first inverter is the first input terminal of the control module, the third input terminal of the first selection unit and the third input terminal of the second selection unit are both the third input terminals of the control module, the output terminal of the first selection unit is the first output terminal of the control module, and the output terminal of the second selection unit is the second output terminal of the control module; the input terminal of the second inverter and the second input terminal of the second selection unit are both the second input terminals of the control module, or the input terminal of the second inverter and the second input terminal of the first selection unit are both the second input terminals of the control module.

[0012] In this embodiment, the control module with the above-described structure allows one input signal of the first selection unit and the second selection unit to be generated by a first square wave signal, and the other input signal to be generated by a second square wave signal. The outputs of the first and second selection units depend on the third square wave signal. By changing the third square wave signal, the first and second selection units can choose to output an inverted signal of the first square wave signal, or output two opposite signals. For example, the first selection unit outputs the second square wave signal, and the second selection unit outputs an inverted signal of the second square wave signal; or, the first selection unit outputs an inverted signal of the second square wave signal, and the second selection unit outputs the second square wave signal. This allows for convenient control of the output signals of the first and second selection units as needed, enabling control of the first pre-charge transistor, the first balanced transistor, the second pre-charge transistor, and the second balanced transistor, ensuring that neither the pre-charge transistor nor the balanced transistor remains continuously in a conducting state. Furthermore, the use of low-cost components achieves the invention's objective while reducing design costs and complexity.

[0013] In one possible implementation of the first aspect embodiment, the control module further includes: a first buffer and a second buffer; the output terminal of the first selection unit is electrically connected to the first pre-charge transistor and the first balance transistor respectively through the first buffer; the output terminal of the second selection unit is electrically connected to the second pre-charge transistor and the second balance transistor respectively through the second buffer.

[0014] In this embodiment, a first buffer and a second buffer are introduced to hold the signals output by the first selection unit and the second selection unit, thereby improving the quality of the output signal and thus making the control effect better.

[0015] In one possible implementation of the first aspect embodiment, the control module includes: an AND gate, a first inverter, a second inverter, a first OR gate, and a second OR gate; the input terminal of the first inverter is used to receive the first square wave signal, the output terminal of the first inverter is connected to the first input terminal of the AND gate, the second input terminal of the AND gate is used to receive the third square wave signal, the output terminal of the AND gate is connected to the first input terminal of the first OR gate, the output terminal of the AND gate is also connected to the first input terminal of the second OR gate, and the output terminal of the first OR gate is electrically connected to the first precharge transistor and the first balancing transistor, respectively; the input terminal of the second inverter is used to receive the second square wave signal, and the output terminal of the second OR gate is electrically connected to the second precharge transistor and the second balancing transistor, respectively; the output of the second inverter... The first input terminal of the first inverter is connected to the second input terminal of the second OR gate, and the second input terminal of the second OR gate is used to receive the second square wave signal; or, the output terminal of the second inverter is connected to the second input terminal of the first OR gate, and the second input terminal of the second OR gate is used to receive the second square wave signal; wherein, the input terminal of the first inverter is the first input terminal of the control module, the second input terminal of the AND gate is the third input terminal of the control module, the output terminal of the first OR gate is the first output terminal of the control module, and the output terminal of the second OR gate is the second output terminal of the control module; the second input terminal of the first OR gate and the input terminal of the second inverter are both the second input terminals of the control module, or the second input terminal of the second OR gate and the input terminal of the second inverter are both the second input terminals of the control module.

[0016] In this embodiment, the control module with the above-described structure generates one input signal of the first OR gate and the second OR gate from a first square wave signal, and the other input signal from a second square wave signal. The third square wave signal serves as the input signal of the AND gate, controlling its output. When the third square wave signal is low, the outputs of the first OR gate and the second OR gate depend on the second square wave signal. At this time, the outputs of the first OR gate and the second OR gate are two opposite signals. For example, the first OR gate outputs the second square wave signal, and the second OR gate outputs the inverted signal of the second square wave signal; or, the first OR gate outputs the inverted signal of the second square wave signal, and the second OR gate outputs the second square wave signal. This achieves the purpose of alternately controlling the first precharge transistor and the second precharge transistor. Furthermore, it utilizes low-cost components, thus reducing design costs and complexity while achieving its inventive purpose.

[0017] In one possible implementation of the first aspect embodiment, if the signal line precharge circuit is applied to the memory, the third wave signal is a square wave signal obtained by performing an OR operation between the read signal and the write signal.

[0018] In this embodiment, when the signal line precharge circuit is applied to the memory, a square wave signal obtained by performing an OR operation between the read signal and the write signal is used as the control signal. This ensures that when the memory has not been read or written for a long time, neither the precharge transistor nor the balance transistor will be in a state of negative or positive gate voltage. This effectively reduces the influence of NBTI or PBTI on the precharge transistor and the balance transistor, achieving the design purpose of anti-aging.

[0019] In one possible implementation of the first aspect embodiment, if the signal line precharge circuit is applied to a sensitive amplifier, the third wave signal is a read signal.

[0020] In this embodiment, when the signal line precharge circuit is applied to the sensitive amplifier, the read signal is used as the control signal so that when the sensitive amplifier has no read operation for a long time, neither the precharge tube nor the balance tube will be in a state of negative gate voltage or positive gate voltage. This can effectively reduce the influence of NBTI or PBTI on the precharge tube and the balance tube, and achieve the design purpose of anti-aging.

[0021] Secondly, embodiments of this application also provide a SOC chip, including a signal line pre-charge circuit provided as described in the first aspect embodiments and / or in combination with any possible implementation of the first aspect embodiments.

[0022] In one possible implementation of the second aspect of the embodiment, the SOC chip is a memory or a sensitive amplifier.

[0023] Thirdly, embodiments of this application also provide an electronic device, including a body and a SOC chip provided as described in the second aspect embodiments and / or in combination with the second aspect embodiments.

[0024] Fourthly, embodiments of this application also provide a pre-charging method, comprising: using a first control signal to control the on / off state of a first pre-charging transistor located on a first signal line, wherein when the first pre-charging transistor is turned on, the first signal line is charged; using a second control signal to control the on / off state of a second pre-charging transistor located on a second signal line, wherein when the second pre-charging transistor is turned on, the second signal line is charged; wherein when the first signal line and the second signal line have not been operated for a preset time, the first control signal and the second control signal are opposite signals to each other, causing the first pre-charging transistor and the second pre-charging transistor to be turned on alternately.

[0025] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale to actual size; the focus is on illustrating the main points of this application.

[0027] Figure 1 This is a schematic diagram showing the connection between the signal line precharge circuit and the memory cell (bit cell) in a prior art memory.

[0028] Figure 2 A schematic diagram of the waveforms related to the pre-charge circuit for signal lines in an existing memory.

[0029] Figure 3 The diagram shows a circuit schematic of a signal line pre-charging circuit provided in an embodiment of this application.

[0030] Figure 4 The diagram shows a circuit schematic of another signal line pre-charging circuit provided in an embodiment of this application.

[0031] Figure 5 The diagram shows a circuit schematic of another signal line pre-charging circuit provided in an embodiment of this application.

[0032] Figure 6 The diagram shows a circuit schematic of another signal line pre-charging circuit provided in an embodiment of this application.

[0033] Figure 7 The diagram shows a circuit schematic of another signal line pre-charging circuit provided in an embodiment of this application.

[0034] Figure 8 An embodiment of this application is shown. Figure 6 The waveform diagram of the pre-charge circuit for the signal line is shown in the figure.

[0035] Figure 9 The diagram shows a circuit schematic of another signal line pre-charging circuit provided in an embodiment of this application.

[0036] Figure 10 The diagram shows a circuit schematic of another signal line pre-charging circuit provided in an embodiment of this application.

[0037] Figure 11A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0039] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0040] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can also refer to an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0042] In researching this application, the inventors discovered that, at current advanced process nodes, the main causes of chip aging include NBTI (Negative Bias Temperature Instability) or PBTI (Positive Bias Temperature Instability). NBTI primarily affects PMOS transistors (Metal Oxide Semiconductor Field Effect Transistors). Applying a negative gate voltage to a PMOS transistor for an extended period at high temperatures leads to the degradation of a series of electrical parameters, such as a negative shift in the threshold voltage and an increase in gate current, ultimately resulting in timing drift and device mismatch. Similarly, PBTI primarily affects NMOS transistors. Applying a positive gate voltage to an NMOS transistor for an extended period at high temperatures also leads to the degradation of a series of electrical parameters, such as a positive shift in the threshold voltage and an increase in gate current, ultimately resulting in timing drift and device mismatch.

[0043] In digital circuit design, circuits may remain in a fixed state for a long time. For example, for SOC (System on Chip) chips such as memory and sensitive amplifiers, the circuit may be in a signal line charging state for a long time. Therefore, NBTI or PBTI is a factor that needs special attention.

[0044] This application will describe an anti-aging scheme for signal line pre-charge circuits in SOC chips such as memory and sensitive amplifiers. It should be noted that the signal line pre-charge circuits provided in the embodiments of this application are not limited to applications in memory and sensitive amplifiers.

[0045] To better understand this application, the pre-charging principle of existing signal line pre-charging circuits will be explained below. Figure 1 This diagram illustrates the connection between the signal line precharge circuit and the memory cell (bit cell) in an existing memory. In the design of the signal line precharge circuit of existing SRAM memory, two cross-coupled PMOS transistors (P0 and P1) are generally used to charge two signal lines (BLT and BLC) with opposite phases, and then a PMOS transistor (P2) is added as a balancing transistor to balance the voltage of BLT and BLC. Figure 1 The P0 and P1 transistors are two pre-charged PMOS transistors that pre-charge the two signal lines, BLT and BLC, to VDD before read / write operations. Simultaneously, the balancing transistor P2 ensures that the BLT and BLC signal lines are at the same potential during charging. Figure 1 The meanings of the various signals involved are as follows:

[0046] WrEn: Write operation enable signal, active high;

[0047] RdEn: Read operation enable signal, active high;

[0048] BLT and BLC are two complementary signal lines that are pre-charged to a high level after the read / write operation is completed.

[0049] WL: Word line signal. When the word line WL is high, the corresponding memory cell (Bitcell) will be opened, and read or write operations will be performed on the Bitcell. The WL signal is only valid when WrEn = 1 or RdEn = 1.

[0050] Precharge: Signal line precharge enable signal, active high level. When the Precharge signal is high level, P0 and P1 precharge transistors are turned on, charging the BLT and BLC signal lines to high level.

[0051] Pchx: Signal line precharge enable signal, active low.

[0052] Figure 2 The diagram illustrates the waveforms of the precharge circuit for signal lines in an existing memory. When the WrEn or RdEn signal is active, the rising edge of the clock CLK signal triggers the rising edge (201) of the word line WL signal and the falling edge (202) of the Precharge signal. The rising edge of the WL signal triggers a write or read operation on the bit cell, while the falling edge of the Precharge signal triggers the rising edge (203) of the Pchx signal, turning off the precharge transistors P0 and P1 and the balance transistor P2, stopping the charging of the BLT and BLC signal lines. When the falling edge of the clock CLK signal arrives, it triggers the falling edge (204) of the WL signal, stopping the read and write operations on the bit cell. At the same time, the falling edge of the clock CLK signal will trigger the rising edge of the Precharge signal (205), and then the Pchx signal will go low (206), turning on P0 and P1 transistors to charge the BLT and BLC signal lines to VDD. Meanwhile, P2 transistor will turn on to ensure that the BLT and BLC signal lines are at the same potential.

[0053] If the memory has not been read or written for a long period of time, or if a certain memory in the entire system has not been accessed for a long period of time, then during this period, the precharge transistors P0, P1, and the balance transistor P2 of the signal line will always be in the conducting state (207). In this way, P0, P1, and P2 will be in a negative gate voltage state for a long time, and the effect of NBTI will be obvious. This will make the precharge transistors P0, P1, and the balance transistor P2 easily experience threshold voltage drift and other performance degradation due to aging after a period of time.

[0054] It should be noted that, Figure 2 The waveform diagram shown is based on Figure 1 The precharge and balance transistors shown are PMOS transistors used as examples. When the precharge and balance transistors are NMOS transistors, the waveform diagrams will change accordingly. For example, the Precharge signal and Pchx signal will flip.

[0055] In view of the problems in the pre-charge circuits of existing SOC chips such as memory and sensitive amplifiers, where the pre-charge transistor on the signal line has a negative gate voltage for a long time during long standby or without access, causing the NBTI effect or the PBTI effect caused by a positive gate voltage for a long time, this application proposes an optimized design scheme and introduces another control scheme to eliminate the continuous bias state of the pre-charge transistor during long standby or without memory access, thereby significantly reducing the NBTI or PBTI effect and achieving an anti-aging effect.

[0056] It should be noted that the defects in the above solutions are the result of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the inventors in the embodiments of the present invention below should be considered as contributions made by the inventors to the present invention.

[0057] The following will combine Figure 3 This application describes the signal line pre-charge circuit provided in its embodiments. Existing signal line pre-charge circuits suffer from the problem of prolonged negative gate voltage (NBTI) or prolonged positive gate voltage (PBTI) in the pre-charge transistors during long-term standby or without access operations. This application optimizes the circuit structure and control logic of the pre-charge and balance transistors in existing signal line pre-charge circuits. This ensures that even when the signal line pre-charge circuit is in standby mode or without access operations for extended periods, neither the pre-charge nor the balance transistor remains in a state of negative or positive gate voltage. This effectively reduces the impact of NBTI or PBTI on the pre-charge and balance transistors, achieving an anti-aging design objective.

[0058] The signal line pre-charge circuit provided in this application includes: a first signal line (such as a BLT signal line or a SAT signal line), a second signal line (such as a BLC signal line or a SAC signal line), a first pre-charge transistor (such as a P0 transistor), a second pre-charge transistor (such as a P1 transistor), a first balancing transistor (such as a P21 transistor), and a second balancing transistor (such as a P22 transistor). It should be noted that the P0, P1, P21, and P22 transistors in this application example are all PMOS transistors; in one embodiment, they can also be replaced with NMOS transistors. The switching principle of an NMOS transistor is the opposite of that of a PMOS transistor. Therefore, the fact that the first pre-charge transistor, the second pre-charge transistor, the first balancing transistor, and the second balancing transistor are PMOS transistors should not be construed as a limitation of this application.

[0059] The first signal line is electrically connected to the power supply (VDD) via a first pre-charge transistor, and the second signal line is electrically connected to the power supply (VDD) via a second pre-charge transistor. When the first pre-charge transistor is turned on, the power supply charges the first signal line; when the second pre-charge transistor is turned on, the power supply charges the second signal line. A first balancing transistor and a second balancing transistor are electrically connected to the first and second signal lines, respectively. Both transistors are used to balance the voltage on the first and second signal lines, ensuring that the voltage on the first and second signal lines is equal.

[0060] The first precharge transistor and the first balancing transistor are simultaneously turned on or off, and the second precharge transistor and the second balancing transistor are simultaneously turned on or off. When the first signal line and the second signal line have not been operated for a preset time (such as one clock cycle CLK) without a specified operation (such as an access operation including read operation or write operation), the first precharge transistor and the second precharge transistor are turned on alternately.

[0061] The signal line pre-charge circuit shown in this application, when the first and second signal lines have not been operated for a preset time, alternately conducts the first and second pre-charge transistors. Similarly, the first and second balanced transistors also conduct alternately. Thus, when the signal line pre-charge circuit is in standby mode for a long time or has not been accessed for a long time, neither the pre-charge transistor nor the balanced transistor will be continuously conducting. P0, P21, P1, and P22 transistors will be in the off state for half the time. This significantly reduces the impact of the NBTI effect on device threshold characteristics, achieving circuit anti-aging and allowing the signal line pre-charge circuit to operate stably for a longer period.

[0062] The signal line pre-charge circuit shown in this application controls the first pre-charge transistor (e.g., P0 transistor), the first balance transistor (e.g., P21 transistor), the second pre-charge transistor (e.g., P1 transistor), and the second balance transistor (e.g., P22 transistor) respectively by introducing two pre-charge enable signals Pchx0 and Pchx1, so that the first pre-charge transistor and the second pre-charge transistor can be turned on alternately.

[0063] In one optional implementation, the signal line pre-charging circuit shown in this application may further include: a control module, such as... Figure 4 As shown. The control module has a first output terminal and a second output terminal. The first output terminal is electrically connected to the first pre-charge transistor and the first balancing transistor, respectively, and the second output terminal is electrically connected to the second pre-charge transistor and the second balancing transistor, respectively. When the first signal line and the second signal line have not been operated for a preset time, the control module is used to alternately control the first pre-charge transistor and the second pre-charge transistor to conduct. For example, the control module can be used to output Pchx0 signal and Pchx1 signal to control the on / off state of transistors P0, P1, P21, and P22. Optionally, in addition to having a first output terminal and a second output terminal, the control module can also have a first input terminal, a second input terminal, and a third input terminal. In this case, the signal line pre-charge circuit, such as... Figure 5 As shown, it is understandable that if... Figure 5 If an OR gate is used as an internal component of the control module, then the control module will have four input terminals. It should be noted that, due to... Figure 5 The third wave signal in the equation is obtained by ORing the WrEn signal and the RdEn signal. Therefore, an OR gate is used to OR the WrEn signal and the RdEn signal. If the third wave signal is either the WrEn signal or the RdEn signal, then an OR gate is not needed; therefore, it cannot be used. Figure 5 The OR gates mentioned herein are to be understood as limitations on this application.

[0064] The first input terminal is used to receive a first square wave signal (which may be a Precharge signal), the second input terminal is used to receive a second square wave signal (which may be a clock CLK signal), and the third input terminal is used to receive a third square wave signal (which may be a WrEn signal, an RdEn signal, or a signal obtained by ORing the WrEn signal and the RdEn signal). In this application, the clock CLK signal is introduced to control the signal line precharge enable signal (Precharge signal), so that when the signal line precharge circuit is in standby mode for a long time or has no access operation for a long time, the precharge transistor and the balance transistor will not be in the conducting state indefinitely. This can significantly reduce the impact of the NBTI effect on the threshold and other characteristics of the device, and achieve the purpose of circuit anti-aging.

[0065] The control module is used to alternately control the first precharge transistor and the second precharge transistor to turn on according to the first square wave signal, the second square wave signal, and the third square wave signal. For example, when the first signal line and the second signal line have not been operated for a preset time, the control module alternately controls the first precharge transistor and the second precharge transistor to turn on according to the first square wave signal, the second square wave signal, and the third square wave signal.

[0066] When the control module has a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, in one optional implementation, the control module may include: a first inverter (e.g., A1), a first selection unit (e.g., U1), a second inverter (e.g., A2), and a second selection unit (e.g., U2). In this case, the control module may include, for example... Figure 6 as well as Figure 7 The two circuit structures are shown.

[0067] Understandably, due to Figure 6 , Figure 7 The third wave signal in the equation is obtained by ORing the WrEn signal and the RdEn signal. Therefore, an OR gate is used to OR the WrEn signal and the RdEn signal. If the third wave signal is either the WrEn signal or the RdEn signal, then an OR gate is not needed; therefore, it cannot be used. Figure 6 , Figure 7 The OR gates mentioned herein should be understood as limitations on this application. Furthermore, if... Figure 6 , Figure 7 If an OR gate located outside the dashed box is used as an internal component of the control module, then the control module also includes an OR gate.

[0068] It should be noted that, Figure 6 , Figure 7 The signal line pre-charge circuit shown is a schematic diagram of a control module including a first buffer (e.g., B1) and a second buffer (e.g., B2). In one embodiment, the control module may not include the first and second buffers, therefore it cannot be used... Figure 6 , Figure 7 The control module shown is to be understood as a limitation of this application.

[0069] The following will combine Figure 6 The connection methods of the various components inside the control module are explained. Figure 7 and Figure 6 The only difference is the location of the second inverter.

[0070] The input terminal of the first inverter is used to receive a first square wave signal (such as a precharge signal). The output terminal of the first inverter is connected to the first input terminal of the first selection unit and the first input terminal of the second selection unit, respectively. The output terminal of the first selection unit is electrically connected to the first precharge transistor and the first balancing transistor, respectively. The third input terminal of the first selection unit is used to receive a third square wave signal (which may be a WrEn signal, an RdEn signal, or a signal obtained by ORing the WrEn signal and the RdEn signal).

[0071] The input terminal of the second inverter is used to receive the second square wave signal (such as the clock CLK signal). The output terminal of the second inverter is connected to the second input terminal of the first selection unit. The second input terminal of the second selection unit is used to receive the second square wave signal. The output terminal of the second selection unit is electrically connected to the second precharge transistor and the second balancing transistor respectively. The third input terminal of the second selection unit is used to receive the third square wave signal.

[0072] The first selection unit is used to selectively output either the inverted signal of the second square wave signal or the inverted signal of the first square wave signal based on the third square wave signal. The second selection unit is used to selectively output either the second square wave signal or the inverted signal of the first square wave signal based on the third square wave signal. For example, when neither the first signal line nor the second signal line has specified an operation for a preset time, the first selection unit is used to selectively output the inverted signal of the second square wave signal based on the third square wave signal, and the second selection unit is used to selectively output the second square wave signal based on the third square wave signal, thereby causing the first precharge transistor and the second precharge transistor to be alternately turned on.

[0073] Wherein, the input terminal of the first inverter is the first input terminal of the control module, the input terminal of the second inverter and the second input terminal of the second selection unit are both the second input terminals of the control module, the third input terminal of the first selection unit and the third input terminal of the second selection unit are both the third input terminals of the control module, the output terminal of the first selection unit is the first output terminal of the control module, and the output terminal of the second selection unit is the second output terminal of the control module.

[0074] In one alternative implementation, such as Figure 6 , Figure 7 As shown, the control module further includes a first buffer (e.g., B1) and a second buffer (e.g., B2). In this case, the control module includes a first inverter, a first selection unit, a second inverter, a second selection unit, a first buffer, and a second buffer. The output of the first selection unit is electrically connected to the first pre-charge transistor and the first balancing transistor via the first buffer; the output of the second selection unit is electrically connected to the second pre-charge transistor and the second balancing transistor via the second buffer. In this case, the output of the first buffer is the first output of the control module, and the output of the second buffer is the second output of the control module.

[0075] The first selection unit and the second selection unit can be implemented in various ways. In one implementation, the first selection unit and the second selection unit can be or include a data selector (multiplexer). In addition, the first selection unit and the second selection unit can also be or include an arbitrator, which is used to selectively select one of the two received input signals for output based on a third wave signal.

[0076] See Figure 6 , Figure 7 It can be seen that one input signal of the first selection unit and the second selection unit is generated by the Precharge signal, and the other input signal is generated by the clock CLK signal. The first selection unit is used to generate the Pchx0 signal, and the second selection unit is used to generate the Pchx1 signal. The third wave signal serves as the control signal or selection signal for the first and second selection units, and is obtained by passing the WrEn signal and the RdEn signal through an OR gate. When there is a read or write operation, the third wave signal is 1 (representing a high level), and the first and second selection units select the input signal containing the Precharge signal for output, that is, output the inverted signal of the Precharge signal. When there is no read or write operation, the third wave signal is 0 (representing a low level), and the first and second selection units select the input signal containing the clock CLK signal for output. Figure 6 The first selection unit outputs the inverted clock CLK signal, and the second selection unit outputs the clock CLK signal. Figure 7 The first selection unit outputs the clock CLK signal, and the second selection unit outputs the inverted clock CLK signal.

[0077] To better understand the principle of the signal line pre-charge circuit shown in this application, the following will be combined with... Figure 8 The waveform diagram shown is used for illustration. It should be noted that... Figure 8 The waveform diagram shown

[0078] for Figure 6 The diagram shown illustrates the waveform of the signal line precharge circuit applied in a memory. At this time, Figure 6

[0079] The memory cell section and word line section are omitted, and only the control logic of the signal line precharge transistor is shown.

[0080] When a read or write operation is performed in the circuit, (WrEn|RdEn) = 1 (indicating a high level). The first selection unit and the second selection unit select the input signal where the Precharge signal is located for output, that is, output the inverted signal of the Precharge signal. At this time, the working state is consistent with the traditional precharge state. The precharge transistors P0 and P1 and the balance transistors P21 and P22 are controlled by the Precharge signal. When the rising edge of the clock CLK signal arrives, it will trigger the rising edge of the WL signal (401). The Bitcell will perform a read or write operation. At this time, it will trigger the falling edge of the Precharge signal (402). The Pchx0 and Pchx1 signals are pulled to a high level by the Precharge signal (403). The P0 and P1 transistors are turned off, stopping the charging of the signal lines. At the same time, the balance transistors P21 and P22 are also turned off. When the falling edge of the clock CLK signal arrives, it will trigger the falling edge of the WL signal (404). At this time, the Bitcell has completed the read / write operation, the Precharge signal becomes high (405), and then the Pchx0 and Pchx1 signals are pulled low (406). The P0 and P1 transistors start to conduct, charging the BLT and BLC signal lines. At the same time, the balance transistors P21 and P22 also conduct, clamping the BLT and BLC signal lines to the same potential.

[0081] When there is no read / write operation, (WrEn|RdEn) = 0 (representing a low level). The first selection unit outputs the inverted signal of the clock CLK signal, and the second selection unit outputs the clock CLK signal. That is, both the Pchx0 and Pchx1 signals are generated by the clock CLK signal. At this time, the phase of the Pchx0 signal is opposite to that of the clock CLK signal, and the phase of the Pchx1 signal is the same as that of the clock CLK signal. When the clock CLK signal is low, the Pchx0 signal is pulled high (407), and the Pchx1 signal is pulled low (408). At this time, the precharge transistor P1 and the balance transistor P22 are turned on, and the precharge transistor P0 and the balance transistor P21 are turned off. P1 will pull the BLC signal line to a high level, and through the balance transistor P22, it will also pull the BLT signal line to a high level, thus enabling the charging operation of the two signal lines. When the clock CLK signal is high, the Pchx0 signal is pulled low (409), and the Pchx1 signal is pulled high (410). At this time, P0 and P21 are turned on, and P1 and P22 are turned off. The precharge transistor P0 will pull the BLT signal line to high and pull the BLC signal line to high through P21.

[0082] As can be seen, when there are no read / write operations, the Pchx0 and Pchx1 signals are controlled by the clock CLK signal. Regardless of whether the clock CLK signal is high or low, one set of precharge transistors and balanced transistors will be turned on to charge the signal lines, while the other set of precharge transistors and balanced transistors will be turned off. As the clock CLK signal flips, the two sets of precharge transistors and balanced transistors can work alternately. While ensuring that the signal lines are charged, the first and second precharge transistors can work alternately. Therefore, transistors P0, P1, P21, and P22 can be in the off state for half the time, and will not be in a negative gate voltage state all the time. This can significantly reduce the impact of the NBTI effect on the threshold and other characteristics of the device, achieve the purpose of circuit anti-aging, and thus enable the memory to work stably for a longer period of time.

[0083] In another optional implementation, when the control module has a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, the control module may include an AND gate (such as AND1), a first inverter (such as A1), a second inverter (such as A2), a first OR gate (such as OR1), and a second OR gate (such as OR2). In this case, the control module includes... Figure 9 and Figure 10 Two schematic diagrams.

[0084] Understandably, due to Figure 9 , Figure 10 The third wave signal in the equation is obtained by ORing the WrEn signal and the RdEn signal. Therefore, an OR gate is used to OR the WrEn signal and the RdEn signal. If the third wave signal is either the WrEn signal or the RdEn signal, then an OR gate is not needed; therefore, it cannot be used. Figure 9 , Figure 10 The OR gates mentioned herein should be understood as limitations on this application. Furthermore, if... Figure 9 , Figure 10 If an OR gate located outside the dashed box is used as an internal component of the control module, then the control module also includes an OR gate.

[0085] The following will combine Figure 9 The connection methods of the various components inside the control module are explained. Figure 10 and Figure 9 The only difference is the location of the second inverter.

[0086] The first inverter has an input terminal for receiving a first square wave signal (such as a precharge signal), an output terminal for receiving a first square wave signal (such as a precharge signal), an output terminal for receiving a second square wave signal (such as a WrEn signal, an RdEn signal, or a signal obtained by ORing a WrEn signal and an RdEn signal), an output terminal for receiving a first square wave signal (such as a precharge signal, a precharge signal, or a signal obtained by ORing a WrEn signal and an RdEn signal), an output terminal for receiving a second square wave signal, and an output terminal for receiving a first precharge transistor and a first balancing transistor.

[0087] The input of the second inverter is used to receive the second square wave signal (such as the clock CLK signal). The output of the second inverter is connected to the second input of the second OR gate. The first input of the second OR gate is connected to the output of the AND gate. The output of the second OR gate is electrically connected to the second precharge transistor and the second balancing transistor, respectively.

[0088] Wherein, the input terminal of the first inverter is the first input terminal of the control module, the second input terminal of the first OR gate and the input terminal of the second inverter are both the second input terminals of the control module, the second input terminal of the AND gate is the third input terminal of the control module, the output terminal of the first OR gate is the first output terminal of the control module, and the output terminal of the second OR gate is the second output terminal of the control module.

[0089] It should be noted that, in one optional implementation, in Figure 9 , Figure 10 Based on the control module shown, it may further include a first buffer (such as B1) and a second buffer (such as B2), not shown in the figure. In this case, the output of the first OR gate is electrically connected to the first pre-charge transistor and the first balancing transistor through the first buffer, and the output of the second OR gate is electrically connected to the second pre-charge transistor and the second balancing transistor through the second buffer. In this case, the output of the first buffer is the first output of the control module, and the output of the second buffer is the second output of the control module.

[0090] See Figure 9 , Figure 10It can be seen that one input signal of the first OR gate and the second OR gate is generated by the Precharge signal, and the other input signal is generated by the clock CLK signal. The first OR gate is used to generate the Pchx0 signal, and the second OR gate is used to generate the Pchx1 signal. The third wave signal serves as the input signal of the AND gate, which is obtained by passing the WrEn signal and the RdEn signal through an OR gate. When there is a read or write operation, the third wave signal is 1, and the output of the AND gate depends on the Precharge signal. When the Precharge signal is high, the AND gate outputs a low level, and the outputs of the first OR gate and the second OR gate depend on the clock CLK signal; when the Precharge signal is low, the AND gate outputs a high level, and the outputs of the first OR gate and the second OR gate depend on the Precharge signal. When there is no read or write operation, the third wave signal is 0, the AND gate outputs a low level signal, and the outputs of the first OR gate and the second OR gate depend on the clock CLK signal.

[0091] When the outputs of the first OR gate and the second OR gate depend on the clock CLK signal, for Figure 9 For example, the first OR gate outputs the clock CLK signal, and the second OR gate outputs the inverted clock CLK signal. Figure 10 For example, the first OR gate outputs the inverted clock CLK signal, and the second OR gate outputs the clock CLK signal.

[0092] The signal line precharge circuit shown in this application embodiment can be applied to SOC chips such as memory and sensitive amplifiers. When the signal line precharge circuit is applied to a memory, the third wave signal is a square wave signal obtained by performing an OR operation between the read and write signals; alternatively, it can be either a read signal or a write signal alone. When the signal line precharge circuit is applied to a sensitive amplifier, where no write operation is involved, the third wave signal is a read signal. Specifically, when the signal line precharge circuit is applied to a memory, the first signal line and the second signal line can be bit lines BLT and BLC. When the signal line precharge circuit is applied to a sensitive amplifier, the first signal line and the second signal line can be data lines SAT and SAC.

[0093] The memory shown in this application can be a mainstream memory commonly found on the market, including but not limited to, Random Access Memory (RAM), Static Random Access Memory (SRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0094] Based on the same inventive concept, this application also provides a SOC chip including the above-described signal line pre-charge circuit. This SOC chip includes, but is not limited to, a memory or a sensitive amplifier.

[0095] The signal line pre-charge circuit provided in the SOC chip embodiment has the same implementation principle and technical effect as the aforementioned signal line pre-charge circuit embodiment. For the sake of brevity, any parts not mentioned in the SOC chip embodiment can be referred to the corresponding content in the aforementioned signal line pre-charge circuit embodiment.

[0096] Based on the same inventive concept, this application also provides an electronic device, which includes a body and a SOC chip as shown above, the SOC chip including at least the signal line pre-charge circuit described above. In one embodiment, the structural block diagram of the electronic device is as follows: Figure 11 As shown. The electronic device includes: a transceiver, a SOC chip, a communication bus, and a processor. The SOC chip includes, but is not limited to, memory or a sensitive amplifier.

[0097] Transceivers, SOC chips, and processors are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected via one or more communication buses or signal lines. The transceiver is used to send and receive data. If the SOC chip is a memory, it can be used to store computer programs, including at least one software functional module that can be stored in the SOC chip or embedded in the operating system (OS) of the electronic device in the form of software or firmware. The processor is used to execute the executable modules stored in the SOC chip.

[0098] A processor may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.

[0099] The aforementioned electronic devices include, but are not limited to, smartphones, tablets, computers, servers, etc.

[0100] Based on the same inventive concept, this application also provides a pre-charging method applied to the above-mentioned signal line pre-charging circuit. The pre-charging method includes steps S1 and S2.

[0101] S1: Use the first control signal to control the on / off state of the first precharge transistor located on the first signal line.

[0102] When the first pre-charge transistor is turned on, the first signal line is charged. The first control signal can be the Pchx0 signal mentioned above.

[0103] S2: Use the second control signal to control the on / off state of the second precharge transistor located on the second signal line.

[0104] When the second pre-charge transistor is turned on, the second signal line is charged. The second control signal can be the Pchx1 signal mentioned above.

[0105] When the first signal line and the second signal line have not been operated for a preset time, the first control signal and the second control signal are opposite signals, causing the first precharge transistor and the second precharge transistor to be turned on alternately.

[0106] The signal line pre-charging circuit provided in the method embodiment has the same implementation principle and technical effect as the aforementioned signal line pre-charging circuit embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned signal line pre-charging circuit embodiment.

[0107] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A signal line pre-charging circuit, characterized in that, include: First signal line, second signal line; A first precharge transistor and a second precharge transistor, wherein the first signal line is electrically connected to the power supply via the first precharge transistor, and the second signal line is electrically connected to the power supply via the second precharge transistor; when the first precharge transistor is turned on, the power supply charges the first signal line, and when the second precharge transistor is turned on, the power supply charges the second signal line. A first balancing transistor and a second balancing transistor, wherein the first balancing transistor is electrically connected to the first signal line and the second signal line respectively, and the second balancing transistor is electrically connected to the first signal line and the second signal line respectively, and both the first balancing transistor and the second balancing transistor are used to balance the voltage on the first signal line and the voltage on the second signal line; The first precharge transistor and the first balance transistor are simultaneously turned on or off, the second precharge transistor and the second balance transistor are simultaneously turned on or off, and when the first signal line and the second signal line have not been operated for a preset time, the first precharge transistor and the second precharge transistor are alternately turned on.

2. The signal line pre-charging circuit according to claim 1, characterized in that, The signal line pre-charging circuit further includes a control module, specifically a first output terminal and a second output terminal. The first output terminal is electrically connected to the first pre-charging transistor and the first balancing transistor, respectively, and the second output terminal is electrically connected to the second pre-charging transistor and the second balancing transistor, respectively. When the first signal line and the second signal line have not been operated for a preset time, the control module is used to alternately control the first precharge transistor and the second precharge transistor to be turned on.

3. The signal line pre-charging circuit according to claim 2, characterized in that, The control module also has a first input terminal, a second input terminal, and a third input terminal; The first input terminal is used to receive a first square wave signal, the second input terminal is used to receive a second square wave signal, and the third input terminal is used to receive a third square wave signal. The control module is used to alternately control the first precharge transistor and the second precharge transistor to turn on according to the first square wave signal, the second square wave signal, and the third square wave signal.

4. The signal line pre-charging circuit according to claim 3, characterized in that, The control module includes: a first inverter, a first selection unit, a second inverter, and a second selection unit; The input terminal of the first inverter is used to receive the first square wave signal. The output terminal of the first inverter is connected to the first input terminal of the first selection unit and the first input terminal of the second selection unit, respectively. The output terminal of the first selection unit is electrically connected to the first precharge transistor and the first balance transistor, respectively. The third input terminal of the first selection unit is used to receive the third square wave signal, and the input terminal of the second inverter is used to receive the second square wave signal. The output terminal of the second inverter is connected to the second input terminal of the first selection unit, and the second input terminal of the second selection unit is used to receive the second square wave signal; or, the output terminal of the second inverter is connected to the second input terminal of the second selection unit, and the second input terminal of the first selection unit is used to receive the second square wave signal. The output terminal of the second selection unit is electrically connected to the second precharge transistor and the second balance transistor, respectively, and the third input terminal of the second selection unit is used to receive the third wave signal; When the first signal line and the second signal line have not been operated for a preset time, the first selection unit is used to selectively output the inverted signal of the second square wave signal according to the third wave signal, and the second selection unit is used to selectively output the second square wave signal according to the third wave signal. Wherein, the input terminal of the first inverter is the first input terminal of the control module, the third input terminal of the first selection unit and the third input terminal of the second selection unit are both the third input terminals of the control module, the output terminal of the first selection unit is the first output terminal of the control module, and the output terminal of the second selection unit is the second output terminal of the control module; the input terminal of the second inverter and the second input terminal of the second selection unit are both the second input terminals of the control module, or the input terminal of the second inverter and the second input terminal of the first selection unit are both the second input terminals of the control module.

5. The signal line pre-charging circuit according to claim 4, characterized in that, The control module further includes: a first buffer and a second buffer; The output of the first selection unit is electrically connected to the first precharge transistor and the first balance transistor respectively through the first buffer; The output of the second selection unit is electrically connected to the second precharge transistor and the second balance transistor respectively through the second buffer.

6. The signal line pre-charging circuit according to claim 3, characterized in that, The control module includes: an AND gate, a first inverter, a second inverter, a first OR gate, and a second OR gate; The input terminal of the first inverter is used to receive the first square wave signal, the output terminal of the first inverter is connected to the first input terminal of the AND gate, the second input terminal of the AND gate is used to receive the third square wave signal, the output terminal of the AND gate is connected to the first input terminal of the first OR gate, the output terminal of the AND gate is also connected to the first input terminal of the second OR gate, and the output terminal of the first OR gate is electrically connected to the first precharge transistor and the first balance transistor respectively. The input terminal of the second inverter is used to receive the second square wave signal, and the output terminal of the second OR gate is electrically connected to the second precharge transistor and the second balancing transistor respectively; the output terminal of the second inverter is connected to the second input terminal of the second OR gate, and the second input terminal of the first OR gate is used to receive the second square wave signal; or, the output terminal of the second inverter is connected to the second input terminal of the first OR gate, and the second input terminal of the second OR gate is used to receive the second square wave signal. Wherein, the input terminal of the first inverter is the first input terminal of the control module, the second input terminal of the AND gate is the third input terminal of the control module, the output terminal of the first OR gate is the first output terminal of the control module, and the output terminal of the second OR gate is the second output terminal of the control module; the second input terminal of the first OR gate and the input terminal of the second inverter are both the second input terminals of the control module, or the second input terminal of the second OR gate and the input terminal of the second inverter are both the second input terminals of the control module.

7. The signal line pre-charging circuit according to any one of claims 3-6, characterized in that, If the signal line precharge circuit is applied to the memory, the third wave signal is a square wave signal obtained by performing an OR operation between the read signal and the write signal.

8. The signal line pre-charge circuit according to any one of claims 3-6, characterized in that, If the signal line precharge circuit is applied to a sensitive amplifier, the third wave signal is a read signal.

9. A SOC chip, characterized in that, Includes the signal line pre-charge circuit as described in any one of claims 1-8.

10. The SOC chip according to claim 9, wherein the SOC chip is a memory or a sensitive amplifier.

11. An electronic device, characterized in that, It includes the body and the SOC chip as described in claim 9 or 10.

12. A pre-charging method, characterized in that, The method, applied to the signal line pre-charge circuit as described in any one of claims 1-8, comprises: The first control signal is used to control the on / off state of the first pre-charge transistor located on the first signal line, wherein when the first pre-charge transistor is turned on, the first signal line is charged; The second control signal is used to control the on / off state of the second precharge transistor located on the second signal line, wherein when the second precharge transistor is turned on, the second signal line is charged; When the first signal line and the second signal line have not been operated for a preset time, the first control signal and the second control signal are opposite signals, causing the first precharge transistor and the second precharge transistor to be turned on alternately.

Images