Radar digital array antenna control method and device

Abstract

The present invention discloses a control method and device for a radar digital array antenna, belonging to the technical field of digital array radars, and is applied to a recording card after configuring working parameters. The method includes: loading a calibration control data packet, and based on the trigger of a synchronization pulse signal, playing back the calibration control data packet to the antenna array TR component, so that the antenna array TR component returns calibrated IQ data; forwarding the calibrated IQ data to a control terminal for disassembly calculation and arrangement to obtain a beam scanning data packet; loading the beam scanning data packet, and based on the trigger of a synchronization pulse signal, playing back the beam scanning data packet to the antenna array TR component, so that the antenna array TR component returns unit-level or sub-array-level echo IQ data; collecting the echo IQ data, and transferring and storing or playing it back to a radar information processing platform. The present invention uses a recording card to replace the traditional beamforming device, eliminating the heavy debugging work between the digital array and its beamforming device and timing module in the actual installation of the radar.

Description

Technical Field

[0001] The present invention relates to the technical field of digital array radars, and particularly relates to a radar digital array antenna control method and device. Background Art

[0002] Since the development of radars to date, they have fully entered the digital age, and all-digital array radars have become increasingly common, that is, unit-level digitization is achieved. Digital array radars have many advantages that cannot be compared with traditional phased array radars. Therefore, relevant research institutes have continuously carried out research on new technologies such as clutter rejection, anti-interference, and waveform diversity.

[0003] A digital array radar is an all-digital phased array radar in which both the receiving and transmitting beams are implemented digitally. Its core is a digital array TR component. A digital beamforming device is often used to control the transceiver of multiple digital array TR components, and they are connected by optical fiber. The beamforming device sends to the TR component a control packet including various waveform parameters, a transceiver switch, filter parameters, and timing. Usually, a radar needs to implement antenna array surface control to complete target detection experiments including beam transmission and echo reception. A typical system consists of multiple devices such as a display and control unit, a timing unit, a beamforming device, a signal processing unit, and a data processing unit. The system construction time is long and the workload is large. Since the internal control interface of the system has a high degree of customization, such as specific protocol content, communication rate, packet format, etc., and the number of array components is large, the beamforming device has characteristics such as a long debugging cycle and a large workload for upgrading and expansion. In the conventional system, it takes several weeks or even months to connect the entire system. If it is a new system or new technology, the time may be even longer. Downlink, the IQ data transmitted from the digital TR component to the digital beamforming device can be collected by a recording card and can be completely processed offline to reproduce all the signals and data processing effects of the actual radar installation, which is effective for verifying new systems and new algorithms. Most importantly, the offline platform has the characteristics of high versatility, efficient debugging, strong analysis means, and easy upgrading and expansion. Uplink, the control interface of the TR component is only an optical fiber, and the commands and timing are both included in the data. If the digital beamforming device can be simulated to send the corresponding data uplink, the control of the antenna array surface can be achieved. Therefore, using a recording device to replace the digital beamforming device to control the digital array TR and collect the echo IQ can greatly improve the efficiency of new technology exploration and verification.

[0004] To control multiple TR components to achieve beam transmission and reception, it is necessary to ensure strict synchronization of the data received at the TR component end and maintain a certain phase relationship with the basic clock, so as to achieve stable timing and continuous control. However, existing recorders / recording cards often cannot achieve precise control of the playback delay, and due to the traditional processing mechanism at the end of the file, uninterrupted continuous playback of multiple files or a single file looped multiple times cannot be achieved, and the recording card often uses centralized control and works independently, without a parallel alignment playback function.

[0005] In the related art, the Chinese invention patent application with application publication number CN109150490A discloses a multi-board pulse synchronization method based on FPGA optical fiber data transmission. Multiple digital receiving boards are connected to the optical fiber processing board through optical fiber. The optical fiber processing board uploads control instructions to the digital receiving board. The digital receiving board pre-processes the radar echo signal and transmits the processed data to the optical fiber processing board. The optical fiber processing board generates a reference synchronization pulse, adds some special characters to the control instruction by sending a control instruction, and restores the pulse signal when the digital receiving board receives the special character. Since the optical fiber delay of all boards is basically the same, the pulse signals restored by each board are at the same time, and the transmission and reception of all TR components at the front end of the control are at the same time, meeting the timing requirements of the system. The multi-board pulse synchronization method adopts the FPGA optical fiber data transmission method, and its uplink control command is generated by the FPGA itself, which solves the problem of synchronous control of radar TR components.

[0006] The Chinese utility model patent with the authorization announcement number CN204758755U discloses a parallel recording power system fault recorder based on high-speed serial communication, including a data acquisition module, a transient and long-state recording module, a sampling synchronization pulse generator, a real-time clock unit and an analysis terminal. The data acquisition module includes multiple data acquisition boards, each of which is used to collect analog quantities and switch quantities of the power system. The data output end of each data acquisition board is respectively connected to the transient analysis terminal, the output end of the sampling synchronization pulse generator is respectively connected to the synchronization pulse input end of each data acquisition board, and the output end of the real-time clock unit is respectively connected to the clock input end of the transient recording module and the long-state recording module. This solution solves the problem of two parallel recordings: transient recording and long-state recording. Summary of the invention

[0007] The technical problem to be solved by the present invention is how to realize high-speed synchronous playback of recorded data of multiple recording cards and realize rapid construction of a test system.

[0008] The present invention solves the above technical problems through the following technical means:

[0009] The present invention proposes a radar digital array antenna control method, which is applied to a record card after configuring working parameters, and the method comprises:

[0010] Loading a correction control data packet, and based on the triggering of a synchronization pulse signal, playing back the correction control data packet to the antenna array TR component, so that the antenna array TR component returns the corrected IQ data;

[0011] Forwarding the corrected IQ data to the control terminal for disassembly, calculation and arrangement to obtain a beam scanning data packet;

[0012] Load the beam scanning data packet, and trigger based on the synchronization pulse signal, and play back the beam scanning data packet to the antenna array TR component, so that the antenna array TR component returns unit-level or sub-array-level echo IQ data;

[0013] Collect the echo IQ data, and transfer and store or play it back to the radar information processing platform.

[0014] The present invention uses a recording card to replace the traditional beamforming device to realize the transceiver control and echo data acquisition of the digital array antenna TR component, omits the heavy debugging work between the digital array and its beamforming device and timing module in the actual installation of the radar, completes the control of the antenna array surface and the acquisition of echo data, and can realize the rapid construction of the test system.

[0015] Further, forwarding the corrected IQ data to the terminal for disassembly calculation and arrangement to obtain a beam scanning data packet includes:

[0016] Forward the corrected IQ data to the control terminal;

[0017] The control terminal performs disassembly calculation on the corrected IQ data to obtain the amplitude-phase correction coefficients of each TR channel;

[0018] The control terminal arranges beam scanning coefficients based on the correction coefficients and the scanning range to obtain the beam scanning data packet.

[0019] Further, the synchronization pulse signal is coherent with the reference clock of the antenna array TR component.

[0020] Further, the working parameters of the recording card include the playback delay, playback period, internal / external Fr trigger, playback times, optical fiber rate, and channel number of each playback channel;

[0021] The correction control data packet carries transmission correction parameters and reception correction parameters;

[0022] The information carried by the beam scanning data packet includes the phase of each channel of the TR component, signal type, bandwidth, pulse width, and operating frequency.

[0023] Further, the method further includes:

[0024] Load the data packet played back to the TR component into the first-level cache;

[0025] When transferring the data in the first-level cache to the second-level cache, judge the integrity and data size of the forwarded data based on the data segment identifier;

[0026] Forward the data with correct judgment results as valid data to the second-level cache.

[0027] In addition, the present invention also provides a control device for a radar digital array antenna. The device includes: a control terminal, a synchronization pulse generator, an antenna array TR component, and several recording cards. The several recording cards and the synchronization pulse generator are connected to a reference clock that is homologous to the antenna array TR component. The recording cards are connected to the control terminal and the radar information processing platform;

[0028] The synchronization pulse generator is used to generate a pulse signal coherent with the reference clock to synchronize the timing of several recording cards and the active array surface;

[0029] The control terminal is used to set the working parameters of the recording cards, generate calibration control data packets and beam scanning data packets;

[0030] The recording card includes a first loading module, a playback module, a forwarding module, a second loading module, and an acquisition module, where:

[0031] The first loading module is used to load the calibration control data packet;

[0032] The playback module is used to, triggered by the first synchronization pulse signal sent by the synchronization pulse generator, playback the calibration control data packet to the antenna array TR component, so that the antenna array TR component returns calibrated IQ data;

[0033] The forwarding module is used to forward the calibrated IQ data to the control terminal for disassembly calculation and arrangement to obtain a beam scanning data packet;

[0034] The second loading module is used to load the beam scanning data packet and, triggered by the second synchronization pulse signal sent by the synchronization pulse generator, playback the beam scanning data packet to the antenna array TR component, so that the antenna array TR component returns unit-level or sub-array-level echo IQ data;

[0035] The acquisition module is used to acquire the echo IQ data and transfer and store or playback it to the radar information processing platform.

[0036] Further, the control terminal includes:

[0037] The disassembly calculation module is used for the control terminal to perform disassembly calculation on the calibrated IQ data to obtain the amplitude-phase correction coefficients of each TR channel;

[0038] The arrangement module is used for the control terminal to arrange beam scanning coefficients based on the correction coefficients and the scanning range to obtain the beam scanning data packet.

[0039] Further, the working parameters include playback delay, playback period, internal / external Fr trigger, number of playback times, optical fiber rate, and number of channels;

[0040] The calibration control data packet carries transmission calibration parameters and reception calibration parameters;

[0041] The beam scanning data packet carries the phase of each channel of the TR component, signal type, bandwidth, pulse width, and operating frequency.

[0042] Further, the recording card uses a ZYNQ chip as the main control and interface chip.

[0043] Further, the recording card includes a cache module, and the cache module includes a first-level cache and a second-level cache;

[0044] The first-level cache is used to directly load the data packet, determine the valid data in the data packet within the ZYNQ based on the data segment identifier, extract and forward it to the second-level cache.

[0045] The advantages of the present invention are as follows:

[0046] (1) The present invention uses a recording card to replace the traditional beamforming device to achieve the transceiver control and echo data acquisition of the TR component of the digital array antenna, eliminating the heavy debugging work between the digital array and its beamforming device and timing module in the radar installation, completing the control of the antenna array surface and the acquisition of echo data, and enabling the rapid construction of the test system.

[0047] (2) The control parameters of the TR component of the antenna array can be edited through the control terminal. The recording card has multiple optical rates that can be set, with good adaptability, and can be applied to all-digital array radars and sub-array digital radars, with a wide range of applications.

[0048] (3) By adopting a two-level cache technology, the echo data of single or multiple files can be played back continuously without gaps, effectively ensuring the continuous control of the digital array TR component and meeting the continuous long-time uninterrupted operation of the system.

[0049] (4) By using two low-cost devices, namely a pulse signal generator and multiple recording cards, the control and echo storage of multiple digital array TR components can be well completed, and the measured echo data can be quickly obtained. Moreover, the recording card uses a ZYNQ chip as the main control and interface chip, which greatly reduces the volume and cost of the equipment for the radar digital array antenna.

[0050] (5) The invention adopts a parallel architecture, which can well expand the number of controlled TR components and can also be used alone for TR component debugging and testing. It can effectively ensure the real-time synchronization of echo data playback among channels in the recording card and between different recording cards, with an alignment accuracy reaching the nanosecond level, and can accurately control the delay of each channel, effectively solving the out-of-sync problem caused by hardware cable transmission, and can be used for remote control and distributed control.

[0051] Additional aspects and advantages of the present invention will be given in part in the following description, will become apparent in part from the following description, or will be learned through the practice of the present invention. Brief Description of the Drawings

[0052] Figure 1 is a schematic flowchart of the radar digital array antenna control method in the first embodiment of the present invention;

[0053] Figure 2 is a schematic flowchart of the control of the antenna array TR components in the first embodiment of the present invention;

[0054] Figure 3 is a schematic framework diagram of the radar digital array antenna control device in the second embodiment of the present invention;

[0055] Figure 4 is a schematic diagram of the connection of multi-recording card synchronization signals in the second embodiment of the present invention;

[0056] Figure 5 is a schematic diagram of the structure of the recording card in the second embodiment of the present invention;

[0057] Figure 6 is a multi-recording card synchronous playback timing diagram in the present invention;

[0058] Figure 7 is a multi-recording card playback delay fine-tuning timing diagram in the present invention;

[0059] Figure 8 is a schematic diagram of the realization of continuous playback by the two-level cache mechanism of the recording card in the present invention. Detailed Embodiments

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0061] As Figures 1 to 2As shown in the figure, the first embodiment of the present invention proposes a method for controlling a radar digital array antenna, which is applied to a recording card after configuring working parameters. The method includes the following steps:

[0062] S10. Load a calibration control data packet, and trigger based on a synchronization pulse signal to replay the calibration control data packet to the antenna array TR component, so that the antenna array TR component returns calibrated IQ data;

[0063] It should be noted that the calibration control data packet is generated by a control terminal and loaded by each recording card.

[0064] S20. Forward the calibrated IQ data to the control terminal for disassembly calculation and arrangement to obtain a beam scanning data packet;

[0065] S30. Load the beam scanning data packet, and trigger based on a synchronization pulse signal to replay the beam scanning data packet to the antenna array TR component, so that the antenna array TR component returns unit-level or sub-array-level echo IQ data;

[0066] It should be noted that the synchronization pulse signal is generated by a pulse signal generator.

[0067] S40. Collect the echo IQ data and transfer and store or replay it to a radar information processing platform.

[0068] It should be noted that in this embodiment, the radar information processing platform is general and is used to analyze and sort out the echo IQ data.

[0069] In this embodiment, a recording card is used to replace the traditional beamforming device to realize the transceiver control and echo data acquisition of the digital array antenna TR component, eliminating the heavy debugging work between the digital array and its beamforming device and timing module in the radar installation, completing the control of the antenna array surface and the acquisition of echo data, and enabling the rapid construction of the test system.

[0070] In one embodiment, the recording card model is RDS-PCIE-1.2GBps-4TB, using a ZYNQ chip as the main control and interface chip, having multi-channel multi-mode optical interfaces, GTX, as well as PCIE3.0, network, USB interfaces, serial ports, and using an SSD solid-state disk as the storage medium. The number of channels of each recording card is ≥4, the optical interface rate is not less than 10Gbps / channel, there are 4 solid-state disks in total, and the storage rate is ≥1.5GB / s.

[0071] In one embodiment, in step S20, when the control terminal disassembles, calculates, and arranges the calibrated IQ data to obtain a beam scanning data packet, it includes the following steps:

[0072] Forward the corrected IQ data to the control terminal;

[0073] The control terminal disassembles and calculates the corrected IQ data to obtain the amplitude-phase correction coefficients of each TR channel;

[0074] The control terminal arranges beam scanning coefficients based on the correction coefficients and the scanning range to obtain the beam scanning data packet.

[0075] It should be noted that data disassembly is to analyze data, including the data header and IQ data therein, and generally multiple channels of data are combined and packed together.

[0076] In one embodiment, the synchronization pulse signal is coherent with the reference clock of the antenna array TR component.

[0077] Specifically, the synchronization pulse generator that generates the synchronization pulse signal and the recording card are connected to the reference clock that is homologous to the antenna array TR component.

[0078] In one embodiment, the operating parameters of the recording card include the playback delay, playback period, internal / external Fr trigger, playback times, optical fiber rate, and number of channels of each playback channel;

[0079] The correction control data packet carries transmission correction parameters and reception correction parameters;

[0080] The beam scanning data packet carries the phase of each channel of the TR component, signal type, bandwidth, pulse width, and operating frequency.

[0081] It should be noted that the operating parameters of the recording card, the correction control data packet, and the beam scanning data packet are all generated by the control terminal. The control parameters for the TR component can be edited by the control terminal. The recording card has multiple optical rates that can be set, with good adaptability, and can be applied to all-digital array radars and sub-array digital radars, and has a wide range of applications.

[0082] In one embodiment, the method further includes the following steps:

[0083] Load the data packet into the first-level cache;

[0084] When transferring the data in the first-level cache to the second-level cache, judge the integrity and data size of the forwarded data based on the data segment identifier;

[0085] Forward the data with correct judgment results as valid data to the second-level cache.

[0086] In this embodiment, by adding fields to represent whether the data segment is complete and the size of the complete data under the minimum processing unit of the recording card, each time the recording card reads data from the SSD disk and places it into the first-level cache, a complete judgment of the data packet will be performed in the FIFO from the first-level cache to the second-level cache. By parsing the fields of the completeness flag and the complete data size, the data packets that are incomplete and do not meet the size requirements are removed as invalid data. In this way, the second-level cache is all continuous control parameter data. A method of zero-interruption cyclic playback is realized, effectively solving the problem of discontinuous playback caused by non-integral segment processing at the end of the file during single-file cyclic playback or multi-file consecutive playback in the traditional playback method, and avoiding the jitter problem of the TR component and the discontinuous problem of system operation caused by discontinuous received data.

[0087] In addition, as Figure 3 shown, a radar digital array antenna control device is proposed in the second embodiment of the present invention. The device includes: a control terminal 10, a synchronization pulse generator 20, an antenna array TR component 30, and a plurality of recording cards 40. The plurality of recording cards 40 and the synchronization pulse generator 20 are connected to a reference clock that is homologous to the antenna array TR component 30. The recording card 40 is connected to the control terminal 10 and the radar information processing platform;

[0088] The synchronization pulse generator 20 is used to generate a pulse signal coherent with the reference clock to synchronize the timing of the plurality of recording cards 40 and the active array surface;

[0089] The control terminal 10 is used to set the working parameters of the recording card 40, generate calibration control data packets and beam scanning data packets;

[0090] The recording card 40 includes a first loading module, a playback module, a forwarding module, a second loading module, and an acquisition module, where:

[0091] The first loading module is used to load the calibration control data packet;

[0092] The playback module is used to trigger based on the first synchronization pulse signal sent by the synchronization pulse generator 20 and play back the calibration control data packet to the antenna array TR component 30, so that the antenna array TR component 30 returns calibrated IQ data;

[0093] The forwarding module is used to forward the calibrated IQ data to the control terminal 10 for disassembly calculation and arrangement to obtain a beam scanning data packet;

[0094] The second loading module is used to load the beam scanning data packet, and based on the trigger of the second synchronization pulse signal sent by the synchronization pulse generator 20, replay the beam scanning data packet to the antenna array TR component 30, so that the antenna array TR component 30 returns unit-level or sub-array-level echo IQ data;

[0095] The acquisition module is used to acquire the echo IQ data and transfer and store or replay it to the radar information processing platform.

[0096] Specifically, as Figure 4 shown, the recording cards 40 are connected in parallel, and several recording cards 40 are interconnected with the synchronization pulse generator 20 through RF cables. Both the recording cards 40 and the synchronization pulse generator 20 are connected to the 10MHz / 20MHz reference clock that is homologous to the digital array TR component.

[0097] Specifically, the recording card 40 is connected to each TR component in the radar digital array antenna one by one, and the calibration channel is connected to the recording card 40.

[0098] The synchronization pulse generator 20 is designed using the system homologous 10MHz clock and has a function of adjustable pulse period, meeting the requirements of 1Hz to 100Hz. It is used to generate a synchronization pulse signal coherent with the reference clock of the array TR component to synchronize the timing of multiple recording cards 40 and the active array surface.

[0099] This solution adopts a parallel architecture, which can well expand the number of controlled TR components, and can also be used alone for TR component debugging and testing; it can effectively ensure the real-time synchronization of the echo data playback of each channel in the recording card 40 and between different recording cards 40, and the alignment accuracy can reach the ns level, and can accurately control the delay of each channel, effectively solving the out-of-synchronization problem caused by hardware cable transmission, and can be used for remote control and distributed control.

[0100] As Figure 5 shown, the recording card 40 uses a ZYNQ chip as the main control and interface chip, has multi-channel multi-mode optical interfaces, GTX, and PCIE3.0, network, USB interfaces, and serial ports, and uses an SSD solid-state disk as the storage medium. The number of channels of each recording card 40 ≥ 4, the optical interface rate is not less than 10Gbps / channel, there are 4 solid-state disks in total, and the storage rate ≥ 1.5GB / s. It has the functions of fiber optic playback and fiber optic data storage to simultaneously complete the uplink control of the array TR and the storage of the downlink IQ echo.

[0101] In this embodiment, a recording card is used to replace the traditional beamforming device to achieve the transceiver control and echo data acquisition of the TR components of the digital array antenna, eliminating the heavy debugging work between the digital array, its beamforming device, and the timing module in the actual radar installation, completing the control of the antenna array surface and the acquisition of echo data, and enabling the rapid construction of the test system.

[0102] In one embodiment, the control terminal 10 includes:

[0103] A disassembly calculation module, which is used for the control terminal 10 to disassemble and calculate the corrected IQ data to obtain the amplitude-phase correction coefficients of each TR channel;

[0104] An arrangement module, which is used for the control terminal 10 to arrange the beam scanning coefficients based on the correction coefficients and the scanning range to obtain the beam scanning data packet.

[0105] In one embodiment, the working parameters include playback delay, playback period, internal / external Fr trigger, number of playback times, fiber optic rate, and number of channels;

[0106] The correction control data packet carries transmission correction parameters and reception correction parameters;

[0107] The beam scanning data packet carries the phase of each channel of the TR component, signal type, bandwidth, pulse width, and operating frequency.

[0108] Furthermore, the recording card 40 is triggered by the coherent synchronization signal sent by the synchronization pulse generator 20. After the synchronization pulse signal triggers each recording card 40 and each channel of the recording card 40, by setting the playback delay time of the control terminal 10, it is ensured that the phase range of the moment when each TR component receives the playback data and the reference clock strictly satisfies a difference of 0.3 - 0.7 cycles from the rising edge of the reference clock.

[0109] For the recording card 40, the control terminal 10 can separately set the time of the delayed playback of the synchronization pulse signal for each recording card 40 and each channel, stepping in units of 5 ns, so as to correct the problem of non-strict synchronization of the received data of the TR components caused by the too long and uneven lengths of the optical fibers between multiple recording cards 40 and the TR components and the jitter of the optoelectronic conversion timing.

[0110] Such as Figure 6As shown in the figure, for the synchronous alignment design timing of the recording card 40, after all the recording cards 40 are connected, when data playback is required, the control terminal 10 sends a playback instruction to each recording card 40 through the network. Each recording card 40 reads the files in the disk and caches the data in the DDR. Since the file playback preparation times of each board are different, after the control terminal 10 receives the status ready returned by each board, the trigger signal emission switch of the synchronous pulse generator 20 is turned on. After each board receives the trigger signal, data playback is uniformly performed at the rising edge of the next reference clock.

[0111] As Figure 7 shown in the figure, for the delay design timing after synchronous alignment of each recording card 40, by setting the delay, the alignment moment of each TR component is adjusted. For example, if the intervals between different TR components in the sparse array are relatively far and the lengths of the optical cables and cables vary greatly, so the reference is not strictly aligned, then playback delay is used for correction. Direct synchronous playback can be regarded as a special mode with a delay of zero. When each board receives the synchronous trigger signal, after the next reference clock arrives, the data is played back after a fixed delay. The fixed time of this delay is measured using the 200MHz clock inside the FPGA in ZYNQ, and the delay accuracy is 5ns. It can be designed as an integer multiple of 5ns to adjust the playback delay of each board for playback. That is, the delay can be set by 1 * 5ns, 2 * 5ns, 3 * 5ns...

[0112] In one embodiment, the recording card 40 includes a cache module, and the cache module includes a first-level cache and a second-level cache;

[0113] The first-level cache is used to load the data packet file, determine the valid data in the data packet based on the data segment identifier, and forward it to the second-level cache.

[0114] As Figure 8As shown, for the two - level cache of the system to achieve continuous uninterrupted control function, in the traditional acquisition and playback mode of the recording device, since the minimum unit of the input data and the stored data of the recording device is inconsistent, generally, 0s or special characters are filled to the minimum unit before storage. As a result, there will be a segment of invalid data playback at the end of each file playback. The final result is that the TR component of the system receives discontinuous or incorrect parameters. This design adopts the method of two - level cache plus data segment identification. Under the minimum processing unit of the recording device, a field is added to indicate whether the segment of data is complete and the size of the complete data. In this case, ZYNQ reads data from the SSD disk into the first - level cache each time. In the FIFO from the first - level cache to the second - level cache, the integrity of the data packet will be judged. By parsing the fields of whether it is complete and the size of the complete data, the redundant invalid data can be removed between the first - and second - level caches. In this way, all the data in the second - level cache is continuous control parameter data, and there will be no remaining invalid data at the end of the file or during file switching. In this way, single - file loop playback or multi - file consecutive playback will not have any interruption, ensuring that the control packets received by the digital TR component are continuous and complete, and avoiding the generation of jitter, out - of - order, and out - of - control situations.

[0115] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer - readable medium for use by an instruction execution system, apparatus, or device (such as a computer - based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer - readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in combination with an instruction execution system, apparatus, or device. More specific examples (non - exhaustive list) of computer - readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read - only memory (ROM), an erasable programmable read - only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read - only memory (CDROM). Additionally, the computer - readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0116] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following technologies well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0117] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0118] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0119] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A control method for a radar digital array antenna, characterized in that, applied to a record card after configuring working parameters, the method includes: loading a calibration control data packet, and triggering based on a synchronization pulse signal, playing back the calibration control data packet to the antenna array TR component, so that the antenna array TR component returns calibrated IQ data; forwarding the calibrated IQ data to a control terminal for disassembly calculation and arrangement to obtain a beam scanning data packet; loading the beam scanning data packet, and triggering based on a synchronization pulse signal, playing back the beam scanning data packet to the antenna array TR component, so that the antenna array TR component returns unit-level or sub-array-level echo IQ data; acquiring the echo IQ data, and transferring and storing or playing it back to a radar information processing platform.

2. The control method for a radar digital array antenna according to claim 1, characterized in that, the forwarding the calibrated IQ data to a terminal for disassembly calculation and arrangement to obtain a beam scanning data packet includes: forwarding the calibrated IQ data to the control terminal; the control terminal performs disassembly calculation on the calibrated IQ data to obtain amplitude-phase calibration coefficients of each TR channel; the control terminal arranges beam scanning coefficients based on the calibration coefficients and the scanning range to obtain the beam scanning data packet.

3. The control method for a radar digital array antenna according to claim 1, characterized in that, the synchronization pulse signal is coherent with the reference clock of the antenna array TR component.

4. The control method for a radar digital array antenna according to claim 1, characterized in that, the working parameters include playback delay, playback period, internal / external Fr trigger, playback times, optical fiber rate, and number of channels; the calibration control data packet carries transmit calibration parameters and receive calibration parameters; the information carried by the beam scanning data packet includes phases of each channel of the TR component, signal type, bandwidth, pulse width, and operating frequency.

5. The control method for a radar digital array antenna according to claim 1, characterized in that, the method further includes: loading the data packet played back to the TR component into a first-level cache; when transferring the data in the first-level cache to a second-level cache, judging the integrity and data size of the forwarded data based on a data segment identifier; forwarding the data with a correct judgment result as valid data to the second-level cache.

6. A control device for a radar digital array antenna, characterized in that, the device includes: a control terminal, a synchronization pulse generator, an antenna array TR component, and several record cards. Several said record cards and the synchronization pulse generator are connected to a reference clock homologous to the antenna array TR component, and the record cards are connected to the control terminal and a radar information processing platform; the synchronization pulse generator is used to generate a pulse signal coherent with the reference clock to synchronize the timings of several said record cards and the active array surface; the control terminal is used to set the working parameters of the record card, generate a calibration control data packet and a beam scanning data packet; the record card includes a first loading module, a playback module, a forwarding module, a second loading module, and an acquisition module, wherein: The first loading module is used to load the calibration control data packet; The playback module is used to, triggered by the first synchronization pulse signal sent by the synchronization pulse generator, playback the calibration control data packet to the antenna array TR component, so that the antenna array TR component returns calibrated IQ data; The forwarding module is used to forward the calibrated IQ data to the control terminal for disassembly calculation and arrangement to obtain a beam scanning data packet; The second loading module is used to load the beam scanning data packet, and triggered by the second synchronization pulse signal sent by the synchronization pulse generator, playback the beam scanning data packet to the antenna array TR component, so that the antenna array TR component returns unit-level or sub-array-level echo IQ data; The acquisition module is used to acquire the echo IQ data and transfer and store or playback it to the radar information processing platform.

7. The radar digital array antenna control device according to claim 6, wherein, the control terminal includes: The disassembly calculation module is used for the control terminal to perform disassembly calculation on the calibrated IQ data to obtain the amplitude-phase calibration coefficients of each TR channel; The arrangement module is used for the control terminal to arrange beam scanning coefficients based on the calibration coefficients and the scanning range to obtain the beam scanning data packet.

8. The radar digital array antenna control device according to claim 6, wherein, the operating parameters of the recording card include the playback delay, playback period, internal / external Fr trigger, playback times, optical fiber rate, and number of channels of each playback channel; The calibration control data packet carries transmission calibration parameters and reception calibration parameters; The beam scanning data packet carries the phase of each channel of the TR component, signal type, bandwidth, pulse width, and operating frequency.

9. The radar digital array antenna control device according to claim 6, wherein, the recording card uses a ZYNQ chip as the main control and interface chip.

10. The radar digital array antenna control device according to claim 6, wherein, the recording card includes a cache module, and the cache module includes a first-level cache and a second-level cache; The first-level cache is used to directly load the data packet, determine the valid data in the data packet within the ZYNQ based on the data segment identifier, extract and forward it to the second-level cache.

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