Execution Method and Device for Host Command

Abstract

The present invention relates to a method and apparatus for executing host commands. The method is implemented by a host interface in a flash memory controller and includes: detecting whether there are a default number of consecutive host long write commands, where the first starting logical block address number indicated by each host long write command is not aligned with the first physical page of a superpage in the flash memory module; if so, calculating an offset such that the second starting logical block address number indicated by the host write command can be aligned with the first physical page of a superpage after adding the offset; and storing a record in a logical block address displacement table, including information on the second starting logical block address number and the offset. Thus, through the record as described above, the present invention can avoid the starting logical block address number requested by subsequent host commands from being misaligned.

Description

Technical Field

[0001] The present invention relates to a storage device, and in particular, to a method and apparatus for executing host commands. Background Art

[0002] Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. A central processing unit (Host) can provide any address for accessing NOR flash memory on an address pin and obtain data stored at that address from a data pin of the NOR flash memory in a timely manner. In contrast, NAND flash memory is not random access but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processing unit needs to write the value of serial bytes into the NAND flash memory to define the type of a request command (such as read, write, erase, etc.) and the address used for this command. The address can point to a page (the smallest data block for a write operation in the flash memory) or a block (the smallest data block for an erase operation in the flash memory).

[0003] Generally speaking, a flash memory controller executes commands issued by a host side in a first-in first-out order, such as a host read command, a host write command, a host erase-write command, etc., to read user data from a specified address of a flash memory cell, write user data to a specified address of the flash memory cell, or erase-write a specified physical block in the flash memory cell. Efficiently executing host commands issued by the host side has always been an important issue. Therefore, the present invention provides a method and apparatus for executing host commands to improve the execution efficiency of host commands. Summary of the Invention

[0004] In view of this, how to alleviate or eliminate the deficiencies in the above-related fields is indeed a problem to be solved.

[0005] The present invention relates to a method for executing a host command, which is executed by a host interface in a flash memory controller and includes: detecting whether there are a default number of consecutive host long write commands, where a first starting logical block address number indicated by each host long write command is not aligned with a first physical page of a super page in a flash memory module; if so, calculating an offset so that a second starting logical block address number indicated by the host write command can be aligned with a first physical page of a super page after adding the offset; adding the offset to the second starting logical block address number to generate a third starting logical block address number; storing a record in a logical block address displacement table, including information on the second starting logical block address number and the offset; and outputting the third starting logical block address number associated with the host write command to a specified position in a command queue, so that a firmware conversion layer drives a flash memory interface to write data to the flash memory module according to the third starting logical block address number associated with the host write command.

[0006] The present invention also relates to an execution device for host commands, comprising: a flash memory interface; a random access memory; a processing unit; and a host interface. The random access memory configures a space for a command queue. The host interface includes a logical block address conversion circuit for detecting whether there are a default number of consecutive host long write commands, wherein the first starting logical block address number indicated by each host long write command is not aligned with the first physical page of a superpage in the flash memory module; if so, calculating an offset such that the second starting logical block address number indicated by the host write command plus the offset can be aligned with the first physical page of a superpage in the flash memory module; adding the second starting logical block address number and the offset to generate a third starting logical block address number; storing a record in the logical block address displacement table, including information on the second starting logical block address number and the offset; and outputting the third starting logical block address number associated with the host write command to a specified position in the command queue, so that the processing unit drives the flash memory interface to write data to the flash memory module according to the third starting logical block address number associated with the host write command when executing the program code of the firmware conversion layer.

[0007] One of the advantages of the above embodiments is that through the setting of the logical block address conversion circuit as described above, the firmware conversion layer can be reduced from spending time and computing resources to fill and write unnecessary dummy data to the flash memory module when driving the flash memory interface to write data.

[0008] Another advantage of the above embodiments is that it reduces the time and computing resources spent by the firmware conversion layer to read these unnecessary dummy data from the flash memory module when driving the flash memory interface to read data.

[0009] Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application.

[0011] Figure 1 It is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 It is a schematic diagram of a flash memory module according to an embodiment of the present invention.

[0013] Figure 3 It is a schematic diagram of a command queue according to an embodiment of the present invention.

[0014] Figure 4Schematic diagram of a super page according to an embodiment of the present invention.

[0015] Figure 5 Schematic diagram of filling dummy data when the starting logical block address (LBA) number is not aligned with the first physical page of a super page.

[0016] Figure 6 Block diagram of an LBA conversion circuit for a host write command according to an embodiment of the present invention.

[0017] Figure 7 Flowchart of a processing method for a host write command according to an embodiment of the present invention.

[0018] Figure 8 Block diagram of an LBA conversion circuit for a host read command or a host erase command according to an embodiment of the present invention.

[0019] Figure 9 Flowchart of a processing method for a host read command or a host erase command according to an embodiment of the present invention.

[0020] Description of reference numerals

[0021] 10 Electronic device

[0022] 110 Host side

[0023] 130 Flash memory controller

[0024] 131 Host interface

[0025] 132 Bus architecture

[0026] 134 Processing unit

[0027] 136 Random access memory

[0028] 138 Direct memory access controller

[0029] 139 Flash memory interface

[0030] 150 Flash memory module

[0031] 151 Interface

[0032] 153#0 to 153#15 NAND flash memory cells

[0033] CH#0 to CH#3 Channels

[0034] CE#0 to CE#3 Enable signals

[0035] 300 Command queue

[0036] 400#0~1, 410#0~1, 420#0~1, 430#0~1 data plane

[0037] P#0, P#1, P#2, P#n, P#n + 1, P#n + 2, P#n + 3 superpages

[0038] 60 is the LBA conversion circuit for the host write command

[0039] 610 LBA displacement table

[0040] 632 divider

[0041] 634, 652, 662, 664, 682, 810 comparators

[0042] 636, 656, 663, 684, 698, 820, 840 output circuits

[0043] 640 AND gate

[0044] 654, 696, 830 adders

[0045] 670 counter

[0046] 692 calculator

[0047] 694 write circuit

[0048] S710~S780 method steps

[0049] S910~S940 method steps Detailed implementation manners

[0050] The embodiments of the present invention will be described below in conjunction with the relevant drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0051] It must be understood that the words "comprising", "including", etc. used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, operations, components, and / or components, but do not exclude the addition of more technical features, numerical values, method steps, operations, components, components, or any combination of the above.

[0052] In the present invention, words such as "first", "second", "third", etc. are used to modify the components in the claims, and are not used to indicate a priority order, precedence relationship, or that one component precedes another component, or the time sequence when performing method steps, but are only used to distinguish components with the same name.

[0053] It should be understood that when a component is described as "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and intermediate components may be present. Conversely, when a component is described as "directly connected" or "directly coupled" to another component, there are no intermediate components. Other words used to describe the relationship between components can be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", and so on.

[0054] Reference Figure 1. The electronic device 10 includes: a host side 110, a flash memory controller 130, and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as the device side. The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers, tablet computers, mobile phones, digital cameras, digital video cameras, etc. The host interface 131 of the host side 110 and the flash memory controller 130 can communicate with each other through communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), Embedded Multi-Media Card (eMMC), etc. The flash memory interface 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other through a Double Data Rate (DDR) communication protocol, for example, Open NAND Flash Interface (ONFI), DDR Toggle, or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general hardware (for example, a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and provides the functions described later when executing software and / or firmware instructions. The processing unit 134 receives host commands through the host interface 131, such as read commands, write commands, erase commands, etc., schedules and executes these commands.The flash memory controller 130 also includes a Random Access Memory (RAM) 136, which can be implemented as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or a combination of the two, for configuring space as a data buffer to store user data (also known as host data) read from the host side 110 and about to be written to the flash memory module 150, as well as user data read from the flash memory module 150 and about to be output to the host side 110. The random access memory 136 can also store data required during the execution process, such as variables, data tables, a Host-to-Flash (H2F) Table, a Flash-to-Host (F2H) Table, etc. The flash memory interface 139 includes a NAND Flash Controller (NFC), providing functions required for accessing the flash memory module 150, such as a Command Sequencer, Low Density Parity Check (LDPC), etc.

[0055] A configurable bus architecture 132 can be provided in the flash memory controller 130 for coupling components to each other to transfer data, addresses, control signals, etc. These components include: a host interface 131, a processing unit 134, a RAM 136, a Direct Memory Access (DMA) controller 138, a flash memory interface 139, etc. The DMA controller 138 can transfer data between components through the bus architecture 132 according to instructions from the processing unit 134. For example, it can transfer data in a specific data buffer in the host interface 131 or the flash memory interface 139 to a specific address in the RAM 136, and transfer data at a specific address in the RAM 136 to a specific data buffer in the host interface 131 or the flash memory interface 139.

[0056] The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (GB), or even multiple terabytes (TB), for storing a large amount of user data, such as high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can be configured as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof after being erased. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 and reads user data from a specified address (source address) in the flash memory module 150 through the flash memory interface 139. The flash memory interface 139 uses multiple electronic signals to coordinate the transfer of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines, clock signals, and control signals. The data lines can be used to transfer commands, addresses, read and written data; the control signal lines can be used to transfer control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), write enable (WE), etc.

[0057] Reference Figure 2 , the interface 151 in the flash memory module 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3. Each channel is connected to four NAND flash memory cells. For example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8, and 153#12, and so on. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can activate one of the activation signals CE#0 to CE#3 through the interface 151 to activate NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15, and then read user data from the activated NAND flash memory cells in parallel, or write user data to the activated NAND flash memory cells.

[0058] In some embodiments, a logical block address (LBA, managed by the host 110) may correspond to 512 bytes of data. The host 110 may issue a host write command to the processing unit 134 through the host interface 131, requesting the device side to write data of multiple LBAs (e.g., 64, 128, 256, etc.) to the flash memory module 150. In addition, the host 110 may issue a host read command to the processing unit 134 through the host interface 131, requesting to read data of multiple LBAs from the device side. To make data access efficient, the processing unit 134 may drive the flash interface 139 to write the data of these LBAs into multiple NAND flash cells in an input / output channel in parallel, or read the data of these LBAs from multiple NAND flash cells in an input / output channel in parallel.

[0059] In some embodiments, the RAM 136 configures space for a command queue, which is used to store commands sent by the host 110 in the order of arrival at the flash controller 130, such as host read commands, host write commands, host erase commands, etc. Refer to Figure 3 , the command queue 300 contains a collection formed by multiple entries. Each entry in the command queue 300 may store a host command, such as a host read command (represented by "R"), a host write command (represented by "W"), etc. The basic principle of operation of the command queue 300 is to add entries (which can be called enqueue) from the end position (such as the position pointed to by the pointer T), and remove entries (which can be called dequeue) from the start position (such as the position pointed to by the pointer H). That is, the first command added to the command queue 300 will also be the first to be removed, conforming to the First-In First-Out (FIFO) principle.

[0060] A NAND flash cell may contain multiple data planes, each data plane contains multiple physical blocks, and each physical block may contain multiple physical pages. Each physical page may store data of multiple (e.g., 16, 32, 64, etc.) LBAs. For example, refer to Figure 4, each NAND flash memory cell contains 2 data planes. NAND flash memory cell 153#0 contains data planes 400#0 and 400#1, NAND flash memory cell 153#1 contains data planes 410#0 and 410#1, and so on. Each physical page can store 16 LBA of data, that is, 8 KB of data. A specific page in NAND flash memory cells 153#0 to 153#3 can form a Super Page for storing 128 LBA of data, that is, 64 KB of data. For example, the 0th physical page of the 0th physical block in all data planes of NAND flash memory cells 153#0 to 153#3 forms a Super Page P#0, the 1st physical page of the 0th physical block in all data planes of NAND flash memory cells 153#0 to 153#3 forms a Super Page P#1, and so on. To optimize the access performance of the flash memory module 150, the processing unit 134 can drive the flash memory interface 139 to write the data of LBA#0 to LBA#127 into Super Page P#0, write the data of LBA#128 to LBA#255 into Super Page P#1, and so on. After that, the processing unit 134 can drive the flash memory interface 139 to read the data of LBA#0 to LBA#127 from Super Page P#0, read the data of LBA#128 to LBA#255 from Super Page P#1, and so on.

[0061] The host 110 can issue a host write command to the processing unit 134 through the host interface 131 to request writing specific data, such as a File System, a Root Directory, User Files, etc. For example, Table 1 shows an example correspondence table between LBA ranges and host data:

[0062] Table 1

[0063] LBA Range Host Data 0x0 to 0x4EFF File System and Root Directory 0x4F00 to 0x204EFF First User File (1GB) 0x204F00 to 0x404EFF Second User File (1GB) 0x404F00 to 0x404F07 Third User File (4KB) 0x404F08 to 0x604F07 Fourth User File (1GB) 0x604F08 to 0x804F07 Fifth User File (1GB) 0x804F08 to 0xA04F07 Sixth User File (1GB) 0xA04F08 to 0xC04F07 Seventh User File (1GB) : :

[0064] The LBA ranges of the file system and the root directory are from "0x0" to "0x4EFF", the LBA range of the first user file is from "0x4F00" to "0x204EFF", and so on.

[0065] To optimize the storage performance, the length of the data requested by each host write command issued by the host 110 does not exceed the super page length. However, if the starting LBA number indicated by a host write command cannot be aligned with the first physical page of a super page in the flash memory module 150, the data write performance will be significantly reduced. For example, to write the fourth user file, the host 110 sequentially issues multiple host write commands to the device side, respectively requesting to write data with LBA ranges of "0x404F08" to "0x404F87", "0x404F88" to "0x405007", "0x405008" to "0x405087", "0x405088" to "0x405107", etc. In some embodiments, when the firmware translation layer (FTL) is executed by the processing unit 134, these host write commands are received through the command queue 300. Then, for each host write command, 64KB of data is written into 2 super pages, and dummy data is filled in the appropriate positions. Refer to Figure 5 Part (a) of, the FTL generates 64KB of data for two super pages for the 64KB of data with the LBA range of "0x404F08" to "0x404F87". The first 64KB of data sequentially includes 4KB of dummy data and 60KB of data with the LBA range of "0x404F08" to "0x404F7F". The second 64KB of data sequentially includes 4KB of data with the LBA range of "0x404F80" to "0x404F87" and 60KB of dummy data. Then, the FTL drives the flash memory interface 139 to write the first 64KB of data into the super page P#n in the flash memory module 150, and writes the second 64KB of data into the super page P#n+1 in the flash memory module 150, where "n" represents a positive integer. Refer to Figure 5 Part (b) of, the FTL generates 64KB of data for two super pages for the 64KB of data with the LBA range of "0x404F88" to "0x405007". The first 64KB of data sequentially includes 4KB of dummy data and 60KB of data with the LBA range of "0x404F88" to "0x404FFF". The second 64KB of data sequentially includes 4KB of data with the LBA range of "0x405000" to "0x405007" and 60KB of dummy data. Then, the FTL drives the flash memory interface 139 to write the first 64KB of data into the super page P#n+2 in the flash memory module 150, and writes the second 64KB of data into the super page P#n+3 in the flash memory module 150, where "n" represents a positive integer. From Figure 5As can be seen from the example, the FTL takes time and computing resources to fill in false data, and the flash memory module 150 also takes time and storage space to write these useless false data, resulting in a significant decrease in the data writing efficiency. In addition, when executing a host read command for these data, the flash memory module 150 takes time to read these useless false data, and the FTL takes time and computing resources to remove the false data, resulting in a significant decrease in the data reading efficiency.

[0066] To solve the above problems, in an embodiment of the present invention, a dedicated LBA conversion circuit (LBA Shifting Circuit) is provided in the host interface 131 to detect whether there are a default number of successive host long-write commands, and the starting LBA number indicated by each host long-write command is not aligned with the first physical page of a super page in the flash memory module 150. If so, calculate an offset so that the starting LBA number indicated by this host write command plus the offset can be aligned with the first physical page of a super page in the flash memory module 150. Then, store a record in the LBA displacement table, including the starting LBA number (as the separation LBA number) indicated by this host write command and the information of the offset, for enabling the starting LBA number after the separation LBA number to be aligned with the first physical page of a super page in the flash memory module 150 after adding the offset. Then, output this host write command to the command queue 300, where parameters such as the changed starting LBA number and the write length are carried, for enabling the FTL to drive the flash interface 139 according to this host write command to perform the corresponding write operation.

[0067] In addition, the dedicated LBA conversion circuit is also used to add the offset to the starting LBA number of this host write command or host read command when the starting LBA number carried in a host write command, host read command or host erase command is equal to the separation LBA number or falls after the separation LBA number. Then, output this host write command or host read command to the command queue 300, where parameters such as the changed starting LBA number and the write or read length are carried, for enabling the FTL to drive the flash interface 139 accordingly to perform the corresponding write or read operation.

[0068] With reference to Figure 6 The embodiment of the LBA conversion circuit 60 for the host write command shown is an embodiment of a method for processing a host write command executed in the host interface 131 according to an embodiment of the present invention. The details are as follows:

[0069] Step S710: Receive a host write command from the host 110. The host write command carries at least parameters such as a command code, a starting LBA number "LBA_start", and a length "LEN", and these parameters are stored in the registers in the host interface 131. The registers in the host interface 131 also record an LBA displacement table 610 for storing information on separating LBA numbers and offsets. For simplicity of description, the embodiments of the present invention describe that the LBA displacement table 610 stores a record of a pair of separated LBA numbers "LBA_sft" and an offset "Offset". Initially, the LBA displacement table 610 may contain a record with a separated LBA number of "0xFFFFFF" and an offset of "0x0". The host interface 131 also includes a register for storing the ending LBA number of the previous host write command plus 1, "LBA_pre_end + 1".

[0070] Step S720: Determine whether the starting LBA number "LBA_start" is greater than or equal to the separated LBA number "LBA_sft" recorded in the LBA displacement table. If so, the process continues with the processing in step S730; otherwise, the process continues with the processing in step S740. For example, when the LBA conversion circuit 60 starts running, the comparator 652 is first started with the signal "EN". The comparator 650 compares the starting LBA number with the separated LBA number in the LBA displacement table 610. If the starting LBA number is greater than or equal to the separated LBA number, a signal is output to start the adder 654; otherwise, a signal is output to the AND gate 640.

[0071] Step S730: Add the offset "Offset" recorded in the LBA displacement table 610 to the starting LBA number, and output the added result to a specified position in the command queue 300. For example, the adder 654 adds the offset "Offset" recorded in the LBA displacement table 610 to the starting LBA number "LBA_start", and drives the output circuit 656 to output the added result to a specified position in the command queue 300.

[0072] Step S740: Determine whether n unaligned consecutive host long write commands are detected, where "n" is a positive integer greater than 1. If so, the process proceeds with the processing in step S750; otherwise, the process proceeds with the processing in step S780. For example, "n" is set to 4.

[0073] For example, when the LBA conversion circuit 60 starts running, it starts the divider 632 with the signal "EN" to divide the starting LBA number by the maximum number of LBAs that a superpage can contain (such as 128, represented by "0x80"). The divider 632 also drives the comparator 634 and outputs the calculated remainder "r" to the comparator 634. The comparator 634 is used to determine whether the remainder is equal to 0. If so, it means that the starting LBA number of this host write command is aligned with the first physical page of a superpage, and the comparator 634 outputs a signal to start the output circuit 636. If the remainder is not equal to 0, it means that the starting LBA number of this host write command is not aligned with the first physical page of a superpage, and the comparator 634 outputs a signal to the AND gate 640.

[0074] When the LBA conversion circuit 60 starts running, it starts the comparator 662 with the signal "EN" to determine whether the length requested by this host write command is equal to or greater than the maximum number of LBAs that a superpage can contain. If it is equal, it means that this host write command is a long write command, and the comparator 662 outputs a signal to the AND gate 640. If it is less, it means that this host write command is not a long write command, and the comparator 662 outputs a signal to start the output circuit 663.

[0075] When the AND gate 640 receives three input signals, it means that the comparator 634 detects that the starting LBA number of this host write command is not aligned with the first physical page of a superpage, the comparator 652 detects that the starting LBA number of this host write command is less than the dividing LBA number recorded in the LBA displacement table 610, and the comparator 662 detects that this host write command is a long write command. The AND gate 640 outputs a signal to start the comparator 664.

[0076] The comparator 664 compares whether the starting LBA number is equal to the ending LBA number of the previous host write command plus 1 "LBA_pre_end + 1". If so, it means that this host write command and the previous host write command form a continuous write operation, and the comparator 664 outputs a signal to increment the counter 670 by 1. If the starting LBA number is not equal to the ending LBA number of the previous host write command plus 1, it means that this host write command and the previous host write command do not form a continuous write operation, and the comparator 664 outputs a signal to reset the counter 670 to 0. The value output by the counter 670 represents the number of continuous host write commands.

[0077] After the counter 670 is changed, it outputs the count value "CNT" and drives the comparator 682. The comparator 682 compares whether the count value is greater than or equal to the default value (such as "0x4"). If so, it means that the default number of consecutive host long write commands is detected. The comparator 682 outputs a signal to drive the calculator 692, the write circuit 694, and the adder 696. If the count value is less than the default value, the comparator 682 outputs a signal to drive the output circuit 684.

[0078] Step S750: Calculate the offset of the first physical page that can align the starting LBA number with the super page. For example, when the 8 least significant bits of the starting LBA label are greater than "0x80", the calculator 692 subtracts the starting LBA label from "0x100" to obtain the offset "Offset". When the 8 least significant bits of the starting LBA label are less than "0x80", the calculator 692 subtracts the starting LBA label from "0x80" to obtain the offset "Offset".

[0079] Step S760: Update the content in the LBA displacement table 610 to store the information of this starting LBA number (as the separated LBA number) and the offset. For example, the write circuit 694 overwrites the original separated LBA number "LBA_sft" in the LBA displacement table 610 with this starting LBA number "LBA_start", and overwrites the original offset in the LBA displacement table 610 with the calculated offset. It should be noted here that the updated LBA displacement table 610 will be written to the flash memory module 150 as a backup at an appropriate time point to prevent sudden power off (SPO).

[0080] Step S770: Add the calculated offset "Offset" to the starting LBA number, and output the added result to the specified position in the command queue 300. For example, the adder 696 adds the offset "Offset" output by the calculator 692 to the starting LBA number "LBA_start", and drives the output circuit 698 to output the added result to the specified position in the command queue 300. It should be noted that the added result can be divisible by the length of a super page.

[0081] Step S780: Output the starting LBA number to the specified position in the command queue 300. For example, when the output circuits 636, 663, or 684 are driven, they output the starting LBA number "LBA_start" to the specified position in the command queue 300.

[0082] Although Figure 6The output circuits 636, 663, and 684 shown in the embodiments are different components, but those skilled in the art can implement any two or all of the output circuits 636, 663, and 684 as the same component, and the present invention is not limited thereby. Although Figure 6 the paired adders 654 and output circuits 656, and the adders 696 and output circuits 698 shown in the embodiments are different paired components, but those skilled in the art can implement the paired adders 654 and output circuits 656, and the adders 696 and output circuits 698 as the same pair of components, and the present invention is not limited thereby.

[0083] Next, based on the host data shown in Table 1, assume that the host 110 issues a series of host write commands shown in Table 2 to request the device to write data for the fourth user file:

[0084] Table 2

[0085]

[0086]

[0087] Since the LBA conversion circuit 60 detects 4 unaligned consecutive host long write commands when processing the host write command "W#3" (the "yes" path in step S740), calculates an offset of "0x78" (step S750); updates the content in the LBA displacement table 610 to store the information separating the LBA number "0x405088" and the offset "0x78" (step S760); and outputs the updated starting LBA number "0x405100" to the specified position in the command queue 300.

[0088] Next, since the starting LBA numbers of the host write commands after the host write command "W#4" are all greater than the separating LBA number "0x405088" recorded in the LBA displacement table 610 (the "yes" path in step S720), the LBA conversion circuit 60 adds the offset "0x78" recorded in the LBA displacement table 610 to each starting LBA number, and outputs the sum to the specified position in the command queue 300 (step S730). Table 3 shows the changes in the starting LBA numbers after being processed by the LBA conversion circuit 60:

[0089] Table 3

[0090]

[0091] In combination with the reference Figure 8The following is an embodiment of the LBA conversion circuit 80 for a host read command or a host erase command. An embodiment of the present invention provides a method for processing a host read command or a host erase command executed in the host interface 131. The details are as follows:

[0092] Step S910: Receive a host read or erase command from the host 110. The host read or erase command carries at least parameters such as a command code, a starting LBA number "LBA_start", and a length, and these parameters are stored in the registers in the host interface 131.

[0093] Step S920: Determine whether the starting LBA number "LBA_start" is greater than or equal to the dividing LBA number "LBA_sft" recorded in the LBA shift table 610. If so, the process continues with the processing of step S930; otherwise, the process continues with the processing of step S940. For example, when the LBA conversion circuit 80 starts running, the comparator 810 is first activated by the signal "EN". The comparator 810 compares the starting LBA number with the dividing LBA number in the LBA shift table 610. If the starting LBA number is greater than or equal to the dividing LBA number, a signal is output to the adder 830; otherwise, a signal is output to activate the output circuit 820.

[0094] Step S930: Add the starting LBA number to the offset "Offset" recorded in the LBA shift table 610, and output the added result to a specified position in the command queue 300. For example, the adder 830 adds the offset "Offset" recorded in the LBA shift table 610 to the starting LBA number "LBA_start", and drives the output circuit 840 to output the added result to a specified position in the command queue 300.

[0095] Step S940: Output the starting LBA number to a specified position in the command queue 300. For example, when the output circuit 820 is driven, the starting LBA number "LBA_start" is output to a specified position in the command queue 300.

[0096] Next, based on the host data shown in Table 1, assume that the host 110 issues a series of host read commands as shown in Table 4 to request the device side to read the data of the third and fourth user files:

[0097] Table 4

[0098]

[0099]

[0100] Since the LBA conversion circuit 80 detects that the starting LBA number is less than the separation LBA number "0x405088" recorded in the LBA displacement table 610 when processing the host read commands "R#0" to "R#3" (the path of "No" in step S920), it directly outputs the starting LBA number to the specified position in the command queue 300 (step S940).

[0101] Next, since the starting LBA numbers of the host read commands after the host read command "R#4" are all greater than the separation LBA number "0x405088" recorded in the LBA displacement table 610 (the path of "Yes" in step S920), the LBA conversion circuit 80 adds the offset "0x78" recorded in the LBA displacement table 610 to each starting LBA number, and outputs the added result to the specified position in the command queue 300 (step S930). Table 5 shows the changes in the starting LBA numbers after being processed by the LBA conversion circuit 80:

[0102] Table 5

[0103]

[0104] Although Figure 8 the embodiment shows that the LBA conversion circuit 80 is a device independent of the LBA conversion circuit 60, those skilled in the art can integrate the Figure 8 components 810 to 840 of Figure 6 into the Figure 6 circuit, and the present invention is not limited thereby. For example, each component in Figure 6 is controlled by a mode signal, and the mode signal indicates that each component in Figure 6 works in a data writing mode and a non-data writing mode (including data reading, data erasing mode, etc.). When the mode signal indicates working in the data writing mode, each component in Figure 6 can be activated to complete the operations associated with the host write command as described above. When the mode signal indicates working in the non-data writing mode, only

[0105] Although the embodiment describes Figure 6 and Figure 8 the output circuits shown in are used to output the original or modified starting LBA number to the specified position in the command queue 300, those skilled in the art can also let each output circuit output information such as command number, command type, operation code, length, etc. to the specified position in the command queue 300, and the present invention is not limited thereby.

[0106] Through the settings of the LBA conversion circuits 60 and 80 as described above, the disadvantages shown in Figure 5 are avoided, that is, the firmware conversion layer spends time and computing resources to fill and write unnecessary false data to the flash memory module 150 when driving the flash memory interface 139 to write data. In addition, the firmware conversion layer also spends time and computing resources to read these unnecessary false data from the flash memory module 150 when driving the flash memory interface 139 to read data.

[0107] Although Figure 1 , Figure 2 , Figure 6 , Figure 8 include the components described above, it does not exclude the use of more other additional components without violating the spirit of the invention to achieve better technical effects. In addition, although Figure 7 , Figure 9 's flowchart is executed in a specified order, but without violating the spirit of the invention, those skilled in the art can modify the order between these steps on the premise of achieving the same effect. Therefore, the present invention is not limited to only using the order as described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, execute more steps sequentially or in parallel, and the present invention should not be limited thereby.

[0108] The above is only a preferred embodiment of the present invention. However, it is not used to limit the scope of the present invention. Any person skilled in the art can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims of this application.

Claims

1. A method for executing host commands, implemented by a host interface in a flash memory controller, wherein, the host interface is coupled to a host side, and is characterized in that the method for executing host commands includes: detecting whether there are a default number of consecutive host long write commands, wherein a first starting logical block address number indicated by each of the host long write commands is not aligned with a first physical page of a superpage in the flash memory module; when detecting that there are the default number of consecutive host long write commands, calculating an offset so that a second starting logical block address number indicated by a host write command, after adding the offset, can be aligned with the first physical page of a superpage in the flash memory module; adding the offset to the second starting logical block address number to generate a third starting logical block address number; storing a record in a logical block address displacement table, including information of the second starting logical block address number and the offset, wherein the second starting logical block address number represents a separated starting logical block address number; and outputting the third starting logical block address number associated with the host write command to a specified position in a command queue, so that a firmware conversion layer drives a flash memory interface to write data to the flash memory module according to the third starting logical block address number associated with the host write command.

2. The method for executing host commands according to claim 1, characterized in that, the third starting logical block address number is divisible by the length of a superpage.

3. The method for executing host commands according to claim 1, characterized in that, it includes: when a fourth starting logical block address number carried in a host command is equal to or after the separated starting logical block address number, adding the offset to the fourth starting logical block address number to generate a fifth starting logical block address number; and outputting the fifth starting logical block address number associated with the host command to the specified position in the command queue, so that the firmware conversion layer drives the flash memory interface to complete a corresponding operation according to the fifth starting logical block address number associated with the host command.

4. The method for executing host commands according to claim 3, characterized in that, the fifth starting logical block address number is divisible by the length of a superpage.

5. An apparatus for executing host commands, characterized in that, it includes: a flash memory interface, coupled to a flash memory module; a random access memory, configuring a space for a command queue; a processing unit, coupled to the random access memory and the flash memory interface; and a host interface, coupled to a host side and the random access memory, including: The first logical block address conversion circuit is used to detect whether there are a default number of consecutive host long write commands, where the first starting logical block address numbers indicated by each of the host long write commands are not aligned with the first physical page of a superpage in the flash memory module; when it is detected that there are the default number of consecutive host long write commands, calculate an offset so that the second starting logical block address number indicated by the host write command plus the offset can be aligned with the first physical page of a superpage in the flash memory module; add the offset to the second starting logical block address number to generate a third starting logical block address number; store a record in the logical block address displacement table, including information about the second starting logical block address number and the offset, where the second starting logical block address number represents the separation starting logical block address number; and output the third starting logical block address number associated with the host write command to a specified position in the command queue, so that the processing unit drives the flash memory interface to write data to the flash memory module according to the third starting logical block address number associated with the host write command when executing the program code of the firmware conversion layer.

6. The execution device of the host command according to claim 5, characterized in that the first logical block address conversion circuit includes: a counter; an AND gate; a divider, configured to divide the second starting logical block address number by the maximum number of logical block addresses that a superpage can contain, and output the calculated remainder; a first comparator, coupled to the divider, for receiving the remainder; and when the remainder is equal to 0, output a first signal to the AND gate; a second comparator, configured to output a second signal to the AND gate when the length requested by the host write command is equal to or greater than the maximum number of logical block addresses that a superpage can contain; a third comparator, configured to, when receiving a third signal corresponding to the first signal and the second signal from the AND gate, determine whether the second starting logical block address number is equal to the ending logical block address number requested by the previous host write command plus 1, and if so, increment the counter by 1; a fourth comparator, coupled to the counter, configured to start a calculator, an adder, and a writing circuit when the count value of the counter is greater than or equal to a default value; the calculator, coupled to the fourth comparator, for calculating the offset; the adder, coupled to the fourth comparator, for adding the offset to the second starting logical block address number to generate the third starting logical block address number; the writing circuit, for storing the record in the logical block address displacement table; and an output circuit, coupled to the adder, for outputting the third starting logical block address number to a specified position in the command queue.

7. The execution device of the host command according to claim 5, characterized in that the logical block address displacement table is stored in the flash memory module as a backup.

8. The execution device of the host command according to claim 5, wherein, the third starting logical block address number is divisible by the length of a superpage.

9. The execution device of the host command according to claim 5, wherein, the host interface includes: a second logical block address conversion circuit, configured to, when the fourth starting logical block address number carried in the host command is equal to or after the separated starting logical block address number, add the offset to the fourth starting logical block address number to generate a fifth starting logical block address number; and output the fifth starting logical block address number associated with the host command to a specified position in the command queue, so that the processing unit drives the flash interface according to the fifth starting logical block address number associated with the host command when executing the program code of the firmware conversion layer to complete the corresponding operation.

10. The execution device of the host command according to claim 9, wherein, the second logical block address conversion circuit includes: a comparator, configured to drive an adder when the fourth starting logical block address number is equal to or after the separated starting logical block address number; the adder, coupled to the comparator, configured to add the offset to the fourth starting logical block address number to generate the fifth starting logical block address number; and an output circuit, coupled to the adder, configured to output the fifth starting logical block address number associated with the host command to a specified position in the command queue.

11. The execution device of the host command according to claim 9, wherein, the fifth starting logical block address number is divisible by the length of a superpage.

12. The execution device of the host command according to claim 9, wherein, the host issues the host command to request writing or reading data starting from the fourth starting logical block address number, and the length of the data is equal to the length of a superpage.

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