Access control method and apparatus, storage medium, electronic device, and system on chip

Abstract

The present disclosure relates to an access control method and device, a storage medium, an electronic device and a system on chip, to reduce power consumption of accessing a joint cache. The method comprises: in response to receiving an access request sent by a target master device, obtaining a target historical access record of the target master device, the target historical access record comprising a way hit by the target master device in historical access; generating access prediction information for the access request according to the target historical access record, the access prediction information being used to indicate a predicted target way to be accessed this time; judging whether the access prediction information is accurate; and if it is determined that the access prediction information is accurate, controlling the target way to respond to the access request.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, in particular, to an access control method and device, a storage medium, an electronic device and a system on chip. BACKGROUND

[0002] In a SOC (System on Chip, also known as system on chip), the speed of a master device accessing an external storage medium is usually slow. For example, on a Bluetooth audio IC chip, the external storage medium is generally SPI NOR FLASH (where SPI refers to Serial Peripheral Interface), and the speed does not exceed 50 MB / s, which is very different from the speed of the internal bus interface of the IC chip.

[0003] In related technologies, in order to improve the access efficiency of the external storage medium, data is generally cached using a cache, and the data exchange between the cache and the external storage medium is completed by hardware and is transparent to software. However, since the cache is usually multi-way associative, if a cache is accessed once, the data of each way needs to be read out at the same time, and then it is compared and judged which way of data to use, and one way is a RAM (Random Access Memory), which is equivalent to accessing multiple RAMs at the same time, so the access power consumption is high. SUMMARY

[0004] The purpose of the present disclosure is to provide an access control method, device, storage medium, electronic device and system on chip, which can effectively reduce the power consumption of accessing the cache.

[0005] In order to achieve the above purpose, according to a first aspect of the present disclosure, an access control method is provided, which is used for a system on chip, the system on chip includes a plurality of master devices and a joint cache, the joint cache is used for common use of the plurality of master devices, and the joint cache includes a plurality of ways, the method includes:

[0006] In response to receiving an access request sent by a target master device, obtaining a target historical access record of the target master device, the target historical access record including a way hit by the target master device in a historical access;

[0007] According to the target historical access record, generating access prediction information for the access request, the access prediction information being used to indicate a target way predicted to be accessed this time.

[0008] determining whether the access prediction information is accurate;

[0009] if it is determined that the access prediction information is accurate, controlling the target way to respond to the access request.

[0010] Optionally, the target history access record of the target master device is obtained in response to receiving the access request, and the target history access record comprises:

[0011] In response to receiving the access request, the identification information of the target master device is determined as target identification information.

[0012] According to a correspondence relationship between the stored multiple identification information and multiple history access records, the history access record corresponding to the target identification information is determined as the target history access record.

[0013] Optionally, the access prediction information for the access request is generated according to the target history access record, and the access prediction information comprises:

[0014] In the target history access record, the way that is hit in the history access closest to receiving the access request is determined as the target way, so as to generate the access prediction information.

[0015] Optionally, the access prediction information for the access request is generated according to the target history access record, and the access prediction information comprises:

[0016] In the target history access record, the way that is hit for a preset number of times continuously and in the history access closest to receiving the access request is determined as the target way, so as to generate the access prediction information.

[0017] Optionally, the determination of whether the access prediction information is accurate comprises:

[0018] The tag record of the target way is obtained.

[0019] The tag record is compared with the address high bit of the access request.

[0020] If the tag record matches the address high bit of the access request, it is determined that the access prediction information is accurate.

[0021] If the tag record does not match the address high bit of the access request, it is determined that the access prediction information is not accurate.

[0022] Optionally, each way of the joint cache memory is provided with a clock gate.

[0023] The obtaining the tag record of the target way comprises:

[0024] controlling a clock gate of the target way to be turned on to generate an access current to the target way;

[0025] After the access current to the target way is generated, reading the tag record of the target way.

[0026] Optionally, each way of the joint cache is provided with a clock gate.

[0027] The method further comprises:

[0028] If it is determined that the access prediction information is inaccurate, controlling clock gates of non-target ways in the joint cache except the target way to be turned on to generate an access current to the non-target ways.

[0029] According to a second aspect of the present disclosure, an access control apparatus is provided for a system on chip, the system on chip comprising a plurality of master devices and a joint cache, the joint cache being used for common use of the plurality of master devices, and the joint cache comprising a plurality of ways, the apparatus comprising:

[0030] an arbitration circuit configured to, in response to receiving an access request sent by a target master device, obtain a target historical access record of the target master device, the target historical access record comprising ways hit by the target master device in historical accesses;

[0031] a prediction module configured to generate, according to the target historical access record, access prediction information for the access request, the access prediction information being used to indicate a target way predicted to be accessed this time;

[0032] a judgment module configured to judge whether the access prediction information is accurate;

[0033] a control module configured to, if it is determined that the access prediction information is accurate, control the target way to respond to the access request;

[0034] wherein each way of the joint cache is provided with a clock gate, and the control module controls the access to the way by controlling the clock gate.

[0035] Optionally, the arbitration circuit comprises:

[0036] a first determination circuit configured to, in response to receiving the access request, determine identification information of the target master device as target identification information;

[0037] The second determining circuit is configured to determine a historical access record corresponding to the target identification information as the target historical access record according to a correspondence between the stored multiple identification information and the multiple historical access records.

[0038] Optionally, the prediction module comprises:

[0039] The first prediction submodule is configured to determine, in the target historical access record, a way that is hit in a historical access closest to receiving the access request as the target way, so as to generate the access prediction information.

[0040] Optionally, the prediction module comprises:

[0041] The second prediction submodule is configured to determine, in the target historical access record, a way that is hit for a preset number of times continuously and in a historical access closest to receiving the access request as the target way, so as to generate the access prediction information.

[0042] Optionally, the judgment module comprises:

[0043] The obtaining submodule is configured to obtain a tag record of the target way.

[0044] The comparison submodule is configured to compare the tag record with a high bit of an address of the access request.

[0045] The first determination submodule is configured to determine that the access prediction information is accurate if the tag record matches the high bit of the address of the access request.

[0046] The second determination submodule is configured to determine that the access prediction information is inaccurate if the tag record does not match the high bit of the address of the access request.

[0047] Optionally, the obtaining submodule is configured to:

[0048] Control a clock gate of the target way to be turned on, so as to generate an access current of the target way.

[0049] After the access current of the target way is generated, read the tag record of the target way.

[0050] Optionally, the control module is further configured to, if it is determined that the access prediction information is inaccurate, control a clock gate of a non-target way in the joint cache memory to be turned on, so as to generate an access current of the non-target way.

[0051] According to a third aspect of the present disclosure, a computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, implements the steps of the method according to the first aspect of the present disclosure.

[0052] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising:

[0053] a memory having stored thereon a computer program;

[0054] a processor configured to execute the computer program in the memory to implement the steps of the method according to the first aspect of the present disclosure.

[0055] According to a fifth aspect of the present disclosure, a system on chip is provided, comprising:

[0056] a plurality of master devices;

[0057] a joint cache for common use by the plurality of master devices, the joint cache comprising a plurality of ways; and

[0058] an access control circuit disposed between the plurality of master devices and the joint cache, the access control circuit being configured to implement the method according to the first aspect of the present disclosure.

[0059] By the above technical solution, in response to receiving an access request sent by a target master device, a target historical access record of the target master device is obtained, the target historical access record comprising a way hit by the target master device in a historical access. Then, according to the target historical access record, access prediction information for the access request is generated, the access prediction information being used to indicate a target way predicted to be accessed this time. Then, it is determined whether the access prediction information is accurate. If it is determined that the access prediction information is accurate, the target way is controlled to respond to the access request. In this way, according to the historical access record of the master device sending the access request, the way that the master device is likely to access this time can be predicted. In the case of accurate prediction, only one way is accessed. Thus, compared with the current mode in which all ways in the cache are necessarily accessed during cache access, the method provided by the present disclosure can only access one way in the case of most accurate prediction, and can significantly reduce the power consumption of cache access.

[0060] Other features and advantages of the present disclosure will be described in detail in the following detailed description section. BRIEF DESCRIPTION OF DRAWINGS

[0061] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the following detailed description, serve to explain the present disclosure. In the drawings:

[0062] Figure 1 is a flowchart of an access control method according to an embodiment of the present disclosure;

[0063] Figure 2 is an exemplary flowchart of a step of judging whether the access prediction information is accurate in the access control method according to the present disclosure;

[0064] Figure 3 is a block diagram of an access control apparatus according to an embodiment of the present disclosure;

[0065] Figure 4 is an exemplary structural schematic diagram of an access control apparatus according to the present disclosure;

[0066] Figure 5 is a block diagram of an electronic device according to an exemplary embodiment;

[0067] Figure 6 is a schematic diagram of a system on chip according to an embodiment of the present disclosure;

[0068] Figure 7 is an exemplary schematic diagram of an access control circuit in a system on chip according to the present disclosure. DETAILED DESCRIPTION

[0069] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0070] Figure 1 is a flowchart of an access control method according to an embodiment of the present disclosure. The method provided by the present disclosure can be applied to a system on chip, in which a plurality of master devices and a joint cache are included. The master devices may, for example, include a CPU (Central Processing Unit), a DSP (Digital Signal Processing), a hardware accelerator, etc. The joint cache is used for common use of the plurality of master devices, and the joint cache includes a plurality of ways.

[0071] As shown in Figure 1 The method provided by the present disclosure can include steps 11-14, which will be described in detail below in combination with steps 11-14.

[0072] In step 11, in response to receiving an access request sent by a target master device, a target historical access record of the target master device is obtained.

[0073] The target historical access record includes a way hit by the target master device in historical access. That is, in the process of the target master device accessing the joint cache, whenever a way is successfully accessed, it can be recorded in the target historical access record. For example, the target historical access record can be a way access record in a period of time. For another example, the target historical access record can be a way access record of a specified number of times.

[0074] In a possible implementation, step 11 can include the following steps:

[0075] In response to receiving the access request, the identification information of the target master device is determined as the target identification information.

[0076] According to the correspondence between the stored multiple identification information and multiple historical access records, the historical access record corresponding to the target identification information is determined as the target historical access record.

[0077] When receiving the access request from the target master device, in response to the access request, the identification information of the target master device can be determined and taken as the target identification information. For example, each of the multiple master devices can be pre-assigned identification information to uniquely represent each master device, so that the identification information of the target master device can be used to uniquely represent the target master device. For example, the identification information can be a device ID. For example, the access request can carry the identification information of the target master device, so that the target identification information can be directly obtained through the access request. For another example, different master devices can send access requests through different information transmission paths, and the information transmission path of a master device has a one-to-one correspondence with the identification information of the master device, so that the target identification information can be determined according to the information transmission path of the received access request.

[0078] After the target identification information is determined, the historical access record corresponding to the target identification information can be determined as the target historical access record according to the correspondence between the stored multiple identification information and multiple historical access records.

[0079] That is, for multiple master devices in the system on chip, the historical access records of different master devices will be recorded respectively, and the historical access record of a master device corresponds to the identification information of the master device, so that the historical access record of the master device can be obtained based on the identification information of the master device. Based on this, according to the correspondence between the stored multiple identification information and multiple historical access records, the historical access record corresponding to the target identification information, i.e., the target historical access record, can be determined.

[0080] In this way, the records of different master devices accessing ways in the system on chip are stored respectively, the actually hit way in the single master device history access can be determined, and the way that the master device is likely to access next can be predicted more accurately, so that the prediction accuracy is improved.

[0081] In step 12, the access prediction information for the access request is generated according to the target history access record.

[0082] The access prediction information is used to indicate the predicted target way to be accessed this time.

[0083] The temporal locality can be understood as that a memory location that is referenced once will be referenced multiple times in the future. The spatial locality can be understood as that if a memory location is referenced, the locations near the memory will also be referenced in the future. Based on the principles of the temporal locality and the spatial locality, the way that is likely to be accessed can be predicted according to the record of the recently hit way of the master device.

[0084] In a possible embodiment, step 12 can include the following steps:

[0085] In the target history access record, the way that is hit in the history access closest to the reception of the access request is determined as the target way, so as to generate the access prediction information.

[0086] That is, when the access request in step 11 is received, the way that is hit last time on the target master device is obtained from the target history access record, and the way is taken as the target way, so as to generate the access prediction information.

[0087] In this way, the way that is hit last time in the target history access record is used for prediction, so that the access prediction information can be generated quickly, and the efficiency of prediction is ensured.

[0088] In another possible embodiment, step 12 can include the following steps:

[0089] In the target history access record, the way that is hit continuously for a preset number of times and is hit in the history access closest to the reception of the access request is determined as the target way, so as to generate the access prediction information.

[0090] That is, when the access request in step 11 is received, the way that is hit continuously for a preset number of times in the recent history access of the target master device is obtained from the target history access record, and the way is taken as the target way, so as to generate the access prediction information. The preset number of times can be set according to actual needs. For example, the preset number of times can be 2.

[0091] For example, assuming that the preset number of times is 2, in a first example, in the record closest to the current record in the target historical access record, the order from early to late in the access time is way1, way1, way2, and it can be determined that the target way is way1. In a second example, in the record closest to the current record in the target historical access record, the order from early to late in the access time is way1, way1, way2, way2, and it can be determined that the target way is way2.

[0092] In the above manner, the multiple access conditions in the target historical access record are used for prediction, so that the access prediction information can be generated more accurately, and the accuracy of the prediction is ensured.

[0093] In step 13, it is determined whether the access prediction information is accurate.

[0094] In a possible implementation, step 13 can include the following steps, as shown in Figure 2

[0095] In step 21, the tag record of the target way is obtained.

[0096] For example, in the present disclosure, each way of the joint cache memory can be provided with a clock gate. By controlling the opening and closing of the clock gate, the access current to the way can be controlled, so that the access to the way can be controlled. If the clock gate provided on a certain way is controlled to be opened, the access current to the way will be generated, and the address and clock will be sent to the way, so that the access to the way can be realized. Correspondingly, step 21 can include the following steps:

[0097] The clock gate of the target way is controlled to be opened to generate the access current to the target way.

[0098] After the access current to the target way is generated, the tag record of the target way is read.

[0099] Each way stores a tag record (Tag), which is used to mark the memory address and comes from the access address. For example, when the CPU accesses the cache, the CPU first accesses the Tag RAM storing the tag record, determines whether there is a corresponding address, and if the address can be matched, data is taken from the cache or written into the cache. Therefore, if the tag record of the target way is to be read, the clock gate of the target way needs to be controlled to be opened first, and then the tag record of the target way is read out.

[0100] In step 22, the tag record is compared with the high bits of the address of the access request. ​

[0101] In step 23, if the tag record matches the high bits of the address of the access request, it is determined that the access prediction information is accurate.

[0102] In step 24, if the tag record does not match the high bits of the address of the access request, it is determined that the access prediction information is inaccurate.

[0103] After obtaining the tag record of the target way, the tag record can be compared with the high bits of the address corresponding to the access request (i.e., the high bits of the address of the target host device) to determine whether the access address can match. If the tag record matches the high bits of the address of the access request, it can be determined that the access prediction information is accurate, otherwise, if the tag record does not match the high bits of the address of the access request, it can be determined that the access prediction information is inaccurate.

[0104] Referring to Figure 1 In step 14, if it is determined that the access prediction information is accurate, the target way is controlled to respond to the access request.

[0105] If it is determined that the access prediction information is accurate, it means that the target way is the way that needs to be accessed this time, and therefore, the target way can be directly controlled to respond to the access request. For example, if the access request is used to request to read data, the data reading can be directly performed, and the read data can be returned to the target host device.

[0106] Optionally, the method provided by the present disclosure can further include the following steps:

[0107] If it is determined that the access prediction information is inaccurate, the clock gate of the non-target way in the joint cache memory except the target way is controlled to be turned on to generate an access current of the non-target way.

[0108] If it is determined that the access prediction information is inaccurate, it means that the target way is not the way that needs to be accessed this time, and the prediction fails. At this time, the clock gate of the non-target way in the joint cache memory except the target way needs to be controlled to be turned on to read the tag record of the non-target way, and then compared with the high bits of the address of the target host device. This part is consistent with the current conventional method.

[0109] According to the technical solution, in response to receiving an access request sent by a target master device, a target historical access record of the target master device is obtained, the target historical access record including a way hit by the target master device in historical access. Then, according to the target historical access record, access prediction information for the access request is generated, the access prediction information being used to indicate a predicted target way to be accessed this time. Then, it is determined whether the access prediction information is accurate. If it is determined that the access prediction information is accurate, the target way is controlled to respond to the access request. In this way, according to the historical access record of the master device sending the access request, the way that the master device is likely to access this time can be predicted. In the case of accurate prediction, only one way is accessed. Therefore, compared with the current mode in which all ways in a joint cache must be accessed during access to the joint cache, the method provided by the present disclosure can only access one way in the case of most accurate prediction, and can significantly reduce the power consumption of accessing the joint cache.

[0110] Figure 3 is a block diagram of an access control device according to an embodiment of the present disclosure. The device is used in a system on chip, which includes a plurality of master devices and a joint cache used for common use by the plurality of master devices, and the joint cache includes a plurality of ways. As shown in Figure 3 , the device 30 includes:

[0111] An arbitration circuit 31 is configured to, in response to receiving an access request sent by a target master device, obtain a target historical access record of the target master device, the target historical access record including a way hit by the target master device in historical access.

[0112] A prediction module 32 is configured to, according to the target historical access record, generate access prediction information for the access request, the access prediction information being used to indicate a predicted target way to be accessed this time.

[0113] A determination module 33 is configured to determine whether the access prediction information is accurate.

[0114] A control module 34 is configured to, if it is determined that the access prediction information is accurate, control the target way to respond to the access request.

[0115] Each way of the joint cache is provided with a clock gate, and the control module controls the access to the way by controlling the clock gate.

[0116] For example, the structure diagram of the access control device 30 provided by the present disclosure can be as shown in Figure 4 . In Figure 4In the embodiment, a plurality of master devices are represented by master device 1 to master device N, and a plurality of ways included in the joint cache memory are represented by first way, second way, third way to Mth way. The arbitration circuit 31 is configured to receive the access request sent by the master device and perform corresponding processing. The prediction module 32 stores a corresponding relationship between a plurality of identification information and a plurality of historical access records, and is configured to generate access prediction information. The judgment module 33 is configured to judge whether the access prediction information generated by the prediction module 32 is accurate. The control module 34 is configured to control the target way to respond to the access request when it is determined that the access prediction information is accurate. In addition, each way of the joint cache memory is provided with a clock gate, and the control module 34 controls the access to the way by controlling the clock gate.

[0117] Optionally, the arbitration circuit 31 comprises:

[0118] The first determination circuit is configured to determine the identification information of the target master device as the target identification information in response to receiving the access request.

[0119] The second determination circuit is configured to determine the historical access record corresponding to the target identification information as the target historical access record according to the corresponding relationship between the plurality of identification information and the plurality of historical access records.

[0120] Optionally, the prediction module 32 comprises:

[0121] The first prediction submodule is configured to determine, in the target historical access record, the way hit in the historical access closest to receiving the access request as the target way, so as to generate the access prediction information.

[0122] Optionally, the prediction module 32 comprises:

[0123] The second prediction submodule is configured to determine, in the target historical access record, the way hit in the historical access closest to receiving the access request as the target way, so as to generate the access prediction information.

[0124] Optionally, the judgment module 33 comprises:

[0125] The acquisition submodule is configured to acquire the tag record of the target way.

[0126] The comparison submodule is configured to compare the tag record with the high bits of the address of the access request.

[0127] The first determination submodule is configured to determine that the access prediction information is accurate if the tag record matches the high bits of the address of the access request.

[0128] A second determining sub-module is configured to determine that the access prediction information is inaccurate if the tag record does not match the high bits of the address of the access request.

[0129] Optionally, the obtaining sub-module is configured to:

[0130] controlling a clock gate of the target way to be turned on to generate an access current to the target way;

[0131] reading a tag record of the target way after the access current to the target way is generated.

[0132] Optionally, the control module is further configured to control a clock gate of a non-target way in the joint cache memory to be turned on to generate an access current to the non-target way if it is determined that the access prediction information is inaccurate.

[0133] As to the apparatus in the above-described embodiments, the specific manners in which various modules perform operations have been described in detail in the embodiments of the method, and thus will not be described in detail here.

[0134] Figure 5 is a block diagram of an electronic device 700 according to an exemplary embodiment. As shown in Figure 5 the electronic device 700 can include a processor 701 and a memory 702. The electronic device 700 can also include one or more of a multimedia component 703, an input / output (I / O) interface 704, and a communication component 705.

[0135] The processor 701 is configured to control overall operations of the electronic device 700 to complete all or part of the steps of the access control method described above. The memory 702 is configured to store various types of data to support operations of the electronic device 700, which can include, for example, instructions for operating any application or method on the electronic device 700, and application-related data, such as contact data, transmitted and received messages, pictures, audio, video, and the like. The memory 702 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic storage, a flash memory, a magnetic disk, or an optical disk. The multimedia component 703 can include a screen and an audio component. The screen can be, for example, a touch screen, and the audio component is configured to output and / or input audio signals. For example, the audio component can include a microphone configured to receive external audio signals. The received audio signals can be further stored in the memory 702 or transmitted through the communication component 705. The audio component also includes at least one speaker configured to output audio signals. The I / O interface 704 provides an interface between the processor 701 and other interface modules, which can be a keyboard, a mouse, a button, and the like. The buttons can be virtual buttons or physical buttons. The communication component 705 is configured to perform wired or wireless communication between the electronic device 700 and other devices. The wireless communication, such as Wi-Fi, Bluetooth, near field communication (NFC), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, and the like, or a combination of one or more of them, is not limited herein. Therefore, the corresponding communication component 705 can include a Wi-Fi module, a Bluetooth module, an NFC module, and the like.

[0136] In an exemplary embodiment, the electronic device 700 can be implemented by one or more Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), controller, microcontroller, microprocessor or other electronic elements for performing the above-mentioned access control method.

[0137] In another exemplary embodiment, a computer readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the above-mentioned access control method. For example, the computer readable storage medium can be the above-mentioned memory 702 including program instructions, which can be executed by the processor 701 of the electronic device 700 to complete the above-mentioned access control method.

[0138] Figure 6 is a schematic diagram of a system on chip according to an embodiment of the present disclosure. As shown in Figure 6 , the system on chip 50 includes:

[0139] a plurality of master devices (indicated by master device 1 to master device N respectively in Figure 6 );

[0140] a joint cache 510 for common use of the plurality of master devices, the joint cache including a plurality of ways;

[0141] an access control circuit 520 disposed between the plurality of master devices and the joint cache, the access control circuit being configured to perform the access control method provided by any embodiment of the present disclosure.

[0142] For example, the access control circuit 520 can be as shown in Figure 7 . In Figure 7In the joint cache 510, the first way, the second way, the third way to the Mth way are represented by the first path, the second path, the third path to the Mth path. The access control circuit 520 includes an arbitration circuit 521, a prediction module 522, a judgment module 523, a control module 524 and a plurality of clock gate controllers. The arbitration circuit 521 is configured to receive the access request sent by the host device and perform corresponding processing. The prediction module 522 stores a corresponding relationship between a plurality of identification information and a plurality of historical access records, and is configured to generate access prediction information. The judgment module 523 is configured to judge whether the access prediction information generated by the prediction module 522 is accurate. The control module 524 controls the access of each way through the clock gate controller. The specific implementation is described in the method part, and will not be repeated here.

[0143] The preferred embodiments of the present disclosure are described in detail above with reference to the drawings, but the present disclosure is not limited to the specific details in the above-described embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

[0144] In addition, it should be noted that each specific technical feature described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, various possible combinations are not described again in the present disclosure.

[0145] In addition, any combination of various different embodiments of the present disclosure can also be made, as long as it does not deviate from the idea of the present disclosure, and it should also be considered as disclosed in the present disclosure.

Claims

1. An access control method characterized by, The method for a system on chip, the system on chip comprising a plurality of master devices and a joint cache memory, the joint cache memory being used for the plurality of master devices to share, and the joint cache memory comprising a plurality of ways, the method comprising: in response to receiving an access request sent by a target master device, obtaining a target historical access record of the target master device, the target historical access record comprising ways hit by the target master device in historical accesses; generating access prediction information for the access request according to the target historical access record, the access prediction information being used to indicate a target way predicted to be accessed this time; determining whether the access prediction information is accurate; if it is determined that the access prediction information is accurate, controlling the target way to respond to the access request; the determining whether the access prediction information is accurate comprises: obtaining a tag record of the target way; comparing the tag record with high bits of an address of the access request; and if the tag record matches the high bits of the address of the access request, determining that the access prediction information is accurate.

2. The method of claim 1, wherein, the obtaining the target historical access record of the target master device in response to receiving the access request comprises: in response to receiving the access request, determining identification information of the target master device as target identification information; determining a historical access record corresponding to the target identification information as the target historical access record according to a correspondence between a plurality of stored identification information and a plurality of historical access records.

3. The method of claim 1, wherein, the generating the access prediction information for the access request according to the target historical access record comprises: in the target historical access record, determining a way hit in a historical access closest to receiving the access request as the target way to generate the access prediction information.

4. The method of claim 1, wherein, the generating the access prediction information for the access request according to the target historical access record comprises: in the target historical access record, determining a way hit in a historical access closest to receiving the access request as the target way to generate the access prediction information.

5. The method of claim 1, wherein, the determining whether the access prediction information is accurate further comprises: if the tag record does not match the high bits of the address of the access request, determining that the access prediction information is not accurate.

6. The method of claim 5, wherein, each way of the joint cache memory is provided with a clock gate; the obtaining the tag record of the target way comprises: controlling the clock gate of the target way to be turned on to generate an access current for the target way; after the access current for the target way is generated, reading the tag record of the target way.

7. The method of claim 6, wherein, the method further comprises: if it is determined that the access prediction information is not accurate, controlling clock gates of non-target ways in the joint cache memory except the target way to be turned on to generate access currents for the non-target ways.

8. An access control device, characterized in that The system on chip includes a plurality of master devices and a joint cache memory for common use of the plurality of master devices, and a plurality of ways are included in the joint cache memory, and the device comprises: An arbitration circuit is configured to, in response to receiving an access request sent by a target master device, acquire a target historical access record of the target master device, the target historical access record including ways hit by the target master device in historical accesses; A prediction module is configured to generate access prediction information for the access request according to the target historical access record, the access prediction information being used to indicate a target way predicted to be accessed this time; A judgment module is configured to judge whether the access prediction information is accurate; A control module is configured to control the target way to respond to the access request if it is determined that the access prediction information is accurate. The judgment module includes: an acquisition submodule configured to acquire a tag record of the target way; a comparison submodule configured to compare the tag record with high-order bits of an address of the access request; and a first determination submodule configured to determine that the access prediction information is accurate if the tag record matches the high-order bits of the address of the access request. Each way of the joint cache memory is provided with a clock gate, and the control module controls the clock gate to realize access to the way.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to realize the steps of the method in any one of claims 1-7.

10. An electronic device, comprising: The system comprises: A memory having a computer program stored thereon; A processor configured to execute the computer program in the memory to realize the steps of the method in any one of claims 1-7.

11. A system on chip, characterized by The system comprises: A plurality of master devices; A joint cache memory for common use of the plurality of master devices, the joint cache memory including a plurality of ways; And An access control circuit arranged between the plurality of master devices and the joint cache memory, the access control circuit being configured to execute the method in any one of claims 1-7.

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