Semiconductor memory devices

Abstract

One embodiment provides a semiconductor memory device capable of reducing peak current during write operations. The semiconductor memory device (2) of one embodiment includes a plurality of memory cells (MT), word lines (WL) connected to the gates of the memory cells (MT), and a voltage generation circuit (281) that generates a voltage supplied to the word lines (WL). Additionally, the semiconductor memory device (2) also includes a sequencer (27) that executes a write sequence to write specific data to the memory cells (MT). The write sequence is repeated multiple times, and the multiple cycles consist of a set of programming operations that write data to the memory cells (MT) and verification operations that verify the data written to the memory cells (MT). The sequencer (27) instructs the voltage generation circuit (281) to set a voltage value supplied to the word lines (WL), and changes the initial intermediate setting value at the start of the verification operation according to the position of the cycle.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-45249 (filed on March 18, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] Semiconductor memory devices include NAND (Not And) flash memory. Summary of the Invention

[0005] One embodiment aims to provide a semiconductor memory device capable of reducing peak current during write operations.

[0006] One embodiment of a semiconductor memory device includes: a plurality of memory cells; word lines connected to the gates of the plurality of memory cells; and bit lines electrically connected to one end of the plurality of memory cells via a plurality of select-gate transistors respectively connected to one end of the plurality of memory cells. Furthermore, the semiconductor memory device also includes: a voltage generation circuit that generates a voltage supplied to the word lines; and a control unit that executes a write sequence to write specific data to the memory cells, the write sequence being repeatedly performed in multiple cycles, the multiple cycles being a set of programming operations for writing data to the memory cells and verification operations for verifying the data written to the memory cells. The control unit instructs the voltage generation circuit to a set value of the voltage supplied to the word lines, and changes the set value at the start of the verification operation, i.e., a first set value, according to the position of the cycle. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a storage device in an implementation method.

[0008] Figure 2 This is a block diagram illustrating an example of the configuration of a non-volatile memory in an implementation.

[0009] Figure 3 This is a diagram illustrating an example of the structure of a block of a three-dimensional NAND memory cell array.

[0010] Figure 4 This is a cross-sectional view of a portion of the semiconductor memory device according to an embodiment.

[0011] Figure 5 This is a diagram illustrating an example of the threshold voltage distribution in an implementation method.

[0012] Figure 6 This is a diagram representing the data encoding of the implementation method.

[0013] Figure 7A It is a graph showing the potential changes of each wiring during programming operations.

[0014] Figure 7B It is a graph showing the potential changes of each wiring during the verification process.

[0015] Figure 8 It is a circuit diagram that represents the sequence of programming actions.

[0016] Figure 9 It is a graph showing the relationship between the number of loops and the programming and verification actions during a write operation based on a standard write sequence.

[0017] Figure 10 It is a graph representing the timing of programming and verification actions during a write operation based on a standard write sequence.

[0018] Figure 11 It is a graph showing the potential changes of each wiring during the write operation.

[0019] Figure 12 This is a block diagram illustrating an example of the configuration of the voltage supply circuit 28 and the line decoder 25.

[0020] Figure 13 This is a block diagram illustrating an example of the specific configuration of the voltage supply circuit 28.

[0021] Figure 14A This is a block diagram illustrating an example of the specific configuration of a pump assembly.

[0022] Figure 14B This is a block diagram illustrating the structure of the first state.

[0023] Figure 14C This is a block diagram illustrating the composition of the second state.

[0024] Figure 14D This is a block diagram illustrating the composition of the third state.

[0025] Figure 15 This is a diagram illustrating an example of a charge pump circuit.

[0026] Figure 16 This is a diagram illustrating the current efficiency characteristics of the second pump 281B relative to the output voltage.

[0027] Figure 17 This diagram illustrates the pump's pressure boosting control during the verification process.

[0028] Figure 18This is a graph showing the potential changes of the non-select word lines during USTRDIS.

[0029] Figure 19 This diagram illustrates the pump's pressurization control during the first half of the write sequence.

[0030] Figure 20 This diagram illustrates the pump's pressure boosting action control in the second half of the write sequence.

[0031] Figure 21 This is a diagram illustrating the pump pressurization control in the second half of the write sequence of the second embodiment. Detailed Implementation

[0032] The embodiments will now be described with reference to the accompanying drawings.

[0033] (First Embodiment)

[0034] (1. Composition)

[0035] (1-1. The Structure of a Memory System)

[0036] Figure 1 This is a block diagram illustrating an example configuration of a memory system according to an embodiment. The memory system of this embodiment includes a memory controller 1 and a non-volatile memory 2, which is a semiconductor storage device. The memory system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a mobile terminal.

[0037] Non-volatile memory 2 is a memory that stores data non-volatilely, such as NAND flash memory. Non-volatile memory 2 is, for example, a NAND memory with each storage cell capable of storing 3 bits, that is, a 3-bit / cell (TLC: Triple Level Cell) NAND memory. Furthermore, non-volatile memory 2 can also be a 1-bit / cell, 2-bit / cell, or 4-bit / cell NAND memory.

[0038] The memory controller 1 controls the writing of data to the non-volatile memory 2 according to write requests from the host. Additionally, the memory controller 1 controls the reading of data from the non-volatile memory 2 according to read requests from the host. Various signals are transmitted and received between the memory controller 1 and the non-volatile memory 2, such as the chip enable signal / CE, the ready / busy signal / RB, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, the read enable signal RE, / RE, the write protection signal / WP, the data signals DQ<7:0>, and the data strobe signals DQS, / DQS.

[0039] For example, the non-volatile memory 2 and the memory controller 1 are respectively formed as semiconductor chips (hereinafter also referred to as "chips").

[0040] The chip enable signal / CE is used to enable non-volatile memory 2. The ready / busy signal / RB is used to indicate whether non-volatile memory 2 is in a ready state (accepting commands from external sources) or a busy state (not accepting commands from external sources). The instruction latch enable signal CLE indicates that the signal DQ<7:0> represents an instruction. The address latch enable signal ALE indicates that the signal DQ<7:0> represents an address. The write enable signal / WE is used to store the received signal into non-volatile memory 2, and is activated each time an instruction, address, or data is received through memory controller 1. During the period when the signal / WE is at the "L" level, it indicates that non-volatile memory 2 should store the signal DQ<7:0>.

[0041] The read enable signals RE and / RE are used to enable memory controller 1 to read data from non-volatile memory 2. For example, they are used to control the operation of non-volatile memory 2 when output signal DQ<7:0> is displayed. The write protect signal / WP is used to instruct non-volatile memory 2 to prohibit writing and erasing data. Signal DQ<7:0> represents the data entities transmitted and received between non-volatile memory 2 and memory controller 1, including instructions, addresses, and data. The data strobe signals DQS and / DQS are used to control the input / output timing of signal DQ<7:0>.

[0042] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected by an internal bus 16.

[0043] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Additionally, the host interface 13 sends user data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0044] Based on the instructions of the processor 12, the memory interface 15 controls the processes of writing user data to the non-volatile memory 2 and reading user data from the non-volatile memory 2.

[0045] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When processor 12 receives a request from the host via host interface 13, it executes control according to that request. For example, processor 12, upon receiving a request from the host, instructs memory interface 15 to write user data and parity data to non-volatile memory 2. Additionally, processor 12, upon receiving a request from the host, instructs memory interface 15 to read user data and parity data from non-volatile memory 2.

[0046] Processor 12 determines the storage area (memory region) on non-volatile memory 2 for user data accumulated in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory region for data in page units (page data) written as units. In this specification, user data stored in one page of non-volatile memory 2 is defined as group data. Group data is typically encoded by ECC circuit 14 and stored as codewords in non-volatile memory 2. In this embodiment, encoding is not mandatory. Memory controller 1 may also store group data in non-volatile memory 2 without encoding, but... Figure 1 The diagram illustrates an example of an encoding configuration. When the memory controller 1 does not perform encoding, the page data is identical to the group data. Alternatively, a codeword can be generated based on a single group of data, or it can be generated based on segmented data formed by dividing the group data. Furthermore, a codeword can also be generated using multiple groups of data.

[0047] Processor 12 determines the memory region of the non-volatile memory 2 to be written to in units of data sets. Physical addresses are allocated to the memory regions of the non-volatile memory 2. Processor 12 uses physical addresses to manage the memory regions to be written to in units of data sets. Processor 12 specifies the determined memory region (physical address) and instructs memory interface 15 to write user data to non-volatile memory 2. Processor 12 manages the mapping between logical addresses (logical addresses managed by the host) and physical addresses of user data. When processor 12 receives a read request containing a logical address from the host, it specifies the physical address corresponding to the logical address, assigns the physical address, and instructs memory interface 15 to read the user data.

[0048] ECC circuit 14 encodes user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes codewords read from non-volatile memory 2.

[0049] RAM 11 temporarily stores user data received from the host before it is transferred to non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 before it is sent to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0050] Figure 1 The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can also be integrated into the non-volatile memory 2.

[0051] When a write request is received from the host, the memory system operates as follows: Processor 12 temporarily stores the data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it into ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword into memory interface 15. Memory interface 15 writes the input codeword into non-volatile memory 2.

[0052] When a read request is received from the host, the memory system operates as follows: The memory interface 15 inputs the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in RAM 11. The processor 12 sends the data stored in RAM 11 to the host via the host interface 13.

[0053] (1-2. The structure of non-volatile memory)

[0054] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment. The non-volatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a line decoder 25, a register 26, a sequencer 27, a voltage supply circuit 28, an input / output pad group 32, a logic control pad group 34, and a power input terminal group 35.

[0055] The memory cell array 23 comprises multiple blocks. Each block BLK contains a memory cell transistor (memory cell). The memory cell array 23 is equipped with multiple bit lines, multiple word lines, and source lines to control the voltage applied to the memory cell transistors. The specific structure of the block BLK will be described below.

[0056] The input / output pad group 32 has multiple terminals (pads) corresponding to the signals DQ<7:0> and data strobe signals DQS and / DQS, and is used to transmit and receive signals containing data between the input / output pad group 32 and the memory controller 1.

[0057] The logic control pad group 34 has multiple terminals (pads) corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP, and is used to send and receive signals with the memory controller 1.

[0058] The / CE signal enables the selection of non-volatile memory 2. The CLE signal latches the instruction sent as the DQ signal into the instruction register. The ALE signal latches the address sent as the DQ signal into the address register. The WE signal enables writing. The RE signal enables reading. The WP signal disables writing and erasing. The R / B signal indicates whether non-volatile memory 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources). The memory controller 1 can determine the status of non-volatile memory 2 by receiving the R / B signal.

[0059] The power input terminal group 35 has multiple terminals for receiving power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss, used to supply various operating power supplies to the non-volatile memory 2 from the outside. The power supply voltage Vcc is the circuit power supply voltage typically supplied externally as the operating power supply, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2.

[0060] The power supply voltage Vpp is a higher voltage than the power supply voltage Vcc, for example, a voltage of 12V. When writing or erasing data to the memory cell array 23, a high voltage of approximately 20V is required. In this case, compared to using the boost circuit of the voltage supply circuit 28 to boost the approximately 3.3V power supply voltage Vcc, boosting the approximately 12V power supply voltage Vpp can generate the required voltage quickly and with low power consumption. On the other hand, for example, when using the non-volatile memory 2 in an environment where a high voltage cannot be supplied, the power supply voltage Vpp may not be supplied. Even without supplying the power supply voltage Vpp, the non-volatile memory 2 can still perform various operations as long as the power supply voltage Vcc is supplied. In other words, the power supply voltage Vcc is the standard power supply supplied to the non-volatile memory 2, while the power supply voltage Vpp is, for example, an additional power supply arbitrarily supplied depending on the usage environment.

[0061] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 transmits and receives signals DQ (e.g., DQ0 to DQ7) with the memory controller 1 via the NAND bus.

[0062] The logic control circuit 21 receives external control signals (e.g., chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP) from the memory controller 1 via the NAND bus. The " / " in the signal name indicates active low. Additionally, the logic control circuit 21 sends the ready / busy signal / RB to the memory controller 1 via the NAND bus.

[0063] The input / output circuit 22 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with the memory controller 1. The input / output circuit 22 transfers the instruction and address contained in the signals DQ<7:0> to register 26. Additionally, the input / output circuit 22 transmits and receives write and read data with the sense amplifier 24.

[0064] Register 26 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of the non-volatile memory 2. Register 26 may contain, for example, SRAM.

[0065] The sequencer 27, acting as the control unit, receives instructions from the register 26 and controls the non-volatile memory 2 according to the sequence of instructions.

[0066] The voltage supply circuit 28 receives a power supply voltage from the external source of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage supply circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, and the line decoder 25, etc.

[0067] The row decoder 25 receives the row address from register 26 and decodes it. Based on the decoded row address, the row decoder 25 performs word line selection. Then, the row decoder 25 transmits the multiple voltages required for write, read, and erase operations to the selected block.

[0068] The sense amplifier 24 receives the column address from register 26 and decodes it. The sense amplifier 24 includes a sense amplifier component group 24A and a data register 24B. The sense amplifier component group 24A is connected to each bit line and selects any bit line based on the decoded column address. Additionally, during data readout, the sense amplifier component group 24A detects and amplifies the data read from the memory cell transistor to the bit line. Furthermore, during data writeout, the sense amplifier component group 24A transmits the write data to the bit line.

[0069] When data is read out, data register 24B temporarily stores the data detected by the sense amplifier component group 24A and serially transmits it to the input / output circuit 22. Conversely, when data is written out, data register 24B temporarily stores the data serially transmitted from the input / output circuit 22 and transmits it to the sense amplifier component group 24A. Data register 24B includes SRAM, etc.

[0070] (1-3. Block Structure of a Memory Cell Array)

[0071] Figure 3 This is a diagram illustrating an example of the block configuration of a three-dimensional storage cell array 23. Figure 3 The diagram shows one block BLK, one of the multiple blocks constituting the memory cell array 23. The other blocks in the memory cell array also have the same characteristics. Figure 3 The same structure. Furthermore, this embodiment is also applicable to two-dimensional memory cell arrays.

[0072] As shown in the figure, a block BLK, for example, contains four string components (SU0 to SU3). Furthermore, each string component SU contains multiple NAND strings NS. Here, each NAND string NS contains eight memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. The memory cell transistors MT have a gate and a charge storage layer to non-volatilely store data. Furthermore, the number of memory cell transistors MT contained in the NAND string NS is eight, but it is not limited to eight; for example, it could be 32, 48, 64, 96, etc.

[0073] The select-gate transistors ST1 and ST2 are shown as a single transistor in the circuit, but their construction can be the same as that of the memory cell transistor. Alternatively, for example, to improve cutoff characteristics, multiple select-gate transistors can be used as select-gate transistors ST1 and ST2 respectively. Furthermore, a dummy cell transistor can be placed between the memory cell transistor MT and the select-gate transistors ST1 and ST2.

[0074] The memory cell transistor MT is configured to be connected in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one side is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other side is connected to the select gate transistor ST2.

[0075] The gates of the select gate transistors ST1 of each of the string components SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3 (hereinafter, they will be referred to as select gate lines SGD without distinction). On the other hand, the gates of the select gate transistors ST2 are all connected to the same select gate line SGS among the multiple string components SU within the same BLK. In addition, the gates of the memory cell transistors MT0 to MT7 within the same BLK are all connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 and select gate line SGS are all connected to the multiple string components SU0 to SU4 within the same BLK, while the select gate line SGD is set independently of each of the string components SU0 to SU3, even within the same BLK.

[0076] The gates of the memory cell transistors MT0 to MT7 that constitute the NAND string NS are connected to word lines WL0 to WL7, respectively. The gates of the memory cell transistors MTi located in the same row within block BLK are connected to the same word line WLi. Furthermore, in the following description, the NAND string NS is sometimes simply referred to as "string".

[0077] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST or other memory cell transistor MT contained in the NAND string NS. As described above, the data of the memory cell transistor MT located within the same BLK is erased at once. On the other hand, data is read and written in units of memory cell groups MG (or in units of pages). In this specification, multiple memory cell transistors MT connected to one word line WLi and belonging to one string component SU are defined as memory cell groups MG. During read and write operations, one word line WLi and one select gate line SGD are selected according to the physical address, and the memory cell group MG is selected.

[0078] (1-4. Cross-sectional structure of non-volatile memory)

[0079] Figure 4 This is a cross-sectional view of a portion of the semiconductor memory device according to an embodiment. Figure 4An example is shown in which a peripheral circuit region corresponding to peripheral circuits such as the sense amplifier 24 or the line decoder 25 is provided on the semiconductor substrate 71, and a memory region is provided on top of the peripheral circuit region. Furthermore, in the following description, two mutually orthogonal directions horizontal to the surface of the semiconductor substrate 71 are designated as the x-direction (first direction) and the y-direction (second direction), and the direction perpendicular to the surface of the semiconductor substrate 71 is designated as the z-direction.

[0080] like Figure 4 As shown, in the memory region MR, the non-volatile memory includes a semiconductor substrate 71, conductors 641-657, memory pillars 634, and contact plugs C0, C1, C2, and CP. Furthermore, in the accompanying drawings described below, illustrations of the p-type or n-type well regions formed on the upper surface portion of the semiconductor substrate 71, the impurity diffusion regions formed within each well region, and the gate insulating film and element separation regions that insulate the well regions are omitted.

[0081] In the memory region MR, a conductor GC is disposed on the semiconductor substrate 71, separated by a gate insulating film (not shown). Additionally, multiple impurity diffusion regions (not shown) are disposed on the semiconductor substrate 71, separated by the conductor GC, and for example, multiple contacts C0 are respectively disposed therein. A memory cell array 23 is disposed on the semiconductor substrate 71, separated by a wiring layer region WR.

[0082] Conductors 641 forming wiring patterns are disposed on each contact C0. For example, conductor GC functions as the gate electrode of the transistor, and conductor 641 functions as the source electrode or drain electrode of the transistor.

[0083] For example, a contact C1 is provided on each conductor 641. For example, a conductor 642 is provided on each contact C1. For example, a contact C2 is provided on each conductor 642. For example, a conductor 643 is provided on each contact C2.

[0084] The wiring patterns of conductors 641, 642, and 643 are disposed in the wiring layer region WR between the sense amplifier circuit (not shown) and the memory cell array. Hereinafter, the wiring layers on which conductors 641, 642, and 643 are disposed will be referred to as wiring layers D0, D1, and D2, respectively. Wiring layers D0, D1, and D2 are disposed in the lower layer of the non-volatile memory 2. Furthermore, while three wiring layers are disposed in the wiring layer region WR here, two or fewer wiring layers, or four or more wiring layers, may also be disposed in the wiring layer region WR.

[0085] Above conductor 643, conductor 644 is disposed, for example, with an interlayer insulating film in between. Conductor 644 is formed, for example, in a plate shape parallel to the xy plane, and functions as a source line SL. Above conductor 644, corresponding to each NAND string NS, conductors 645 to 654 are sequentially stacked, for example. An interlayer insulating film (not shown) is disposed between adjacent conductors in the z-direction.

[0086] Conductors 645 to 654 are formed, for example, in the form of plates parallel to the xy plane. For example, conductor 645 functions as the select gate line SGS, conductors 646 to 653 function as word lines WL0 to WL7 respectively, and conductor 654 functions as the select gate line SGD.

[0087] Each memory post 634 is columnar, penetrating and contacting the conductors 645 to 654 respectively. For example, the memory post 634 includes a conductor post 638 on the central side, a tunnel insulating film 637 formed on the outside of the conductor post 638, a charge storage film 636 formed on the outside of the tunnel insulating film 637, and a barrier insulating film 635 formed on the outside of the charge storage film 636.

[0088] For example, the portion where memory pillar 634 intersects with conductor 645 functions as selection transistor ST2. The portions where memory pillar 634 intersects with conductors 646-653 respectively function as memory cell transistors (memory cells) MT. The portion where memory pillar 634 intersects with conductor 654 functions as selection transistor ST1.

[0089] A conductor 655 is disposed on a layer above the upper surface of the memory cylinder 634, separated by an interlayer insulating film. The conductor 655 is formed as a line extending along the x-direction, corresponding to the bit line BL. A plurality of conductors 655 are arranged at intervals in the y-direction (not shown). The conductor 655 is electrically connected to a conductor cylinder 638 within one memory cylinder 634 corresponding to each string assembly SU.

[0090] Specifically, in each string component SU, for example, a contact plug CP is provided on the conductive post 638 within each memory post 634, and a conductor 645 is provided on the contact plug CP. Furthermore, this configuration is not limited to this; the conductive post 638 and the conductor 645 within the memory post 634 can also be connected via multiple contacts or wiring.

[0091] On top of the layer where conductor 655 is disposed, conductor 656 is disposed through an interlayer insulating film. On top of the layer where conductor 656 is disposed, conductor 657 is disposed through an interlayer insulating film.

[0092] Conductors 656 and 657 correspond, for example, to wiring used to connect wiring disposed in the memory cell array to peripheral circuitry disposed under the memory cell array. Conductors 656 and 657 can also be connected using columnar contacts (not shown). Here, the layer on which conductor 655 is disposed is referred to as wiring layer M0, the layer on which conductor 656 is disposed is referred to as wiring layer M1, and the layer on which conductor 657 is disposed is referred to as wiring layer M2.

[0093] like Figure 4 As shown, in this embodiment, the semiconductor memory device has wiring layers D0, D1, and D2 formed on the lower layer of the string assembly SU. Additionally, wiring layers M0, M1, and M2 are formed on the upper layer of the string assembly SU. The wiring layers D0, D1, and D2 are, for example, tungsten wiring formed using a metal inlay method.

[0094] Wiring layer M2 is, for example, an aluminum wiring formed using anisotropic etching such as reactive ion etching (RIE). Wiring layer M2 has a relatively thick film and low resistance, therefore it is used for basic power supply wiring (Vcc, Vss). Wiring layer M1 is, for example, a copper (Cu) wiring formed using a metal inlay method. Cu wiring has high wiring reliability, including high electromigration resistance; therefore, wiring layer M1 is used for signal lines that actually need to transmit data. Wiring layer M0 is, for example, a Cu wiring formed using a metal inlay method. Besides being used as bit lines BL, it is also used for a portion of basic power supply wiring to enhance power supply. Furthermore, for wiring other than basic power supply wiring such as signal lines, it is preferable to use upper wiring layers (e.g., wiring layer M2) to form wiring with the lowest possible resistance.

[0095] (1-5. Threshold voltage distribution of memory cell transistors)

[0096] Figure 5 This is a diagram illustrating an example of the threshold voltage distribution in an embodiment of the present invention. Figure 5 The diagram illustrates an example of the threshold voltage distribution for a 3-bit / cell non-volatile memory 2. In the non-volatile memory 2, information is stored based on the amount of charge accumulated in the charge accumulation layer of the memory cell. Each memory cell has a threshold voltage corresponding to the amount of charge. Furthermore, multiple data values ​​stored in the memory cell are respectively assigned to multiple regions of the threshold voltage (threshold voltage distribution regions).

[0097] Figure 5 The eight distributions (mountain-shaped) labeled Er, A, B, C, D, E, F, and G represent eight threshold voltage distribution regions. Thus, each memory cell has a threshold voltage distribution separated by seven boundaries. Figure 5 The horizontal axis represents the threshold voltage, and the vertical axis represents the distribution of the number of storage cells (cell count).

[0098] In this embodiment, the region with a threshold voltage below VrA is referred to as region Er, the region with a threshold voltage above VrA and below VrB is referred to as region A, the region with a threshold voltage above VrB and below VrC is referred to as region B, and the region with a threshold voltage above VrC and below VrD is referred to as region C. Furthermore, in this embodiment, the region with a threshold voltage above VrD and below VrE is referred to as region D, the region with a threshold voltage above VrE and below VrF is referred to as region E, the region with a threshold voltage above VrF and below VrG is referred to as region F, and the region with a threshold voltage above VrG is referred to as region G.

[0099] Furthermore, the threshold voltage distributions corresponding to regions Er, A, B, C, D, E, F, and G are respectively referred to as distributions Er, A, B, C, D, E, F, and G (distributions 1 to 8). VrA to VrG are the threshold voltages that form the boundaries of each region.

[0100] In the non-volatile memory 2, multiple data values ​​are respectively mapped to multiple threshold voltage distribution regions of the memory cell. This mapping is called data encoding. This data encoding is predetermined, and during data writing (programming), the memory cell is injected with charge in a manner that corresponds to the threshold voltage distribution region of the data value stored according to the data encoding. Furthermore, during data reading, a read voltage is applied to the memory cell, and the data is determined based on whether the threshold voltage of the memory cell is lower or higher than the read voltage.

[0101] Figure 6 This is a diagram illustrating the data encoding of an implementation method. In this implementation method, the following is used: Figure 5 The eight threshold voltage distribution regions shown correspond to eight 3-bit data values. The relationship between the threshold voltage and the bit data values ​​corresponding to the Upper, Middle, and Lower pages is as follows.

[0102] • Storage cells with threshold voltage within the Er region are in a state of storing "111".

[0103] • Storage cells with threshold voltage within region A are storing a state of "101".

[0104] • Storage cells with threshold voltage in region B are in a state of storing "001".

[0105] • Storage cells with threshold voltage in region C are in a state of storing "011".

[0106] • Storage cells with threshold voltage within region D are in a state of storing "010".

[0107] • Memory cells with threshold voltage in region E are storing a state of "110".

[0108] • Storage cells with threshold voltage in region F are storing a state of "100".

[0109] • Storage cells with threshold voltage within region G are in a state of storing "000".

[0110] In this way, the state of the 3 bits of data in each memory cell can be represented in each region of the threshold voltage. Furthermore, when the memory cell is in an unwritten state ("erased" state), the threshold voltage of the memory cell is within the Er region. Additionally, in the code shown here, "111" data is stored in the Er (erased) state, and "101" data is stored in the A state; thus, the data changes by only 1 bit between any two adjacent states. In this way, Figure 6 The encoding shown is Gray code, where the data changes by only 1 bit between any two adjacent regions.

[0111] also, Figure 5 The example provided illustrates a case with eight discretely distributed voltage levels, representing an ideal state immediately after data is written. However, in reality, adjacent voltage levels may overlap. For instance, disturbances after data writing can cause the upper edge of distribution Er to overlap with the lower edge of distribution A. In such cases, techniques like ECC can be used to correct the data.

[0112] (2. Action)

[0113] Next, the data writing operation of this embodiment will be explained.

[0114] (2-1. The concept of write operation)

[0115] First, the write operation of this embodiment will be briefly explained. The write operation generally includes a programming operation and a verification operation. When writing multi-valued data to the memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to the value corresponding to the data value. If a programming voltage VPGM and a bit line voltage Vbl are applied to the memory cell transistor MT, electrons are injected into the charge accumulation film of the memory cell transistor MT, and the threshold voltage rises. The amount of electron injection can be increased by increasing the programming voltage VPGM, thereby increasing the threshold voltage of the memory cell transistor MT. However, since memory cell transistors MT differ, the amount of electron injection in each memory cell transistor MT will be different even when the same programming voltage VPGM is applied. The temporarily injected electrons are retained until the erase operation is performed. Therefore, while gradually increasing the programming voltage VPGM, multiple programming and verification operations (loops) are performed to keep the threshold voltage within a range that allows it to be the threshold voltage that should be set for each memory cell transistor MT.

[0116] Programming is an action that raises the threshold voltage by injecting electrons into the charge accumulation layer (or maintains the threshold voltage by disabling injection). Hereinafter, the action of raising the threshold voltage will be referred to as "'0' programming" or "'0' writing," assigning "0" data to the bit line BL that is the target of "0" programming. On the other hand, the action of maintaining the threshold voltage will be referred to as "'1' programming," "'1' writing," or "write disabling," assigning "1" data to the bit line BL that is the target of "1" programming.

[0117] The verification action is a read operation performed as part of the write operation. After the programming operation, the verification action determines whether the threshold voltage of the memory cell transistor MT has reached the target level by reading data. Once the threshold voltage of the memory cell transistor MT has reached the target level, writing to it is disabled. By repeatedly performing this combination of programming and verification actions, the threshold voltage of the memory cell transistor MT rises to the target level.

[0118] Figure 7A This is a graph showing the potential changes of each wiring during the write operation (programming operation). Furthermore, Figure 7A The voltages shown are also generated by the voltage supply circuit 28 controlled by the sequencer 27.

[0119] Programming operations are performed based on the programming voltage and bit line voltage applied to the word line and bit line. For the string component SU (select SU) of the block to be written (BLK, select BLK), before applying the programming voltage VPGM, the select gate line SGD (SGD_sel) is pre-set to, for example, 5V, turning on the select gate transistor ST1. During programming, the select gate line SGS is, for example, 0V. Therefore, the select gate transistor ST2 is turned off. Then, when the programming voltage VPGM is applied, the select gate line SGD (SGD_sel) is, for example, 2.5V. Thus, the on / off state of the select gate transistor ST1 is determined based on the bit line voltage connected to the bit line BL of the select gate transistor ST1.

[0120] Additionally, for the non-write-object string component SU (non-select SU) of the block BLK (select BLK) to be written, similarly, before applying the programming voltage VPGM, the select gate line SGD (SGD_usel) is pre-set to, for example, 5V, turning on the select gate transistor ST1. Then, when the programming voltage VPGM is applied, the select gate line SGD (SGD_usel) is set to, for example, 0V. Thus, the select gate transistor ST1 is electrically disconnected from the bit line BL, becoming non-conductive.

[0121] Furthermore, in the non-write target block BLK (non-select BLK), 0 is applied to the select gate line SGD and the select gate line SGS. As a result, select transistors ST1 and ST2 are turned off.

[0122] As described above, the sense amplifier 24 transmits data to each bit line BL. A ground voltage Vss, for example 0V, is applied as the bit line voltage Vbl_L to the bit line BL assigned "0" data. A write inhibit voltage Vinhibit (e.g., 2.5V) is applied as the bit line voltage Vbl_H to the bit line BL assigned "1" data. Therefore, when the programming voltage VPGM is applied, the select gate transistor ST1 connected to the bit line BL assigned "0" data is turned on, and the select gate transistor ST1 connected to the bit line BL assigned "1" data is turned off. The memory cell transistor MT connected to the turned-off select gate transistor ST1 is disabled from writing.

[0123] The memory cell transistor MT connected to the select gate transistor ST1, which is in the on state, injects electrons into the charge accumulation film according to the voltage applied to the word line WL. The memory cell transistor MT connected to the word line WL, which is given a voltage VPASS as its word line voltage, is in the on state regardless of the threshold voltage, but does not inject electrons into the charge accumulation film. On the other hand, the memory cell transistor MT connected to the word line WL, which is given a programming voltage VPGM as its word line voltage, injects electrons into the charge accumulation film according to the programming voltage VPGM.

[0124] In other words, the line decoder 25 selects any word line WL in the selection block BLK, applies a programming voltage VPGM to the selected word line, and applies a voltage VPASS to the other word lines (non-selected word lines) WL. The programming voltage VPGM is a high voltage used to inject electrons into the charge accumulation film according to the tunneling phenomenon, and VPGM > VPASS. Figure 8 The image shows the status of the string component SU at this time.

[0125] Figure 8 It is a circuit diagram that represents the sequence of programming actions. Figure 8 The diagram shows the two NAND strings corresponding to bit line BL for writing "0" and bit line BL for writing "1". Additionally, it shows the case when word line WL3 is selected.

[0126] As shown in the figure, voltage VPGM is applied to the select word line WL3, and voltage VPASS is applied to the non-select word lines WL0~WL2 and WL4~WL7.

[0127] Furthermore, in the NAND string corresponding to the bit line BL that is written to "0", the select transistor ST1 becomes ON. Therefore, the channel potential Vch of the memory cell transistor MT3 connected to the select word line WL3 becomes 0V. That is, the potential difference between the control gate and the channel increases, resulting in electrons being injected into the charge accumulation layer, and the threshold voltage of the memory cell transistor MT3 rising.

[0128] In the NAND string corresponding to the bit line BL that is written with "1", the select transistor ST1 becomes off. Therefore, the channel of the memory cell transistor MT3 connected to the select word line WL3 electrically floats, causing the channel potential Vch to rise until it approaches the voltage VPGM through capacitive coupling with word lines WL, etc. In other words, the potential difference between the control gate and the channel decreases, resulting in no electrons being injected into the charge accumulation layer, and the threshold voltage of the memory cell transistor MT3 is maintained (the higher the threshold voltage distribution level, the less the threshold voltage changes).

[0129] In this way, the voltage of the word line WL is controlled by the line decoder 25, and data is supplied to each bit line BL by the sensing amplifier 24, thereby performing a writing operation (programming operation) on each memory cell transistor MT of the memory cell array 23.

[0130] Figure 7B This is a graph showing the potential changes of each wiring during the readout (verification) process. Furthermore, Figure 7B The voltages shown are also generated by the voltage supply circuit 28 controlled by the sequencer 27.

[0131] The line decoder 25 applies a readout voltage to the select word line WL (hereinafter also referred to as WL_sel), while the sensing amplifier 24 senses the data read from the bit line BL, determining whether the readout data is "0" or "1", and thus performing a verification operation, i.e., reading data from the multi-valued memory cell transistors. Furthermore, to turn on the memory cell transistors connected to the non-select word line WL (hereinafter also referred to as WL_usel), the line decoder 25 applies a sufficiently high voltage VREAD to the non-select word line WL_usel to turn on each memory cell transistor. Alternatively, a voltage VREADK slightly higher than VREAD can be applied to adjacent word lines to facilitate the turn-on of memory cell transistors connected to adjacent word lines.

[0132] Additionally, the line decoder 25 applies a voltage VSG to the select gate line SGD (hereinafter also referred to as SGD_sel) of the string component (select string component) constituting the read-out object in the string component SU, to turn on the select gate transistor ST1, and applies a voltage Vss (e.g., 0V) to turn off the select gate transistor ST1 to the select gate line SGD (hereinafter also referred to as the non-select gate line SGD_usel) constituting the string component (non-select string component) constituting the read-out object. Alternatively, after applying the voltage VSG to the non-select gate line SGD_usel to turn on the select gate transistor ST1, a voltage Vss to turn off the select gate transistor ST1 may be applied.

[0133] The line decoder 25 applies a readout voltage to the select word line WL_sel and a voltage VREAD or VEREDK to the non-select word line WL_usel. During readout, the sense amplifier 24 stabilizes the bit line BL at a fixed voltage (e.g., 1V) while simultaneously charging the sense node SEN (not shown) within the sense amplifier assembly group 24A to a specific precharge voltage Vpre higher than the bit line BL voltage. In this state, the logic control circuit 21 connects the sense node SEN to the bit line BL. As a result, current flows from the sense node SEN to the bit line BL, and the voltage of the sense node SEN gradually decreases.

[0134] The voltage at the sensing node SEN varies depending on the threshold voltage of the memory cell transistor connected to the corresponding bit line BL. Specifically, when the threshold voltage of the memory cell transistor is lower than the read voltage, the transistor is on, a larger cell current flows through it, and the voltage at the sensing node SEN decreases more rapidly. Conversely, when the threshold voltage of the memory cell transistor is higher than the read voltage, the transistor is off, a smaller cell current flows through it, or no cell current flows through it, and the voltage at the sensing node SEN decreases more slowly.

[0135] The write state of the memory cell transistor is determined by the rate of voltage drop at the sensing node SEN, and the result is stored in the data latch circuit. For example, at the first point in a specific first period after the discharge of charge from the sensing node SEN begins, it is determined whether the voltage of the sensing node SEN is low (hereinafter also referred to as "L") or high (hereinafter also referred to as "H"). For example, when the threshold voltage of the memory cell transistor is lower than the read voltage, the memory cell transistor is fully turned on, and a large cell current flows through the memory cell transistor. Therefore, the voltage of the sensing node SEN drops rapidly, and the voltage drop is relatively large. At the first point in time, the sensing node SEN becomes "L".

[0136] Furthermore, when the threshold voltage of the memory cell transistor is higher than the read voltage, the memory cell transistor is in the off state, and the cell current flowing in the memory cell transistor is very small, or there is no cell current flowing in the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases very slowly, and the voltage drop is relatively small. At point 1, the sensing node SEN still remains in the "H" state.

[0137] In this way, by applying a readout voltage to the select word line WL_sel using the line decoder 25 and monitoring the state of the sensing node SEN by the sensing amplifier circuit, it can be determined whether the threshold voltage of the memory cell transistor is higher or lower than the readout voltage. Therefore, by applying the voltage between each level as the readout voltage to the select word line WL_sel, the level of each memory cell transistor can be determined, and the data assigned to each level can be read out.

[0138] For example, by allocating data to the eight threshold voltage distributions of a TLC, each memory cell transistor in the TLC can store 3 bits of data. Each memory cell transistor is written to at any of the Er, A, B, ..., G levels corresponding to the eight threshold voltage distributions. During readout, the data value of each memory cell transistor can be determined by applying voltages VrA to VrG. Furthermore, in the following description, the readout voltages applied to the select word line WL_sel during the verification operation are referred to as voltages VfyA to VfyG.

[0139] (2-2. Specific examples of write operations)

[0140] When describing the writing operation in this embodiment, firstly, using Figure 9 The standard write sequence is explained in detail. Figure 9 The example shown illustrates how data is written by repeatedly performing a combination of programming and verification actions 19 times. This repeated action is called a "loop".

[0141] Figure 9 The diagram shows the target voltage levels for the verification actions performed in each loop. As shown, in the first and second loops, the verification action is performed only at voltage level "A". That is, during the verification action, voltage VfyA is applied to the select word line WL_sel, while voltages VfyB to VfyG are not applied. In the following third and fourth loops, the verification action is performed at both voltage levels "A" and "B". That is, during the verification action, voltages VfyA and VfyB are applied sequentially to the select word line WL_sel, while voltages VfyC to VfyG are not applied.

[0142] In the 5th and 6th loops, the verification is performed on the "A", "B", and "C" voltage levels. That is, during the verification, voltages VfyA, VfyB, and VfyC are applied sequentially to the select word line WL_sel, while voltages VfyD to VfyG are not applied. Furthermore, the verification operation targeting the "A" level is completed in the 6th loop. This is because, empirically, 6 loops are sufficient to roughly complete the programming of the "A" level.

[0143] Furthermore, in the 7th and 8th loops, the verification operation is performed using the "B", "C", and "D" levels. That is, during the verification operation, voltages VfyB, VfyC, and VfyD are applied sequentially to the select word line WL_sel. Moreover, the verification operation using the "B" level is completed during the 8th write operation. Then, in the 9th and 10th loops, the verification operation is performed using the "C", "D", and "E" levels. That is, during the verification operation, voltages VfyC, VfyD, and VfyE are applied sequentially to the select word line WL_sel. Moreover, the verification operation using the "C" level is completed during the 10th loop. The same process is then repeated up to the "G" level for a maximum of 19 loops.

[0144] Figure 10 This is a graph representing the timing of programming and verification actions during a write operation based on the standard write sequence. For example... Figure 10 As shown, in the first and second loops, the verification action is performed only at the "A" level. That is, one verification action is performed for each programming action. In the third and fourth loops, the verification action is performed at both the "A" and "B" levels. That is, two verification actions are performed for each programming action. In the twelfth loop, from the fifth loop until the verification action at the "D" level is completed, three verification actions are performed for each programming action. Thereafter, the same pattern continues, with verification actions performed at the set specific levels for each programming action. Ultimately, in 19 loops, 19 programming actions and 42 verification actions were performed.

[0145] Furthermore, the above explanation assumes that the maximum number of verification actions can be performed. For example... Figure 9 As shown, the verification operation targeting the "A" level can be performed a maximum of 6 times from the 1st to the 6th loop. Similarly, the verification operation targeting the "B" level can be performed a maximum of 6 times from the 3rd to the 8th loop. The same applies to other levels. Here, for example, there are multiple memory cell transistors MT that write to the "A" level, and multiple lines BL ("A") connected to these memory cell transistors MT. Therefore, strictly speaking, for example, there might be a situation where, if all memory cell transistors MT that write to the "A" level pass the verification operation targeting the "A" level in the 5th loop, the bit line BL ("A") does not perform a verification operation in the 6th loop. This situation will also be the case in the following explanation.

[0146] The voltage VPGM applied to the select word line WL_sel in the first programming operation, the increase in voltage VPGM in subsequent programming operations, and the loop that starts the verification operation at each level are set based on the worst-case scenario of faster writing. It is necessary to fully ensure that the setting range is met in order to avoid writing beyond the target level.

[0147] The number of loops in the write operation described above, the voltage of the select word line WL_sel in each loop (voltage VPGM), and the verification action object level in each loop are stored in the sequencer 27 as a standard write sequence. When performing a write operation on the memory cell array 23 based on the standard write sequence, a control signal based on the standard write sequence is output from the sequencer 27 to the sense amplifier 24 and the line decoder 25.

[0148] Next, the potential changes of each wiring during the write operation (programming operation + verification operation) will be explained. Figure 11 It is a graph showing the potential changes of each wiring during a write operation. Figure 11 The potential changes of each wiring are illustrated using the third cycle as an example. Additionally, Figure 11 The diagram shows the channel potential of the NAND string corresponding to the bit line BL for writing "1" (corresponding to the solid line, also referred to as the disable channel potential below), and the channel potential of the NAND string corresponding to the bit line BL for writing "0" (corresponding to the single-point chain line, also referred to as the programming channel potential below). Figure 11 The write operation is performed between time t1 and time t5. The programming operation is performed between time t1 and time t3. The verification operation is performed between time t3 and time t5.

[0149] The programming action has an actual programming period (time t1 to time t2, hereinafter referred to as the actual programming period) and a transition period to the verification action (time t2 to time t3, hereinafter referred to as the VPASS2VREAD period). The actual programming period is the period during which the action of raising the threshold voltage of the memory cell transistor MT is performed (or maintaining the threshold voltage by disabling injection). That is, according to Figure 7A The potential changes shown are used to set and change the potential of each line. The non-select word line WL_usel is applied with a voltage VPASS (e.g., 10V), and the select word line WL_sel is applied with the programming voltage VPGM3 of the third cycle (e.g., 13V). Additionally, the select gate line SGD_sel is applied with a voltage VSGD (e.g., 2.5V), and the non-select gate lines SGD_usel and SGS are applied with a voltage Vss. Furthermore, Figure 11 In the middle, the following was omitted. Figure 7A The potential change shown is the first half of the potential change; only the second half is shown.

[0150] During actual programming, the NAND string corresponding to the bit line BL of the "1" write object is turned off along with the select gate transistors ST1 and ST2. Therefore, the channel potential of this NAND string, which is also the disable channel potential, is boosted due to the capacitive coupling between the select word line WL_sel and the disable channel, and the capacitive coupling between the non-select word line WL_usel and the disable channel. Furthermore, the boost level is based on the following equation (1).

[0151] Forbidden Channel Potential

[0152] =Vint+α(VPGM+(VPASS×number of non-select word lines WL_usel)

[0153] -(Vtcell × number of word lines WL))(1)

[0154] In equation (1), Vint is the voltage applied to the channel first, and Vtcell is the threshold voltage of the cell.

[0155] The VPASS2VREAD period is a time when the voltages of the select word line WL_sel and the non-select word line WL_usel are discharged before the verification operation. Previously, during VPASS2VREAD, the voltages of the select word line WL_sel and the non-select word line WL_usel were discharged, reducing them to ground voltage Vss (e.g., 0V). In contrast, during... Figure 11 In one example, only the voltages of the select word line WL_sel and the non-select word line WL_usel are discharged to the voltage VPASS2VREAD. The voltage VPASS2VREAD is set to be higher than the ground voltage Vss and lower than the voltage that first charges to word line WL during the verification operation. Figure 11 In one example shown, the voltage is VREAD. The voltage VPASS2VREAD is set to approximately 3-6V. By discharging only the voltages of the select word line WL_sel and the non-select word line WL_usel to VPASS2VREAD, the current flowing from the word line WL can be reduced, improving operating efficiency. As the voltage of the select word line WL_sel decreases, the disable channel potential also decreases below the value of VPASS2VREAD (Vinh).

[0156] also, Figure 11 During VPASS2VREAD, the voltage VSS2VSG of the select gate lines SGD_sel, SGD_usel, and SGS is set to be approximately 1V higher than the voltage Vss and lower than the voltage VSGD (the voltage applied to the select gate line SGD_sel during programming, e.g., 2.5V), but the voltage level is not limited to this. The voltage VSS2VSG can be, for example, the voltage Vss, or other specific voltage levels.

[0157] The verification process has an anti-interference period (time t3 to time t4, hereinafter referred to as the USTRDIS period) and an actual verification period (time t4 to time t5, hereinafter referred to as the actual verification period). The USTRDIS period is the period during which all channels are turned on at the start of the actual verification process to prevent interference (unexpected rise in threshold voltage). That is, when the cells belonging to the select word line WL_sel in the non-selection string are not turned on, the potential on the drain side rises, and the potential on the source side becomes VCELSRC, resulting in a large potential difference. In this case, HCI (Hot carrier injection) occurs, causing a change in the threshold voltage of nearby cells. To deal with this phenomenon, the non-selection gate line SGD_usel on the drain side of the non-selection string is turned on to remove the boosted potential, thereby preventing a potential difference between the drain and source sides. This prevents an unexpected rise in threshold voltage. A voltage VSG (e.g., 5V) is applied to the select gate lines SGD_sel, SGD_usel, and SGS to turn on the select gate transistors ST1 and ST2. Apply a sufficiently high voltage VREAD (e.g., 8V) to the select word line WL_sel and the non-select word line WL_usel to turn on the transistors of each memory cell.

[0158] During the actual verification, the select gate lines SGD_sel and SGS are maintained at voltage VSG (e.g., 5V). Meanwhile, the non-select gate line SGD_usel is reduced to voltage Vss (e.g., 0V), used to turn off the select gate transistor ST1. Additionally, during the actual verification, the non-select word line WL_usel is maintained at voltage VREAD. Conversely, the select word line WL_sel changes to voltages VfyA and VfyB, used to read the A and B levels. Throughout the entire verification process, the select gate transistor ST2 of all NAND strings is turned on. Therefore, the disable channel potential becomes 0V.

[0159] (2-3. Voltage control of each wiring during the write operation)

[0160] Next, use Figures 12-17 The generation and control of the voltage applied to each wiring line during the write operation are explained. Figure 12 This is a block diagram illustrating an example of the configuration of the voltage supply circuit 28 and the line decoder 25. Furthermore, Figure 12 Only a portion of the voltage supply circuit 28 is shown in the diagram.

[0161] Figure 12In this circuit, voltage supply circuit 28 generates various voltages, including those required for programming and reading operations of the memory cell transistor MT. Voltage supply circuit 28 includes SG drivers 28A that supply voltage to signal lines SG0-SG4, and multiple CG drivers 28B that supply voltage to signal lines CG0-CG7 respectively. These signal lines SG0-SG4 and CG0-CG7 are branched by the line decoder 25 and connected to the wiring of each BLK. Specifically, signal lines SG0-SG3 function as global drain-side select gate lines, connected via the line decoder 25 to the select gate lines SGD0-SGD3 in each BLK as local select gate lines. Signal lines CG0-CG7 function as global word lines, connected via the line decoder 25 to the word lines WL0-WL7 in each BLK as local word lines. Signal line SG4 functions as a global source-side select gate line, connected via the line decoder 25 to the select gate line SGS in each BLK as a local select gate line.

[0162] The voltage supply circuit 28 is controlled by the sequencer 27 to generate various voltages. The SG driver (select gate line driver) 28A and the CG driver (word line driver) 28B supply the generated voltages to the corresponding signal lines SG0 to SG4 and signal lines CG0 to CG7, respectively.

[0163] The line decoder 25 has multiple switch circuit groups 25A corresponding to each block, and multiple block decoders 25B corresponding to each of the multiple switch circuit groups 25A. Each switch circuit group 25A includes multiple transistors TR_SG0 to TR_SG4 that connect signal lines SG0 to SG4 to select gate lines SGD0 to SGD4 respectively, and multiple transistors TR_CG0 to TR_CG7 that connect signal lines CG0 to CG7 to word lines WL0 to WL7 respectively. Transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7 are high-voltage transistors.

[0164] When each block decoder 25B is assigned according to its row address, it supplies the block selection signal BLKSEL to the gates of transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7. As a result, in the switching circuit group 25A that supplies the block selection signal BLKSEL from the block decoder 25B assigned according to the row address, transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7 are turned on and conducted. Therefore, the voltage supplied from the power generation circuit 28 to the signal lines SG0 to SG4 and signal lines CG0 to CG7 is supplied to the selection gate lines SGD0 to SGD3, SGS, and word lines WL0 to WL7 contained in the block BLK to be operated.

[0165] In other words, the voltage supply circuit 28 and the line decoder 25 supply voltages such as VPGM or VCGRV to the select word line WL, and voltages such as VREAD or VREADK to the non-select word line WL. Additionally, for example, voltages such as VSGD are supplied to the select gate line SGD (SGD_sel) connected to the select gate transistor ST1 of the string component SU that is subject to operation, and voltages such as Vss are supplied to the select gate line SGD (SGD_usel) connected to the select gate transistor ST1 of the string component SU that is not subject to operation, where Vss is 0V.

[0166] Figure 13 This is a block diagram illustrating an example of the specific configuration of the voltage supply circuit 28. The voltage supply circuit 28 includes a voltage generation circuit 281, a regulator circuit 282, an SG driver 28A, and a CG driver 28B. The circuits for generating the various voltages required for the operation of the word line WL will be described in detail below.

[0167] The voltage generation circuit 281 uses the voltage input from the power input terminal group 35 to generate various voltages required for the operation of each part of the non-volatile memory 2. The voltage generation circuit 281 includes a first pump 281A, a second pump 281B, and a third pump 281C. The first pump 281A generates a voltage VPGM, which serves as the programming voltage. The second pump 281B generates voltages VPASS, VREAD, and VPASS2VREAD. The third pump 281C generates a voltage VCGRV, which serves as the verification voltage.

[0168] The regulating circuit 282 generates a voltage using the voltage input from the voltage generating circuit 281, and this voltage remains a fixed value even if the input voltage or output current varies. The regulating circuit 282 has three regulators 282A to 282C. Regulator 282A generates voltage VPGM using the voltage input from the first pump 281A. Regulator 282B generates voltage VPASS, VREAD, or VPASS2VREAD using the voltage input from the second pump 281B. Regulator 282C generates voltage VCGRV using the voltage input from the third pump 281C. The voltages generated by regulators 282A to 282C are input to the CG driver 28B.

[0169] The CG driver 28B has multiple input terminals, each of which can be input with various input voltages, allowing multiple voltages to be input from the regulator circuit 282. Each input terminal of the CG driver 28B is connected to an output terminal via switches T1, T2, and T3 configured on the respective supply paths of the various voltages. By selecting and turning on any one of the switches T1, T2, and T3, a voltage is applied to the supply path connected to the selected switch, resulting in a voltage appearing at the output terminal.

[0170] In other words, the voltage input from regulator 282A is supplied to the output terminal via switch T1. The voltage input from regulator 282B is supplied to the output terminal via switch T2. The voltage input from regulator 282C is supplied to the output terminal via switch T3.

[0171] Furthermore, like the CG driver 28B, the SG driver 28A has multiple input terminals, each of which can be input with various input voltages, allowing multiple voltages to be input from the regulator circuit 282. Each input terminal of the SG driver 28A is connected to one output terminal via switches T1, T2, ... configured on the respective supply paths of the various voltages. By selecting and turning on any one of the switches T1, T2, ..., a voltage supplied to the supply path connected to the selected switch appears at the output terminal.

[0172] The operation of each part of the voltage supply circuit 28 is controlled by the sequencer 27. For example, the sequencer 27 controls the selection of the switches T1, T2, and T3 to be in the ON state, the voltage generated by each pump 281A to 281C in the voltage generation circuit 281, and the voltage value generated by each regulator 282A to 282C in the regulator circuit 282.

[0173] Figure 14A This is a block diagram illustrating an example of the specific configuration of the second pump 281B. The second pump 281B, for example, includes four pump assemblies PU1 to PU4 and nine switching circuits SW1 to SW9. The pump assemblies PU1 to PU4 each include, as follows: Figure 15 The charge pump circuit shown is an example.

[0174] Figure 15 This diagram illustrates an example of a charge pump circuit. The charge pump circuit constituting the pump assembly PU includes n+1 NMOS transistors NM1 to NM(n+1) and n capacitors C1 to Cn. The NMOS transistors NM1 to NM(n+1) are each connected as diodes, functioning as diodes. The current paths of the NMOS transistors NM1 to NM(n+1) are connected in series sequentially.

[0175] One end of capacitors C1 to Cn is electrically connected to one end of NMOS transistors NM1 to NMn, respectively. A clock signal CLK is supplied to the other end of capacitors C1, C3, ..., C(2m-1) connected to NMOS transistors NM1, NM3, ..., and the odd-numbered NMOS transistors NM(2m-1) (where m = 1, 2, ...). A clock signal / CLK is supplied to the other end of capacitors C2, C4, ..., C(2m) connected to NMOS transistors NM2, NM4, ..., and the even-numbered NMOS transistors NM(2m). A voltage Vsup (e.g., the power supply voltage Vcc) is input to the other end of NMOS transistor NM1. Furthermore, capacitors C1 to Cn are repeatedly charged and discharged according to the clock signals CLK and / CLK. As a result, an output voltage Vout greater than Vsup is generated, and this output voltage Vout is transmitted (output) from one end of NMOS transistor NM(n+1).

[0176] The four pump components PU1 to PU4 constituting the second pump 281B can be configured into the following three circuits by switching the switching circuits SW1 to SW9 on / off. Figures 14B-14D This is a block diagram showing an example of the specific connection state of each unit constituting the second pump 281B. The first circuit configuration (first state) is a configuration in which four pump assemblies PU1 to PU4 are connected in parallel between the input and output terminals. Figure 14B This is a block diagram illustrating the composition of state 1. For example... Figure 14B As shown, switch circuits SW1-3 and SW7-9 are turned on, and switch circuit SW4-6 is turned off, thereby connecting the four pump assemblies PU1-PU4 in parallel between the input and output terminals.

[0177] The second circuit configuration (second state) is to connect pump components PU1 and PU2 in series to form pump component group PUG1, connect pump components PU3 and PU4 in series to form pump component group PUG2, and connect pump component group PUG1 and pump component group PUG2 in parallel. Figure 14C This is a block diagram illustrating the composition of the second state. For example... Figure 14C As shown, in state 2, switch circuits SW2, 4, 6, and 8 are turned on, while switch circuits SW1, 3, 5, 7, and 9 are turned off. By turning on switch circuit SW4, pump assemblies PU1 and PU2 are connected in series, thus forming pump assembly group PUG1. Furthermore, by turning on switch circuit SW6, pump assemblies PU3 and PU4 are connected in series, thus forming pump assembly group PUG2. By turning on SW2 and 8, pump assembly groups PUG1 and PUG2 are connected in parallel between the input and output terminals.

[0178] The third circuit configuration is a configuration in which pump assemblies PU1 to PU4 are connected in series. Figure 14D This is a block diagram illustrating the composition of the third state. For example... Figure 14D As shown, by turning on the switching circuits SW4-6 and turning off the switching circuits SW1-3 and SW7-9, the four pump assemblies PU1-PU4 are connected in series between the input and output terminals.

[0179] Figure 16 This is a diagram illustrating the current efficiency characteristics of the second pump 281B relative to the output voltage. Figure 16 In the diagram, dashed lines represent the characteristics of state 1, single-dot chain lines represent the characteristics of state 2, and double-dot chain lines represent the characteristics of state 3. Additionally, solid lines represent the characteristics of the second pump when high-efficiency current supply is achieved. For example... Figure 16 As shown, the current efficiency characteristics of the second pump 281B vary depending on the circuit configuration. In the first state ( Figure 14B In the case of a circuit configuration where pump assemblies PU1 to PU4 are connected in parallel between the input and output terminals, current can be supplied efficiently in the region where the output voltage Vout is low (e.g., below 5V) compared to other states. However, as the output voltage Vout increases, the current efficiency decreases, and when it exceeds a certain output voltage Vout (e.g., 8V), it becomes impossible to supply current.

[0180] On the other hand, in the second state ( Figure 14C In the second state, specifically in a circuit configuration consisting of two pump groups (PUs connected in series between the input and output terminals) connected in parallel, the current efficiency is lower than in the first state but higher than in the third state in the region where the output voltage Vout is low. Current efficiency decreases as the output voltage Vout increases, but the rate of decrease (characteristic slope) relative to the increase in output voltage Vout is smaller than in the first state. Therefore, if the output voltage Vout exceeds a certain voltage (e.g., 5V), current can be supplied more efficiently than in the first state. However, because the rate of decrease (characteristic slope) in current efficiency is greater than in the third state, the current efficiency is lower than in the third state in the region where the output voltage Vout is high (e.g., above 8V). In other words, in the second state, in the region where the output voltage Vout is in the middle (e.g., the region where the output voltage Vout is between 5V and 8V), current can be supplied more efficiently compared to other states.

[0181] Furthermore, in the third state ( Figure 14DIn the case where the circuit configuration involves connecting pump assemblies PU1 to PU4 in series between the input and output terminals, the current efficiency is lower than in the first and second states in the region where the output voltage Vout is low. However, the rate of decrease in current efficiency (characteristic slope) is smaller than in the first and second states. Therefore, in the region where the output voltage Vout is high (e.g., above 8V), the current efficiency is higher than in the first and second states. In other words, in the third state, in the region where the output voltage Vout is high (e.g., above 8V), current can be supplied more efficiently compared to other states.

[0182] In this way, in regions with low output voltage (e.g., below 5V), the circuit configuration in state 1 supplies current with the highest efficiency; in regions with intermediate output voltage (e.g., between 5V and 8V), the circuit configuration in state 2 supplies current with the highest efficiency; and in regions with high output voltage (e.g., above 8V), the circuit configuration in state 3 supplies current with the highest efficiency. Therefore, the second pump 281B switches to a state that supplies current with high efficiency based on the output voltage. In other words, the current characteristics achieved in the second pump 281B become... Figure 16 The characteristics are shown by the solid line. Furthermore, the state switching of the second pump 281B is controlled by a sequencer 27. The sequencer 27 indicates the switching circuit configuration of the second pump 281B based on the set value of the output voltage Vout.

[0183] Furthermore, if the current consumption of the non-volatile memory 2 increases suddenly, it may adversely affect its operation. Therefore, when charging the signal lines SG0-SG4 and CG0-CG7 from the voltage supply circuit 28, do not charge rapidly, but charge gradually in stages. Figure 17 This diagram illustrates the pump pressure boosting control during verification operations. The following explanation uses the operation control of the second pump 281B during USTRDIS as an example to illustrate the pump pressure boosting control during verification operations.

[0184] The voltage of the non-selection word line WL_usel is VPASS2VREAD (e.g., 6V) at time t3. During USTRDIS, the voltage of the non-selection word line WL_usel must be boosted to VREAD (e.g., 8V). At time t3, the output voltage Vout of the second pump 281B is set to 8V for charging. In this case, the second pump 281B continuously drives pump components PU1 to PU4 until the output voltage Vout reaches 8V. That is, pump components PU1 to PU4 continuously perform boosting operations according to the period of the input clock signal CLK until the output voltage Vout reaches 8V. For example, if Vout is boosted by 0.2V using one pumping operation, 10 pumping operations are required to boost the output voltage Vout from 6V to 8V. When 10 pumping operations are performed continuously, the current consumption for charging will be concentrated within 10 cycles of the clock signal CLK. In other words, the current consumed per unit time, or the peak current, becomes very large at time t3.

[0185] To prevent a short-term concentration of current consumption and a reduction in peak current, sequencer 27 sets the output voltage Vout of the second pump 281B to multiple intermediate setpoints in increments of voltage Vstp (e.g., 0.4V), instead of increasing from the initial value to 8V. This allows the output voltage Vout to rise in stages. When the output voltage Vout of the second pump 281B reaches an intermediate setpoint, sequencer 27, after a specific period (pause period), raises the setpoint to the next intermediate setpoint, performing a boost operation.

[0186] Figure 17 In this diagram, BINVM represents the set value of the output voltage Vout of the second pump 281B, set by the sequencer 27. At time t3, the sequencer 27 sets the output voltage Vout of the second pump 281B to the value obtained by adding a step voltage Vstp (e.g., 0.4V) to the voltage VPASS2VREAD (e.g., 6V). The second pump 281B performs, for example, two pumping operations, boosting the output voltage Vout by 0.4V. After a pause period following the completion of the boosting operation of the second pump 281B, the sequencer 27 sets the output voltage Vout of the second pump 281B to the value after another 0.4V increase (e.g., 6.8V). The sequencer 27 increases the set value step voltage Vstp (e.g., 0.4V) successively until the output voltage Vout of the second pump 281B reaches the voltage VREAD (e.g., 8V). In this way, by setting a pause period and gradually increasing the set value of the output voltage Vout of the second pump 281B, the pumping action can be dispersed, thus preventing current consumption from concentrating in a short period of time and reducing the peak current.

[0187] (2-4. Potential changes of non-select word lines during USTRDIS)

[0188] Figure 18 This is a graph showing the potential changes of the non-select word lines during USTRDIS. As described above, during USTRDIS, all channels are turned on to prevent an unexpected rise in the threshold voltage. That is, a voltage VSG (e.g., 5V) is applied to the select gate lines SGD_sel, SGD_usel, and SGS to turn on the select gate transistors ST1 and ST2. A sufficiently high voltage VREAD (e.g., 8V) is applied to the non-select word line WL_usel to turn on each memory cell transistor.

[0189] During the VPASS2VREAD period prior to USTRDIS (from time t2 to time t3), the inhibit channel potential (the channel potential of the NAND string corresponding to the bit line BL of the "1" write object) is boosted to a specific level due to the capacitive coupling between the select word line WL_sel and the non-select word line WL_usel and the inhibit channel.

[0190] At time t3, when the select gate transistors ST1 and ST2 are turned on, all channels are turned on. Therefore, the inactive channel potential drops to ground voltage Vss. As the inactive channel potential decreases, the voltage of the non-select word line WL_usel also decreases due to the capacitive coupling between the non-select word line WL_usel and the inactive channel. Hereinafter, the voltage drop in the non-select word line WL_usel starting from voltage VPASS2VREAD is defined as voltage Vdwn.

[0191] On the other hand, at time t3, sequencer 27 sets the initial intermediate setting value of the output voltage Vout of the second pump 281B to the value obtained by increasing the step voltage Vstp (e.g., 0.4V) from the voltage VPASS2VREAD (e.g., 6V). The second pump 281B continuously drives pump assemblies PU1 to PU4 to perform pumping operations to boost the output voltage Vout to the initial intermediate setting value. As the voltage of the non-select word line WL_usel decreases, the second pump 281B must boost the output voltage Vout by an amount equivalent to the step voltage Vstp + voltage Vdwn. Therefore, during the period when the output voltage Vout is boosted to the initial intermediate setting value, pumping operations are performed continuously, resulting in a concentration of current consumption in a short period of time and an increase in peak current.

[0192] Furthermore, with the initial intermediate setting set to 6.4V, the second pump is set to state 2. The voltage of the non-select word line WL_usel has decreased from voltage VPASS2VREAD by an amount equivalent to voltage Vdwn, therefore it should originally be set to state 1. However, according to the control, the second pump is set to state 2, which has a lower current efficiency than state 1, thus increasing the pumping action required for boosting.

[0193] (2-5. Operation of the voltage generation circuit in the implementation)

[0194] Next, refer to Figure 19 , 20 The operation control of the second pump 281B in this embodiment will be explained. Figure 19 This diagram illustrates the pump pressurization control during the first half of the write sequence. Figure 20 This diagram illustrates the pump pressurization control in the second half of the write sequence.

[0195] The voltage drop of the non-select word line WL_usel during USTRDIS is due to capacitive coupling with the inhibit channel. Therefore, in the first half of the write sequence cycle, when the number of bit lines BL for "1" writes is small and the number of bit lines BL for "0" writes is large, the number of NAND strings corresponding to bit lines BL for "1" writes is small, and the number of NAND strings corresponding to bit lines BL for "0" writes is large. Consequently, the effective opposing area between the inhibit channel and the non-select word line WL_usel is small, while the effective opposing area between the programming channel and the non-select word line WL_usel is large. Therefore, the voltage drop (Vdwn) of the non-select word line WL_usel that accompanies the decrease in the inhibit channel potential at the beginning of USTRDIS is also small.

[0196] On the other hand, as the write sequence loop progresses, the number of bit lines BL for "1" write objects increases, while the number of bit lines BL for "0" write objects decreases. Therefore, the number of NAND strings corresponding to bit lines BL for "1" write objects increases, and the number of NAND strings corresponding to bit lines BL for "0" write objects decreases. Consequently, the effective opposing area between the inhibit channel and the non-select word line WL_usel increases, while the effective opposing area between the programming channel and the non-select word line WL_usel decreases. Therefore, the voltage drop (voltage Vdwn) of the non-select word line WL_usel as the inhibit channel potential decreases after the start of the USTRDIS period increases. Therefore, in this embodiment, the write sequence loop is divided into two parts, and different methods are used to control the operation of the second pump 281B in the first and second halves of the loop.

[0197] like Figure 19As shown, the motion control of the second pump 281B in the first half-cycle utilizes and uses Figure 17 The same method is used for explanation. That is, at time t3, sequencer 27 sets the initial intermediate setting value of the output voltage Vout of the second pump 281B to the value obtained by adding a step voltage Vstp (e.g., 0.4V) to the voltage VPASS2VREAD (e.g., 6V). Furthermore, the state of the second pump 281B is set to a state corresponding to the setting value of the output voltage Vout. For example, when the setting value of the output voltage Vout is 6.4V, and the current efficiency characteristic of the second pump 281B is... Figure 16 Under the characteristics shown, sequencer 27 sets the state of the second pump 281B to the second state. The second pump 281B, under the control of sequencer 27, boosts the output voltage Vout to the initial intermediate set value (e.g., 6.4V). During the initial boost operation in USTRDIS, the second pump 281B must boost the output voltage Vout by an amount equivalent to the step voltage Vstp + voltage Vdwn. However, in the first half of the cycle, because the voltage drop (voltage Vdwn) of the non-select word line WL_usel is small, the increment of the pumping action is also small. Therefore, although the peak current increases, the increase is small.

[0198] When the output voltage Vout of the second pump 281B has risen to the initial intermediate setting value, the sequencer 27, after a specific pause period, sets the next intermediate setting value of the output voltage Vout of the second pump 281B to the value increased by the step voltage Vstp. Additionally, the sequencer 27 sets the state of the second pump 281B to the state corresponding to the next intermediate setting value. Thereafter, the sequencer 27 causes the intermediate setting value of the output voltage Vout of the second pump 281B to rise in stages, including pause periods, until the output voltage Vout of the second pump 281B reaches the voltage VREAD.

[0199] On the other hand, the operation control of the second pump 281B in the second half of the cycle differs from the control of the first half of the cycle at the initial intermediate setpoint level. For example... Figure 20 As shown, at time t3, sequencer 27 sets the initial intermediate setting value of the output voltage Vout of the second pump 281B to a value lower than the voltage VPASS2VREAD (e.g., 6V) (e.g., 4.8V). The amount of voltage drop from VPASS2VREAD is determined by considering the voltage drop (Vdwn) of the non-selection word line WL_usel. Furthermore, the state of the second pump 281B is set to a state corresponding to the set value of the output voltage Vout. For example, when the set value of the output voltage Vout is 4.8V, and the current efficiency characteristic of the second pump 281B is... Figure 16Under the characteristics shown, sequencer 27 sets the state of the second pump 281B to state 1. Following the control of sequencer 27, the second pump 281B boosts the output voltage Vout to the initial intermediate set value (e.g., 4.8V). The operation control after the output voltage Vout is boosted to the initial intermediate set value is... Figure 19 The motion control in the first half of the loop shown is the same.

[0200] exist Figure 18 In the comparative example control shown, the initial intermediate setpoint of the output voltage Vout is set to the voltage VPASS2VREAD + step voltage Vstp (e.g., 6.4V). In contrast, in... Figure 20 In the control of this embodiment shown, the voltage VPASS2VREAD is set to a value lower than (e.g., 6V) (e.g., 4.8V). That is, in this embodiment, during the boost operation control of the second pump 281B in the latter half of the cycle, the initial intermediate setting value of the output voltage Vout is set to a value close to the potential of the non-selection word line WL_usel before boosting, taking into account the voltage drop (voltage Vdwn) of the non-selection word line WL_usel. Furthermore, by controlling the initial intermediate setting value in this way, the state of the second pump 281B can be set to a state where current can be supplied most efficiently near the potential of the non-selection word line WL_usel before boosting, taking into account the voltage drop (voltage Vdwn) of the non-selection word line WL_usel. Therefore, during the period of boosting the output voltage Vout to the initial intermediate setting value, the number of consecutive pumping operations can be reduced. Therefore, the concentration of current consumption in a short period can be suppressed, thereby reducing peak current.

[0201] Furthermore, by setting the initial intermediate setting value to a low value, the boost time required for the output voltage Vout to reach the target value (voltage VREAD) becomes longer. However, in this implementation, the standard sequence is divided into a first half-cycle and a second half-cycle. In the first half-cycle, where the voltage drop (voltage Vdwn) of the non-select word line WL_usel is smaller, the intermediate setting value is set to a normal value (voltage VPASS2VREAD + step voltage Vstp), thereby suppressing the increase in the execution time of the entire standard sequence.

[0202] Furthermore, the boundary between the first and second half of the cycle can be arbitrarily set. For example, in a page that is being written to, the boundary can be the point at which all cells at the second-to-last level (F level) have passed verification, or the point at which verification at that level has been completed a specific number of times. For example, in Figure 9 In the case of the standard write sequence shown, a boundary is set in any loop between the 12th and 17th iterations, and the first half of the loop before the boundary is executed. Figure 19The control shown indicates that the second half of the cycle occurs after the dividing line. Figure 20 The controls shown.

[0203] Alternatively, for example, in a page that becomes the target of a write operation, the dividing line can be the point at which all cells at the third level from the top (E level) have passed verification, or the point at which verification at that level has been completed a specific number of times. However, this is not a limitation; the dividing line between the first and second halves of the cycle can also be well-defined based on the progress of the write operation.

[0204] Furthermore, as described above, the standard sequence is divided into two parts, and the initial intermediate settings of the first half-loop and the second half-loop are changed. However, the standard sequence can also be divided into three or more parts, and the initial intermediate settings are adjusted while taking into account the voltage drop (voltage Vdwn) of the non-selection word line WL_usel in each segment.

[0205] (Second Implementation)

[0206] Next, the semiconductor memory device according to the second embodiment will be described. In this embodiment, the method for controlling the voltage supplied to the non-select word line WL_usel differs from that of the semiconductor memory device of the first embodiment. The device configuration and other operations are the same as in the first embodiment, therefore, descriptions are omitted. Hereinafter, only the differences from the first embodiment will be described.

[0207] Figure 21 This diagram illustrates the pump boosting operation control in the latter half of the write sequence according to the second embodiment. The diagram also explains the pump boosting operation control and usage in the first half of the write sequence. Figure 19 The first embodiment described herein is the same.

[0208] like Figure 21 As shown, in the second half of the cycle, sequencer 27 controls the voltage VPASS2VREAD after the discharge of the non-selection word line WL_usel during VPASS2VREAD to a lower value than the voltage value in the first half of the cycle. For example, if the voltage VPASS2VREAD in the first half of the cycle is 6.0V, sequencer 27 changes the voltage VPASS2VREAD in the second half of the cycle to 4.8V. Furthermore, the value of the voltage VPASS2VREAD in the second half of the cycle is determined taking into account the amount of voltage drop of the non-selection word line WL_usel that accompanies the decrease in the potential of the disabled channel.

[0209] like Figure 21As shown, sequencer 27 sets the initial intermediate setting value of the output voltage Vout of the second pump 281B to the value obtained by adding a step voltage Vstp (e.g., 0.4V) to the voltage VPASS2VREAD (e.g., 4.4V). Additionally, the state of the second pump 281B is set to a state corresponding to the set value of the output voltage Vout. For example, when the set value of the output voltage Vout is 4.4V and the current efficiency characteristic of the second pump 281B is... Figure 16 Under the characteristics shown, sequencer 27 sets the state of the second pump 281B to state 1. Following the control of sequencer 27, the second pump 281B boosts the output voltage Vout to the initial intermediate set value (e.g., 4.8V). The operation control after the output voltage Vout is boosted to the initial intermediate set value is... Figure 19 The motion control in the first half of the loop shown is the same.

[0210] In this embodiment, the voltage VPASS2VREAD in the second half of the loop is set lower than that in the first half of the loop. Therefore, the voltage drop (voltage Vdwn) of the non-select word line WL_usel, which is associated with the inhibition of channel potential reduction, is smaller. During the initial boost operation during USTRDIS, the second pump 281B must boost the output voltage Vout by an amount equivalent to the step voltage Vstp + voltage Vdwn. However, voltage Vdwn is lower than... Figure 18 The comparative example shown is small, therefore, the number of pumping operations during the boost operation up to the initial intermediate setting can be reduced. Therefore, current consumption can be suppressed from concentrating in a short period, thus reducing peak current. Furthermore, by setting the voltage VPASS2VREAD to a lower value, the inactive channel potential (Vinh) during VPASS2VREAD is also reduced, thus minimizing the impact of the voltage drop on the non-selection word line WL_usel when the non-selection gate line SGD_usel is turned on.

[0211] Furthermore, in the second half of the loop, by setting the voltage VPASS2VREAD to a lower value than in the first half, the boost time required for the output voltage Vout to reach the target value (voltage VREAD) becomes longer. Additionally, the current reduction effect during VPASS2VREAD is also reduced. However, in this implementation, the standard sequence is divided into a first half and a second half. In the first half of the loop, where the voltage drop (voltage Vdwn) of the non-selection word line WL_usel is smaller, the voltage VPASS2VREAD is set to a higher value without changing it. Therefore, the reduction in current reduction effect is prevented, and the increased execution time of the entire standard sequence is suppressed.

[0212] Furthermore, in this embodiment, similar to the first embodiment, the boundary between the first and second half of the cycle can be well set based on the progress of the write operation. Alternatively, the standard sequence can be divided into three or more parts, and the voltage VPASS2VREAD value can be set individually within each division.

[0213] Several embodiments of the present invention have been described, but these embodiments are illustrative only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the invention as described in the claims and its equivalents.

[0214] [Explanation of Symbols]

[0215] 1. Memory controller

[0216] 2. Non-volatile memory

[0217] 12 processors

[0218] 13 Host Interface

[0219] 14 ECC Circuit

[0220] 15. Memory Interface

[0221] 16 Internal Bus

[0222] 21 Logic Control Circuit

[0223] 22 Input / Output Circuit

[0224] 23-cell storage array

[0225] 24 Sensing Amplifier

[0226] 24A Data Register

[0227] 24B Sensing Amplifier Assembly

[0228] 25-line decoder

[0229] 25A Switching Circuit Group

[0230] 25B Block Decoder

[0231] 26 Registers

[0232] 27 Sequencer

[0233] 28 Voltage supply circuit

[0234] 28A SG drive

[0235] 28B CG Driver

[0236] 32 Input / Output Pads

[0237] 33 pads

[0238] 34 Logic Control Pads

[0239] 35 Power input terminal blocks

[0240] 281 Voltage Generation Circuit

[0241] 281A Pump No. 1

[0242] 281B Pump No. 2

[0243] 281C Pump No. 3

[0244] 282 Regulator Circuit.

Claims

1. A semiconductor memory device comprising: Multiple storage units; Word lines are connected to the gates of the plurality of memory cells; Bit lines are electrically connected to one end of the plurality of memory cells via a plurality of select gate transistors respectively connected to one end of the plurality of memory cells; A voltage generating circuit generates a voltage supplied to the word line; and The control unit executes a write sequence to write specific data to the storage unit. The write sequence is repeated multiple times, and each multiple cycle consists of a set of programming actions for writing data to the storage unit and verification actions for checking the data written to the storage unit. The control unit instructs the voltage generation circuit to supply a set value for the voltage to the word line. The voltage has the set value, i.e., the first set value, at the start of the verification action in the first cycle of the plurality of cycles, and the set value, i.e., the second set value, at the start of the verification action in the second cycle of the plurality of cycles; The second setting value is lower than the first setting value; In the write sequence, the second loop is the loop following the first loop; The storage unit has a selectable storage unit and a non-selectable storage unit; In the programming operation, the control unit: A first voltage is applied to a first portion of the bit line, the first portion being electrically connected to one end of the selected memory cell; A second voltage is applied to a second portion of the bit line, the second portion being electrically connected to one end of the non-selected memory cell; The first voltage is lower than the second voltage.

2. The semiconductor memory device of claim 1, wherein the first cycle is a cycle executed before a set boundary cycle in a plurality of cycles executed by the write sequence, and the second cycle is a cycle executed after the set boundary cycle in a plurality of cycles executed by the write sequence.

3. The semiconductor memory device according to claim 1, wherein the programming action includes an actual programming action of writing data to the memory cell and a shift adjustment action of adjusting the voltage of the word line to shift to the verification action, and the control unit changes the setting value, i.e., the third setting value, during the shift adjustment action according to the position of the cycle.

4. The semiconductor memory device of claim 3, wherein the control unit sets the third setting value in the loop executed after the set boundary loop to be lower than the third setting value in the loop executed before the set boundary loop in the plurality of loops executed by the write sequence.

5. The semiconductor memory device of claim 1, wherein the selected memory cell is a data write target, and the non-selected memory cell is any other memory cell. The control unit changes the first set value of the voltage supplied to the word line connected to the gate of the non-selected memory cell according to the position of the cycle.

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