A chip differential unit testing method and device for dynamic card control

Abstract

The present invention relates to the field of semiconductor wafer testing, and provides a chip differential unit testing method with dynamic card control, comprising: setting three test gears; card control with the three test gears to test the differential unit of the chip to be tested, so as to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested; and comparing the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested with a reference truth table to obtain the test result of the differential unit of the chip to be tested. The present invention realizes the test of the differential unit of the chip by setting the gear for dynamic card control and setting the truth table for automatic verification, so as to prevent the differential unit of the good chip from being overkilled.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor wafer testing, and in particular to a chip differential unit testing method and device with dynamic card control. Background Art

[0002] In order to ensure the normal operation of the EEPROM memory, testing is essential. During the test, the Pass and Fail situations of common cells are unilateral, and the corresponding gear distribution is also unilateral. However, there is a special situation for differential cell products. It will fail at high and low gears, and pass at the middle gear. As long as a die has a 4-gear window, it is a good product. The existing test uses the traditional form of only carding a single gear, which will cause serious overkill. This test scheme for a single gear will not be applicable. For this, a special test scheme is needed to prevent overkill and unnecessary yield loss. Summary of the invention

[0003] The purpose of the present invention is to provide a chip differential unit testing method and device with dynamic card control, which can solve the above problems.

[0004] The technical solution provided by the present invention is as follows:

[0005] A chip differential unit testing method for dynamic card control, comprising:

[0006] Set three test gears;

[0007] The three test gears are used to perform card control, and the differential unit of the chip to be tested is tested to obtain the corresponding values ​​of the voltage and current of each differential unit of the chip to be tested;

[0008] The values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are compared with a reference truth table to obtain a test result of the differential unit of the chip to be tested.

[0009] In some embodiments, before the three test gears are used to perform card control and test the differential unit of the chip to be tested to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested, the method further includes:

[0010] A benchmark truth table is established based on historical test data of historical chip differential units.

[0011] In some embodiments, the three test gears are used to perform card control to test the differential unit of the chip to be tested, so as to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested, including:

[0012] Performing a read and write test on the differential unit of the chip under test at each gear position, and obtaining the values ​​corresponding to the voltage and current of the differential unit of the chip under test after each read and write test.

[0013] In some embodiments, comparing the values ​​corresponding to the voltage and current of the differential unit of the chip under test with the reference truth table to obtain the test result of the differential unit of the chip under test includes:

[0014] The numerical values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, and the binary values ​​are compared with the array of the reference truth table;

[0015] When the binary value exists in the reference truth table, the test result is determined to be passed.

[0016] In some embodiments, the numerical values ​​corresponding to the voltage and current of the differential unit of the chip under test are binary values, and after comparing the binary values ​​with the array of the reference truth table, the method further includes:

[0017] When the binary value does not exist in the reference truth table, the test result is determined to be a failure.

[0018] A chip differential unit testing device with dynamic card control, comprising:

[0019] Setting module, used to set three test gears;

[0020] A test module, used for performing card control at the three test gears to test the differential unit of the chip to be tested, so as to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested;

[0021] The acquisition module is used to compare the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested with the reference truth table to obtain the test result of the differential unit of the chip to be tested.

[0022] In some embodiments, the method further comprises: establishing a module for:

[0023] A benchmark truth table is established based on historical test data of historical chip differential units.

[0024] In some embodiments, the testing module is used to:

[0025] Performing a read and write test on the differential unit of the chip under test at each gear position, and obtaining the values ​​corresponding to the voltage and current of the differential unit of the chip under test after each read and write test.

[0026] In some embodiments, the acquisition module is used to:

[0027] The numerical values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, and the binary values ​​are compared with the array of the reference truth table;

[0028] When the binary value exists in the reference truth table, the test result is determined to be passed.

[0029] In some embodiments, the acquisition module is further used to:

[0030] When the binary value does not exist in the reference truth table, the test result is determined to be a failure.

[0031] The chip differential unit testing method and device for dynamic card control provided by the present invention can at least achieve the following technical effects:

[0032] The present invention realizes the test of the chip differential unit by setting the gear position for dynamic card control and setting the truth table for automatic verification, thereby preventing the differential unit of the good chip from being overkilled. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The preferred implementation manner will be described below in a clear and understandable manner in conjunction with the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of a dynamic card-controlled chip differential unit testing method.

[0034] Figure 1 It is a schematic diagram of a chip differential unit testing method of dynamic card control in the present invention;

[0035] Figure 2 It is the IDAC of the usual case of the prior art;

[0036] Figure 3 is the special case of differential IDAC;

[0037] Figure 4 is a schematic diagram of a reference truth table in the present invention;

[0038] Figure 5 It is a schematic diagram of a chip differential unit testing device with dynamic card control in the present invention. DETAILED DESCRIPTION

[0039] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0040] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0041] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0042] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0043] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0045] In one embodiment, Figure 1 As shown, the present invention provides a chip differential unit testing method for dynamic card control, comprising:

[0046] S100 has three test settings.

[0047] Specifically, the common cell pass and fail situations are unilateral. The gear distribution is unilateral, such as Figure 2 For differential cell products, there is a special situation where the product will fail at high and low gears, and pass at the middle gear. As long as a die has a 4-gear window, it is a good product. Figure 3 shown.

[0048] In this embodiment, the essence of chip data storage is the migration of electrons. The ability of electrons to enter and exit the cell is commonly known as the write depth, which is manifested in the voltage and current of the cell. After the cell is repeatedly erased, the voltage and current of the cell will decrease. The current standard is that the erase and write can reach 100w times. The voltage that will drop after 100w erase and write is basically the space of 3 gears.

[0049] Each time you set the gear card control, set 3 gears respectively. From the perspective of reliability, a 4-gear window can ensure 1 million times of reliability. Figure 3 As shown, the selection of 3 gears is derived from the analysis of a large amount of measured data. In this embodiment, 6 / 9 / 12 gears are preferred, wherein there are 4 gear windows between the three gears.

[0050] S200 performs card control at the three test gears to test the differential units of the chip to be tested, so as to obtain the corresponding values ​​of the voltage and current of each differential unit of the chip to be tested.

[0051] Specifically, the read and write functions of each chip differential unit are checked once. For example, the chip is "read" by an ATE tester. During the test, the chip will output a string of data to the tester. The data output from the chip is compared with the data preset in the ATE test program. If they are consistent, they are considered correct. The fail output is "0" and the pass output is "1".

[0052] Specifically, the level value is reflected in the chip through gears, and different gears represent different voltages / currents.

[0053] S300 compares the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested with a reference truth table to obtain a test result of the differential unit of the chip to be tested.

[0054] Specifically, after the output is the value of "0" and "1", the truth table listed is compared to make a judgment. Among them, the array composed of values ​​is established according to the voltage and current of the cell inside the chip.

[0055] Exemplarily, pass and fail are determined based on the cells of historical chips and the standards given by the design, and then the voltage and current of the chip cells are monitored in real time by the algorithm of this embodiment and compared with the historical specs. If two adjacent gears pass, a 4-gear window can be guaranteed (which means that the die is a good product).

[0056] It should be noted that when the chip reads the storage unit, it can usually add an intermediate level to the control gate of the chip unit, whose value is between the two threshold values ​​Vth, so that the high-open tube with electrons in the floating gate cannot be turned on, while the low-open tube after the floating gate is discharged can be turned on normally, thereby distinguishing whether the data stored in the unit is "1" or "0". By controlling the value of the intermediate level, the card control measurement is used to leave enough space between "0" and "1" to ensure the number of times the chip can be erased and written.

[0057] Through the targeted and specialized testing scheme of the present embodiment, overkilling of chip differential units is prevented, thereby avoiding unnecessary yield loss.

[0058] In one embodiment, the present invention provides a chip differential unit testing method for dynamic card control, specifically comprising:

[0059] S100 has three test settings.

[0060] Specifically, the common cell pass and fail situations are unilateral. The gear distribution is unilateral, such as Figure 2 For differential cell products, there is a special situation where the product will fail at high and low gears, and pass at the middle gear. As long as a die has a 4-gear window, it is a good product. Figure 3 shown.

[0061] In this embodiment, the essence of chip data storage is the migration of electrons. The ability of electrons to enter and exit the cell is commonly known as the write depth, which is manifested in the voltage and current of the cell. After the cell is repeatedly erased, the voltage and current of the cell will decrease. The current standard is that the erase and write can reach 100w times. The voltage that will drop after 100w erase and write is basically the space of 3 gears.

[0062] Each time you set the gear card control, set 3 gears respectively. From the perspective of reliability, a 4-gear window can ensure 1 million times of reliability. Figure 3 As shown, the selection of 3 gears is derived from the analysis of a large amount of measured data. In this embodiment, 6 / 9 / 12 gears are preferred, wherein there are 4 gear windows between the three gears.

[0063] S200 performs card control at the three test gears to test the differential units of the chip to be tested, so as to obtain the corresponding values ​​of the voltage and current of each differential unit of the chip to be tested.

[0064] Specifically, the read and write functions of each chip differential unit are checked once. For example, the chip is "read" by an ATE tester. During the test, the chip will output a string of data to the tester. The data output from the chip is compared with the data preset in the ATE test program. If they are consistent, they are considered correct. The fail output is "0" and the pass output is "1".

[0065] Specifically, the level value is reflected in the chip through gears, and different gears represent different voltages / currents.

[0066] Before the step S300 performs card control at the three test gears to test the differential unit of the chip to be tested to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested, the step further includes:

[0067] A benchmark truth table is established based on historical test data of historical chip differential units.

[0068] Specifically, in the test program, first list an array. Take the truth table in the figure above as an example to create an array {21, 23, 27, 31, 33, 37}.

[0069] For example, Figure 4 The last P / F column shown has 6 rows of P in total. The values ​​of these 6 Ps. Take the first P of the group 0x02 as an example. The result 010001 is converted from binary to 21.

[0070] Among them, the A mode will measure three times (6 / 9 / 12 once each), and the B mode will measure three times (6 / 9 / 12 once each), a total of 6 times, which are combined together to output a 6-bit binary number.

[0071] Each output result is compared with the number in the array. If it belongs to the array, the test result is judged as PASS.

[0072] Specifically, the values ​​of the truth table are assembled into an array. Each time the data of a die is verified, the output value is compared with the value in the array. If it is in the array, it is judged as a pass. If it is not in the array, it is judged as a fail.

[0073] S300 compares the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested with a reference truth table to obtain a test result of the differential unit of the chip to be tested.

[0074] Specifically, after the output is the value of "0" and "1", the truth table listed is compared to make a judgment. Among them, the array composed of values ​​is established according to the voltage and current of the cell inside the chip.

[0075] Exemplarily, pass and fail are determined based on the cells of historical chips and the standards given by the design, and then the voltage and current of the chip cells are monitored in real time by the algorithm of this embodiment and compared with the historical specs. If two adjacent gears pass, a 4-gear window can be guaranteed (which means that the die is a good product).

[0076] Through the targeted and specialized testing scheme of the present embodiment, overkilling of chip differential units is prevented, thereby avoiding unnecessary yield loss.

[0077] In one embodiment, the card control is performed at the three test gears to test the differential unit of the chip to be tested to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested, including:

[0078] Performing a read and write test on the differential unit of the chip under test at each gear position, and obtaining the values ​​corresponding to the voltage and current of the differential unit of the chip under test after each read and write test.

[0079] In one embodiment, comparing the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested with the reference truth table to obtain the test result of the differential unit of the chip to be tested includes:

[0080] The numerical values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, and the binary values ​​are compared with the array of the reference truth table;

[0081] When the binary value exists in the reference truth table, the test result is determined to be passed.

[0082] In one embodiment, the numerical values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, and after comparing the binary values ​​with the array of the reference truth table, the method further includes:

[0083] When the binary value does not exist in the reference truth table, the test result is determined to be a failure.

[0084] In one embodiment, Figure 5 As shown, the present invention provides a chip differential unit testing device with dynamic card control, comprising:

[0085] The setting module 100 is used to set three test gears.

[0086] The test module 200 is used to perform card control with the three test gears to test the differential unit of the chip to be tested, so as to obtain the corresponding values ​​of the voltage and current of each differential unit of the chip to be tested.

[0087] The acquisition module 300 is used to compare the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested with a reference truth table to obtain the test result of the differential unit of the chip to be tested.

[0088] In one embodiment, it further includes: establishing a module for:

[0089] A benchmark truth table is established based on historical test data of historical chip differential units.

[0090] In one embodiment, the test module is used to:

[0091] Performing a read and write test on the differential unit of the chip under test at each gear position, and obtaining the values ​​corresponding to the voltage and current of the differential unit of the chip under test after each read and write test.

[0092] In one embodiment, the acquisition module is used to:

[0093] The numerical values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, and the binary values ​​are compared with the array of the reference truth table;

[0094] When the binary value exists in the reference truth table, the test result is determined to be passed.

[0095] In one embodiment, the acquisition module is further used to:

[0096] When the binary value does not exist in the reference truth table, the test result is determined to be a failure.

[0097] By using the targeted and specialized testing device of this embodiment, overkilling of chip differential units can be prevented, thereby avoiding unnecessary yield loss.

[0098] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned program modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program units or modules to complete all or part of the functions described above. The program modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into a processing unit, and the above-mentioned integrated unit can be implemented in the form of hardware or in the form of software program units. In addition, the specific names of the program modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

[0099] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0100] Those of ordinary skill in the art will appreciate that the units of the examples described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0101] In the embodiments provided in the present application, it should be understood that the disclosed system can be implemented in other ways. Exemplarily, the embodiments described above are merely schematic. Exemplarily, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation. Exemplarily, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0102] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0103] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0104] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A chip differential unit testing method with dynamic card control, It is characterized in that include: Set three test gears; The card is controlled at the three test positions to perform a read and write test on the differential unit of the chip to be tested, so as to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested; The voltage and current values ​​of the differential unit of the chip to be tested are compared with the reference truth table to obtain the test results. The output values ​​are judged against the truth table. The value array is established based on the voltage and current of the differential unit of the chip to be tested. If two adjacent test gears are passed, it can be guaranteed that there are 4 gear windows, and the differential unit of the chip to be tested is judged to be a good product.

2. The chip differential unit testing method for dynamic card control according to claim 1, It is characterized in that Before the card control is performed at the three test gears to test the differential unit of the chip to be tested to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested, the method further includes: A benchmark truth table is established based on historical test data of historical chip differential units.

3. The chip differential unit testing method of dynamic card control according to claim 1, It is characterized in that The method of performing card control with the three test gears to test the differential unit of the chip to be tested to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested includes: Performing a read and write test on the differential unit of the chip under test at each gear position, and obtaining the values ​​corresponding to the voltage and current of the differential unit of the chip under test after each read and write test.

4. The chip differential unit testing method of dynamic card control according to any one of claims 1 to 3, It is characterized in that The comparing the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested with the reference truth table to obtain the test result of the differential unit of the chip to be tested includes: The numerical values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, and the binary values ​​are compared with the array of the reference truth table; When the binary value exists in the reference truth table, the test result is determined to be passed.

5. The chip differential unit testing method of dynamic card control according to claim 4, It is characterized in that When the values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, after comparing the binary values ​​with the array of the reference truth table, the method further includes: When the binary value does not exist in the reference truth table, the test result is determined to be a failure.

6. A chip differential unit test device with dynamic card control, It is characterized in that include: Setting module, used to set three test gears; A test module, used for performing card control with the three test gears, and performing read and write tests on the differential units of the chip to be tested, so as to obtain the values ​​corresponding to the voltage and current of each differential unit of the chip to be tested; The acquisition module is used to compare the voltage and current values ​​of the differential unit of the chip to be tested with the reference truth table to obtain the test results, and make a judgment based on the output values ​​against the truth table. The value array is established based on the voltage and current of the differential unit of the chip to be tested. If two adjacent test gears are passed, it can be guaranteed that there are 4 gear windows, that is, the differential unit of the chip to be tested is judged to be a good product.

7. The chip differential unit testing device for dynamic card control according to claim 6, It is characterized in that Also includes: Create modules for: A benchmark truth table is established based on historical test data of historical chip differential units.

8. The chip differential unit testing device for dynamic card control according to claim 6, It is characterized in that The test module is used to: Performing a read and write test on the differential unit of the chip under test at each gear position, and obtaining the values ​​corresponding to the voltage and current of the differential unit of the chip under test after each read and write test.

9. The chip differential unit testing device for dynamic card control according to any one of claims 6 to 8, It is characterized in that The acquisition module is used to: The numerical values ​​corresponding to the voltage and current of the differential unit of the chip to be tested are binary values, and the binary values ​​are compared with the array of the reference truth table; When the binary value exists in the reference truth table, the test result is determined to be passed.

10. The chip differential unit testing device of dynamic card control according to claim 9, It is characterized in that The acquisition module is further used for: When the binary value does not exist in the reference truth table, the test result is determined to be a failure.

Images