Display device

Abstract

A display device is provided, the display device including a first display area and a second display area located on opposite sides of a display area. The display device includes first to third sub-pixels. The first to third sub-pixels are disposed in the first display area and the second display area. The first sub-pixel and the second sub-pixel are arranged in a first column adjacent to a first boundary, and the third sub-pixel is arranged in a second column. The second sub-pixel and the first sub-pixel are arranged in a third column adjacent to a second boundary, and the third sub-pixel is arranged in a fourth column. The third sub-pixel is arranged in a first column of a first sub-area. The first sub-pixel and the second sub-pixel are arranged in a first column of a third sub-area. The first to third sub-pixels are not disposed in a second column of the first sub-area and the third sub-area.

Description

Technical Field

[0001] The embodiments of the invention generally relate to a display device. More specifically, the embodiments of the invention relate to a display device comprising subpixels of different sizes. Background Technology

[0002] Flat panel displays are used as alternatives to cathode ray tube displays due to their lightweight and thin profile. Representative examples of such flat panel displays include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0003] Such a display device may include a display area in which an image is displayed and a peripheral area in which no image is displayed. For example, subpixels may be disposed in the display area. In this case, the subpixels may be arranged in a row-wise repeating pattern where red / green-blue / green (RG-BG) subpixels are repeated. The display area is arranged within the display area. Furthermore, the peripheral area can be located on either side of the display area. For example, gate drivers, transmit signal drivers, etc., can be located in the peripheral area.

[0004] Recently, a display device has been developed in which subpixels are formed in a peripheral region to display an image, even in the peripheral region. In this case, the display device can be configured such that the sizes of the subpixels disposed in the display region are different from the sizes of the subpixels disposed in the peripheral region.

[0005] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] The device constructed according to embodiments of the invention can improve the image quality of the device by stacking sub-pixels with pixel circuits.

[0007] Additional features of the inventive concept will be set forth in the description below, and will become apparent in part from the description or may be learned by practice of the inventive concept.

[0008] An embodiment provides a display device including sub-pixels.

[0009] According to an embodiment of the inventive concept, a display device includes a display area, a first display area, and a second display area. The first display area is located on one side of the display area and includes a first sub-area and a second sub-area. The second display area is located on the opposite side of the display area and includes a third sub-area and a fourth sub-area. The display device includes a substrate and a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The first sub-pixels, second sub-pixels, and third sub-pixels are disposed on the substrate in the display area, the first display area, and the second display area. The first sub-pixels and second sub-pixels are repeatedly arranged in a first column of the display area adjacent to a first boundary between the display area and the first sub-area, and the third sub-pixels are repeatedly arranged in a second column of the display area. The second sub-pixels and first sub-pixels are repeatedly arranged in a third column of the display area adjacent to a second boundary between the display area and the third sub-area, and the third sub-pixels are repeatedly arranged in a fourth column of the display area. The third sub-pixels are repeatedly arranged in a first column of the first sub-area adjacent to the first boundary, and the second column of the first sub-area is located between the first boundary and the first column of the first sub-area. The first and second sub-pixels are repeatedly arranged in the first column of the third sub-region adjacent to the second boundary, and the second column of the third sub-region is located between the second boundary and the first column of the third sub-region. The first to third sub-pixels are not set in the second column of the first sub-region and the second column of the third sub-region.

[0010] In an embodiment, the third column of the first sub-region may be adjacent to the first column of the first sub-region, and the fourth column of the first sub-region may be located between the first and third columns of the first sub-region. The second sub-pixel and the first sub-pixel may be arranged repeatedly in the third column of the first sub-region.

[0011] In this embodiment, the first to third sub-pixels may not be set in the fourth column of the first sub-region.

[0012] In an embodiment, the first to third sub-pixels can be arranged in a zigzag shape in the first and second columns of the display area in the order of first sub-pixel, third sub-pixel, second sub-pixel, and third sub-pixel.

[0013] In an embodiment, the third column of the third sub-region may be adjacent to the first column of the third sub-region, and the fourth column of the third sub-region may be located between the first and third columns of the third sub-region. The third sub-pixels may be repeatedly arranged in the third column of the third sub-region.

[0014] In this embodiment, the first to third sub-pixels may not be set in the fourth column of the third sub-region.

[0015] In an embodiment, the first to third sub-pixels can be arranged in a zigzag shape in the third and fourth columns of the display area in the order of the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel.

[0016] In one embodiment, the display device may further include a first circuit structure disposed on a substrate in a second sub-region.

[0017] In an embodiment, the display device may further include a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits connected to first to third sub-pixels disposed in the display area, the first display area, and the second display area, wherein the first pixel circuits, second pixel circuits, and third pixel circuits are respectively connected to the first to third sub-pixels. The first to third pixel circuits respectively connected to the first to third sub-pixels disposed in the second sub-region may be disposed in the first sub-region.

[0018] In an embodiment, the display device may further include a second circuit structure disposed on the substrate in a fourth sub-region.

[0019] In an embodiment, the display device may further include a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits connected to first to third sub-pixels disposed in the display area, the first display area, and the second display area, wherein the first pixel circuits, second pixel circuits, and third pixel circuits are respectively connected to the first to third sub-pixels. The first to third pixel circuits respectively connected to the first to third sub-pixels disposed in the fourth sub-region may be disposed in the third sub-region.

[0020] In an embodiment, the number of first and second sub-pixels arranged in the first column of the display area can be equal to the number of third sub-pixels arranged in the second column of the display area, and the number of third sub-pixels arranged in the first column of the first sub-region can be less than the number of first and second sub-pixels arranged in the first column of the display area.

[0021] In one embodiment, the number of third sub-pixels arranged in the first column of the first sub-region may be half the number of first and second sub-pixels arranged in the first column of the display area.

[0022] In this embodiment, the first display area and the second display area can be parallel to each other and face each other. The second and third columns of the display areas can be located between the first and fourth columns of the display areas, and the second column of the first sub-region can be located between the first column of the display area and the first column of the first sub-region. The second column of the third sub-region can be located between the fourth column of the display area and the first column of the third sub-region. The sizes of the first to third sub-pixels disposed in the first and second display areas can be larger than the sizes of the first to third sub-pixels disposed in the display areas, respectively.

[0023] According to an embodiment of the inventive concept, a display device includes a display area, a first display area, and a second display area. The first display area is located on one side of the display area and includes a first sub-area and a second sub-area. The second display area is located on the opposite side of the display area and includes a third sub-area and a fourth sub-area. The display device includes a substrate and a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The first sub-pixels, second sub-pixels, and third sub-pixels are disposed on the substrate in the display area, the first display area, and the second display area. The first and second sub-pixels can be repeatedly arranged in a first column adjacent to a first boundary between the display area and the first sub-area, and the third sub-pixels can be repeatedly arranged in a second column of the display area. The second sub-pixels and first sub-pixels can be repeatedly arranged in a third column adjacent to a second boundary between the display area and the third sub-area, and the third sub-pixels can be repeatedly arranged in a fourth column of the display area. A first sub-pixel column including third sub-pixels can be disposed in the first sub-area adjacent to the first boundary. A second sub-pixel column including third sub-pixels can be disposed in the third sub-area adjacent to the second boundary. The distance between the first sub-pixel column and the second column of the display area can be equal to the distance between the second sub-pixel column and the fourth column of the display area.

[0024] In an embodiment, the display device may further include a third sub-pixel column, a fourth sub-pixel column, and a fifth sub-pixel column. The third sub-pixel column may be spaced apart from the first sub-pixel column in the first sub-region along a direction from the display area to the first display area, and may include both a second sub-pixel and a first sub-pixel. The fourth sub-pixel column may be spaced apart from the third sub-pixel column in the first sub-region along the same direction, and may include a third sub-pixel. The fifth sub-pixel column may be spaced apart from the fourth sub-pixel column in the first sub-region along the same direction, and may include both a first sub-pixel and a second sub-pixel.

[0025] In an embodiment, the separation distance between the first sub-pixel column and the third sub-pixel column in this direction may be less than the separation distance between the third sub-pixel column and the fourth sub-pixel column in this direction.

[0026] In an embodiment, the display device may further include a sixth sub-pixel column, a seventh sub-pixel column, and an eighth sub-pixel column. The sixth sub-pixel column may be disposed in the third sub-region between the fourth column and the second sub-pixel column of the display area, and may include a first sub-pixel and a second sub-pixel. The seventh sub-pixel column may be spaced apart from the second sub-pixel column in the third sub-region in the direction from the display area to the third sub-region, and may include a second sub-pixel and a first sub-pixel. The eighth sub-pixel column may be spaced apart from the seventh sub-pixel column in the third sub-region in this direction, and may include a third sub-pixel.

[0027] In an embodiment, the separation distance between the second sub-pixel column and the sixth sub-pixel column in this direction may be less than the separation distance between the second sub-pixel column and the seventh sub-pixel column in this direction.

[0028] According to an embodiment of the inventive concept, a display device includes a display area, a first display area, and a second display area. The first display area is located on one side of the display area and includes a first sub-area and a second sub-area. The second display area is located on the opposite side of the display area and includes a third sub-area and a fourth sub-area. The display device includes a substrate and a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The first sub-pixels, second sub-pixels, and third sub-pixels are disposed on the substrate in the display area, the first display area, and the second display area. The first sub-pixels and second sub-pixels can be repeatedly arranged in a first column of the display area adjacent to a first boundary between the display area and the first sub-area, and the third sub-pixels can be repeatedly arranged in a second column of the display area. The third sub-pixels can be repeatedly arranged in a third column of the display area adjacent to a second boundary between the display area and the third sub-area, and the first sub-pixels and second sub-pixels can be repeatedly arranged in a fourth column of the display area. The third sub-pixels can be repeatedly arranged in the first column of the first sub-area adjacent to the first boundary, and the second column of the first sub-area can be located between the first boundary and the first column of the first sub-area. The third sub-pixel can be repeatedly arranged in the first column of the third sub-region adjacent to the second boundary, and the second column of the third sub-region can be located between the second boundary and the first column of the third sub-region. The first to third sub-pixels may not be set in the second column of the first sub-region and the second column of the third sub-region.

[0029] According to an embodiment of the inventive concept, the first sub-pixel to the third sub-pixel are not disposed in the second column of the first sub-region and the second column of the third sub-region, so that no defects occur in the process of forming the light-emitting layer of each of the first sub-pixel to the third sub-pixel adjacent to the first boundary and the second boundary.

[0030] According to an embodiment of the inventive concept, in a display device, the distance between the first sub-pixel column and the second column of the display area is substantially equal to the distance between the second sub-pixel column and the fourth column of the display area, such that the value of the roughness index (R index) can be relatively reduced, and the image quality of the display device can be relatively improved.

[0031] According to an embodiment of the inventive concept, when the arrangement of sub-pixels in the first and last columns of the display area is identical, and the arrangement of sub-pixels in the first display area and the arrangement of sub-pixels in the second display area are symmetrical to each other, the value of the R-index can be relatively reduced, and the image quality of the display device can be relatively improved. Furthermore, no defects occur in the process of forming the light-emitting layer of each of the first to third sub-pixels adjacent to the first and second boundaries.

[0032] It should be understood that both the preceding general description and the following detailed description are illustrative and explanatory, and are intended to provide further explanation of the invention as claimed. Attached Figure Description

[0033] The accompanying drawings illustrate embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0034] The embodiments can be understood in more detail from the following description taken in conjunction with the accompanying drawings.

[0035] Figure 1 This is a plan view showing a display device constructed according to an embodiment based on the principles of the invention.

[0036] Figure 2 It is shown Figure 1 A circuit diagram of an example of the circuit structure included in a display device.

[0037] Figure 3 It is shown Figure 1 A circuit diagram of another example of the circuit structure included in the display device.

[0038] Figure 4 It is shown Figure 1 The circuit diagram of the sub-pixels and pixel circuits included in the display device.

[0039] Figure 5 It is shown Figure 1 A magnified plan view of region A.

[0040] Figure 6 It is shown Figure 1 A magnified plan view of region B.

[0041] Figure 7 It is along Figure 5 A sectional view taken from line I-I'.

[0042] Figure 8 It is along Figure 5 The sectional view taken from line II-II'.

[0043] Figure 9 It is along Figure 5 The sectional view taken from line III-III'.

[0044] Figure 10 It is along Figure 5 A sectional view taken from line IV-IV'.

[0045] Figure 11 and Figure 12 It is shown Figure 5 and Figure 6 A plan view of an example of the connecting electrodes shown.

[0046] Figure 13 and Figure 14 It is shown Figure 5 and Figure 6 A plan view of another example of the connecting electrodes shown.

[0047] Figure 15 and Figure 16 It is shown Figure 1 A plan view of an example arrangement of subpixels included in a display device.

[0048] Figure 17 and Figure 18 This is a plan view illustrating a display device according to an embodiment of the inventive concept.

[0049] Figure 19 and Figure 20 This is a plan view illustrating a display device according to an embodiment of the inventive concept.

[0050] Figure 21 It is shown Figure 19 and Figure 20 A plan view of an example arrangement of sub-pixels included in a display device. Detailed Implementation

[0051] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, the specific shapes, constructions, and characteristics of the embodiments may be used or implemented in another embodiment without departing from the inventive concept.

[0052] Unless otherwise stated, the illustrated embodiments should be understood as providing features of different details in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0053] Crosshairs and / or shading are typically used in accompanying drawings to clarify boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular sequence of processes may be performed differently than the sequence described when embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0054] When an element, such as a layer, is referred to as being "on," "connected to," or "bonded to" another element or layer, it can be directly "on," directly connected to, or directly bonded to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary element. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0056] Spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes to describe the relationship of one element to another (or other elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be positioned “above” other elements or features. Thus, the descriptive term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms “comprising,” “including,” and / or variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus allowing for the interpretation of inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0058] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized embodiments and / or intermediate structures. Thus, variations in the shapes illustrated are contemplated as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not necessarily be interpreted as limited to the specific shapes shown for a particular region, but rather include deviations in shape caused, for example, by manufacturing processes. In this way, the regions shown in the figures can be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, thus not necessarily intended to be limiting.

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0060] In the following, a display device according to one or more embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements.

[0061] Figure 1 This is a plan view showing a display device constructed according to an embodiment based on the principles of the invention.

[0062] Reference Figure 1The display device 100 may include a substrate 110, first to third sub-pixels R, B, and G (e.g., red sub-pixel R, blue sub-pixel B, and green sub-pixel G), a first circuit structure 800, a second circuit structure 900, etc. Additionally, the display device 100 may include a display area 10, a first display area 20, and a second display area 30. In this case, the first display area 20 may include a first sub-area 21 and a second sub-area 22, and the second display area 30 may include a third sub-area 31 and a fourth sub-area 32. Figure 1 In an alternative embodiment of the implementation shown, the display device 100 may further include first pixel circuits to third pixel circuits respectively connected to the first sub-pixels to the third sub-pixels R, B and G.

[0063] The first display area 20 can be located on one side of the display area 10, and the second display area 30 can be located on the opposite side of the display area 10. In other words, the display area 10 can be located between the first display area 20 and the second display area 30. The first display area 20 and the second display area 30 can face each other and can be substantially parallel to each other. In addition, the first sub-area 21 can be positioned closer to the display area 10 than the second sub-area 22, and the third sub-area 31 can be positioned closer to the display area 10 than the fourth sub-area 32.

[0064] The first to third sub-pixels R, B, and G can be disposed on the substrate 110 in the display area 10, the first display area 20, and the second display area 30. The first to third sub-pixels R, B, and G can be arranged such that the red / green-blue / green (RG-BG) sub-pixels are repeatedly arranged in a first direction D1 (e.g., the row direction) parallel to the top surface of the display device 100 (e.g., in...). (in the plan).

[0065] For example, each of the first to third sub-pixels R, B, and G can correspond to Figure 4 The organic light-emitting diode (OLED) shown, and the first to third pixel circuits can correspond to Figure 4 The pixel circuit PC shown can display images in the display area 10, the first display area 20, and the second display area 30 through the first sub-pixels to the third sub-pixels R, B, and G, and the first pixel circuit to the third pixel circuit.

[0066] In the display area 10, the first sub-pixel R can be superimposed with the first pixel circuit connected to the first sub-pixel R, the second sub-pixel B can be superimposed with the second pixel circuit connected to the second sub-pixel B, and the third sub-pixel G can be superimposed with the third pixel circuit connected to the third sub-pixel G.

[0067] In the first sub-region 21 and the third sub-region 31, the first sub-pixel R can be superimposed with the first pixel circuit connected to the first sub-pixel R, the second sub-pixel B can be superimposed with the second pixel circuit connected to the second sub-pixel B, and the third sub-pixel G can be superimposed with the third pixel circuit connected to the third sub-pixel G.

[0068] In the second sub-region 22 and the fourth sub-region 32, the first sub-pixel R may not be superimposed with the first pixel circuit connected to the first sub-pixel R, the second sub-pixel B may not be superimposed with the second pixel circuit connected to the second sub-pixel B, and the third sub-pixel G may not be superimposed with the third pixel circuit connected to the third sub-pixel G. For example, since the first circuit structure 800 and the second circuit structure 900 are respectively provided in the second sub-region 22 and the fourth sub-region 32, the space for arranging the first pixel circuits to the third pixel circuits connected to the first sub-pixels to the third sub-pixels R, B, and G may be insufficient. Therefore, the first pixel circuits to the third pixel circuits connected to the first sub-pixels to the third sub-pixels R, B, and G provided in the second sub-region 22 may be provided in the first sub-region 21, and the first pixel circuits to the third pixel circuits connected to the first sub-pixels to the third sub-pixels R, B, and G provided in the fourth sub-region 32 may be provided in the third sub-region 31 (see Figure 5 ).

[0069] Each of the first to third pixel circuits may include at least one driving transistor, at least one switching transistor, at least one capacitor, etc. In an embodiment, each of the first to third pixel circuits may include one driving transistor (e.g., Figure 4 The first transistor TR1), and six switching transistors (e.g., Figure 4 The second to seventh transistors TR2, TR3, TR4, TR5, TR6 and TR7), and a storage capacitor (e.g., Figure 4 Storage capacitors (CST), etc.

[0070] In this embodiment, the sizes of the first to third sub-pixels R, B, and G disposed in the display area 10 may differ from the sizes of the first to third sub-pixels R, B, and G disposed in the first display area 20 and the second display area 30, respectively. For example, the sizes of the first to third sub-pixels R, B, and G disposed in the first display area 20 and the second display area 30 may be larger than the sizes of the first to third sub-pixels R, B, and G disposed in the display area 10, respectively. In this case, the construction of the first to third pixel circuits disposed in the display area 10 (e.g., the number of transistors and the number of capacitors) may differ from the construction of the first to third pixel circuits disposed in the first display area 20 and the second display area 30, respectively.

[0071] Additionally, the display device 100 may also include a pad (also called a "soldering pad") area located below the display area 10. Pad electrodes may be disposed in the pad area. External devices configured to provide signals and power to the display device 100 may be electrically connected to the pad electrodes via a flexible printed circuit board or a printed circuit board. The external devices may generate data signals, gate signals, transmit control signals, gate initialization signals, initialization voltages, power supply voltages, etc., and these signals may be provided to the first circuit structure 800, the second circuit structure 900, the first pixel circuit to the third pixel circuit, and the first sub-pixels to the third sub-pixels R, B, and G via the pad electrodes and the flexible printed circuit board. Furthermore, a driver integrated circuit may be mounted on the flexible printed circuit board. In other embodiments, the driver integrated circuit may be mounted on the display device 100 adjacent to the pad electrodes.

[0072] The first circuit structure 800 can be disposed on the substrate 110 in the second sub-region 22, and the second circuit structure 900 can be disposed on the substrate 110 in the fourth sub-region 32. The first circuit structure 800 and the second circuit structure 900 may include a gate driver, a transmit signal driver, etc.

[0073] The gate driver can receive gate signals from an external device, and the gate signals can be provided to the first pixel circuit to the third pixel circuit through the gate driver. The transmit signal driver can receive transmit control signals from an external device, and the transmit control signals can be provided to the first pixel circuit to the third pixel circuit through the transmit signal driver.

[0074] In one embodiment, although the first circuit structure 800 and the second circuit structure 900 are respectively disposed in the second sub-region 22 and the fourth sub-region 32, the display device 100 includes all the first to third sub-pixels R, B, and G disposed in the display area 10, the first display area 20, and the second display area 30, so that an image can be displayed across the entire top surface of the display device 100. In other embodiments, the first display area 20 may be absent, and the first circuit structure 800 disposed in the second sub-region 22 may be disposed together with the second circuit structure 900 in the fourth sub-region 32.

[0075] However, when viewed in a plan view, although each of the display area 10, the first display area 20, and the second display area 30 according to one or more embodiments has been described as having a rectangular shape, the shape is not limited thereto. For example, when viewed in a plan view, each of the display area 10, the first display area 20, and the second display area 30 may have a triangular shape, a rhombus shape, another polygonal shape, a circular shape, a racetrack shape, or an elliptical shape.

[0076] Figure 2 It is shown Figure 1 A circuit diagram of an example of the circuit structure included in a display device. Figure 2 The circuit structure shown can correspond to a gate stage included in a gate driver.

[0077] Reference Figure 2 The first circuit structure 800 (or the second circuit structure 900) may include a first driving unit 1210, a second driving unit 1220, an output unit 1230, and a first transistor M1.

[0078] Output unit 1230 may include a fifth transistor M5 and a sixth transistor M6. Output unit 1230 may control the voltage supplied to output terminal 1004 based on the voltages of the first node N1 and the second node N2. The fifth transistor M5 may be connected between the first drive power (VGH) wiring (e.g., a high supply voltage wiring) and output terminal 1004, and the gate electrode of the fifth transistor M5 may be connected to the first node N1. The fifth transistor M5 may control the connection between the first drive power (VGH) wiring and output terminal 1004 based on the voltage applied to the first node N1. The sixth transistor M6 may be connected between output terminal 1004 and third input terminal 1003, and the gate electrode of the sixth transistor M6 may be connected to the second node N2. The sixth transistor M6 may control the connection between output terminal 1004 and third input terminal 1003 based on the voltage applied to the second node N2. Output unit 1230 may be driven by a buffer. In some embodiments, the fifth transistor M5 and / or the sixth transistor M6 may have a configuration in which multiple transistors are connected in parallel with each other.

[0079] The first driving unit 1210 may include a second transistor M2, a third transistor M3, and a fourth transistor M4. The first driving unit 1210 can control the voltage of the third node N3 based on clock signals supplied to the first input terminal 1001, the second input terminal 1002, and the third input terminal 1003. The second transistor M2 may be connected between the first input terminal 1001 and the third node N3, and the gate electrode of the second transistor M2 may be connected to the second input terminal 1002. The second transistor M2 can control the connection between the first input terminal 1001 and the third node N3 based on the clock signal supplied to the second input terminal 1002. The third transistor M3 and the fourth transistor M4 may be connected in series between the third node N3 and the first drive power (VGH) wiring. The third transistor M3 may be connected between the fourth transistor M4 and the third node N3, and the gate electrode of the third transistor M3 may be connected to the third input terminal 1003. The third transistor M3 can control the connection between the fourth transistor M4 and the third node N3 based on the clock signal supplied to the third input terminal 1003. A fourth transistor M4 can be connected between the third transistor M3 and the first drive power (VGH) wiring, and the gate electrode of the fourth transistor M4 can be connected to the first node N1. The fourth transistor M4 can control the connection between the third transistor M3 and the first drive power (VGH) wiring based on the voltage of the first node N1.

[0080] The second driving unit 1220 may include a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2. The second driving unit 1220 can control the voltage of the first node N1 based on the voltage at the second input terminal 1002 and the third node N3. The first capacitor C1 may be connected between the second node N2 and the output terminal 1004. The first capacitor C1 may be charged with voltage based on the on / off state of the sixth transistor M6. The second capacitor C2 may be connected between the first node N1 and the first drive power (VGH) wiring. The second capacitor C2 may be charged with the voltage applied to the first node N1. The seventh transistor M7 may be connected between the first node N1 and the second input terminal 1002, and the gate electrode of the seventh transistor M7 may be connected to the third node N3. The seventh transistor M7 can control the connection between the first node N1 and the second input terminal 1002 based on the voltage at the third node N3. An eighth transistor M8 may be connected between the first node N1 and the second drive power (VGL) wiring (e.g., a low supply voltage wiring), and the gate electrode of the eighth transistor M8 may be connected to the second input terminal 1002. The eighth transistor M8 may control the connection between the first node N1 and the second drive power (VGL) wiring based on a clock signal from the second input terminal 1002. A first transistor M1 may be connected between the third node N3 and the second node N2, and the gate electrode of the first transistor M1 may be connected to the second drive power (VGL) wiring. The first transistor M1 may maintain the electrical connection between the third node N3 and the second node N2 while maintaining a conducting state. In some embodiments, the first transistor M1 may limit the voltage drop level of the third node N3 based on the voltage of the second node N2. In other words, even when the voltage of the second node N2 drops below the voltage of the second drive power VGL, the voltage of the third node N3 will not become lower than the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the second drive power VGL.

[0081] Therefore, the first circuit structure 800 can transmit the gate signal (e.g., Figure 4 The gate signal GW is output to the output terminal 1004.

[0082] However, although the first circuit structure 800 has been described as including eight transistors and two capacitors, the construction of the embodiments described herein is not limited thereto. For example, the first circuit structure 800 may have a construction including at least one transistor and at least one capacitor.

[0083] Figure 3 It is shown Figure 1 A circuit diagram of another example of the circuit structure included in the display device. Figure 3 The circuit structure shown can correspond to a transmit signal stage included in a transmit signal driver.

[0084] Reference Figure 3 The first circuit structure 800 (or the second circuit structure 900) may include a first signal processing unit 2100, a second signal processing unit 2200, a third signal processing unit 2300, and an output unit 2400.

[0085] The first signal processing unit 2100 may include an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The first signal processing unit 2100 can control the voltages of the twenty-second node N22 and the twenty-first node N21 based on signals supplied to the first input terminal 2001 and the second input terminal 2002. The eleventh transistor M11 may be connected between the first input terminal 2001 and the twenty-first node N21, and the gate electrode of the eleventh transistor M11 may be connected to the second input terminal 2002. When a clock signal is supplied to the second input terminal 2002, the eleventh transistor M11 may be turned on. The twelfth transistor M12 may be connected between the second input terminal 2002 and the twenty-second node N22, and the gate electrode of the twelfth transistor M12 may be connected to the twenty-first node N21. The twelfth transistor M12 may be turned on or off based on the voltage of the twenty-first node N21. The thirteenth transistor M13 can be connected between the second drive power (VGL) wiring and the twenty-second node N22, and the gate electrode of the thirteenth transistor M13 can be connected to the second input terminal 2002. When a clock signal is supplied to the second input terminal 2002, the thirteenth transistor M13 can be turned on.

[0086] The second signal processing unit 2200 may include a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eleventh capacitor C11, and a twelfth capacitor C12. The second signal processing unit 2200 can control the voltages of the twenty-first node N21 and the twenty-third node N23 based on the clock signal supplied to the third input terminal 2003 and the voltage of the twenty-first node N22. The fourteenth transistor M14 may be connected between the fifteenth transistor M15 and the twenty-first node N21, and the gate electrode of the fourteenth transistor M14 may be connected to the third input terminal 2003. When the clock signal is supplied to the third input terminal 2003, the fourteenth transistor M14 may be turned on. The fifteenth transistor M15 may be connected between the first drive power (VGH) wiring and the fourteenth transistor M14, and the gate electrode of the fifteenth transistor M15 may be connected to the twenty-second node N22. The fifteenth transistor M15 may be turned on or off based on the voltage of the twenty-second node N22. The sixteenth transistor M16 can be connected between the first electrode of the seventeenth transistor M17 and the third input terminal 2003, and the gate electrode of the sixteenth transistor M16 can be connected to the twenty-second node N22. The sixteenth transistor M16 can be turned on or off based on the voltage of the twenty-second node N22. The seventeenth transistor M17 can be connected between the first electrode of the sixteenth transistor M16 and the twenty-third node N23, and the gate electrode of the seventeenth transistor M17 can be connected to the third input terminal 2003. When a clock signal is supplied to the third input terminal 2003, the seventeenth transistor M17 can be turned on. The eleventh capacitor C11 can be connected between the twenty-first node N21 and the third input terminal 2003. The twelfth capacitor C12 can be connected between the twenty-second node N22 and the first electrode of the seventeenth transistor M17.

[0087] The third signal processing unit 2300 may include an eighteenth transistor M18 and a thirteenth capacitor C13. The third signal processing unit 2300 can control the voltage of the twenty-third node N23 based on the voltage of the twenty-first node N21. The eighteenth transistor M18 may be connected between the first drive power (VGH) wiring and the twenty-third node N23, and the gate electrode of the eighteenth transistor M18 may be connected to the twenty-first node N21. The eighteenth transistor M18 may be turned on or off based on the voltage of the twenty-first node N21. The thirteenth capacitor C13 may be connected between the first drive power (VGH) wiring and the twenty-third node N23.

[0088] Output unit 2400 may include a nineteenth transistor M19 and a twentieth transistor M20. Output unit 2400 may control the voltage supplied to output terminal 2004 based on the voltages of the twenty-first node N21 and the twenty-third node N23. Nineteenth transistor M19 may be connected between the first drive power (VGH) wiring and output terminal 2004, and the gate electrode of nineteenth transistor M19 may be connected to the twenty-third node N23. Nineteenth transistor M19 may be turned on or off based on the voltage of the twenty-third node N23. Twentieth transistor M20 may be connected between output terminal 2004 and the second drive power (VGL) wiring, and the gate electrode of twenty-second transistor M20 may be connected to the twenty-first node N21. Twentieth transistor M20 may be turned on or off based on the voltage of the twenty-first node N21. Output unit 2400 may be driven by a buffer. In some embodiments, nineteenth transistor M19 and / or twentieth transistor M20 may have a configuration in which multiple transistors are connected in parallel with each other.

[0089] Therefore, the second circuit structure 900 can transmit control signals (e.g., Figure 4 The transmit control signal (EM) is output to the output terminal 2004.

[0090] However, although the second circuit structure 900 has been described as including ten transistors and three capacitors, the construction of the embodiments described herein is not limited thereto. For example, the second circuit structure 900 may have a construction including at least one transistor and at least one capacitor.

[0091] In an embodiment, the display device 100 may have wherein Figure 2 circuit structure and Figure 3 The circuit structures are respectively set in the second sub-region 22 and the fourth sub-region 32, or in the configuration thereof. Figure 2 circuit structure or Figure 3 The circuit structure is configured in each of the second sub-region 22 and the fourth sub-region 32.

[0092] Figure 4 It is shown Figure 1 The circuit diagram of the sub-pixels and pixel circuits included in the display device.

[0093] Reference Figure 4 Each of the first to third sub-pixels R, B, and G included in the display device 100 may correspond to an organic light-emitting diode (OLED), and each of the first to third pixel circuits included in the display device 100 may correspond to a pixel circuit PC. When viewed in a cross-sectional view of the display device 100, the pixel circuit PC may be disposed on the substrate 110, and the organic light-emitting diode (OLED) may be disposed on the pixel circuit PC.

[0094] The pixel circuit PC may include first transistors through seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7, and a storage capacitor CST. The first transistor TR1 may correspond to a driving transistor, and the second through seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7 may correspond to switching transistors. Each of the first through seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7 may include a first terminal, a second terminal, a channel terminal, and a gate terminal. In some embodiments, the first terminal may be a source terminal, and the second terminal may be a drain terminal. In some embodiments, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

[0095] Organic light-emitting diodes (OLEDs) can output light based on a drive current ID. An OLED may include a first terminal and a second terminal. In one embodiment, the second terminal of the OLED may receive a low supply voltage ELVSS, and the first terminal may receive a high supply voltage ELVDD. For example, the first terminal of the OLED may be an anode terminal, and the second terminal may be a cathode terminal. In another embodiment, the first terminal of the OLED may be a cathode terminal, and the second terminal may be an anode terminal.

[0096] The first transistor TR1 can generate a drive current ID. In an embodiment, the first transistor TR1 can operate in the saturation region. In this case, the first transistor TR1 can generate the drive current ID based on the voltage difference between the gate terminal and the source terminal of the first transistor TR1. Additionally, the grayscale level can be represented based on the magnitude of the drive current ID supplied to the organic light-emitting diode OLED. In some embodiments, the first transistor TR1 can operate in the linear region. In this case, the grayscale level can be represented based on the total time the drive current ID is supplied to the organic light-emitting diode OLED within a frame.

[0097] The gate terminal of the second transistor TR2 can receive the gate signal GW. For example, it can be obtained from... Figure 2 The gate stage shown provides a gate signal GW, and the gate signal GW can be applied to the gate terminal of the second transistor TR2 via gate signal (GW) wiring. The first terminal of the second transistor TR2 can receive a data signal DATA. The second terminal of the second transistor TR2 can be connected to the first terminal of the first transistor TR1. For example, it can be obtained from... Figure 2The gate stage shown provides a gate signal GW, and the gate signal GW can be applied to the gate terminal of the second transistor TR2 via a gate signal (GW) wiring. The second transistor TR2 can supply a data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the second transistor TR2 can operate in the linear region.

[0098] The gate terminal of the third transistor TR3 can receive the gate signal GW. For example, it can be obtained from... Figure 2 The gate stage shown provides a gate signal GW, and the gate signal GW can be applied to the gate terminal of the third transistor TR3 via gate signal (GW) wiring. The first terminal of the third transistor TR3 can be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 can be connected to the second terminal of the first transistor TR1. The third transistor TR3 can connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during the active period of the gate signal GW. In this case, the third transistor TR3 can operate in the linear region. In other words, the third transistor TR3 can diode-connect the first transistor TR1 during the active period of the gate signal GW.

[0099] The initialization voltage VINT is provided to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7, and the initialization voltage wiring can be connected to the first terminal of the storage capacitor CST through the fourth transistor TR4.

[0100] The gate terminal of the fourth transistor TR4 can receive the gate initialization signal GI. The first terminal of the fourth transistor TR4 can receive the initialization voltage VINT. The second terminal of the fourth transistor TR4 can be connected to the gate terminal of the first transistor TR1.

[0101] The fourth transistor TR4 can supply an initialization voltage VINT to the gate terminal of the first transistor TR1 during the activation period of the gate initialization signal GI. In this case, the fourth transistor TR4 can operate in the linear region. In other words, the fourth transistor TR4 can initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In one embodiment, the initialization voltage VINT can have a voltage level sufficiently lower than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT can be supplied to the gate terminal of the first transistor TR1. In other embodiments, the initialization voltage can have a voltage level sufficiently higher than the voltage level of the data signal DATA maintained by the storage capacitor in the previous frame, and the initialization voltage can be applied to the gate terminal of the first transistor TR1.

[0102] The gate terminal of the fifth transistor TR5 can receive the transmit control signal EM. For example, it can be received from... Figure 3 The transmit signal stage shown provides a transmit control signal EM, which can be applied to the gate terminal of a fifth transistor TR5 via the transmit control signal (EM) wiring. The first terminal of the fifth transistor TR5 can be connected to a high supply voltage (ELVDD) wiring. The second terminal of the fifth transistor TR5 can be connected to the first terminal of a first transistor TR1. The fifth transistor TR5 can supply the high supply voltage ELVDD to the first terminal of the first transistor TR1 during the active period of the transmit control signal EM. Conversely, the fifth transistor TR5 can cut off the supply of the high supply voltage ELVDD during the deactivation period of the transmit control signal EM. In this case, the fifth transistor TR5 can operate in the linear region. Because the fifth transistor TR5 supplies the high supply voltage ELVDD to the first terminal of the first transistor TR1 during the active period of the transmit control signal EM, the first transistor TR1 can generate a drive current ID. Additionally, because the fifth transistor TR5 cuts off the supply of the high supply voltage ELVDD during the deactivation period of the transmit control signal EM, the data signal DATA supplied to the first terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0103] The gate terminal of the sixth transistor TR6 can receive the transmit control signal EM. For example, it can be received from... Figure 3The transmit signal stage shown provides a transmit control signal EM, which can be applied to the gate terminal of a sixth transistor TR6 via transmit control signal (EM) wiring. The first terminal of the sixth transistor TR6 can be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 can be connected to the first terminal of an organic light-emitting diode (OLED). During the active period of the transmit control signal EM, the sixth transistor TR6 can supply the OLED with a drive current ID generated by the first transistor TR1. In this case, the sixth transistor TR6 can operate in the linear region. In other words, since the sixth transistor TR6 supplies the OLED with the drive current ID generated by the first transistor TR1 during the active period of the transmit control signal EM, the OLED can output light. Furthermore, since the sixth transistor TR6 electrically isolates the first transistor TR1 from the OLED during the deactivation period of the transmit control signal EM, a data signal DATA (more precisely, a data signal compensated for the threshold voltage) supplied to the second terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0104] The gate terminal of the seventh transistor TR7 can receive the diode initialization signal GB. The first terminal of the seventh transistor TR7 can receive the initialization voltage VINT. The second terminal of the seventh transistor TR7 can be connected to the first terminal of the organic light-emitting diode (OLED). The seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the OLED during the active period of the diode initialization signal GB. In this case, the seventh transistor TR7 can operate in the linear region. In other words, the seventh transistor TR7 can initialize the first terminal of the OLED to the initialization voltage VINT during the active period of the diode initialization signal GB.

[0105] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between a high power supply voltage (ELVDD) wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power supply voltage (ELVDD) wiring. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the deactivation period of the gate signal GW. The deactivation period of the gate signal GW may include the activation period of the emitter control signal EM, and the drive current ID generated by the first transistor TR1 may be supplied to the organic light-emitting diode (OLED) during the activation period of the emitter control signal EM. Therefore, based on the voltage level maintained by the storage capacitor CST, the drive current ID generated by the first transistor TR1 may be supplied to the organic light-emitting diode (OLED).

[0106] However, although the pixel circuit PC according to the embodiments described herein has been described as including seven transistors and a storage capacitor, the construction of the embodiments described herein is not limited thereto. For example, the pixel circuit PC may have a construction including at least one transistor and at least one storage capacitor.

[0107] Figure 5 It is shown Figure 1 A magnified plan view of a portion of region A. Figure 6 It is shown Figure 1 A magnified plan view of region B. For ease of description, the first to third sub-pixels R, B, and G set in display region 10 will be defined as first sub-pixel 101, second sub-pixel 102, and third sub-pixel 103, respectively, and the first to third sub-pixels R, B, and G set in the first display region 20 and the second display region 30 will be defined as first sub-pixel 201, second sub-pixel 202, and third sub-pixel 203, respectively.

[0108] Reference Figure 5 and Figure 6 The first to third sub-pixels 101, 102, and 103 can be arranged throughout the entire substrate 110. As described above, the first to third sub-pixels 101, 102, and 103 can be arranged in a manner that... Plan layout.

[0109] The first sub-pixel 101 and the second sub-pixel 102 can be repeatedly arranged in a first column 10a adjacent to the first boundary between the display area 10 and the first sub-region 21 (e.g., corresponding to a second direction D2 orthogonal to the first direction D1). For example, the first sub-pixel 101 can be located at the top of the first row and first column 10a of the display area 10, the second sub-pixel 102 can be located at the top of the second row and first column 10a of the display area 10, the first sub-pixel 101 can be located at the top of the third row and first column 10a of the display area 10, and the second sub-pixel 102 can be located at the top of the fourth row and first column 10a of the display area 10. In this application, the reference numeral following "i-th row and j-th column" is the reference numeral for "j-th column". For example, "10a" in "first row and first column 10a" is the reference numeral for "first column".

[0110] Additionally, the third sub-pixel 103 can be repeatedly arranged in the second column 10b of the display area 10. For example, the third sub-pixel 103 can be located at the bottom of the first row, second column 10b of the display area 10; the third sub-pixel 103 can be located at the bottom of the second row, second column 10b of the display area 10; the third sub-pixel 103 can be located at the bottom of the third row, second column 10b of the display area 10; and the third sub-pixel 103 can be located at the bottom of the fourth row, second column 10b of the display area 10. For example, the first column 10a can be located between the second column 10b and the first boundary.

[0111] Similarly, the second sub-pixel 102 and the first sub-pixel 101 can be repeatedly arranged in the third column 10c of the display area 10 adjacent to the second boundary between the display area 10 and the third sub-region 31. For example, the second sub-pixel 102 can be located at the top of the first row and third column 10c of the display area 10, the first sub-pixel 101 can be located at the top of the second row and third column 10c of the display area 10, the second sub-pixel 102 can be located at the top of the third row and third column 10c of the display area 10, and the first sub-pixel 101 can be located at the top of the fourth row and third column 10c of the display area 10.

[0112] Additionally, the third sub-pixel 103 can be repeatedly arranged in the fourth column 10d of the display area 10. For example, the third sub-pixel 103 can be located at the bottom of the first row and fourth column 10d of the display area 10, the bottom of the second row and fourth column 10d of the display area 10, the bottom of the third row and fourth column 10d of the display area 10, and the bottom of the fourth row and fourth column 10d of the display area 10. For example, the fourth column 10d can be located between the third column 10c and the second boundary.

[0113] In this way, In this arrangement, the first to third sub-pixels 101, 102, and 103 can be arranged throughout the entire display area 10. In other words, the first to third sub-pixels 101, 102, and 103 can be arranged in a zigzag shape in the first column 10a and second column 10b of the display area 10, following the order of first sub-pixel 101, third sub-pixel 103, second sub-pixel 102, and third sub-pixel 103. Alternatively, the first to third sub-pixels 101, 102, and 103 can be arranged in a zigzag shape in the third column 10c and fourth column 10d of the display area 10, following the order of second sub-pixel 102, third sub-pixel 103, first sub-pixel 101, and third sub-pixel 103.

[0114] The first to third sub-pixels 201, 202, and 203 can be arranged throughout the entire first display area 20 and the second display area 30. As described above, the first to third sub-pixels 201, 202, and 203 can be arranged in a manner that... Plan layout.

[0115] The third sub-pixel 203 can be repeatedly arranged in the first column 20a of the first sub-region 21 adjacent to the first boundary. For example, the third sub-pixel 203 can be set at the top of the first column 20a in the second row (e.g., corresponding to the second row of the display area 10) of the first sub-region 21, and the third sub-pixel 203 can be set at the top of the first column 20a in the fourth row (e.g., corresponding to the fourth row of the display area 10) of the first sub-region 21.

[0116] Additionally, the second column 20b of the first sub-region 21 may be located between the first boundary and the first column 20a of the first sub-region 21. The third column 20c of the first sub-region 21 may be adjacent to the first column 20a of the first sub-region 21, and the fourth column 20d of the first sub-region 21 may be located between the first column 20a and the third column 20c of the first sub-region 21.

[0117] The second sub-pixel 202 and the first sub-pixel 201 can be repeatedly arranged in the third column 20c of the first sub-region 21. For example, the second sub-pixel 202 can be set at the top of the third column 20c of the first row (e.g., corresponding to the first row of the display area 10) of the first sub-region 21, and the first sub-pixel 201 can be set at the top of the third column 20c of the third row (e.g., corresponding to the third row of the display area 10) of the first sub-region 21.

[0118] In this embodiment, the first sub-pixel to the third sub-pixel 201, 202 and 203 may not be set in the second column 20b and the fourth column 20d of the first sub-region 21.

[0119] For example, the sizes of the first to third sub-pixels 201, 202, and 203 can be relatively larger than the sizes of the first to third sub-pixels 101, 102, and 103, respectively. In this case, considering the process margin of the fine metal mask used in the process of forming the light-emitting layer included in each of the first to third sub-pixels 201, 202, and 203, the first to third sub-pixels 201, 202, and 203 must be spaced apart from each other by a relatively larger distance than the distance between the first to third sub-pixels 101, 102, and 103. Therefore, the first to third sub-pixels 201, 202, and 203 are not located in the second column 20b and the fourth column 20d of the first sub-region 21, so that no defects occur in the process of forming the light-emitting layer of each of the first to third sub-pixels 201, 202, and 203. Furthermore, the first to third sub-pixels 101, 102 and 103 can be set in all columns of the display area 10, and the display area 10 may exclude columns in which the first to third sub-pixels 101, 102 and 103 are not set.

[0120] In this way, In this design, the first to third sub-pixels 201, 202, and 203 can be arranged throughout the entire first sub-region 21 and the second sub-region 22. In other words, the first to third sub-pixels 201, 202, and 203 can be arranged in a zigzag shape in the first to fourth columns 20a, 20b, 20c, and 20d of the first sub-region 21, following the order of second sub-pixel 202, third sub-pixel 203, first sub-pixel 201, and third sub-pixel 203. For reference, the second column 20b, first column 20a, fourth column 20d, and third column 20c can be arranged sequentially from the first boundary in the first sub-region 21 along the direction from the display area 10 to the first display area 20.

[0121] Similarly, the first sub-pixel 201 and the second sub-pixel 202 can be repeatedly arranged in the first column 30a of the third sub-region 31 adjacent to the second boundary. For example, the first sub-pixel 201 can be located at the top of the first column 30a of the first row (e.g., corresponding to the first row of the display area 10) of the third sub-region 31, and the second sub-pixel 202 can be located at the top of the first column 30a of the third row (e.g., corresponding to the third row of the display area 10) of the third sub-region 31.

[0122] Additionally, the second column 30b of the third sub-region 31 may be located between the second boundary and the first column 30a of the third sub-region 31. The third column 30c of the third sub-region 31 may be adjacent to the first column 30a of the third sub-region 31, and the fourth column 30d of the third sub-region 31 may be located between the first column 30a and the third column 30c of the third sub-region 31.

[0123] The third sub-pixel 203 can be repeatedly arranged in the third column 30c of the third sub-region 31. For example, the third sub-pixel 203 can be set at the top of the third column 30c of the second row (e.g., corresponding to the second row of the display area 10) of the third sub-region 31, and the third sub-pixel 203 can be set at the top of the third column 30c of the fourth row (e.g., corresponding to the fourth row of the display area 10) of the third sub-region 31.

[0124] In this embodiment, the first sub-pixel to the third sub-pixel 201, 202 and 203 may not be set in the second column 30b and the fourth column 30d of the third sub-region 31.

[0125] For example, the sizes of the first to third sub-pixels 201, 202, and 203 can be relatively larger than the sizes of the first to third sub-pixels 101, 102, and 103, respectively. In this case, considering the process margin of the fine metal mask used in the process of forming the light-emitting layer included in each of the first to third sub-pixels 201, 202, and 203, the first to third sub-pixels 201, 202, and 203 must be spaced apart from each other by a relatively larger distance than the distance between the first to third sub-pixels 101, 102, and 103. Therefore, the first to third sub-pixels 201, 202, and 203 are not disposed in the second column 30b and the fourth column 30d of the third sub-region 31, so that no defects occur in the process of forming the light-emitting layer of each of the first to third sub-pixels 201, 202, and 203. Furthermore, the first to third sub-pixels 101, 102 and 103 can be set in all columns of the display area 10, and the display area 10 may exclude columns in which the first to third sub-pixels 101, 102 and 103 are not set.

[0126] In this way, In this design, the first to third sub-pixels 201, 202, and 203 can be arranged throughout the entire third sub-region 31 and fourth sub-region 32. In other words, the first to third sub-pixels 201, 202, and 203 can be arranged in a zigzag shape in the first to fourth columns 30a, 30b, 30c, and 30d of the third sub-region 31, following the order of first sub-pixel 201, third sub-pixel 203, second sub-pixel 202, and third sub-pixel 203. For reference, the second column 30b, the first column 30a, the fourth column 30d, and the third column 30c can be arranged sequentially from the second boundary in the third sub-region 31 along the direction from the display area 10 to the second display area 30. Additionally, the second column 10b and the third column 10c of the display area 10 can be located between the first column 10a and the fourth column 10d of the display area 10, the second column 20b of the first sub-area 21 can be located between the first column 10a of the display area 10 and the first column 20a of the first sub-area 21, and the second column 30b of the third sub-area 31 can be located between the fourth column 10d of the display area 10 and the first column 30a of the third sub-area 31.

[0127] In an embodiment, the number of first sub-pixels 101 and second sub-pixels 102 arranged in the first column 10a of the display area 10 can be equal to the number of third sub-pixels 103 arranged in the second column 10b of the display area 10. Furthermore, the number of third sub-pixels 203 arranged in the first column 20a of the first sub-region 21 can be less than the number of first sub-pixels 101 and second sub-pixels 102 arranged in the first column 10a of the display area 10. For example, the number of third sub-pixels 203 arranged in the first column 20a of the first sub-region 21 can be half the number of first sub-pixels 101 and second sub-pixels 102 arranged in the first column 10a of the display area 10.

[0128] As described above, the display device 100 may include first pixel circuitry to third pixel circuitry. In an embodiment, the first pixel circuitry to third pixel circuitry connected to the first to third sub-pixels 101, 102, and 103 disposed in the display area 10 may be disposed in the display area 10 between the substrate 110 and the first to third sub-pixels 101, 102, and 103 (see [link to documentation]). Figure 7 ).

[0129] For example, connected to the first sub-pixel 101 located in the first row and first column 10a of the display area 10 (e.g., Figure 7 The first pixel circuit of the first sub-pixel 101 (e.g., Figure 7The first pixel circuit PC11 can be superimposed on the first sub-pixel 101 in the first row and first column 10a. The second pixel circuit connected to the second sub-pixel 102 in the second row and first column 10a of the display area 10 can be superimposed on the second sub-pixel 102 in the second row and first column 10a. The first pixel circuit connected to the first sub-pixel 101 in the third row and first column 10a of the display area 10 can be superimposed on the first sub-pixel 101 in the third row and first column 10a. The second pixel circuit connected to the second sub-pixel 102 in the fourth row and first column 10a of the display area 10 can be superimposed on the second sub-pixel 102 in the fourth row and first column 10a. Additionally, the third pixel circuit connected to the third sub-pixel 103 disposed in the first row, second column, 10b of the display area 10 can be superimposed on the third sub-pixel 103 disposed in the first row, second column, 10b; the third pixel circuit connected to the third sub-pixel 103 disposed in the second row, second column, 10b of the display area 10 can be superimposed on the third sub-pixel 103 disposed in the second row, second column, 10b of the display area 10; the third pixel circuit connected to the third sub-pixel 103 disposed in the third row, second column, 10b of the display area 10 can be superimposed on the third sub-pixel 103 disposed in the third row, second column, 10b of the display area 10; and the third pixel circuit connected to the third sub-pixel 103 disposed in the fourth row, second column, 10b of the display area 10 can be superimposed on the third sub-pixel 103 disposed in the fourth row, second column, 10b of the display area 10.

[0130] Furthermore, the first pixel circuit to the third pixel circuit connected to the first sub-pixels 201, 202, and 203 disposed in the first display area 20 can be disposed in the first sub-region 21 between the substrate 110 and the first sub-pixels 201, 202, and 203 disposed in the first sub-region 21. In other words, the first pixel circuit to the third pixel circuit can be disposed only in the first sub-region 21, and the first circuit structure 800 (e.g., Figure 9 The first circuit structure 800 shown can be disposed between the substrate 110 and the first to third sub-pixels 201, 202 and 203 disposed in the second sub-region 22.

[0131] For example, connected to the third sub-pixel 203 located in the second row and first column 20a of the first sub-region 21 (e.g., Figure 8 The third pixel circuit of the third sub-pixel 203 shown (e.g., Figure 8The third pixel circuit (PC23) can be stacked with the third sub-pixel 203 in the second row, first column 20a. In this case, the third sub-pixel 203 disposed in the second row, first column 20a can be connected to the third pixel circuit via the connecting electrode 621 and the contact hole 721. In some embodiments, the third pixel circuit can also be disposed in the second row, second column 20b (i.e., disposed in both the second row, first column 20a and the second row, second column 20b), or it can be disposed only in the second row, second column 20b.

[0132] Additionally, the third pixel circuit connected to the third sub-pixel 203 disposed in the fourth row, first column, 20a of the first sub-region 21 can be superimposed on the third sub-pixel 203 in the fourth row, first column, 20a. In this case, the third sub-pixel 203 disposed in the fourth row, first column, 20a can be connected to the third pixel circuit via the connecting electrode 641 and the contact hole 741. In some embodiments, the third pixel circuit can also be disposed in the fourth row, second column, 20b (i.e., disposed in both the fourth row, first column, 20a and the fourth row, second column, 20b), or it can be disposed only in the fourth row, second column, 20b.

[0133] Furthermore, the second pixel circuit connected to the second sub-pixel 202 disposed in the first row, third column, 20c of the first sub-region 21 can be superimposed on the second sub-pixel 202 in the first row, third column, 20c. In this case, the second sub-pixel 202 disposed in the first row, third column, 20c can be connected to the second pixel circuit via the connecting electrode 611 and the contact hole 711. In some embodiments, the second pixel circuit can also be disposed in the first row, fourth column, 20d (i.e., disposed in both the first row, third column, 20c and the first row, fourth column, 20d), or it can be disposed only in the first row, fourth column, 20d.

[0134] Furthermore, the first pixel circuit connected to the first sub-pixel 201 disposed in the third row and third column 20c of the first sub-region 21 can be superimposed on the first sub-pixel 201 in the third row and third column 20c. In this case, the first sub-pixel 201 disposed in the third row and third column 20c can be connected to the first pixel circuit through the connecting electrode 631 and the contact hole 731. In some embodiments, the first pixel circuit can also be disposed in the third row and fourth column 20d (i.e., disposed in both the third row and third column 20c and the third row and fourth column 20d), or it can be disposed only in the third row and fourth column 20d.

[0135] In this way, the first pixel circuits to the third pixel circuits connected to the first sub-pixels to the third sub-pixels 201, 202, and 203 disposed in the fifth to eighth columns of the first sub-region 21 can also be superimposed on the first sub-pixels to the third sub-pixels 201, 202, and 203 disposed in the fifth to eighth columns. In other words, the first sub-pixels to the third sub-pixels 201, 202, and 203 disposed in the fifth to eighth columns can be connected to the first pixel circuits to the third pixel circuits via connecting electrodes 612, 622, 632, and 642 and contact holes 712, 722, 732, and 742, respectively.

[0136] Connect to the first sub-pixel 201 located in the first row and seventh column of the second sub-region 22 (e.g., Figure 9 The first pixel circuit of the first sub-pixel 201 shown (e.g., Figure 10 The first pixel circuit (PC21) shown can be disposed in the first row and first column 20a of the first sub-region 21. In this case, the first sub-pixel 201 disposed in the first row and seventh column can be connected to the first pixel circuit via the connecting electrode 614 and the contact hole 714. In some embodiments, the first pixel circuit can also be disposed in the first row and second column 20b of the first sub-region 21 (i.e., disposed in both the first row and first column 20a and the first row and second column 20b), or it can be disposed only in the first row and second column 20b.

[0137] Additionally, the second pixel circuit connected to the second sub-pixel 202 located in the first row and third column of the second sub-region 22 can be located in the first row and fifth column of the first sub-region 21. In this case, the second sub-pixel 202 located in the first row and third column can be connected to the second pixel circuit via the connecting electrode 613 and the contact hole 713. In some embodiments, the second pixel circuit can also be located in the first row and sixth column of the first sub-region 21 (i.e., located in both the first row and fifth column and the first row and sixth column), or it can be located only in the first row and sixth column.

[0138] Furthermore, a third pixel circuit connected to a third sub-pixel 203 disposed in the second row and fifth column of the second sub-region 22 can be disposed in the second row and third column 20c of the first sub-region 21. In this case, the third sub-pixel 203 disposed in the second row and fifth column can be connected to the third pixel circuit via a connecting electrode 624 and a contact hole 724. In some embodiments, the third pixel circuit can also be disposed in the second row and fourth column 20d of the first sub-region 21 (i.e., disposed in both the second row and third column 20c and the second row and fourth column 20d), or it can be disposed only in the second row and fourth column 20d.

[0139] Furthermore, the third pixel circuit connected to the third sub-pixel 203 disposed in the second row and first column of the second sub-region 22 can be disposed in the second row and seventh column of the first sub-region 21. In this case, the third sub-pixel 203 disposed in the second row and first column can be connected to the third pixel circuit via the connecting electrode 623 and the contact hole 723. In some embodiments, the third pixel circuit can also be disposed in the second row and eighth column of the first sub-region 21 (i.e., disposed in both the second row and seventh column and the second row and eighth column), or it can be disposed only in the second row and eighth column.

[0140] In this way, the first pixel circuit to the third pixel circuit connected to the first sub-pixels to the third sub-pixels 201, 202, and 203 disposed in the third and fourth rows of the second sub-region 22 can also be disposed in the first column 20a, the third column 20c, the fifth column, and the seventh column of the first sub-region 21. In other words, the first sub-pixels to the third sub-pixels 201, 202, and 203 disposed in the third and fourth rows can be connected to the first pixel circuit to the third pixel circuit via connecting electrodes 633, 634, 643, and 644 and contact holes 733, 734, 743, and 744, respectively.

[0141] Furthermore, the first pixel circuit to the third pixel circuit connected to the first to third sub-pixels 201, 202, and 203 disposed in the second display area 30 can be disposed in the third sub-region 31 between the substrate 110 and the first to third sub-pixels 201, 202, and 203 disposed in the third sub-region 31. In other words, the first pixel circuit to the third pixel circuit can be disposed only in the third sub-region 31, and the second circuit structure 900 can be disposed between the substrate 110 and the first to third sub-pixels 201, 202, and 203 disposed in the fourth sub-region 32.

[0142] Since the arrangement of the first pixel circuits to the third pixel circuits connected to the first to third sub-pixels 201, 202, and 203 disposed in the second display area 30 is similar to the arrangement of the first pixel circuits to the third pixel circuits connected to the first sub-pixels 201, 202, and 203 disposed in the first display area 20, its description will be omitted for the sake of brevity. In other words, the first to third sub-pixels 201, 202, and 203 disposed in the first to eighth columns of the third sub-region 31 can be connected to the first pixel circuits to the third pixel circuits respectively through connecting electrodes 811, 812, 821, 822, 831, 832, 841, and 842 and contact holes 911, 912, 921, 922, 931, 932, 941, and 942. Additionally, the first to third sub-pixels 201, 202, and 203 located in the first to eighth columns of the fourth sub-region 32 can be connected to the first to third pixel circuits via connecting electrodes 813, 814, 823, 824, 833, 834, 843, and 844, and contact holes 913, 914, 923, 924, 933, 934, 943, and 944, respectively.

[0143] According to the embodiment described herein, the first to third sub-pixels 201, 202 and 203 are not disposed in the second column 20b of the first sub-region 21 and the second column 30b of the third sub-region 31, so that no defects occur in the process of forming the light-emitting layer of each of the first to third sub-pixels 201, 202 and 203 adjacent to the first boundary and the second boundary.

[0144] However, although the display device 100 according to the embodiments described herein has been specifically described as an organic light-emitting diode display device, the construction of the embodiments described herein is not limited thereto. In other embodiments, the display device 100 may include a liquid crystal display (LCD), a field emission display (FED), a plasma display device (PDP), and an electrophoretic display device (EPD).

[0145] Figure 7 It is along Figure 5 A cross-sectional view taken by line I-I'. Figure 8 It is along Figure 5 The sectional view taken from line II-II'. Figure 9 It is along Figure 5 The sectional view taken from line III-III'. Figure 10 It is along Figure 5 A sectional view taken from line IV-IV'.

[0146] Reference Figure 5 , Figure 7 , Figure 8, Figure 9 and Figure 10 The display device 100 may include a substrate 110, a first pixel circuit PC11 of the display area 10, a first sub-pixel 101 of the display area 10, a third pixel circuit PC23 of the first display area 20, a third sub-pixel 203 of the first display area 20, a first pixel circuit PC21 of the first display area 20, a first sub-pixel 201 of the first display area 20, a first circuit structure 800 of the second sub-area 22, a gate insulating layer 150, an interlayer insulating layer 190, a first planarization layer 270, a second planarization layer 275, connecting electrodes 530, 614, 622 and 624, a pixel defining layer 310, etc.

[0147] In this configuration, the first pixel circuit PC11 may include a first transistor 255a and a second transistor 250a. The first transistor 255a includes an active layer 135a, a gate electrode 175a, a source electrode 215a, and a drain electrode 235a. The second transistor 250a includes an active layer 130a, a gate electrode 170a, a source electrode 210a, and a drain electrode 230a. Furthermore, the first sub-pixel 101 may include a lower electrode 290a, a light-emitting layer 330a, and an upper electrode 340. The first pixel circuit PC11 may correspond to... Figure 4 The pixel circuit PC, and the first sub-pixel 101 can correspond to Figure 4 Organic light-emitting diodes (OLEDs). For example, the first transistor 255a may correspond to the first transistor TR1 of the pixel circuit PC, and the second transistor 250a may correspond to one of the second to seventh transistors TR2, TR3, TR4, TR5, TR6 and TR7 of the pixel circuit PC.

[0148] Additionally, the third pixel circuit PC23 may include a third transistor 255b and a fourth transistor 250b. The third transistor 255b includes an active layer 135b, a gate electrode 175b, a source electrode 215b, and a drain electrode 235b. The fourth transistor 250b includes an active layer 130b, a gate electrode 170b, a source electrode 210b, and a drain electrode 230b. Furthermore, the third sub-pixel 203 may include a lower electrode 290b, a light-emitting layer 330b, and an upper electrode 340. The third pixel circuit PC23 can correspond to... Figure 4 The pixel circuit PC, and the third sub-pixel 203 can correspond to Figure 4 Organic light-emitting diodes (OLEDs). For example, the third transistor 255b may correspond to the first transistor TR1 of the pixel circuit PC, and the fourth transistor 250b may correspond to one of the second to seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7 of the pixel circuit PC.

[0149] Furthermore, the first pixel circuit PC21 may include a fifth transistor 255c and a sixth transistor 250c. The fifth transistor 255c includes an active layer 135c, a gate electrode 175c, a source electrode 215c, and a drain electrode 235c. The sixth transistor 250c includes an active layer 130c, a gate electrode 170c, a source electrode 210c, and a drain electrode 230c. The first sub-pixel 201 may include a lower electrode 290c, a light-emitting layer 330c, and an upper electrode 340. The first pixel circuit PC21 may correspond to... Figure 4 The pixel circuit PC, and the first sub-pixel 201 can correspond to Figure 4 Organic light-emitting diodes (OLEDs). For example, the fifth transistor 255c may correspond to the first transistor TR1 of the pixel circuit PC, and the sixth transistor 250c may correspond to one of the second to seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7 of the pixel circuit PC.

[0150] Furthermore, the first circuit structure 800 may include a first circuit transistor 855 and a second circuit transistor 850. The first circuit transistor 855 includes an active layer 735, a gate electrode 775, a source electrode 815, and a drain electrode 835. The second circuit transistor 850 includes an active layer 730, a gate electrode 770, a source electrode 810, and a drain electrode 830. The first circuit structure 800 may correspond to... Figure 2 gate driver or Figure 3 The transmit signal driver. For example, the first circuit transistor 855 or the second circuit transistor 850 can correspond to... Figure 2 One of the first to eighth transistors M1, M2, M3, M4, M5, M6, M7, and M8, or which may correspond to Figure 3 One of the eleventh to twentieth transistors M11, M12, M13, M14, M15, M16, M17, M18, M19 and M20.

[0151] Furthermore, the display device 100 may also include a second pixel circuit and a third pixel circuit for the display area 10, a second sub-pixel 102 and a third sub-pixel 103 for the display area 10, a second pixel circuit for the first display area 20, a second sub-pixel 202 for the first display area 20, a first pixel circuit to a third pixel circuit for the second display area 30, first sub-pixels to third sub-pixels 201, 202 and 203 for the second display area 30, and a second circuit structure 900 for the fourth sub-area 32, such as... Figure 5 and Figure 6 As shown in the image.

[0152] A substrate 110, which may be made of transparent or opaque materials, can be provided. The substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda-lime glass substrate, an alkali-free glass substrate, etc.

[0153] In other embodiments, the substrate 110 may be a flexible, transparent resin substrate. Examples of transparent resin substrates that can be used as the substrate 110 include polyimide substrates. In this case, the polyimide substrate may have a stacked structure including a first polyimide layer, a barrier film layer, a second polyimide layer, etc.

[0154] Since the display device 100 includes a display area 10, a first display area 20, and a second display area 30, the substrate 110 can also be divided into a display area 10, a first display area 20, and a second display area 30.

[0155] like Figure 7 As shown, the first transistor 255a and the second transistor 250a can be disposed on the substrate 110 in the display area 10. In other words, the first pixel circuit PC11 can be disposed between the substrate 110 and the second planarization layer 275 in the display area 10 to at least partially overlap with the first sub-pixel 101.

[0156] The connection electrode 530 can be disposed on the first pixel circuit PC11 in the display area 10. The connection electrode 530 can be connected to the drain electrode 230a through a contact hole formed in the first planarization layer 270.

[0157] The first sub-pixel 101 can be disposed on the first pixel circuit PC11. The first sub-pixel 101 can be electrically connected to the first pixel circuit PC11 via the connecting electrode 530. In other words, the lower electrode 290a can be connected to the connecting electrode 530 via a contact hole formed in the second planarization layer 275. In an embodiment, the lower electrode 290a can have a first width a1, and the contact hole formed in the first planarization layer 270 can be superimposed on the lower electrode 290a.

[0158] like Figure 8 As shown, the third transistor 255b and the fourth transistor 250b can be disposed on the substrate 110 in the first sub-region 21. In other words, the third pixel circuit PC23 can be disposed between the substrate 110 and the second planarization layer 275 in the first sub-region 21 to at least partially overlap with the third sub-pixel 203.

[0159] Connecting electrodes 622 and 624 can be disposed on the third pixel circuit PC23 in the first sub-region 21. Connecting electrode 622 can be connected to drain electrode 230b through contact hole 722 formed in the first planarization layer 270. In addition, connecting electrode 624 can extend on the first planarization layer 270 in the first direction D1.

[0160] The third sub-pixel 203 can be disposed on the third pixel circuit PC23. The third sub-pixel 203 can be electrically connected to the third pixel circuit PC23 via the connecting electrode 622. In other words, the lower electrode 290b can be connected to the connecting electrode 622 via a contact hole formed in the second planarization layer 275. In an embodiment, the lower electrode 290b can have a second width a2 greater than the first width a1, and the contact hole 722 formed in the first planarization layer 270 can be non-overlapping with the lower electrode 290b.

[0161] like Figure 9 and Figure 10 As shown, the first circuit transistor 855 and the second circuit transistor 850 can be disposed on the substrate 110 in the second sub-region 22. In other words, the first circuit structure 800 can be disposed between the substrate 110 and the second planarization layer 275 in the second sub-region 22 to at least partially overlap with the first sub-pixel 201.

[0162] The connecting electrode 614 can be disposed on the first circuit structure 800 in the second sub-region 22. The connecting electrode 614 may not be electrically connected to the first circuit structure 800.

[0163] The fifth transistor 255c and the sixth transistor 250c can be disposed on the substrate 110 in the first sub-region 21. In other words, the first pixel circuit PC21 can be disposed between the substrate 110 and the second planarization layer 275 in the first sub-region 21, without overlapping with the first sub-pixel 201 disposed in the second sub-region 22.

[0164] The connection electrode 614 can be disposed on the first pixel circuit PC21 in the first sub-region 21. The connection electrode 614 can be connected to the drain electrode 230c through a contact hole 714 formed in the first planarization layer 270. In other words, the connection electrode 614 can be disposed on the first planarization layer 270 in the second sub-region 22 and the first sub-region 21, and the connection electrode 614 can extend on the first planarization layer 270 in the first direction D1 and the second direction D2.

[0165] The first sub-pixel 201 can be disposed on the first circuit structure 800. The first sub-pixel 201 can be electrically connected to the first pixel circuit PC21 disposed in the first sub-region 21 via the connecting electrode 614. In other words, the lower electrode 290c can be connected to the connecting electrode 614 via a contact hole formed in the second planarization layer 275. In an embodiment, the lower electrode 290c can have a second width a2, and the contact hole 714 formed in the first planarization layer 270 can be non-overlapping with the lower electrode 290c.

[0166] Active layers 130a, 135a, 130b, 135b, 130c, 135c, 730, and 735 may be disposed on substrate 110. Each of active layers 130a, 135a, 130b, 135b, 130c, 135c, 730, and 735 may include metal-oxide-semiconductor, amorphous silicon, polycrystalline silicon, organic semiconductor, etc.

[0167] A gate insulating layer 150 may be disposed on active layers 130a, 135a, 130b, 135b, 130c, 135c, 730, and 735. The gate insulating layer 150 may include silicon compounds, metal oxides, etc. For example, the gate insulating layer 150 may include silicon oxide (SiO₂). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), silicon carbonitride (SiC) x N y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x ), tantalum oxide (TaO) x ), hafnium oxide (HfO) x Zirconium oxide (ZrO) x Titanium oxide (TiO) x In some embodiments, the gate insulating layer 150 may have a multilayer structure comprising multiple insulating layers formed of mutually different materials.

[0168] Gate electrodes 170a, 175a, 170b, 175b, 170c, 175c, 770, and 775 may be disposed on the gate insulating layer 150. Each of the gate electrodes 170a, 175a, 170b, 175b, 170c, 175c, 770, and 775 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, each of the gate electrodes 170a, 175a, 170b, 175b, 170c, 175c, 770, and 775 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum-containing alloys, and aluminum nitride (AlN). x ), silver alloys, tungsten nitride (WN) x Copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiN) x ), Chromium nitride (CrN) x ), Tantalum nitride (TaN) x ), SrRuO x O y ), zinc oxide (ZnO) x Indium tin oxide (ITO), tin oxide (SnO) x Indium oxide (InO) x Gallium oxide (GaO) x Indium zinc oxide (IZO), etc. These can be used individually or in combination with each other. In some embodiments, each of the gate electrodes 170a, 175a, 170b, 175b, 170c, 175c, 770 and 775 can have a multilayer structure comprising multiple metal layers.

[0169] Interlayer insulating layer 190 may be disposed on gate electrodes 170a, 175a, 170b, 175b, 170c, 175c, 770, and 775. Interlayer insulating layer 190 may include silicon compounds, metal oxides, etc. In some embodiments, interlayer insulating layer 190 may have a multilayer structure comprising multiple insulating layers formed of mutually different materials.

[0170] Source electrodes 210a, 215a, 210b, 215b, 210c, 215c, 810, and 815, and drain electrodes 230a, 235a, 230b, 235b, 230c, 235c, 830, and 835 may be disposed on interlayer insulating layer 190. Each of the source electrodes 210a, 215a, 210b, 215b, 210c, 215c, 810, and 815, and the drain electrodes 230a, 235a, 230b, 235b, 230c, 235c, 830, and 835 may include metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In some embodiments, each of the source electrodes 210a, 215a, 210b, 215b, 210c, 215c, 810 and 815 and the drain electrodes 230a, 235a, 230b, 235b, 230c, 235c, 830 and 835 may have a multilayer structure comprising multiple metal layers.

[0171] The first planarization layer 270 may be disposed on the source electrodes 210a, 215a, 210b, 215b, 210c, 215c, 810, and 815, and the drain electrodes 230a, 235a, 230b, 235b, 230c, 235c, 830, and 835. The first planarization layer 270 may include an organic insulating material. For example, the first planarization layer 270 may include a photoresist, a polyacrylamide resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylamide resin, an epoxy resin, etc.

[0172] The second planarization layer 275 may be disposed on the first planarization layer 270. The second planarization layer 275 may include an organic insulating material.

[0173] The pixel defining layer 310 may be disposed on the second planarization layer 275. The pixel defining layer 310 may include an organic insulating material.

[0174] Figure 11 and Figure 12 It is shown Figure 5 and Figure 6 A plan view of an example of the connecting electrodes shown.

[0175] Reference Figure 11 and Figure 12 The connecting electrode 614 can extend in the second direction D2 in the first row and first column 20a of the first sub-region 21, and the contact hole 714 can be located at the upper end of the first row and first column 20a. In addition, the connecting electrode 613 can extend in the second direction D2 in the first row and fifth column of the first sub-region 21, and the contact hole 713 can be located at the upper end of the first row and fifth column.

[0176] The connecting electrode 624 can extend in the second direction D2 in the second row and third column 20c of the first sub-region 21, and the contact hole 724 can be located at the upper end of the second row and third column 20c. In addition, the connecting electrode 623 can extend in the second direction D2 in the second row and seventh column of the first sub-region 21, and the contact hole 723 can be located at the upper end of the second row and seventh column.

[0177] The connecting electrode 634 can extend in the second direction D2 in the third row and first column 20a of the first sub-region 21, and the contact hole 734 can be located at the upper end of the third row and first column 20a. In addition, the connecting electrode 633 can extend in the second direction D2 in the third row and fifth column of the first sub-region 21, and the contact hole 733 can be located at the upper end of the third row and fifth column.

[0178] The connecting electrode 644 can extend in the second direction D2 in the fourth row and third column 20c of the first sub-region 21, and the contact hole 744 can be located at the upper end of the fourth row and third column 20c. In addition, the connecting electrode 643 can extend in the second direction D2 in the fourth row and seventh column of the first sub-region 21, and the contact hole 743 can be located at the upper end of the fourth row and seventh column.

[0179] In this way, each of the connecting electrodes 813, 814, 823, 824, 833, 834, 843 and 844 provided in the first to fourth rows of the second display area 30 can extend in the second direction D2, and the contact holes 913, 914, 923, 924, 933, 934, 943 and 944 can be located at the upper end.

[0180] Figure 13 and Figure 14 It is shown Figure 5 and Figure 6 A plan view of another example of the connecting electrodes shown.

[0181] Reference Figure 13 and Figure 14 The connecting electrode 611 can extend to the first row and fourth column 20d of the first sub-region 21, and can extend from the first row and fourth column 20d in the second direction D2, so that the contact hole 711 can be located at the upper end of the first row and fourth column 20d. Additionally, the connecting electrode 612 can extend to the first row and eighth column of the first sub-region 21, and can extend from the first row and eighth column in the second direction D2, so that the contact hole 712 can be located at the upper end of the first row and eighth column.

[0182] The connecting electrode 621 can extend to the second row and second column 20b of the first sub-region 21, and can extend from the second row and second column 20b in the second direction D2, such that the contact hole 721 can be located at the upper end of the second row and second column 20b. Additionally, the connecting electrode 622 can extend to the second row and sixth column of the first sub-region 21, and can extend from the second row and sixth column in the second direction D2, such that the contact hole 722 can be located at the upper end of the second row and sixth column.

[0183] The connecting electrode 631 can extend to the third row and fourth column 20d of the first sub-region 21, and can extend from the third row and fourth column 20d in the second direction D2, so that the contact hole 731 can be located at the upper end of the third row and fourth column 20d. Additionally, the connecting electrode 632 can extend to the third row and eighth column of the first sub-region 21, and can extend from the third row and eighth column in the second direction D2, so that the contact hole 732 can be located at the upper end of the third row and eighth column.

[0184] The connecting electrode 641 can extend to the fourth row and second column 20b of the first sub-region 21, and can extend from the fourth row and second column 20b in the second direction D2, such that the contact hole 741 can be located at the upper end of the fourth row and second column 20b. Additionally, the connecting electrode 642 can extend to the fourth row and sixth column of the first sub-region 21, and can extend from the fourth row and sixth column in the second direction D2, such that the contact hole 742 can be located at the upper end of the fourth row and sixth column.

[0185] In this way, each of the connecting electrodes 811, 812, 821, 822, 831, 832, 841 and 842 provided in the first to fourth rows of the second display area 30 can extend in the direction opposite to the first direction D1 and in the second direction D2, and the contact holes 911, 912, 921, 922, 931, 932, 941 and 942 can be located at the upper end.

[0186] Figure 15 and Figure 16 It is shown Figure 1 A plan view of an example arrangement of subpixels included in a display device.

[0187] Reference Figure 15 and Figure 16 The first to third sub-pixels R, B, and G can be arranged such that the red / green-blue / green (RG-BG) sub-pixels are repeated in the first direction D1. For example, when with Figure 5 and Figure 6 One When comparing structures, Figure 15 and Figure 16 One The structure can be symmetrical in the second direction D2. In other embodiments, one The structure can be realized as a symmetrical structure in the first direction D1.

[0188] Figure 17 and Figure 18 This is a plan view showing a display device according to an embodiment. Figure 17 and Figure 18 The display device 1000 shown may have the same characteristics as the reference. Figures 1 to 6 The described display device 100 has a substantially the same or similar construction. Figure 17 and Figure 18 For the sake of brevity, omissions and references are omitted. Figures 1 to 6 Redundant descriptions of components that are substantially the same or similar. For example, Figure 17 It can correspond to the example shown Figure 1 A magnified plan view of a portion of region A. Figure 18 It can correspond to the example shown Figure 1 A magnified plan view of region B.

[0189] Reference Figure 17 and Figure 18 ,and Figure 5 and Figure 6 Compared to the display device 100 shown, the display device 1000 can be configured such that the position of the third sub-pixel 203 disposed in the first display area 20 and the second display area 30 is different.

[0190] For example, the third sub-pixels 203 set in the second and fourth rows in the first display area 20 can be relatively shifted in the direction opposite to the first direction D1 (e.g., the direction from the second display area 30 to the first display area 20), and the third sub-pixels 203 set in the second and fourth rows in the second display area 30 can be relatively shifted in that direction.

[0191] Because the first to third sub-pixels 101, 102 and 103 set in the display area 10 and the first to third sub-pixels 201, 202 and 203 set in the first display area 20 and the second display area 30 are The layout of the display device 1000 necessitates consideration of the roughness index (R-index). A high R-index can lead to image quality defects such as spots and streaks. Specifically, since green subpixels have a significant impact on the R-index, the spacing between the third subpixel 103 and the third subpixel 203, which have the greatest influence on the R-index, must be substantially the same or similar at the first boundary between the display area 10 and the first sub-region 21, and at the second boundary between the display area 10 and the third sub-region 31.

[0192] In an embodiment, such as Figure 17 As shown, the first sub-pixel column, including the third sub-pixel 203 (e.g., the third sub-pixel 203 located at the boundary between the first column 20a and the fourth column 20d), can be located in the first sub-region 21 adjacent to the first boundary. Figure 18 As shown, the second sub-pixel column, including the third sub-pixel 203 (e.g., the third sub-pixel 203 located at the boundary between the third column 30c and the fourth column 30d), can be located in the third sub-region 31 adjacent to the second boundary. The distance g1 of the first sub-pixel column from the second column 10b of the display area 10 can be substantially equal to the distance g2 of the second sub-pixel column from the fourth column 10d of the display area 10.

[0193] Furthermore, the third sub-pixel column in the first sub-region 21, which includes the second sub-pixel 202 and the first sub-pixel 201 (e.g., the second sub-pixel 202 and the first sub-pixel 201 disposed in the third column 20c), may be spaced apart from the first sub-pixel column in the direction from the display area 10 to the first display area 20. The fourth sub-pixel column in the first sub-region 21, which includes the third sub-pixel 203 (e.g., the third sub-pixel 203 disposed at the boundary between the fifth and eighth columns), may be spaced apart from the third sub-pixel column in this direction. The fifth sub-pixel column in the first sub-region 21, which includes the first sub-pixel 201 and the second sub-pixel 202 (e.g., the first sub-pixel 201 and the second sub-pixel 202 disposed in the seventh column), may be spaced apart from the fourth sub-pixel column in this direction.

[0194] Furthermore, the separation distance between the first sub-pixel column and the third sub-pixel column in this direction can be smaller than the separation distance between the third sub-pixel column and the fourth sub-pixel column in this direction.

[0195] Similarly, a sixth sub-pixel column in the third sub-region 31, comprising a first sub-pixel 201 and a second sub-pixel 202 (e.g., the first and second sub-pixels 201 and 202 disposed in the first column 30a), can be disposed between the fourth column 10d of the display area 10 and the second sub-pixel column. A seventh sub-pixel column in the third sub-region 31, comprising a second sub-pixel 202 and a first sub-pixel 201 (e.g., the second and first sub-pixels 202 and 201 disposed in the fifth column), can be spaced apart from the second sub-pixel column in the direction from the display area 10 to the third sub-region 31. An eighth sub-pixel column in the third sub-region 31, comprising a third sub-pixel 203 (e.g., the third sub-pixel 203 disposed at the boundary between the seventh and eighth columns), can be spaced apart from the seventh sub-pixel column in this direction. The separation distance between the second and sixth sub-pixel columns in this direction can be smaller than the separation distance between the second and seventh sub-pixel columns in this direction.

[0196] According to the embodiment described herein, in the display device 1000, the distance g1 from the first sub-pixel column to the second column 10b of the display area 10 is substantially equal to the distance g2 from the second sub-pixel column to the fourth column 10d of the display area 10, such that the value of the R exponent can be relatively reduced and the image quality of the display device 1000 can be relatively improved.

[0197] Figure 19 and Figure 20 This is a plan view showing a display device according to an embodiment. Figure 19 and Figure 20 The display device 1100 shown may have the same characteristics as the reference. Figures 1 to 6 The described display device 100 has a substantially the same or similar construction. Figure 19 and Figure 20 For the sake of brevity, omissions and references are omitted. Figures 1 to 6 Redundant descriptions of components that are substantially the same or similar. For example, Figure 19 It can correspond to the example shown Figure 1 A magnified plan view of a portion of region A. Figure 20 It can correspond to the example shown Figure 1 A magnified plan view of region B.

[0198] Reference Figure 19 and Figure 20 When with Figure 5 and Figure 6 Compared to the display device 100 shown, the display device 1100 can be configured such that the subpixel arrangement of the first subpixel 101 and the second subpixel 102 disposed in the first column 10a of the display area 10 is applied to the second column 30b of the third sub-region 31. In other words, the arrangement of subpixels in the first column (e.g., the first column 10a) and the last column (the second column 30b) of the display area 10 can be the same. Furthermore, the arrangement of the first to third subpixels 201, 202, and 203 disposed in the first display area 20 can be symmetrical to the arrangement of the first to third subpixels 201, 202, and 203 disposed in the second display area 30.

[0199] In this configuration, the second column 30b of the third sub-region 31 can also be included in the display area 10, and the boundary between the second column 30b and the first column 30a of the third sub-region 31 can be defined as the second boundary between the display area 10 and the third sub-region 31. Furthermore, the fourth column 10d of the display area 10 can be defined as the third column of the display area 10, and the second column 30b of the third sub-region 31 can be defined as the fourth column of the display area 10. Additionally, the fourth column 30d of the third sub-region 31 can be defined as the first column of the third sub-region 31, and the first column 30a of the third sub-region 31 can be defined as the second column of the third sub-region 31.

[0200] The interval between the second column 10b of the display area 10, in which the third sub-pixel 103 is disposed, and the first column 20a of the first sub-region 21, in which the third sub-pixel 203 is disposed, can become equal to the interval between the fourth column 10d of the display area 10, in which the third sub-pixel 103 is disposed (i.e., the newly defined third column of the display area 10) and the fourth column 30d of the third sub-region 31, in which the third sub-pixel 203 is disposed (e.g., the newly defined first column of the third sub-region 31).

[0201] Alternatively, the first to third sub-pixels 201, 202 and 203 may not be set in the second column 20b of the first sub-region 21 and the first column 30a of the third sub-region 31 (e.g., a newly defined second column).

[0202] According to the display device 1100 of the embodiment described herein, when the arrangement of sub-pixels in the first and last columns of the display area 10 is identical, and the arrangement of sub-pixels in the first display area 20 is symmetrical to the arrangement of sub-pixels in the second display area 30, the value of the R-index can be relatively reduced, and the image quality of the display device 1100 can be relatively improved. Furthermore, no defects occur in the process of forming the light-emitting layer of each of the first to third sub-pixels 201, 202, and 203 adjacent to the first and second boundaries.

[0203] Figure 21 It is shown Figure 19 and Figure 20 A plan view of an example arrangement of subpixels included in a display device.

[0204] Reference Figure 21 When set with Figure 19 and Figure 20 Compared to the sub-pixel arrangement in the second column 30b of the third sub-region 31 of the display device 1100, Figure 21The diagram illustrates a configuration in which a first sub-pixel 201 can be located in the first row and second column 30b of the third sub-region 31, and a second sub-pixel 202 can be located in the fourth row and second column 30b of the third sub-region 31. In other words, the sub-pixel may not be located in the second column 30b in either the second or third row. In other embodiments, the sub-pixel may be located in the second column 30b in only at least one of the first to fourth rows.

[0205] The embodiments described herein can be applied to various electronic devices that include display devices. For example, the embodiments described herein can be applied to many electronic devices, such as vehicle display devices, ship display devices, aircraft display devices, portable communication devices, exhibition display devices, information transmission display devices, medical display devices, etc.

[0206] The foregoing is a description of the embodiments and should not be construed as limiting them.

[0207] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising a display area, a first display area, and a second display area, wherein the first display area is located on one side of the display area and includes a first sub-area and a second sub-area, and the second display area is located on the opposite side of the display area and includes a third sub-area and a fourth sub-area, the display device comprising: Base; as well as Multiple first sub-pixels, multiple second sub-pixels, and multiple third sub-pixels are disposed on the substrate in the display area, the first display area, and the second display area. The plurality of first sub-pixels and the plurality of second sub-pixels are repeatedly arranged in a first column of the display area adjacent to a first boundary between the display area and the first sub-region, and the plurality of third sub-pixels are repeatedly arranged in a second column of the display area. The plurality of second sub-pixels and the plurality of first sub-pixels are repeatedly arranged in a third column adjacent to the second boundary between the display area and the third sub-region of the display area, and the plurality of third sub-pixels are repeatedly arranged in a fourth column of the display area. The plurality of third sub-pixels are repeatedly arranged in a first column of the first sub-region adjacent to the first boundary, and a second column of the first sub-region is located between the first boundary and the first column of the first sub-region. The plurality of first sub-pixels and the plurality of second sub-pixels are repeatedly arranged in a first column of the third sub-region adjacent to the second boundary, and the second column of the third sub-region is located between the second boundary and the first column of the third sub-region. The plurality of first sub-pixels to the plurality of third sub-pixels are not set in the second column of the first sub-region and the second column of the third sub-region.

2. The display device according to claim 1, wherein, The third column of the first sub-region is adjacent to the first column of the first sub-region, and the fourth column of the first sub-region is located between the first column and the third column of the first sub-region. The plurality of second sub-pixels and the plurality of first sub-pixels are repeatedly arranged in the third column of the first sub-region.

3. The display device according to claim 2, wherein, The plurality of first sub-pixels to the plurality of third sub-pixels are not set in the fourth column of the first sub-region.

4. The display device according to claim 1, wherein, The plurality of first sub-pixels to the plurality of third sub-pixels are arranged in a zigzag shape in the first and second columns of the display area in the order of first sub-pixel, third sub-pixel, second sub-pixel and third sub-pixel.

5. The display device according to claim 1, wherein, The third column of the third sub-region is adjacent to the first column of the third sub-region, and the fourth column of the third sub-region is located between the first column and the third column of the third sub-region. The plurality of third sub-pixels are repeatedly arranged in the third column of the third sub-region.

6. The display device according to claim 5, wherein, The plurality of first sub-pixels to the plurality of third sub-pixels are not set in the fourth column of the third sub-region.

7. The display device according to claim 1, wherein, The plurality of first sub-pixels to the plurality of third sub-pixels are arranged in a zigzag shape in the third and fourth columns of the display area in the order of the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel.

8. The display device according to claim 1, further comprising: A first circuit structure is disposed on the substrate in the second sub-region.

9. The display device according to claim 8, further comprising: A plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits are connected to the plurality of first sub-pixels to the plurality of third sub-pixels disposed in the display area, the first display area, and the second display area, wherein the plurality of first pixel circuits, the plurality of second pixel circuits, and the plurality of third pixel circuits are respectively connected to the plurality of first sub-pixels to the plurality of third sub-pixels. The plurality of first pixel circuits to the plurality of third pixel circuits, which are respectively connected to the plurality of first sub-pixels to the plurality of third sub-pixels disposed in the second sub-region, are disposed in the first sub-region.

10. The display device according to claim 1, further comprising: A second circuit structure is disposed on the substrate in the fourth sub-region.

11. The display device according to claim 10, further comprising: A plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits are connected to the plurality of first sub-pixels to the plurality of third sub-pixels disposed in the display area, the first display area, and the second display area, wherein the plurality of first pixel circuits, the plurality of second pixel circuits, and the plurality of third pixel circuits are respectively connected to the plurality of first sub-pixels to the plurality of third sub-pixels. The plurality of first pixel circuits to the plurality of third pixel circuits, which are respectively connected to the plurality of first sub-pixels to the plurality of third sub-pixels disposed in the fourth sub-region, are disposed in the third sub-region.

12. The display device according to claim 1, wherein, The number of the plurality of first sub-pixels and the plurality of second sub-pixels arranged in the first column of the display area is equal to the number of the plurality of third sub-pixels arranged in the second column of the display area, and The number of the plurality of third sub-pixels arranged in the first column of the first sub-region is less than the number of the plurality of first sub-pixels and the plurality of second sub-pixels arranged in the first column of the display area.

13. The display device according to claim 12, wherein, The number of the plurality of third sub-pixels arranged in the first column of the first sub-region is half the number of the plurality of first sub-pixels and the plurality of second sub-pixels arranged in the first column of the display area.

14. The display device according to claim 1, wherein, The first display area and the second display area are parallel to each other and face each other. The second and third columns of the display area are located between the first and fourth columns of the display area, the second column of the first sub-region is located between the first column of the display area and the first column of the first sub-region, and the second column of the third sub-region is located between the fourth column of the display area and the first column of the third sub-region. The sizes of the plurality of first sub-pixels to the plurality of third sub-pixels disposed in the first display area and the second display area are respectively larger than the sizes of the plurality of first sub-pixels to the plurality of third sub-pixels disposed in the display area.

15. A display device, the display device comprising a display area, a first display area, and a second display area, the first display area being located on one side of the display area and including a first sub-area and a second sub-area, the second display area being located on the opposite side of the display area and including a third sub-area and a fourth sub-area, the display device comprising: Base; as well as Multiple first sub-pixels, multiple second sub-pixels, and multiple third sub-pixels are disposed on the substrate in the display area, the first display area, and the second display area. The plurality of first sub-pixels and the plurality of second sub-pixels are repeatedly arranged in a first column of the display area adjacent to a first boundary between the display area and the first sub-region, and the plurality of third sub-pixels are repeatedly arranged in a second column of the display area. The plurality of second sub-pixels and the plurality of first sub-pixels are repeatedly arranged in a third column adjacent to the second boundary between the display area and the third sub-region of the display area, and the plurality of third sub-pixels are repeatedly arranged in a fourth column of the display area. A first sub-pixel column, including the plurality of third sub-pixels, is disposed in the first sub-region adjacent to the first boundary. A second sub-pixel column, including the plurality of third sub-pixels, is disposed in the third sub-region adjacent to the second boundary, and The distance between the first sub-pixel column and the second column of the display area is equal to the distance between the second sub-pixel column and the fourth column of the display area.

16. The display device according to claim 15, further comprising: The third sub-pixel column is spaced apart from the first sub-pixel column in the first sub-region in the direction from the display area to the first display area, and includes the plurality of second sub-pixels and the plurality of first sub-pixels; A fourth sub-pixel column, spaced apart from the third sub-pixel column in the direction within the first sub-region, and including the plurality of third sub-pixels; as well as The fifth sub-pixel column is spaced apart from the fourth sub-pixel column in the first sub-region in the direction therein, and includes the plurality of first sub-pixels and the plurality of second sub-pixels.

17. The display device according to claim 16, wherein, The separation distance between the first sub-pixel column and the third sub-pixel column in the direction is less than the separation distance between the third sub-pixel column and the fourth sub-pixel column in the direction.

18. The display device according to claim 15, further comprising: The sixth sub-pixel column is disposed in the third sub-region between the fourth column and the second sub-pixel column in the display area, and includes the plurality of first sub-pixels and the plurality of second sub-pixels; The seventh sub-pixel column is spaced apart from the second sub-pixel column in the third sub-region in the direction from the display area to the third sub-region, and includes the plurality of second sub-pixels and the plurality of first sub-pixels; as well as The eighth sub-pixel column is spaced apart from the seventh sub-pixel column in the direction in the third sub-region and includes the plurality of third sub-pixels.

19. The display device according to claim 18, wherein, The separation distance between the second sub-pixel column and the sixth sub-pixel column in the direction is less than the separation distance between the second sub-pixel column and the seventh sub-pixel column in the direction.

20. A display device, the display device comprising a display area, a first display area, and a second display area, the first display area being located on one side of the display area and including a first sub-area and a second sub-area, the second display area being located on the opposite side of the display area and including a third sub-area and a fourth sub-area, the display device comprising: Base; as well as Multiple first sub-pixels, multiple second sub-pixels, and multiple third sub-pixels are disposed on the substrate in the display area, the first display area, and the second display area. The plurality of first sub-pixels and the plurality of second sub-pixels are repeatedly arranged in a first column of the display area adjacent to a first boundary between the display area and the first sub-region, and the plurality of third sub-pixels are repeatedly arranged in a second column of the display area. The plurality of third sub-pixels are repeatedly arranged in a third column adjacent to the second boundary between the display area and the third sub-region, and the plurality of first sub-pixels and the plurality of second sub-pixels are repeatedly arranged in a fourth column of the display area. The plurality of third sub-pixels are repeatedly arranged in a first column of the first sub-region adjacent to the first boundary, and a second column of the first sub-region is located between the first boundary and the first column of the first sub-region. The plurality of third sub-pixels are repeatedly arranged in a first column of the third sub-region adjacent to the second boundary, and the second column of the third sub-region is located between the second boundary and the first column of the third sub-region. The plurality of first sub-pixels to the plurality of third sub-pixels are not set in the second column of the first sub-region and the second column of the third sub-region.

Images