semiconductor devices

Abstract

An embodiment relates to a semiconductor device comprising a plurality of IGBT regions and a plurality of diode regions alternately arranged along a first direction, and comprising first to third electrodes and a semiconductor portion. The semiconductor portion comprises a collector layer of a first conductivity type, low-concentration and high-concentration cathode layers of a second conductivity type, a drift layer of a second conductivity type, an anode layer and a base layer of a first conductivity type, and an emitter layer of a second conductivity type. The low-concentration cathode layer and the high-concentration cathode layer are in contact with the first electrode. When the diode region on the lower surface of the semiconductor portion is divided into three equal parts along the first direction, namely, a first peripheral region, a central region, and a second peripheral region, the area ratio of the low-concentration cathode layer in the central region is higher than the area ratios of the low-concentration cathode layer in the first and second peripheral regions.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-43773 (filing date: March 17, 2021), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device. Background Art

[0003] In recent years, demand for power devices with low switching losses has increased in industrial equipment and automobiles. For example, RC-IGBTs (reverse conducting IGBTs), which combine an IGBT (insulated gate bipolar transistor) and an FRD (fast recovery diode) on a single chip, are being used. Even RC-IGBTs are being required to further reduce switching losses. Furthermore, RC-IGBTs are also required to have stable operation. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor device capable of achieving low loss and stable operation.

[0005] A semiconductor device according to an embodiment is a semiconductor device in which multiple IGBT regions and multiple diode regions are arranged alternately along a first direction. The semiconductor device comprises first to third electrodes, a semiconductor portion, and an insulating film. The semiconductor portion comprises a collector layer, a low-concentration cathode layer, a high-concentration cathode layer, a drift layer, an anode layer, a base layer, and an emitter layer. The semiconductor portion comprises a collector layer of the first conductivity type disposed on the first electrode, a low-concentration cathode layer of the second conductivity type, a high-concentration cathode layer of the second conductivity type, a drift layer of the second conductivity type, an anode layer of the first conductivity type, a base layer of the first conductivity type, and an emitter layer of the second conductivity type. The collector layer is disposed in the IGBT region and is in contact with the first electrode. The low-concentration cathode layer and the high-concentration cathode layer are disposed in the diode region and are in contact with the first electrode. The impurity concentration of the high-concentration cathode layer is higher than that of the low-concentration cathode layer. The drift layer is disposed on the collector layer, the low-concentration cathode layer, and the high-concentration cathode layer. Multiple anode layers are disposed locally on the drift layer in the diode region. A plurality of base layers are locally provided on the drift layer in the IGBT region. The emitter layer is provided on the base layer in the IGBT region. When the diode region in the lower surface of the semiconductor portion is divided into three equal parts along the first direction: a first peripheral region, a central region, and a second peripheral region, the area ratio of the low-concentration cathode layer in the central region is higher than the area ratio of the low-concentration cathode layer in the first peripheral region and the second peripheral region. The second electrode is provided on the semiconductor portion in the IGBT region and the diode region, and is connected to the anode layer and the emitter layer. The third electrode is provided in the IGBT region, and is opposite to the emitter layer, the base layer, and the drift layer. The insulating film is provided between the semiconductor portion and the third electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.

[0007] Figure 2 It is a bottom view showing the semiconductor device according to the first embodiment.

[0008] Figure 3 Yes Figure 1 An enlarged top view of area A.

[0009] Figure 4 (a) in the Figure 3 The partial cross-sectional view of the CC' line shown, Figure 4 (b) in the Figure 3 A partial cross-sectional view along line DD' is shown.

[0010] Figure 5 Yes Figure 2 An enlarged bottom view of area B.

[0011] Figure 6 yes Figure 5 An enlarged cross-sectional view along line EE' is shown.

[0012] Figure 7 This is an enlarged bottom view showing the cathode layer in the first modification example of the first embodiment.

[0013] Figure 8 This is an enlarged bottom view showing the cathode layer in the second modification of the first embodiment.

[0014] Figure 9 It is an enlarged bottom view showing the cathode layer in the third modification of the first embodiment.

[0015] Figure 10 It is an enlarged bottom view showing the cathode layer in the second embodiment.

[0016] Figure 11 It is an enlarged bottom view showing an arrangement pattern of a cathode layer in a modification of the second embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, each embodiment will be described with reference to the drawings.

[0018] The drawings are schematic diagrams, and the relationship between the thickness and width of each part, the size ratios between parts, and other aspects do not necessarily correspond to actual parts. Furthermore, even when depicting identical parts, their dimensions and ratios may differ depending on the drawing. Furthermore, in this specification and the drawings, elements identical to those described in previously mentioned drawings are denoted by the same reference numerals, and detailed descriptions are omitted where appropriate.

[0019] (First embodiment)

[0020] Figure 1 It is a top view showing the semiconductor device according to this embodiment. Figure 2 It is a bottom view showing the semiconductor device according to this embodiment. Figure 3 Yes Figure 1 An enlarged top view of area A. Figure 4 (a) in the Figure 3 The partial cross-sectional view of the CC' line shown, Figure 4 (b) in the Figure 3 A partial cross-sectional view along line DD' is shown. Figure 5 Yes Figure 2 An enlarged bottom view of area B. Figure 6yes Figure 5 An enlarged cross-sectional view along line EE' is shown.

[0021] exist Figure 1 and Figure 4 In (a) and (b), the protective film and wiring layer are omitted. Figure 3 In FIG, the second electrode 22 and the insulating film 32 described later are omitted. Figure 5 In the figure, the first electrode 21 described later is omitted. From the viewpoint of visibility, in the drawing, a portion showing the surface of the high-concentration cathode layer 18 described later is dotted.

[0022] like Figure 1 、 Figure 4 As shown in (a) and (b) of FIG. 1 , the semiconductor device 101 according to this embodiment is an RC-IGBT in which multiple IGBT regions R1 and multiple diode regions R2 are alternately arranged. In the semiconductor device 101 , multiple IGBT regions R1 are provided, and diode regions R2 are provided between adjacent IGBT regions R1.

[0023] like Figure 1 、 Figure 2 As shown, the IGBT region R1 and the diode region R2 extend in one direction, and the length of the IGBT region R1 in a direction perpendicular to the one direction, that is, the width, is greater than the width of the diode region R2.

[0024] like Figure 1 As shown, the second electrode 22 and the gate pad 23 p are provided on the upper surface of the semiconductor device 101. A termination insulating film 70 is provided at the edge of the upper surface of the semiconductor device 101.

[0025] The second electrode 22 is, for example, an emitter electrode in the IGBT region R1 , and is, for example, an anode electrode in the diode region R2 .

[0026] like Figure 2 As shown, the semiconductor device 101 is provided with a first electrode 21 on the bottom surface. The first electrode 21 is provided on substantially the entire lower surface of the semiconductor device 101. The first electrode 21 is, for example, a collector electrode in the IGBT region R1 and a cathode electrode in the diode region R2.

[0027] Here, for the sake of convenience, in this specification, Figure 1 As shown, the direction in which IGBT region R1 and diode region R2 are arranged is referred to as "direction X," the direction perpendicular to direction X in which IGBT region R1 and diode region R2 extend is referred to as "direction Y," and the direction perpendicular to directions X and Y is referred to as "direction Z." The length in direction X is also referred to as "width."

[0028] The direction from the first electrode 21 toward the second electrode 22 is referred to as "upper," and the opposite direction is referred to as "lower." This is for convenience and has nothing to do with the direction of gravity. The upper direction is the Z direction.

[0029] like Figure 3 and Figure 4 As shown in (a) and (b), the semiconductor device 101 has a semiconductor portion 10, a third electrode 23, a gate insulating film 31 and an insulating film 32 in addition to the above-mentioned first electrode 21, second electrode 22, gate pad 23p and terminal insulating film 70.

[0030] like Figure 4 As shown in (a) and (b) of FIG. 1 , the semiconductor portion 10 is provided above the first electrode 21 and below the second electrode 22. The semiconductor portion 10 is generally rectangular in shape and has an upper surface, side surfaces, and a lower surface 10A. The semiconductor portion 10 includes a collector layer 11, a buffer layer 12, a drift layer 13, a p-type layer 14, an emitter layer 15, a cathode layer 16, a base contact 61, and an anode contact 62.

[0031] like Figure 4 As shown in (a) and (b) in FIG1 , the collector layer 11 is provided below the semiconductor portion 10 in the IGBT region R1. The lower surface of the collector layer 11 constitutes the lower surface 10A of the semiconductor portion 10 in the IGBT region R1 and is in contact with the first electrode 21. The collector layer 11 is a semiconductor of the first conductivity type, for example, a p-type semiconductor. The impurity concentration of the collector layer 11 is, for example, 1×10 17 cm -3 More than and less than 1×10 20 cm -3 .

[0032] like Figure 4 (a), (b) and Figure 5 As shown, the cathode layer 16 is provided in the lower portion of the semiconductor portion 10 in the diode region R2. The lower surface of the cathode layer 16 constitutes the lower surface 10A of the semiconductor portion 10 in the diode region R2 and is in contact with the first electrode 21. The cathode layer 16 is a semiconductor of the second conductivity type, for example, an n-type semiconductor. Figure 5 As shown, the cathode layer 16 includes a plurality of low-concentration cathode layers 17 and a plurality of high-concentration cathode layers 18. As will be described later, the concentration of impurities serving as donors in the high-concentration cathode layers 18 is higher than that in the low-concentration cathode layers 17.

[0033] like Figure 4As shown in (a) and (b), the buffer layer 12 is provided on the collector layer 11 and the cathode layer 16, and is in contact with the collector layer 11 and the cathode layer. The buffer layer 12 is a semiconductor of the second conductivity type, for example, an n-type semiconductor. The impurity concentration of the buffer layer 12 is, for example, lower than the impurity concentration of the cathode layer 16. The impurity concentration of the buffer layer 12 is, for example, 1×10 16 cm -3 More than and less than 1×10 17 cm -3 .

[0034] like Figure 4 As shown in (a) and (b) of FIG5 , the drift layer 13 is provided on the buffer layer 12. The upper portion of the drift layer 13 faces the lower portions of the plurality of third electrodes 23 via the gate insulating film 31. The drift layer 13 is a semiconductor of the second conductivity type, for example, an n-type semiconductor. The impurity concentration of the drift layer 13 is lower than that of the buffer layer 12.

[0035] The third electrode 23 is, for example, a gate electrode. Figure 3 and Figure 4 As shown in (a) and (b) of FIG. 1 , the third electrodes 23 are provided in trenches formed in the upper portion of the semiconductor portion 10 in the IGBT region R1 and the diode region R2. A plurality of third electrodes 23 extend along the direction Y and are arranged at approximately equal intervals along the direction X. The third electrodes 23 are covered with a gate insulating film 31 except for their upper surfaces.

[0036] like Figure 4 As shown in (a) and (b), the p-type layer 14 is provided between two adjacent third electrodes 23 on the drift layer 13. The p-type layer 14 includes a base layer 14i provided in the IGBT region R1 and an anode layer 14d provided in the diode region R2.

[0037] like Figure 4 As shown in (a) and (b) of FIG5 , the third electrode 23 in the IGBT region R1 faces the drift layer 13, the base layer 14i, the emitter layer 15, and the base contact 61 via the gate insulating film 31. The third electrode 23 in the diode region R2 faces the drift layer 13, the anode layer 14d, and the anode contact 62 via the gate insulating film 31.

[0038] like Figure 3 、 Figure 4 As shown in FIG. 5( b ), the anode layer 14 d is partially disposed on the upper portion of the semiconductor portion 10 . Specifically, it is disposed on the upper portion of the semiconductor portion 10 between adjacent anode contacts 62 and is in contact with the second electrode 22 .

[0039] The p-type layer 14 is a semiconductor of the first conductivity type, and is composed of, for example, a p-type semiconductor. The impurity concentration of the p-type layer 14 is, for example, 1×1017 cm -3 More than and less than 1×10 18 cm -3 .

[0040] like Figure 4 As shown in (b) in FIG. 1 , the emitter layer 15 is partially provided on the base layer 14i in the IGBT region R1. The emitter layer 15 is provided on the upper portion of the semiconductor portion 10 and is in contact with the second electrode 22. Figure 3 As shown, a plurality of emitter layers 15 are arranged extending along the direction X and arranged at substantially equal intervals along the direction Y. The emitter layer 15 is a semiconductor of the second conductivity type, for example, an n-type semiconductor. The impurity concentration of the emitter layer 15 is, for example, 1×10 20 cm -3 More than and less than 1×10 21 cm -3 .

[0041] like Figure 3 、 Figure 4 As shown in (a) of FIG. 1 , a plurality of base contacts 61 are provided on the base layer 14i, for example, between adjacent emitter layers 15. The base contacts 61 are provided on the upper portion of the semiconductor portion 10 and are in contact with the second electrode 22. The base contacts 61 are made of a first conductivity type semiconductor, for example, a p-type semiconductor.

[0042] like Figure 3 、 Figure 4 As shown in (a) in FIG. 1 , a plurality of anode contacts 62 are partially provided on the anode layer 14d. The anode contact 62 is provided on the upper portion of the semiconductor portion 10 and is in contact with the second electrode 22. Figure 3 As shown, the plurality of anode contacts 62 are arranged along the direction X at substantially equal intervals.

[0043] The anode contact 62 is a semiconductor of the first conductivity type, for example, a p-type semiconductor. The impurity concentration of the anode contact 62 and the base contact 61 is, for example, 1×10 19 cm -3 More than and less than 1×10 20 cm -3 .

[0044] In this manner, an IGBT is formed in IGBT region R1, with first electrode 21 serving as the collector, second electrode 22 serving as the emitter, and third electrode serving as the gate. Furthermore, a diode (FRD) is formed in diode region R2, with first electrode 21 serving as the cathode and second electrode 22 serving as the anode. Consequently, semiconductor device 101 functions as an RC-IGBT.

[0045] Hereinafter, the low-concentration cathode layer 17 and the high-concentration cathode layer 18 will be described in detail by taking one diode region R2 as an example.

[0046] like Figure 5 、 Figure 6 As shown, in one diode region R2 , a plurality of low-concentration cathode layers 17 and a plurality of high-concentration cathode layers 18 are alternately arranged along the direction X. For example, seven high-concentration cathode layers 18 are provided and arranged along the direction X. For example, six low-concentration cathode layers 17 are provided and arranged between adjacent high-concentration cathode layers 18 .

[0047] like Figure 5 As shown, the lengths of the six low-concentration cathode layers 17 in the direction Y are substantially the same as the lengths of the seven high-concentration cathode layers 18 in the direction Y.

[0048] like Figure 6 As shown, the low-concentration cathode layer 17 and the high-concentration cathode layer 18 are provided between the first electrode 21 and the buffer layer 12 .

[0049] The low-concentration cathode layer 17 and the high-concentration cathode layer 18 are made of a second conductivity type semiconductor, for example, an n-type semiconductor. The concentration of impurities serving as donors in the high-concentration cathode layer 18 is higher than that in the low-concentration cathode layer 17 .

[0050] The concentration of the impurity serving as a donor in the low-concentration cathode layer 17 is, for example, 1×10 16 cm -3 More than and less than 1×10 17 cm -3 The concentration of the impurity that serves as a donor in the high-concentration cathode layer 18 is, for example, 1×10 18 cm -3 More than and less than 1×10 20 cm -3 The impurity concentration of the low-concentration cathode layer 17 and the impurity concentration of the buffer layer 12 are, for example, substantially the same.

[0051] like Figure 5 、 Figure 6 As shown, here, the lower surface 10A of the semiconductor portion 10 in a diode region R2 provided between adjacent IGBT regions R1 is divided into three equal parts along the direction X. The divided regions are defined as a first peripheral region R21, a central region R23, and a second peripheral region R22. For ease of explanation, in the diode region R2, the central side in the direction X is referred to as the "central side," and the end sides in the direction X are referred to as the "end sides."

[0052] like Figure 5 、 Figure 6As shown, three high-concentration cathode layers 18 (hereinafter sometimes referred to as first high-concentration cathode layers 181 ) and two low-concentration cathode layers 17 (hereinafter sometimes referred to as first low-concentration cathode layers 171 ) are arranged in the first peripheral region R21 .

[0053] Three high-concentration cathode layers 18 (hereinafter sometimes referred to as second high-concentration cathode layers 182) and two low-concentration cathode layers 17 (hereinafter sometimes referred to as second low-concentration cathode layers 172) are arranged in the second peripheral region R22. The first high-concentration cathode layer 181 and the second high-concentration cathode layer 182 provided at the end are edge high-concentration cathode layers 18e and are in contact with the collector layer 11.

[0054] In the central region R23, one high-concentration cathode layer 18 (hereinafter sometimes referred to as the central high-concentration cathode layer 183) and two low-concentration cathode layers 17 (hereinafter sometimes referred to as the central low-concentration cathode layer 173) are arranged. Figure 5 、 Figure 6 As shown, the central high-concentration cathode layer 183 is arranged at the center of the diode region P2 in the direction X, and the two central low-concentration cathode layers 173 are arranged on the end sides of the central high-concentration cathode layer 183 .

[0055] like Figure 5 、 Figure 6 As shown, the widths of the two central low-concentration cathode layers 173 are, for example, substantially the same. The widths of the first low-concentration cathode layer 171 and the second low-concentration cathode layer 172 are, for example, substantially the same. The width of the central low-concentration cathode layer 173 is smaller than the width of the first low-concentration cathode layer 171 and smaller than the width of the second low-concentration cathode layer 172. The widths of the two first high-concentration cathode layers 181 on the end sides are, for example, substantially the same, and are, for example, larger than the width of the central first high-concentration cathode layer 181.

[0056] The widths of the two second high-concentration cathode layers 182 at the end sides are, for example, substantially the same, and are larger than the width of the second high-concentration cathode layer 182 at the center side. The width of the edge high-concentration cathode layer 18e is, for example, smaller than the width of the center high-concentration cathode layer 183. Thus, the width of the high-concentration cathode layer 18 decreases from the end sides toward the center side of the diode region R2.

[0057] The width of the two first high-concentration cathode layers 181 at the end and the width of the two second high-concentration cathode layers 182 at the end are, for example, 5 to 10 μm, which is approximately 2 to 3 times the length, i.e., the width, of the third electrode 23 in the direction X. The width of the central low-concentration cathode layer 173 is, for example, greater than the width of the edge high-concentration cathode layer 18e.

[0058] According to the relationship between the width of the low-concentration cathode layer 17 and the high-concentration cathode layer 18 and the length in the direction Y as described above, the area ratios occupied by the low-concentration cathode layer 17 and the high-concentration cathode layer 18 in the first peripheral region R21, the second peripheral region R22 and the central region R23 are respectively as described below.

[0059] like Figure 5 As shown, the area ratio of the low-concentration cathode layer 173 in the central region R23 is higher than the area ratio of the low-concentration cathode layer 171 in the first peripheral region R21, and higher than the area ratio of the low-concentration cathode layer 172 in the second peripheral region R22. The area ratio of the low-concentration cathode layer 171 in the first peripheral region R21 and the area ratio of the low-concentration cathode layer 172 in the second peripheral region R22 are, for example, substantially the same.

[0060] The area ratio of the high-concentration cathode layer 183 in the central region R23 is lower than the area ratio of the high-concentration cathode layer 181 in the first peripheral region R21, and is lower than the area ratio of the high-concentration cathode layer 182 in the second peripheral region R22. The area ratio of the high-concentration cathode layer 181 in the first peripheral region R21 and the area ratio of the high-concentration cathode layer 182 in the second peripheral region R22 are, for example, substantially the same.

[0061] In the first peripheral region R21, the area ratio of the high-concentration cathode layer 181 is higher than the area ratio of the low-concentration cathode layer 171. In the second peripheral region R22, the area ratio of the high-concentration cathode layer 182 is higher than the area ratio of the low-concentration cathode layer 172. In the central region R23, the area ratio of the low-concentration cathode layer 173 is higher than the area ratio of the high-concentration cathode layer 183.

[0062] Hereinafter, the operation of the semiconductor device 101 according to this embodiment will be described.

[0063] The semiconductor device 101 is connected, for example, between a power supply and a load such as a motor. When a voltage is applied to the semiconductor device 101 by the power supply, such that the first electrode 21 is positive and the second electrode 22 is negative, and a potential equal to or higher than a threshold value is applied to the third electrode 23, the IGBT formed in the IGBT region R1 turns on, holes are injected from the first electrode 21, electrons are injected from the second electrode 22, and a collector current flows from the first electrode 21 to the second electrode 22.

[0064] When the potential of third electrode 23 falls below the threshold, the IGBT enters the off state, and the collector current stops. At this time, a voltage is applied to the load connected to semiconductor device 101, with second electrode 22 as the positive electrode and first electrode 21 as the negative electrode. This causes holes to be ejected from IGBT region R1 through collector layer 11 and electrons to be ejected through emitter layer 15.

[0065] On the other hand, in the diode region R2, since a forward voltage is applied to the diode, a circulating current flows from the second electrode 22 to the first electrode 21. At this time, holes flow from the second electrode 22 via the anode layer 14d, and electrons flow from the first electrode 21 via the cathode layer 16, increasing the conductivity of the drift layer 13. As a result, the circulating current increases.

[0066] In this case, the higher the impurity concentration of the cathode layer 16 in the diode region R2, the more electrons flow through the cathode layer 16. As a result, the conductivity modulation effect in the diode region R2 increases, the resistance of the drift layer 13 decreases, and the circulating current increases. On the other hand, since the lower the impurity concentration of the cathode layer 16, the less electrons flow, the conductivity modulation effect decreases, and the resistance of the drift layer 13 increases. As a result, the circulating current decreases.

[0067] Reducing the circulating current is an effective way to reduce the switching loss of the semiconductor device 101. To this end, it is preferable to reduce the impurity concentration of the cathode layer 16. However, reducing the impurity concentration of the cathode layer 16 can easily cause snapback, making the operation of the semiconductor device 101 unstable. In particular, near the IGBT region R1 in the diode region R2, some of the holes in the drift layer 13 of the diode region R2 are ejected from the collector layer 11 of the IGBT region R1. This reduces the number of holes injected from the drift layer 13 into the cathode layer 16, and this further reduces the number of electrons injected from the cathode layer 16 into the drift layer 13. Therefore, snapback is more likely to occur near the IGBT region R1 in the diode region R2.

[0068] Therefore, in this embodiment, to achieve both reduced circulating current and suppressed snapback, a low-concentration cathode layer 17 and a high-concentration cathode layer 18 are provided in the cathode layer 16, and their area ratios are varied depending on their positions within the diode region R2. In the semiconductor device 101, since the area ratio of the low-concentration cathode layer 17 in the central region R23 is high, the amount of carrier injection is reduced, resulting in lower switching losses during reverse recovery operation.

[0069] On the other hand, in the first and second peripheral regions R21 and R22, the high area ratio of the high-concentration cathode layer 18 increases the amount of carrier injection, enhancing the conductivity modulation effect and reducing the resistance value in the buffer layer 12 and drift layer 13 located directly above the first and second peripheral regions R21 and R22. This suppresses the outflow of carriers from the buffer layer 12 and drift layer 13 located directly above the first and second peripheral regions R21 and R22 to the buffer layer 12 and drift layer 13 in the adjacent IGBT region R1, thereby suppressing the reduction in the amount of holes discharged from the cathode layer 16 in the first and second peripheral regions R21 and R22. Since the amount of electron injection increases and decreases according to the amount of holes discharged from the cathode layer 16, electron injection into the cathode layer 16 in the first and second peripheral regions R21 and R22 is efficient. As described above, since the conductivity modulation effect is excellent in the portions of the buffer layer 12 and the drift layer 13 adjacent to the IGBT region R1 , snapback can be suppressed.

[0070] Furthermore, the buffer layer 12 and drift layer 13 located directly above the first and second peripheral regions R21 and R22 have low resistance values. This allows holes to flow from the buffer layer 12 and drift layer 13 in the central region R23, increasing the amount of holes and effectively suppressing snapback. Consequently, the operation of the semiconductor device 101 is stabilized.

[0071] Hereinafter, a method for manufacturing the semiconductor device 101 according to this embodiment will be described.

[0072] For example, prepare - The buffer layer 12 is formed by ion implanting n-type impurities from the lower surface 10A of the semiconductor portion 10 toward the portion where the buffer layer 12 is to be formed.

[0073] Next, p-type impurities are ion-implanted from the lower surface 10A of the semiconductor portion 10 toward the portion where the collector layer 11 is to be formed, for example, using photolithography, to form the collector layer 11 .

[0074] Next, n-type impurities are ion-implanted from the lower surface 10A of the semiconductor portion 10 toward the portion where the high-concentration cathode layer 18 is to be formed, for example, using photolithography. The portion of the cathode layer 16 where the high-concentration cathode layer 18 is not formed is the low-concentration cathode layer 17.

[0075] Hereinafter, the effects of the semiconductor device 101 according to this embodiment will be described.

[0076] In the semiconductor device 101 according to this embodiment, the cathode layer 16 includes a low-concentration cathode layer 17 and a high-concentration cathode layer 18. The area ratio of the low-concentration cathode layer in the first peripheral region R21 and the second peripheral region R22 adjacent to the IGBT region R1 is lower than the area ratio of the low-concentration cathode layer in the central region R23. As a result, the semiconductor device 101 can reduce switching losses during reverse recovery operation and suppress the occurrence of snapback.

[0077] In the case where the structure of the semiconductor device 101 involved in this embodiment is not used, for example, in order to reduce the switching loss during the reverse recovery action, it is possible to consider suppressing the injection amount of carriers entering from the cathode side to reduce the current during the reverse recovery action. Specifically, for example, it is possible to consider reducing the impurity concentration of the cathode layer. In this case, since the injection amount of carriers becomes lower when the diode is turned on, the number of carriers in the buffer layer and the drift layer becomes smaller, and the conductivity modulation effect becomes smaller. As a result, the resistance values ​​of the buffer layer and the drift layer in the diode region are similar to the resistance values ​​of the buffer layer and the drift layer in the IGBT region, resulting in holes invading the IGBT region R1 and reducing the amount of holes discharged from the cathode layer. As a result, since the injection amount of electrons into the cathode layer is reduced, the carrier density in the diode region becomes lower, making it easier for fast recovery to occur.

[0078] In addition, as another means, there is a means of controlling the life time by irradiating the semiconductor portion 10 of the diode region with electron beams. However, in this case, the semiconductor portion 10 of the adjacent IGBT region R1 is also irradiated with electron beams, which may deteriorate the characteristics of the IGBT.

[0079] In contrast to these means, according to the present embodiment, the amount of carrier injection can be reduced while suppressing snapback without performing lifetime control, thereby achieving low loss.

[0080] In the present embodiment, the low-concentration cathode layer 17 and the high-concentration cathode layer 18 are symmetrically arranged in the diode region R2 . However, the present invention is not limited thereto and they may be asymmetrically arranged.

[0081] The number and width of the low-concentration cathode layers 17 and high-concentration cathode layers 18 in one diode region R2 are not limited to the above description. For example, the number of low-concentration cathode layers 17 and high-concentration cathode layers 18 is preferably greater than that of the present embodiment without causing a sharp change in carrier density.

[0082] In addition, the central high-concentration cathode layer 183 is arranged in the center of the diode region P2 in the direction X, but is not limited to this. For example, the high-concentration cathode layer 18 and the low-concentration cathode layer 17 can also be arranged in a manner such that the central low-concentration cathode layer 173 is arranged in the center of the diode region R2 in the direction X.

[0083] (First Modification of the First Embodiment)

[0084] The cathode layer 16 a in this modification example includes a plurality of high-concentration cathode layers 18 having substantially the same width and different arrangement densities in the direction X.

[0085] Figure 7 This is an enlarged bottom view showing the cathode layer in this modification. Figure 7 , the first electrode 21 is omitted.

[0086] The arrangement density of the high-concentration cathode layer 18 in the first peripheral region R21 and the second peripheral region R22 is higher than that in the central region R23. Therefore, the area occupancy rate of the high-concentration cathode layer 18 is higher in the first peripheral region R21 and the second peripheral region R22 than in the central region R23, and the area occupancy rate of the low-concentration cathode layer 17 is lower in the first peripheral region R21 and the second peripheral region R22 than in the central region R23.

[0087] The configuration, operation, and effects other than those described above in this embodiment are the same as those in the first embodiment.

[0088] (Second Modification of the First Embodiment)

[0089] The cathode layer 16 b in this modification example includes a plurality of low-concentration cathode layers 17 having substantially the same width and different arrangement densities in the direction X.

[0090] Figure 8 This is an enlarged bottom view showing the cathode layer in this modification. Figure 8 , the first electrode 21 is omitted.

[0091] The arrangement density of the low-concentration cathode layer 17 in the first peripheral region R21 and the second peripheral region R22 is lower than that in the central region R23. Therefore, the area occupancy rate of the low-concentration cathode layer 17 in the first peripheral region R21 and the second peripheral region R22 is lower than that in the central region R23, and the area occupancy rate of the high-concentration cathode layer 18 in the first peripheral region R21 and the second peripheral region R22 is higher than that in the central region R23.

[0092] The configuration, operation, and effects other than those described above in this embodiment are the same as those in the first embodiment.

[0093] (Third Modification of First Embodiment)

[0094] In the cathode layer 16 c in this modification, the widths of the high-concentration cathode layer 18 and the low-concentration cathode layer 17 change continuously.

[0095] Figure 9 FIG is an enlarged bottom view showing the cathode layer in this modification. Figure 9 , the first electrode 21 is omitted.

[0096] The width of the high-concentration cathode layer 18 decreases from the end side toward the center side, while the width of the low-concentration cathode layer 17 increases from the end side toward the center side. As a result, the area occupancy rate of the high-concentration cathode layer 18 is higher in the first peripheral region R21 and the second peripheral region R22 than in the central region R23, while the area occupancy rate of the low-concentration cathode layer 17 is lower in the first peripheral region R21 and the second peripheral region R22 than in the central region R23.

[0097] The configuration, operation, and effects other than those described above in this embodiment are the same as those in the first embodiment.

[0098] (Second embodiment)

[0099] The cathode layer 16d in this embodiment also has a plurality of partial low-concentration cathode layers 17p separated in direction Y, a side portion 17t extending from a portion of the low-concentration cathode layer 17 toward the center side or the end side, a plurality of partial high-concentration cathode layers 18p separated in direction Y, and a side portion 18t extending from a portion of the high-concentration cathode layer 18 toward the center side or the end side.

[0100] Figure 10 : is an enlarged bottom view showing the cathode layer in this embodiment. Figure 10 , the first electrode 21 is omitted.

[0101] In the first peripheral region R21 of this embodiment, two first high-concentration cathode layers 181 , a plurality of side portions 18t extending from the edge high-concentration cathode layer 18e toward the center, one first low-concentration cathode layer 171 , and a plurality of partial low-concentration cathode layers 17p are provided.

[0102] The second peripheral region R22 includes two second high-concentration cathode layers 182, multiple side portions 18t extending from the edge high-concentration cathode layer 18e toward the center, one second low-concentration cathode layer 172, and multiple partial low-concentration cathode layers 17p. The partial low-concentration cathode layer 17p is the low-concentration cathode layer 17 located at the extreme edge of the diode region R2.

[0103] like Figure 7 As shown, in the first peripheral region R21 and the second peripheral region R22 , the area ratio of the high-concentration cathode layer 18 is larger than the area ratio of the low-concentration cathode layer 17 by an amount corresponding to the provision of the side portion 18 t and a portion of the low-concentration cathode layer 17 p .

[0104] In the central region R23, two central low-concentration cathode layers 173, multiple side portions 17t extending toward the center from the central low-concentration cathode layers 173, and multiple partial high-concentration cathode layers 18p are provided. The multiple side portions 17t and the multiple partial high-concentration cathode layers 18p in the central region R23 are provided at the center of the diode region R2 in the direction X.

[0105] like Figure 7 As shown, in the central region R23 , the area ratio of the low-concentration cathode layer 17 is larger than the area ratio of the high-concentration cathode layer 18 by an amount corresponding to the provision of the side portion 17 t and a portion of the high-concentration cathode layer 18 p .

[0106] According to this embodiment, the impurity concentration of the cathode layer 16 is more easily adjusted by using the partial low-concentration cathode layer 17p, the partial high-concentration cathode layer 18p, and the side portions 17t and 18t. In addition, the photolithography and ion implantation in the first embodiment enable complex patterning of the low-concentration cathode layer 17 and the high-concentration cathode layer 18 as in this embodiment.

[0107] According to this embodiment, similarly to the first embodiment, the switching loss during the reverse recovery operation can be reduced and the occurrence of snapback can be suppressed.

[0108] In addition, the shapes of the low-concentration cathode layer 17 and the high-concentration cathode layer 18 in the lower surface 10A of the semiconductor portion 10 are formed by combining rectangular shapes, but are not limited to this. They can also be circular or similar shapes, polygonal shapes other than quadrilaterals such as triangles, or shapes formed by combining these.

[0109] The configuration, operation, and effects other than those described above in this embodiment are the same as those in the first embodiment.

[0110] (Modification of the Second Embodiment)

[0111] In the present modification, the cathode layer 16 e is formed along the direction Y with a plurality of arrangement patterns P1 .

[0112] Figure 11 This is an enlarged bottom view showing the arrangement pattern of the cathode layer in this modification. Figure 11 , the first electrode 21 is omitted.

[0113] Arrangement pattern P1 includes, for example, a plurality of high-concentration cathode layers 18 having substantially the same width and arranged at a substantially uniform density in direction X, and low-concentration cathode layers 17 disposed between the plurality of high-concentration cathode layers 18. The edge high-concentration cathode layers 18e extend, for example, along direction Y and are continuous with, for example, the edge high-concentration cathode layers 18e of the adjacent arrangement pattern P1. For the high-concentration cathode layers 18 other than the edge high-concentration cathode layers 18e, the length in direction Y decreases as they move from the edge toward the center.

[0114] Therefore, the area occupancy of the high-concentration cathode layer 18 is higher in the first and second peripheral regions R21 and R22 than in the central region R23 , and the area occupancy of the low-concentration cathode layer 17 is lower in the first and second peripheral regions R21 and R22 than in the central region R23 .

[0115] The configuration, operation, and effects other than those described above in this embodiment are the same as those in the first embodiment.

[0116] According to the embodiment of the present invention, a semiconductor device capable of achieving low loss and stable operation can be provided.

[0117] The embodiments of the present invention have been described above with reference to specific examples. However, the embodiments of the present invention are not limited to these specific examples. For example, with respect to the specific configurations and materials of the semiconductor portion, first electrode, second electrode, and third electrode included in the semiconductor device, as long as a person skilled in the art can implement the present invention in the same manner and obtain the same effect by appropriately selecting from the known range, such configurations are included in the scope of the present invention. A solution formed by combining any two or more elements of each specific example within a technically achievable range is included in the scope of the present invention as long as it includes the gist of the present invention.

Claims

1. A semiconductor device comprising a plurality of IGBT regions and a plurality of diode regions alternately arranged along a first direction, wherein: have: a first electrode; a semiconductor portion provided on the first electrode, The semiconductor portion has: a collector layer of a first conductivity type provided in the IGBT region and connected to the first electrode, a second conductive type low-concentration cathode layer provided in the diode region and connected to the first electrode, a high-concentration cathode layer provided in the diode region and in contact with the first electrode and having a second conductive type and having an impurity concentration higher than that of the low-concentration cathode layer; a second conductive type drift layer provided on the collector layer, the low-concentration cathode layer, and the high-concentration cathode layer; a plurality of anode layers of the first conductivity type locally provided on the drift layer in the diode region, a plurality of first conductivity type base layers locally provided on the drift layer in the IGBT region, and an emitter layer of a second conductivity type provided on the base layer in the IGBT region, When the diode region on the lower surface of the semiconductor portion is divided into three equal parts along the first direction, namely, a first peripheral region, a central region, and a second peripheral region, the area ratio of the low-concentration cathode layer in the central region is higher than the area ratios of the low-concentration cathode layer in the first peripheral region and the second peripheral region; a second electrode, provided on the semiconductor portion in the IGBT region and the diode region, and connected to the anode layer and the emitter layer; a third electrode, disposed in the IGBT region, facing the emitter layer, the base layer, and the drift layer; as well as An insulating film is provided between the semiconductor portion and the third electrode.

2. The semiconductor device according to claim 1, wherein On the lower surface of the semiconductor portion in the diode region, a plurality of the high-concentration cathode layers are spaced apart from each other along the first direction, with the low-concentration cathode layer interposed between them.

3. The semiconductor device according to claim 2, wherein The plurality of low-concentration cathode layers and the plurality of high-concentration cathode layers extend along a second direction crossing the first direction.

4. The semiconductor device according to claim 1, wherein The length of the low-concentration cathode layer in the central region in the first direction is greater than the length of the low-concentration cathode layer in the first peripheral region in the first direction.

5. The semiconductor device according to claim 1, wherein The length of the high-concentration cathode layer in the first peripheral region in the first direction is greater than the length of the high-concentration cathode layer in the central region in the first direction.

6. The semiconductor device according to claim 1, wherein The high-concentration cathode layer arranged on the end side of the first peripheral region in the first direction is an edge high-concentration cathode layer in contact with the collector layer.

7. The semiconductor device according to claim 6, wherein: The length of the low-concentration cathode layer in the central region in the first direction is greater than the length of the edge high-concentration cathode layer in the first direction.

8. The semiconductor device according to claim 1, wherein The semiconductor portion further includes a second conductivity type buffer layer provided between the collector layer and the drift layer, between the low concentration cathode layer and the drift layer, and between the high concentration cathode layer and the drift layer. The impurity concentration of the buffer layer is higher than the impurity concentration of the drift layer.

9. The semiconductor device according to claim 1, wherein The high-concentration cathode layer has a plurality of partial high-concentration cathode layers separated in a direction intersecting the first direction, A portion of the low-concentration cathode layer is provided between adjacent portions of the high-concentration cathode layers.

10. The semiconductor device according to claim 1, wherein The low-concentration cathode layer has a plurality of partial low-concentration cathode layers separated in a direction intersecting the first direction, A portion of the high-concentration cathode layer is provided between adjacent portions of the low-concentration cathode layers.

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