Low-current mismatch, wide output swing and programmable charge pump circuit

Abstract

The present invention discloses a charge pump circuit with low current mismatch, wide output swing and programmability, which is composed of a triple programmable current source array, switching transistors M1-M34, an operational amplifier OPA, and a current source compensation circuit. By means of the negative feedback of the operational amplifier, a charge pump circuit with low mismatch, high flatness and wide output voltage swing is realized, achieving low spurious and low noise performance in the frequency source system, and achieving the purpose of low cost and low power consumption. This circuit can be implemented in CMOS process. Due to its simple structure, small area and low power consumption, it can be very conveniently integrated into the frequency source system.

Description

Technical Field

[0001] The present invention relates to the technical field of charge pump circuits, and particularly to a charge pump circuit with low current mismatch, wide output swing and programmability. Background Art

[0002] The frequency source is a core module in millimeter-wave radars and communication systems. Factors such as the phase noise and reference spurs of the frequency source system will not only seriously degrade the performance of the communication system, but also cause the radar to detect false targets. Therefore, it is of great significance to optimize the phase noise and reference spurs of the frequency source system.

[0003] The reference spurs of the frequency source system are a key index, which mainly come from the frequency discriminator and phase discriminator and the charge pump circuit. When the phase-locked loop enters the locked state, the frequency discriminator and phase discriminator will output a fixed narrow pulse to eliminate the phase discrimination blind area. During this narrow pulse, the charge and discharge current source switches of the charge pump are both in the open state. When the magnitudes of the charge and discharge currents in the charge pump do not match, the charge pump will then draw current from or inject current into the loop filter at this time. The change in current will cause the voltage of the voltage-controlled oscillator to jitter periodically, which is also called voltage ripple, and it will be manifested as spurious interference at the position of the carrier reference clock in the signal spectrum output by the frequency source. However, the performance of existing charge pumps still needs to be further improved. Summary of the Invention

[0004] The purpose of the present invention is to address the technical defects existing in the prior art, and to provide a charge pump circuit with low current mismatch, wide output swing and programmability, which is a novel charge pump circuit based on a source switch using an operational amplifier for negative feedback. The charge pump with programmable source switch negative feedback can reduce reference spurs and minimize the impact of the reference spurs of the frequency source system on the radar or communication system as much as possible.

[0005] The technical solution adopted to achieve the purpose of the present invention is as follows:

[0006] A charge pump circuit with low current mismatch, wide output swing and programmability, which is composed of a triple programmable current source array, switching transistors M1 - M34, an operational amplifier OPA, and a current source compensation circuit; switching transistors M1, M6, M11 are charging current source switches, and switching transistors M2, M7, M12 are complementary switches corresponding to the charging power source switches; switching transistors M18, M23, M28 are discharging current source switches, and switching transistors M19, M24, M29 are complementary switches corresponding to the discharging current source switches; M3, M8, M13 are triple charging current source arrays, M4, M5, M9, M10 are triple charging current source array gating switches, switching transistors M17, M15 are 1:1 current mirrors, the gates of switching transistors M1, M6, M11 are connected to VUP, the sources of switching transistors M1, M4, M6, M9, M11, M14, M16 are connected to VDD, the drain of switching transistor M1 is connected to the drain of switching transistor M2 and the source of switching transistor M3; the gate of switching transistor M4 is connected to EN1, the source is connected to the gate of switching transistor M3 and the source of switching transistor M5, the gate of switching transistor M5 is connected to NE1N, the gates of switching transistors M2, M7, M12 are connected to VUPN and the sources are floating;

[0007] The drain of switching transistor M5 is connected to the gate of switching transistor M17, the drains of switching transistors M3, M8, M13 are connected to the non-inverting input terminal of the operational amplifier OPA, the gate of switching transistor M6 is connected to the gate of switching transistor M7 and the source of switching transistor M8, the gate of switching transistor M8 is connected to the sources of switching transistors M10 and M9, the gate of switching transistor M10 is connected to EN2N and the drain is connected to the gate of switching transistor M17, the drain of switching transistor M11 is connected to the drain of switching transistor M12 and the source of switching transistor M13, the gates of switching transistors M13 and M15 are connected and then connected to the gate of switching transistor M17, the source of switching transistor M15 is connected to the drain of switching transistor M14, the gates of switching transistors M14 and M16 are connected and then grounded, the gate of switching transistor M16 is connected to the source of switching transistor M17;

[0008] The switching transistors M20, M25, and M30 form a triple discharge current source array, and the switching transistors M21, M22, M26, and M27 are the gating switches of the triple discharge current source array; the drain of the switching transistor M15 is connected to the negative input terminal of the operational amplifier OPA, the drain of the switching transistor M13 is connected to the gate of the switching transistor M33 and the drains of the switching transistors M20, M25, and M30, the drain of the switching transistor M32 is connected to the negative input terminal of the operational amplifier OPA, the drain of the switching transistor M32 is connected to the drain of the switching transistor M33 and is connected to one end of the bandgap reference current source ICP, the other end of the bandgap reference current source ICP is grounded, the source of the switching transistor M33 is connected to the drain and gate of the switching transistor M34, the source of the switching transistor M34 is grounded, the source of the switching transistor M32 is connected to the drain of the switching transistor M31, the gate of the switching transistor M31 is connected to VDD and the source is grounded, the gate of the switching transistor M32 is connected to the gate of the switching transistor M30 and then connected to the drains of the switching transistors M21 and M26, the source of the switching transistor M30 is connected to the drains of the switching transistors M28 and M29, the source of the switching transistor M26 is connected to the source of the switching transistor M27 and the gate of the switching transistor M25, the source of the switching transistor M25 is connected to the drains of the switching transistors M24 and M23, the source of the switching transistor M23 is connected to the gate of the switching transistor M20 and the source of the switching transistor M22, the source of the switching transistor M20 is connected to the drains of the switching transistors M19 and M18, the gates of the switching transistors M19, M24, and M29 are connected to VDNN and the sources are floating, the gates of the switching transistors M18, M23, and M28 are connected to VDN and the sources are grounded, and the output terminal of the operational amplifier OPA is connected to the gates of the switching transistors M32 and M30 and then grounded.

[0009] Among them, the gates of the switching transistors M13 and M15 are connected and then connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to VDD.

[0010] Among them, the output terminal of the operational amplifier OPA is connected to the gates of the switching transistors M32 and M30 and then grounded through a capacitor C1.

[0011] Among them, the output terminal of the operational amplifier OPA is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the negative input terminal of the operational amplifier OPA.

[0012] The programmable novel wide output swing of the present invention realizes a charge pump circuit with low mismatch, high flatness, and wide output voltage swing through the negative feedback of the operational amplifier, realizes the low spurious and low noise performance of the frequency source system, and achieves the purpose of low cost and low power consumption; this circuit can be implemented in the CMOS process, and due to its simple structure, small area, and low power consumption, it can be very conveniently integrated into the frequency source system. Description of the Drawings

[0013] Figure 1 is the circuit diagram of the low current mismatch, wide output swing and programmable charge pump circuit of the present invention. Detailed implementation mode

[0014] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0015] As Figure 1 shown, the low current mismatch, wide output swing and programmable charge pump circuit of the embodiment of the present invention is composed of a triple programmable current source array, switching transistors M1-M34, an operational amplifier OPA, and a current source compensation circuit; switching transistors M1, M6, M11 are charging current source switches, and switching transistors M2, M7, M12 are complementary switches corresponding to the charging power source switches; switching transistors M18, M23, M28 are discharging current source switches, and switching transistors M19, M24, M29 are complementary switches corresponding to the discharging current source switches; M3, M8, M13 are triple charging current source arrays, M4, M5, M9, M10 are triple charging current source array selection switches, switching transistors M17, M15 are 1:1 current mirrors, the gates of switching transistors M1, M6, M11 are connected to VUP, the sources of switching transistors M1, M4, M6, M9, M11, M14, M16 are connected to VDD, the drain of switching transistor M1 is connected to the drain of switching transistor M2 and the source of switching transistor M3; the gate of switching transistor M4 is connected to EN1, the source is connected to the gate of switching transistor M3 and the source of switching transistor M5, the gate of switching transistor M5 is connected to NE1N, the gates of switching transistors M2, M7, M12 are connected to VUPN and the sources are floating;

[0016] the drain of switching transistor M5 is connected to the gate of switching transistor M17, the drains of switching transistor M3, switching transistor M8, switching transistor M13 are connected to the positive input terminal of the operational amplifier OPA, the gate of switching transistor M6 is connected to the gate of switching transistor M7 and the source of switching transistor M8, the gate of switching transistor M8 is connected to the source of switching transistor M10 and the source of switching transistor M9, the gate of switching transistor M10 is connected to EN2N and the drain is connected to the gate of switching transistor M17, the drain of switching transistor M11 is connected to the drain of switching transistor M12 and the source of switching transistor M13, the gates of switching transistor M13 and switching transistor M15 are connected and then connected to the gate of switching transistor M17, the source of switching transistor M15 is connected to the drain of switching transistor M14, the gates of switching transistor M14 and switching transistor M16 are connected and then grounded, and the gate of switching transistor M16 is connected to the source of switching transistor M17;

[0017] The switching transistors M20, M25, and M30 form a triple discharge current source array, and the switching transistors M21, M22, M26, and M27 are the gating switches of the triple discharge current source array; the drain of the switching transistor M15 is connected to the negative input terminal of the operational amplifier OPA, the drain of the switching transistor M13 is connected to the gate of the switching transistor M33 and the drains of the switching transistors M20, M25, and M30, the drain of the switching transistor M32 is connected to the negative input terminal of the operational amplifier OPA, the drain of the switching transistor M32 is connected to the drain of the switching transistor M33 and is connected to one end of the bandgap reference current source ICP, the other end of the bandgap reference current source ICP is grounded, the source of the switching transistor M33 is connected to the drain and gate of the switching transistor M34, the source of the switching transistor M34 is grounded, the source of the switching transistor M32 is connected to the drain of the switching transistor M31, the gate of the switching transistor M31 is connected to VDD and the source is grounded, the gate of the switching transistor M32 is connected to the gate of the switching transistor M30 and then connected to the drains of the switching transistors M21 and M26, the source of the switching transistor M30 is connected to the drains of the switching transistors M28 and M29, the source of the switching transistor M26 is connected to the sources of the switching transistors M27 and M25, the source of the switching transistor M25 is connected to the drains of the switching transistors M24 and M23, the source of the switching transistor M23 is connected to the gates of the switching transistors M20 and M22, the source of the switching transistor M20 is connected to the drains of the switching transistors M19 and M18, the gates of the switching transistors M19, M24, and M29 are connected to VDNN and the sources are floating, the gates of the switching transistors M18, M23, and M28 are connected to VDN and the sources are grounded, and the output terminal of the operational amplifier OPA is connected to the gates of the switching transistors M32 and M30 and then grounded.

[0018] Among them, EN1 and EN1N, EN2 and EN2N are two sets of differential signals, which are enable signals output by the serial peripheral interface (SPI). When EN1 is at a high level, EN1N is at a low level, and the switching transistors M4 and M22 are turned on, and the switching transistors M5 and M21 are turned off, and the charge pump current becomes twice the original; similarly, when EN2 is at a high level, the switching transistors M9 and M27 are turned on, and the switching transistors M10 and M26 are turned off, and the charge pump current also becomes twice the original; when both EN1 and EN2 are at a high level, both EN1N and EN2N are at a low level, and the current of the charge pump becomes three times the original. By controlling EN1 and EN1N, EN2 and EN2N, which are two sets of differential enable signals, through SPI, the purpose of programmable control of the charge pump current of one time, two times, and three times can be achieved.

[0019] Among them, VUP and VUPN, VDN and VDNN are two pairs of differential pulse signals output by the frequency discriminator and phase detector. When VUP is at a low level, the switching transistors M1, M6, and M11 are turned on, and the charge pump charging current source is turned on to charge the loop filter. At this time, VUPN is at a high level, and M2, M7, and M12 are turned off, which can cancel out the non-ideal effects of the charging switching transistors. Similarly, when VDN is at a high level, the switching transistors M18, M23, and M28 are turned on, and the charge pump discharging current source is turned on to discharge the loop filter. At this time, VDNN is at a low level, and M19, M24, and M29 are turned off, which can cancel out the non-ideal effects of the discharging switching transistors.

[0020] Among them, the gates of switching transistor M13 and switching transistor M15 are connected to each other and then connected to one end of capacitor C2, and the other end of capacitor C2 is connected to VDD.

[0021] Among them, the output terminal of operational amplifier OPA is connected to the gates of switching transistor M32 and switching transistor M30, and then grounded through a capacitor C1.

[0022] Among them, the output terminal of operational amplifier OPA is connected to one end of resistor R1, the other end of resistor R1 is connected to one end of capacitor C3, and the other end of capacitor C3 is connected to the negative input terminal of operational amplifier OPA.

[0023] In the embodiment of the present invention, the switching transistors M1, M6, and M11 are the switches of the charging current source, and the switching transistors M2, M7, and M12 are the complementary switches corresponding to the charging switches; the switching transistors M18, M23, and M28 are the switches of the discharging current source, and the switching transistors M19, M24, and M29 are the complementary switches corresponding to the discharging switches. The switching transistors M17 and M15 form a 1:1 current mirror, the switching transistors M3, M8, and M13 form a triple charging current source array, and the switching transistors M20, M25, and M30 form a triple discharging current source array. The switching transistors M4, M5, M9, and M10 are the gating switches of the triple charging current source array, and the switching transistors M21, M22, M26, and M27 are the gating switches of the triple discharging current source array, supporting the adjustable charge pump charging and discharging current of 50uA - 150uA.

[0024] Among them, the two input terminals of operational amplifier OPA are respectively connected to the drains of the two transistors M13 and M15, and the leakage voltages of the two transistors are ensured to be equal through feedback, eliminating the current mismatch caused by the channel modulation effect.

[0025] Among them, the resistor R1 and the capacitor C3 serve as the Miller compensation circuit in the feedback circuit, making the phase margin of the feedback structure reach more than 50°, ensuring the stability of the system.

[0026] Among them, the bandgap reference current source Icp provides a stable 50uA current for the charge pump current mirror.

[0027] Among them, filter capacitors C1 and C2 are respectively connected between the gates of current sources M13, M15 and M30, M32 and ground to reduce the influence brought by the non-ideal effects of the switches.

[0028] Among them, the gate of switch M33 is connected to the output voltage terminal of the charge pump, and the current of the bandgap reference current source Icp is compensated by the voltage change at the feedback output terminal to ensure that the output current of the charge pump remains flat within a wide output voltage range.

[0029] In the embodiment of the present invention, by introducing operational amplifier OPA to clamp the drain voltages of the two current source transistors of switch M13 and switch M15, the mismatch of the charging and discharging currents is reduced. The output terminal of the operational amplifier is connected to the gates of switch M30 and switch M32 to ensure that the charging current of the charge pump still maintains a high value when the circuit is powered on, and the loop can still feedback normally. Finally, the current mismatch is less than 0.1%.

[0030] As the output voltage decreases, the charging and discharging currents will decrease due to the channel length modulation effect of the current mirror transistors, and the change of the charge pump current will cause the change of the PLL loop bandwidth, which may lead to the instability of the PLL loop.

[0031] To offset the influence brought by the channel modulation effect, a dynamic compensation circuit is used to compensate the current source, as Figure 1 shown by switch M33 and switch M34, and finally the current change is less than 2%.

[0032] When the clock signal controls the on and off of the switch, the charging and discharging of Cgd of the switch by the pulse causes high-frequency glitches, which will cause the mismatch of the charging and discharging currents.

[0033] To offset this glitch, a clock feedthrough cancellation Dummy transistor is introduced. In the figure, complementary pulse signals are connected to the gates of switch M1 and switch M2, so that the high-frequency glitch currents generated by VUPN and VUP can cancel each other out, thus eliminating the influence of clock feedthrough.

[0034] The novel charge pump proposed by the present invention has small current mismatch and large output voltage swing; by using the negative feedback clamping voltage of the operational amplifier, the dynamic adjustment of the charging and discharging matching can be achieved, enhancing the robustness of the circuit structure; the analog circuit design with small-size active MOS transistors as the main body greatly alleviates the chip area problem brought by large-area passive devices, making the chip miniaturization easier to integrate and reducing the cost of tape-out at the same time; the proposed programmable current source array can adapt to a variety of loop bandwidth selections, and the output current of the charge pump can be adjusted by controlling bits, thus enhancing the wide applicability of this charge pump.

[0035] The foregoing has shown and described the basic principles, main features and advantages of the present invention. For a person skilled in the art, it is obvious that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and without departing from the spirit or basic features of the present invention, the present invention can be implemented in other specific forms;

[0036] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes that fall within the meaning and scope of the equivalent elements of the claims in the present invention, and any reference signs in the claims should not be regarded as limiting the claims involved.

[0037] In addition, it should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A low-current mismatch, wide-output swing, and programmable charge pump circuit, characterized in that , it is composed of a triple-programmable current source array, switching transistors M1-M34, an operational amplifier OPA, and a current source compensation circuit; switching transistors M1, M6, and M11 are charging current source switches, and switching transistors M2, M7, and M12 are complementary switches corresponding to the charging power source switches; switching transistors M18, M23, and M28 are discharging current source switches, and switching transistors M19, M24, and M29 are complementary switches corresponding to the discharging current source switches; M3, M8, and M13 are triple-charging current source arrays, M4, M5, M9, and M10 are triple-charging current source array gating switches, switching transistors M17 and M15 are 1:1 current mirrors, the gates of switching transistors M1, M6, and M11 are connected to VUP, the sources of switching transistors M1, M4, M6, M9, M11, M14, and M16 are connected to VDD, the drain of switching transistor M1 is connected to the drain of switching transistor M2 and the source of switching transistor M3; the gate of switching transistor M4 is connected to EN1, the source is connected to the gate of switching transistor M3 and the source of switching transistor M5, the gate of switching transistor M5 is connected to NE1N, the gates of switching transistors M2, M7, and M12 are connected to VUPN and the sources are floating; the drain of switching transistor M5 is connected to the gate of switching transistor M17, the drains of switching transistors M3, M8, and M13 are connected to the non-inverting input terminal of the operational amplifier OPA, the gate of switching transistor M6 is connected to the gate of switching transistor M7 and the source of switching transistor M8, the gate of switching transistor M8 is connected to the source of switching transistor M10 and the source of switching transistor M9, the gate of switching transistor M10 is connected to EN2N and the drain is connected to the gate of switching transistor M17, the drain of switching transistor M11 is connected to the drain of switching transistor M12 and the source of switching transistor M13, the gates of switching transistors M13 and M15 are connected and then connected to the gate of switching transistor M17, the source of switching transistor M15 is connected to the drain of switching transistor M14, the gates of switching transistors M14 and M16 are connected and then grounded, and the gate of switching transistor M16 is connected to the source of switching transistor M17; The switching transistors M20, M25, and M30 form a triple discharge current source array, and the switching transistors M21, M22, M26, and M27 are the gating switches of the triple discharge current source array; the drain of the switching transistor M15 is connected to the negative input terminal of the operational amplifier OPA, the drain of the switching transistor M13 is connected to the gate of the switching transistor M33 and the drains of the switching transistors M20, M25, and M30, the drain of the switching transistor M32 is connected to the negative input terminal of the operational amplifier OPA, the drain of the switching transistor M32 is connected to the drain of the switching transistor M33 and is connected to one end of the bandgap reference current source ICP, the other end of the bandgap reference current source ICP is grounded, the source of the switching transistor M33 is connected to the drain and gate of the switching transistor M34, the source of the switching transistor M34 is grounded, the source of the switching transistor M32 is connected to the drain of the switching transistor M31, the gate of the switching transistor M31 is connected to VDD and the source is grounded, the gate of the switching transistor M32 is connected to the gate of the switching transistor M30 and then connected to the drains of the switching transistors M21 and M26, the source of the switching transistor M30 is connected to the drains of the switching transistors M28 and M29, the source of the switching transistor M26 is connected to the source of the switching transistor M27 and the gate of the switching transistor M25, the source of the switching transistor M25 is connected to the drains of the switching transistors M24 and M23, the source of the switching transistor M23 is connected to the gate of the switching transistor M20 and the source of the switching transistor M22, the source of the switching transistor M20 is connected to the drains of the switching transistors M19 and M18, the gates of the switching transistors M19, M24, and M29 are connected to VDNN and the sources are floating, the gates of the switching transistors M18, M23, and M28 are connected to VDN and the sources are grounded, and the output terminal of the operational amplifier OPA is connected to the gates of the switching transistors M32 and M30 and then grounded.

2. The low-current mismatch, wide-output swing, and programmable charge pump circuit according to claim 1, characterized in that, the gates of the switching transistors M13 and M15 are connected and then connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to VDD.

3. The low-current mismatch, wide-output swing, and programmable charge pump circuit according to claim 1, characterized in that, the output terminal of the operational amplifier OPA is connected to the gates of the switching transistors M32 and M30 and then grounded through a capacitor C1.

4. The low-current mismatch, wide-output swing, and programmable charge pump circuit according to claim 1, characterized in that, the output terminal of the operational amplifier OPA is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the negative input terminal of the operational amplifier OPA.

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