Current source driver circuit, analog-to-digital converter and receiver

Abstract

The current source driving circuit, the analog-digital converter and the receiver, wherein the current source driving circuit comprises: a latch circuit module, adapted to output a first latch signal and a first latch inverted signal based on a first input signal, and output a second latch signal and a second latch inverted signal based on a second input signal; a differential complementary circuit module comprising two complementary switch group sub-modules, any switch group sub-module being coupled with one of a first current source branch and a second current source branch; and a driving circuit module, adapted to output a plurality of switch control signals to the switch group sub-modules of the differential complementary circuit module based on the first latch signal, the first latch inverted signal, the second latch signal and the second latch inverted signal, so that at any time, there is a switch in a conducting state in the switch group sub-module corresponding to any current source branch, to drive the current source in the corresponding current source branch. The above scheme can avoid current source reconstruction.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of electronic circuit technology, and in particular to a current source drive circuit, an analog-to-digital converter, and a receiver. Background Technology

[0002] Receivers can be categorized into superheterodyne, zero-IF, and low-IF (IF) receivers based on their architecture. Currently, zero-IF and IF receivers are commonly used, each with its own advantages and disadvantages. Wi-Fi communication typically uses zero-IF receivers, while Bluetooth and some narrowband communications usually use IF receivers.

[0003] Reference Figure 1 The diagram shows a low-IF receiver structure that can be applied in Bluetooth / Bluetooth Low Energy (BT / BLE) modules. The low-IF receiver 10 can be composed of a low-noise amplifier (LNA), transconductance (gm), mixer, transimpedance amplifier (TIA), complex filter 1A, and analog-to-digital converter (ADC). The low-IF receiver 10 can be coupled to the physical layer (PHY). After the radio frequency signal is received by the antenna, it is amplified by the LNA and demodulated to obtain two quadrature signals: an in-phase (I) input signal and a quadrature (Quadrature) input signal. For the I and Q input signals, the voltage input signal is converted into a current output signal by the gm. The current-form RF signal is down-converted to a low intermediate frequency by a mixer, and the down-converted current signal is converted into a voltage output signal by the TIA. The complex filter IA filters out out-of-band noise and interference. Then, the ADC converts the received analog signal into a digital signal and outputs it to the PHY for signal modulation, demodulation and other processing. There are generally two implementation methods for ADCs: successive approximation analog-to-digital converters (SAR ADCs) and Σ-Δ (Sigma-Delta, SD) modulation ADCs. Considering power consumption and complexity, SAR ADCs are often chosen.

[0004] With the rise of applications such as the Internet of Things (IoT) and True Wireless Stereo (TWS), higher demands are being placed on the power consumption of BT / BLT products. To reduce power consumption, [measurements are often made to...]. Figure 1The low-IF receiver with the structure shown is improved. For example... Figure 2 The schematic diagram of another low-IF receiver shown is similar to... Figure 1 The difference is that it can Figure 1 The complex filter 1A and SAR ADC in the model are implemented using a complex continuous-time SDADC (Complex CT SDADC) 2A, which saves the complex filter 1A.

[0005] While using a complex continuous-time SDADC can reduce system power consumption, mismatch between the in-phase quadrature (IQ) channels is a significant problem. This mismatch generates a mirror signal at negative frequencies, thus degrading system demodulation performance. Among all mismatches in the IQ channels, the mismatch in the feedback analog-to-digital converter (DAC) has the largest impact.

[0006] To solve the mismatch problem between the I and Q channels, the circuit design can be further optimized. One common way to eliminate the mismatch between the I and Q feedback DACs is to swap the DAC current sources of the I and Q channels according to a certain rule.

[0007] Multi-bit feedback DACs are commonly used in low-power SD ADC designs. However, mismatch in multi-bit DACs is a serious problem, severely degrading modulator performance. Therefore, for the DACs in the I or Q channels, it is necessary to randomly select DAC units according to certain requirements to break down the mismatch into noise, and then use noise shaping to push it to higher frequencies, thereby improving modulator performance. Therefore, in addition to swapping the DACs in the I and Q channels, the DAC units in the I and Q channels also need to be switched. Current-controlled DACs are one of the common DAC implementation methods.

[0008] However, one problem with the above implementation is that it is difficult to guarantee that the switches connected to each current source will not be turned off simultaneously under any input. This may result in the current source needing to be re-established, which in turn leads to a degrade in the performance of the complex continuous-time SDADC. Summary of the Invention

[0009] In view of this, embodiments of this specification provide a current source drive circuit, an analog-to-digital converter, and a receiver, which enable the current source to be re-established under any circumstances, thereby improving the stability of the current source drive circuit and thus improving the performance of the analog-to-digital converter and receiver using it.

[0010] First, this specification provides a current source driving circuit, suitable for driving a current source, the current source driving circuit including:

[0011] The latch circuit module is adapted to output a first latch signal and a first latch inverted signal based on a first input signal, and to output a second latch signal and a second latch inverted signal based on a second input signal;

[0012] A differential complementary circuit module includes two complementary switch group sub-modules, wherein each switch group sub-module is coupled to one of the first current source branch and the second current source branch, and the switch group sub-module includes multiple coupled switches.

[0013] The driving circuit module is coupled to the latching circuit module and the differential complementary circuit module respectively, and is adapted to output a multiplexed switch control signal to the switch group submodule of the differential complementary circuit module based on the first latching signal, the first latching inverted signal, the second latching signal and the second latching inverted signal, so that at any time, there is a switch in the switch group submodule corresponding to any current source branch that is in the on state to drive the current source in the corresponding current source branch.

[0014] This specification also provides an analog-to-digital converter, including: a first input path, a second input path, and a feedback path, wherein:

[0015] The first input path is adapted to obtain a first output signal based on the first input signal and the first feedback signal output by the feedback path;

[0016] The second input path is adapted to obtain a second output signal based on the second input signal and the second feedback signal output by the feedback path;

[0017] The feedback path, coupled to the first input path and the second input path respectively, includes:

[0018] First current source branch;

[0019] Second current source branch;

[0020] The current source driving circuit described in any embodiment of this specification has a first input terminal coupled to the output terminal of the first input path, and uses the first output signal output by the first input path as the first input signal of the feedback path; its second input terminal coupled to the output terminal of the second input path, and uses the second output signal output by the second input path as the second input signal of the feedback path; based on the first input signal and the second input signal, the first feedback path digital-to-analog converter and the first current source branch are turned on, and the second feedback path digital-to-analog converter and the second current source branch are turned on.

[0021] The feedback path digital-to-analog converter is adapted to output the first feedback signal to the first input path and output the second feedback signal to the second input path based on the switching control of the current source drive circuit.

[0022] This specification also provides an embodiment of a receiver, including:

[0023] The demodulation device is suitable for demodulating radio frequency input signals to obtain in-phase and quadrature first and second input signals;

[0024] The analog-to-digital converter described in any embodiment of this specification is adapted to perform analog-to-digital conversion on the first input signal and the second input signal to obtain a first path output signal and a second path output signal.

[0025] The current source driving circuit provided in the embodiments of this specification includes a latching circuit module, a driving circuit module, and a differential complementary circuit module. The differential complementary circuit module includes two complementary switch group sub-modules. Each switch group sub-module is coupled to one of the first and second current source branches. The switch group sub-module includes multiple coupled switches. Based on the first input signal, the latching circuit module outputs a first latch signal and a first latch inverted signal, and based on the second input signal, outputs a second latch signal and a second latch. The inverted signal is then used by the drive circuit module to output multiple switching signals to the switch group submodule of the differential complementary circuit module based on the first latch signal, the first latch inverted signal, the second latch signal, and the second latch inverted signal. This ensures that at any given time, a switch in the switch group submodule corresponding to any current source branch is in the on state to drive the current source in the corresponding current source branch. In other words, all switches connected to the current source will not be turned off simultaneously. Therefore, the current source does not need to be re-established under any circumstances, thereby improving the performance of the analog-to-digital converter and receiver using it.

[0026] Furthermore, the driving circuit module includes a logic control submodule and two non-overlapping clock submodules coupled to the logic control submodule and having the same structure. The logic control submodule performs a preset logical operation based on the first latch signal and the second latch signal, outputting a first control signal and a second control signal. Then, the two non-overlapping clock submodules, based on the input first latch signal, the first latch inverted signal, the first control signal, and the second control signal, respectively, output multiplexed switch control signals to the corresponding switch group submodules. Therefore, by controlling the operational logic of the logic control submodule, the two non-overlapping clocks can be controlled to... Since a switch in the submodule is always in the ON state, there is always a current source in the first current source branch and the second current source branch that is in the ON state. This means that the current source does not need to be re-established under any circumstances. For analog-to-digital converters using the current source drive circuit in the embodiments of this specification, the current source is driven by the current source drive circuit. Since there is always a current source in the first current source branch and the second current source branch that is in the ON state, the current source reconstruction can be avoided during the process of eliminating the mismatch of the analog-to-digital converter by exchanging the first current source and the second current source in the feedback path of the analog-to-digital converter. Therefore, the performance of the analog-to-digital converter and the receiver using it can be improved.

[0027] Furthermore, since each current source branch includes a first current source and a second current source coupled between the power supply and ground with opposite current flows, and each current source branch includes two output terminals with opposite current flows, and the switch group submodule includes a control switch coupled between the first current source and the second current source on the corresponding current source branch, bidirectional switching of current flow can be achieved for any current source branch at any time.

[0028] Furthermore, the logic control submodule includes an XOR gate unit, a first delay unit, and a second delay unit coupled in sequence. The XOR gate unit has a first input terminal adapted to input the first latch signal, a second input terminal adapted to input the second latch signal, and an output terminal coupled to the input terminal of the first delay unit and the first input terminal of the second delay unit, respectively. The output terminal of the first delay unit is adapted to output the first control signal, and the output terminal of the second delay unit is adapted to output the second control signal. The delay duration of the second delay unit is less than the delay duration of the first delay unit. Since the first control signal and the second control signal have the delay duration of the second delay unit, controlling the two non-overlapping clock submodules with the first and second control signals ensures that at any given time, a switch in the corresponding current source branch's switch group submodule is in a conducting state, thus activating the current source coupled to it.

[0029] Furthermore, the non-overlapping clock submodule includes two identical and coupled non-overlapping clock units. Each non-overlapping clock unit includes a third delay unit, a second NAND gate unit, a first NOR gate unit, and a fourth NOT gate. On one hand, the first control signal and the output signal of the third delay unit are input to the second NAND gate unit, and the output terminal of the second NAND gate unit outputs a corresponding switch control signal to control the on / off state of the control switch of the current source branch coupled to it. On the other hand, the second control signal and the output signal of the third delay unit are input to the first NOR gate unit, and the first NOR gate unit is coupled to the fourth NOT gate. The fourth NOT gate outputs a switch control signal to the control switch coupled to it to control the on / off state of the control switch of the current source branch coupled to it. In this way, at any given time, there is a switch coupled to the non-overlapping clock submodule in both the first current source branch and the second current source branch that is in the on state, conducting the corresponding current source. This can prevent the current source reconstruction from occurring during the exchange of the first input signal and the second input signal in the analog-to-digital converter.

[0030] Furthermore, when the first current source branch and the second current source branch respectively include a first current source and a second current source with opposite current flows, and each current source branch includes two output terminals with opposite current flows, the non-overlapping clock unit further includes a fifth NOT gate and a sixth NOT gate. The fifth NOT gate is coupled to the output terminal of the second NAND gate, and the sixth NOT gate is coupled to the output terminal of the fourth NOT gate. By outputting control signals to the control switches coupled to the current sources and the output terminals of the corresponding current source branches through the non-overlapping clock unit, the on / off state and flow direction of the current sources in the corresponding current source branches can be controlled. This ensures that during the exchange of the first input signal and the second input signal of the analog-to-digital converter, both the first current source branch and the second current source branch have current sources in a conducting state, thereby avoiding current source reconstruction.

[0031] Furthermore, the third delay unit includes an AND gate, a fourth delay unit, and a seventh NOT gate coupled in sequence, wherein the output terminal of the seventh NOT gate serves as the first output terminal of the first delay unit, and the output terminal of the fourth delay unit serves as the output terminal of the third delay unit, so that the timing of the switch control signals output by the second AND gate unit and the fourth NOT gate in the non-overlapping clock unit is more synchronized, so that at any given time, at least one switch in the switch group submodule coupled to a current source is in the on state.

[0032] Furthermore, by setting the delay duration of the first delay unit to be greater than that of the fourth delay unit, and by adjusting the delay times of the first and fourth delay units according to actual applications, different conduction overlap times can be obtained.

[0033] Furthermore, the relative duration of the delay in the drive circuit depends only on the number of logic gates, making it less susceptible to the effects of voltage, temperature, and process angle, thus exhibiting better robustness.

[0034] Furthermore, through a time delay calibration module coupled to the first delay unit and the fourth delay unit respectively, the initial delay duration of the fourth delay unit is set to a fixed value, and the delay adjustment step size of the first delay unit is 1 / 2 of the total adjustment step size. N The preset test clock signal is input to the delay calibration module, so that the first delay unit accumulates and counts until the output of the delay calibration module meets the preset conditions. The duration corresponding to the first delay unit is used as the delay duration of the first delay unit in the current source drive circuit. This can minimize the absolute value of the difference between the delay duration of the first delay unit and the fourth delay unit, thereby reducing the delay of the entire current source drive circuit. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of a low-intermediate frequency receiver is shown.

[0037] Figure 2 A schematic diagram of another low-intermediate frequency receiver is shown;

[0038] Figure 3 A schematic diagram of a complex continuous-time SDADC is shown.

[0039] Figure 4 A schematic diagram of a current source drive circuit according to an embodiment of this specification is shown;

[0040] Figure 5 A schematic diagram of a latch circuit module in an embodiment of this specification is shown;

[0041] Figure 6 A schematic diagram showing the connection relationship between the modules of a current source drive circuit in an embodiment of this specification is shown.

[0042] Figure 7 A schematic diagram of a differential complementary circuit module in an embodiment of this specification is shown.

[0043] Figure 8 A schematic diagram of the structure of a drive circuit module in an embodiment of this specification is shown;

[0044] Figures 9A-9D The diagram shows the waveforms of the input signal switching process and the corresponding switch group submodule's switching control signals in the embodiments of this specification.

[0045] Figure 10 A schematic diagram of the structure of a time delay calibration module in an embodiment of this specification is shown;

[0046] Figure 11 An embodiment of this specification is shown. Figure 10 The flowchart shown corresponds to the automatic calibration module for the time delay calibration module.

[0047] Figure 12 A schematic diagram of the structure of an analog-to-digital converter according to an embodiment of this specification is shown;

[0048] Figure 13 A schematic diagram of another analog-to-digital converter in an embodiment of this specification is shown;

[0049] Figure 14 A schematic diagram of the structure of a receiver according to an embodiment of this specification is shown. Detailed Implementation

[0050] As described in the background section, the mismatch between the I and Q channels of complex continuous-time SDADCs is a significant problem. This mismatch generates a mirror signal at negative frequencies, thus reducing the system's demodulation performance. Among all the mismatches in the I and Q channels, the mismatch in the DAC used for feedback has the largest impact.

[0051] Figure 3 A schematic diagram of a complex continuous-time SDADC is shown, wherein the SDADC 30 includes an in-phase signal input path 31, a quadrature signal input path 32, and a feedback path 33, wherein:

[0052] The in-phase signal input path 31 is adapted to obtain a first output signal outI based on the first input signal inI and the first feedback signal I output by the feedback path;

[0053] The orthogonal signal input path 32 is adapted to obtain a second output signal outQ based on the second input signal inQ and the second feedback signal Q output by the feedback path;

[0054] More specifically, both the in-phase input path 31 and the quadrature signal input path 32 include an adder, a filter, and a quantizer, wherein:

[0055] In the in-phase signal input path 31, the adder accumulates the first input signal inI and the first feedback signal I fed back by the feedback path. The filter, together with other modules in the loop, performs filtering to eliminate quantization noise. The quantizer quantizes the continuous signal output by the filter into a discrete signal, completing the basic function of analog-to-digital conversion.

[0056] The feedback path 33 is coupled to the in-phase signal input path 31 and the quadrature signal input path 32, respectively, and includes a data weighted averaging (DWA) module, a drive circuit, and a feedback digital-to-analog converter DCI+DACQ shared by the I and Q paths, wherein:

[0057] The DWA module mainly transforms the digital signal output by the quantizer and then sends it to the DCI+DACQ. Under the control of the driving circuit, the feedback digital-to-analog converters DCI+DACQ respectively feed back the first feedback signal I to the in-phase signal input path 31 and the second feedback signal Q to the quadrature signal input path 32.

[0058] A common method to eliminate the mismatch between the I and Q feedback DACs is to swap the current sources of the I and Q DACs according to a certain rule (not shown). One specific approach is to swap the current sources of the I and Q DACs when the input signals of the I and Q feedback DACs are the same, and not to swap the current sources of the I and Q DACs when the input signals of the I and Q feedback DACs are different.

[0059] Multi-bit feedback DACs are commonly used in low-power SD ADC designs. However, mismatch in multi-bit DACs is a serious problem, severely degrading modulator performance. Therefore, for the DACs in the I or Q channels, it is necessary to randomly select DAC units according to certain requirements to break down the mismatch into noise, which is then shaped to push the signal to higher frequencies. Thus, in addition to swapping the DACs in the I and Q channels, the DAC units in the I and Q channels also need to be switched. Current-controlled DACs are one of the common DAC implementation methods.

[0060] However, the above implementation method brings a problem: the switching of the IQ current source itself and the switching of the exchange current source will increase the number of switches. At the same time, it is difficult to guarantee that the switches connected to each current source will not be turned off at the same time under any input, which will cause the current source to need to be re-established, thus leading to a decrease in the demodulation performance of the complex continuous-time SDADC.

[0061] To ensure that the current source does not need to be re-established under any circumstances, thereby improving the stability of the current source drive circuit and ultimately enhancing the performance of the ADC, this specification provides a current source drive circuit, including a latch circuit module, a drive circuit module, and a differential complementary circuit module coupled in sequence. The differential complementary circuit module includes two complementary switch group sub-modules, each of which is coupled to one of the first and second current source branches. Each switch group sub-module includes multiple coupled switches. Based on the first input signal, the latch circuit module outputs a first latch signal and a first latch inverted signal, and based on the first input signal... The system receives two input signals and outputs a second latch signal and a second latch inverted signal. The drive circuit module then outputs multiple switching signals to the switch group submodule of the differential complementary circuit module based on the first latch signal, the first latch inverted signal, the second latch signal, and the second latch inverted signal. This ensures that at any given time, a switch in the switch group submodule corresponding to any current source branch is in the ON state to drive the current source in the corresponding current source branch. In other words, all switches connected to the current source will not be turned off simultaneously. Therefore, the current source does not need to be re-established under any circumstances, thereby improving the performance of the analog-to-digital converter and receiver using it.

[0062] To enable those skilled in the art to better understand and implement the embodiments of this specification, the implementation principles are described in detail below with reference to the accompanying drawings and specific application circuits.

[0063] Reference Figure 4 The schematic diagram of the current source drive circuit shown is illustrated in the embodiments of this specification, such as... Figure 4 As shown, the current source driving circuit 40 is adapted to drive a current source. More specifically, it can drive the current sources on the first current source branch 4A and the second current source branch 4B respectively. The current source driving circuit 40 may include: a latching circuit module 41, a differential complementary circuit module 43, and a driving circuit module 42, wherein:

[0064] The latch circuit module 41 is adapted to output a first latch signal data1p and a first latch inverted signal data1n based on a first input signal data1, and to output a second latch signal data2p and a second latch inverted signal data2n based on a second input signal data2.

[0065] The differential complementary circuit module 43 includes two complementary switch group sub-modules (e.g., the first switch group sub-module 431 and the second switch group sub-module 432), wherein each switch group sub-module is coupled to one of the current source branches of the first current source branch 4A and the second current source branch 4B, and the switch group sub-module includes multiple coupled switches.

[0066] The driving circuit module 42 is coupled to the latch circuit module 41 and the differential complementary circuit module 43 respectively. It is adapted to output multiple switch control signals (e.g., multiple switch control signals SWi, SWj) to the switch group sub-modules of the differential complementary circuit module 43 (e.g., the first switch group sub-module 431 and the second switch group sub-module 432) based on the first latch signal data1p, the first latch inverted signal data1n, the second latch signal data2p, and the second latch inverted signal data2n. This ensures that at any given time, a switch in the switch group sub-module corresponding to any current source branch (e.g., the first current source branch 4A and the second current source branch 4B) is in the on state, thereby driving the current source in the corresponding current source branch (e.g., the first current source branch 4A or the second current source branch 4B).

[0067] Using the aforementioned current source drive circuit, the latch module 41 outputs the first latch signal data1p, the first latch inverted signal data1n, the second latch signal data2p, and the second latch inverted signal data2n based on the first input signal data1 and the second input signal data2. The drive circuit module 42 then outputs multiplexed switch control signals to the switch group submodules in the differential complementary circuit module 43 based on these signals. Since either of the two complementary switch group submodules in the differential complementary circuit module 43 is connected to one of the first current source branch or the second current source branch... The current source branches are coupled, and the switch group submodule includes multiple coupled switches. Therefore, regardless of whether the first input signal data1 and the second input signal data2 are the same or different, or during the switching process of the first input signal data1 and the second input signal data2, through the cooperation of the driving circuit module 42, the latching circuit module 41 and the differential complementary circuit module 43, a switch in the switch group submodule corresponding to the first current source branch and the second current source branch can be in the conducting state. That is, at any time, under any signal of the first input signal and the second input signal, the current source in any current source branch driven by the current source driving circuit 40 will not be turned off, thus avoiding the current source from being re-established, thereby enhancing the performance of the ADC using it.

[0068] To enable those skilled in the art to better understand and implement this system, the following illustrates specific circuit structures that ensure at any given time, a switch in the corresponding switch group submodule of any current source branch is in the ON state to drive the current source in the corresponding current source branch. Examples of the circuit structures for the latch circuit module, differential complementary circuit module, and drive circuit module are provided below.

[0069] In a specific implementation, the latch circuit module may include two latch sub-modules with identical structures, wherein each latch sub-module has an input terminal adapted to receive the first input signal or the second input signal, a first output terminal adapted to output a latch signal in phase with the corresponding input signal, and a second output terminal adapted to output a latch signal out of phase with the corresponding input signal.

[0070] In a specific example of this specification, the latch submodule includes: a first NOT gate, a second NOT gate, and a latch connected in sequence, wherein: the first input terminal of the latch is coupled to the output terminal of the first NOT gate, the second input terminal of the latch is coupled to the output terminal of the second NOT gate, the first output terminal of the latch is adapted to output the latch signal of the corresponding path, and the second output terminal of the latch is adapted to output the latch inverted signal of the corresponding path.

[0071] Reference Figure 5 The circuit diagram shown is of a latch circuit module 50. The latch circuit module 50 includes two identical first latch submodules 51 and second latch submodules 52, wherein:

[0072] The first latch submodule 51 includes: a first NOT gate NOT11, a second NOT gate NOT12, and a first latch 51A, which are coupled in sequence. The first NOT gate NOT11 outputs a first delayed inverted signal m based on the first input signal data1 after a delay. The second NOT gate NOT12 outputs a second delayed inverted signal n based on the first delayed inverted signal m after a delay. The first input terminal of the first latch 51A is coupled to the output terminal of the first NOT gate NOT11, and the second input terminal of the first latch 51A is coupled to the output terminal of the second NOT gate NOT12. The first output terminal of the first latch 51A is adapted to output the latch signal of the corresponding path, i.e., the first latch signal data1p, and the second output terminal of the first latch 51A is adapted to output the latch inverted signal of the corresponding path, i.e., the first latch inverted signal data1n.

[0073] As a specific example, the first latch 51A may specifically include: a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM4, and a fourth NMOS transistor NM4, wherein: the gate of the third NMOS transistor serves as the first input terminal of the first latch 51A, adapted to input the first delayed inverted signal m; the gate of the fourth NMOS transistor NM4 serves as the second input terminal of the first latch 51A, adapted to input the second delayed inverted signal n; the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both coupled to the power supply VCC; the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM4, and the fourth NMOS transistor NM4 serve as the second input terminal of the first latch 51A, adapted to input the second delayed inverted signal n; the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both coupled to the power supply VCC; the first NMOS transistor NM1, the second NMOS transistor NM2, and the fourth NMOS transistor NM4 serve as the second input terminal of the first latch 51A, adapted to input the second delayed inverted signal n; the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both coupled to the power supply VCC; the first NMOS transistor NM1, the second NMOS transistor PM ... PM2 serve as the second input terminal of the first latch 51A, adapted to input the second delayed inverted signal n; the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both coupled to the power supply VCC; the first NMOS transistor The drains of the body transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 are all coupled to ground; the source of the first NMOS transistor NM1, the source of the third NMOS transistor NM3, the drain of the first PMOS transistor PM1, the gate of the second NMOS transistor NM2, and the gate of the second PMOS transistor PM2 are cross-coupled and adapted to output the first latch signal data1p; the source of the second NMOS transistor NM2, the source of the fourth NMOS transistor NM4, the drain of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, and the gate of the first PMOS transistor PM1 are cross-coupled and adapted to output the first latch inverted signal data1n.

[0074] Similarly, the second latch submodule 52 may include the same circuit structure as the first latch submodule 51. As a specific example, the second latch submodule 52 may include: a third NOT gate NOT21, a fourth NOT gate NOT22, and a second latch 52A coupled in sequence, wherein: the third NOT gate NOT21 outputs a third delayed inverted signal x based on the second input signal data2; the fourth NOT gate NOT22 outputs a fourth delayed inverted signal y based on the third delayed inverted signal x; the first input terminal of the second latch 52A is coupled to the output terminal of the third NOT gate NOT21 and is adapted to input the third delayed inverted signal x; the second input terminal of the second latch 52A is coupled to the output terminal of the fourth NOT gate NOT22 and is adapted to input the fourth delayed inverted signal y; the first output terminal of the second latch 52A is adapted to output the latch signal of the corresponding path, i.e., the second latch signal data2p; and the second output terminal of the second latch 52A is adapted to output the latch inverted signal of the corresponding path, i.e., the second latch inverted signal data2n.

[0075] Continue to refer to Figure 5The second latch 52A may have the same structure as the first latch 51A. As a specific example, the second latch 52A may include: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8, wherein: the gate of the seventh NMOS transistor is adapted to input the third delayed inverted signal x; the gate of the eighth NMOS transistor NM8 is adapted to input the fourth delayed inverted signal y; the sources of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both coupled to the power supply VCC; the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6... The drains of the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are both coupled to ground; the source of the fifth NMOS transistor NM5, the source of the seventh NMOS transistor NM7, the drain of the third PMOS transistor PM3, the gate of the sixth NMOS transistor NM6, and the gate of the fourth PMOS transistor PM4 are cross-coupled and adapted to output the second latch signal data2p; the source of the sixth NMOS transistor NM6, the source of the eighth NMOS transistor NM8, the drain of the fourth PMOS transistor PM4, the gate of the fifth NMOS transistor NM5, and the gate of the seventh PMOS transistor PM7 are cross-coupled and adapted to output the second latch inverted signal data2n.

[0076] Using the above-described latch circuit module, intermediate node signals m, n, x, and y are generated based on the input signals data1 and data2, respectively. Based on these intermediate node signals m, n, x, and y, output signals data1p, data1n, data2p, and data2n are obtained. With this latch circuit module, since the first NOT gate NOT11, the second NOT gate NOT12, the third NOT gate NOT21, and the fourth NOT gate NOT22, as well as the first latch 51A and the second latch 52A, are all basic circuit units, the edge delays of the first latched signal data1p and the first latched inverted signal data1n, as well as the edge delays of the second latched signal data2p and the second latched inverted signal data2n, can be reduced. This further improves the switching performance and efficiency during the switching process between the first input signal data1 and the second input signal data2.

[0077] In specific implementations, the first latch 51A and the second latch 52A can also adopt latches with other structures, as long as they can output synchronously inverted first latch signals data1p and data1n based on the first delayed inverted signal m and the second delayed inverted signal n, and output synchronously inverted second latch signals data2p and data2n based on the third delayed inverted signal x and the fourth delayed inverted signal y.

[0078] It is understood that the latch circuit module can also be other forms of latch structure. In a specific embodiment of this specification, the two latch sub-modules with identical structures in the latch circuit module can be composed of only two NOT gates connected in series. Specifically, refer to... Figure 5 The first latch submodule 51 may consist only of a first NOT gate NOT11 and a second NOT gate NOT12 connected in series; the second latch submodule 52 may consist only of a third NOT gate NOT21 and a fourth NOT gate NOT22 connected in series. In this embodiment, the output signal m of the first NOT gate NOT11 can be directly used as the first latched inverted signal data1n, and the output signal n of the second NOT gate NOT12 can be used as the first latched signal data1p; and the output signal x of the third NOT gate NOT21 can be directly used as the second latched inverted signal data2n, and the output signal y of the fourth NOT gate NOT22 can be used as the second latched signal data2p. In specific implementation, the timing of the first latched signal data1p, the first latched inverted signal data1n, the second latched signal data2p, and the second latched inverted signal data2n can be adjusted in the subsequent drive circuit module to keep the timing of the four synchronized.

[0079] To enable those skilled in the art to better understand and implement some example schemes in the embodiments of this specification, which drive the current source in the corresponding current source branch by ensuring that at any given time, a switch in the switch group submodule corresponding to any current source branch is in the conducting state, thereby avoiding current source reconstruction.

[0080] Figure 6 A schematic diagram showing the connection relationship of various modules in a current source drive circuit is provided. Figure 7 A schematic diagram of a differential complementary circuit module is shown. Figure 8 A schematic diagram of a drive circuit module is shown below. Figures 6 to 8 The driving principle of the current source drive circuit is explained in detail.

[0081] In some embodiments of this specification, the differential complementary circuit module can be a fully differential complementary circuit module or a half differential complementary circuit module. For example... Figure 7 The diagram illustrates a fully differential complementary circuit module, wherein a fully differential complementary circuit 70 is coupled to a first current source branch and a second current source branch, respectively, to form fully differential complementary current sources. The first current source branch I1 includes: a first current source Ip1 and a second current source In1 coupled between the power supply VCC and ground, with opposite current flows. The second current source branch includes: a first current source Ip2 and a second current source In2 coupled between the power supply VCC and ground, with opposite current flows. The first and second current source branches each include two output terminals with opposite current flows. Specifically, as shown... Figure 7 As shown, the first current source branch includes: a first output terminal iop1 and a second output terminal ion1 with current flowing in opposite directions; the second current source branch includes: a first output terminal iop2 and ion2 with current flowing in opposite directions.

[0082] like Figure 6 The diagram illustrates a current source driving circuit. The current source driving circuit 60 includes a latching circuit module 61, a driving circuit module 80, and a differential complementary current source 70. The differential complementary current source integrates a differential complementary circuit module, a first current source branch, and a second current source branch. Its working principle is explained below based on the signal flow direction:

[0083] The latch circuit module 61 can output a first latch signal data1p and a first latch inverted signal data1n based on the first input signal data1, and output a second latch signal data2p and a second latch inverted signal data2n based on the second input signal data2. Furthermore, the drive circuit module 62 outputs 16 switching control signals (swn1_o, swn1_inv_o, swp1_o, swp1_o, ex_swn1_o, ex_swn1_o, ex_swn1_inv_o, ex_swp1_o, ex_swp1_o, ex_swp1_inv_o, swn2_o, swn2_inv_o, swp2_o, ex_swn2_o, ex_swn2_inv_o, ex_swp2_o, ex_swp2_inv_o, ex_swn2_o, ex_swn2_inv_o, ex_swp2_o, ex_swp2_inv_o) to the differential complementary current source 70 based on the first latch signal data1p, the first latch inverted signal data1n, the second latch signal data2p, and the second latch inverted signal data2n.

[0084] In practical implementation, any switch group submodule in the differential complementary circuit module can include: an on-switch unit and a switching unit, wherein:

[0085] The switching unit includes a current source coupled to the corresponding current source branch and the output terminal of the corresponding current source branch, and is adapted to conduct the current source output path formed by the current source on the corresponding current source branch and the output terminal of the corresponding branch based on the received switch enable control signal.

[0086] The switching unit is coupled between the output terminals of different current source branches and is adapted to switch the output terminal of the current source coupled to it based on the received switch enable control signal.

[0087] As can be seen from the above, the conducting switch unit includes multiple conducting switches, and the switching switch unit includes multiple switching switches.

[0088] Continue to refer to Figure 6 and Figure 7 As shown, in Figure 7 In the fully differential complementary circuit module 7A shown, multiple MOS transistors coupled between the first current source branch and the second current source branch are used as on switches or switching switches to form a fully differential complementary current source 70, which includes multiple N-type transistors and P-type transistors. To distinguish them from the transistors in the aforementioned latching circuit module, the NMOS transistors in the fully differential complementary circuit module are uniformly referred to as N-type switching transistors, or simply N-type transistors, and the PMOS transistors in the fully differential complementary circuit module are uniformly referred to as P-type switching transistors, or simply P-type transistors.

[0089] Specifically, such as Figure 7As shown, in the fully differential complementary circuit 70, the first N-type transistor N1, the second N-type transistor N2, the first P-type transistor P1, and the second P-type transistor P2 act as conducting switches, forming a first complementary fully differential current source I01 with the current sources I1p and I1n of the first current source branch I1. Here, swn1, swp1, swn1_inv, and swp1_inv are switch enable control terminals. The switch enable control terminals swn1 and swn1_inv receive complementary signals, and the switch enable control terminals swp1 and swp1_inv receive complementary signals. The third N-type transistor N3, the fourth N-type transistor N4, and the third... P-type transistor P3 and the fourth P-type transistor P4, along with the current sources I2p and I2n of the second current source branch I2, form the second complementary fully differential current source I02. Here, swn2, swp2, swn2_inv, and swp2_inv are switch enable control terminals. The switch enable control terminals swn2 and swn2_inv receive complementary signals, as do the switch enable control terminals swp2 and swp2_inv. The outputs of the complementary fully differential current sources Ip1 and In1 are iop1 and ion1, respectively; the outputs of the complementary fully differential current sources Ip2 and In2 are iop2 and ion2, respectively. The fifth N-type transistor N5, the sixth N-type transistor N6, the seventh N-type transistor N7, the eighth N-type transistor N8, and the fifth P-type transistor P5, the sixth P-type transistor P6, the seventh P-type transistor P7, and the eighth P-type transistor P8 serve as switching switches for the first complementary fully differential current source I01 and the first complementary fully differential current source I02. ex_swn1, ex_swp1, ex_swn2, ex_swp2, ex_swn1_inv, ex_swp1_inv, ex_swn2_inv, and ex_swp2_inv are the enable control terminals of the switching switches.

[0090] The following is for reference Figure 8 The schematic diagram of the driving circuit module shown illustrates a specific scheme in which the driving circuit module controls the switching of the switches in the differential circuit module based on the signal output by the latching circuit module, so that at any given time, there is a switch in the switch group submodule corresponding to any current source branch that is in the conducting state.

[0091] In some embodiments of this specification, such as Figure 8 As shown, the drive circuit module 80 includes: logic control

[0092] The driving circuit module includes: a logic control submodule 81, and two non-overlapping clock submodules coupled to the logic control submodule and having the same structure, namely a first non-overlapping clock submodule 82 and a second non-overlapping clock submodule 83, wherein:

[0093] The logic control submodule 81 is adapted to perform preset logic operations based on the first latch signal data1p and the second latch signal data2p, and output the first control signal a and the second control signal b.

[0094] The two non-overlapping clock submodules respectively output switch control signals to the complementary switch group submodules. For any non-overlapping clock submodule, it is adapted to output multiple switch control signals to the switch group submodule corresponding to the corresponding current source branch based on the latch signal, latch inverted signal, first control signal a, and second control signal b input from the corresponding latch submodule, so that at any given time, a switch in the switch group submodule corresponding to the corresponding current source branch is in the on state.

[0095] Specifically, such as Figure 8 As shown, the first non-overlapping clock submodule 82 is adapted to output multiple switch control signals to the switch group submodule corresponding to the first current source branch I1 based on the input first latch signal data1p, the first latch inverted signal data1n, the first control signal a and the second control signal b, so that there is a switch in the switch group submodule corresponding to the first current source branch I1 in the on state at any time.

[0096] The second non-overlapping clock submodule 83 is adapted to output multiple switch control signals to the switch group submodule corresponding to the second current source branch I2 based on the input second latch signal data2p, the second latch inverted signal data2n, the first control signal a and the second control signal b, so that at any time, there is a switch in the switch group submodule corresponding to the second current source branch I2 in the on state.

[0097] In some embodiments of this specification, reference continues to be made to... Figure 8 The logic control submodule 81 may include: an XOR gate, a first delay unit delay1, and a second delay unit delay2, wherein:

[0098] The XOR gate unit has a first input terminal adapted to input the first latch signal data1p, a second input terminal adapted to input the second latch signal data2p, and its output terminal coupled to the input terminal of the first delay unit delay1 and the first input terminal of the second delay unit delay2, respectively.

[0099] The first delay unit delay1 has its input terminal coupled to the output terminal of the XOR gate unit, and its output terminal is adapted to output the first control signal a, and is coupled to the second input terminal of the second delay unit delay2.

[0100] The second delay unit delay2 is adapted to output the second control signal b;

[0101] Wherein: the delay duration of the second delay unit delay2 is less than the delay duration of the first delay unit delay1.

[0102] As a specific example, the second delay unit delay2 includes: a first NAND gate unit NAND1 and a fifth NOT gate NOT5, wherein:

[0103] The first NAND gate unit NAND1 has a first input terminal adapted to be coupled to the output terminal of the XOR gate unit XOR and the input terminal of the first delay unit delay1, a second input terminal coupled to the output terminal of the first delay unit delay1, adapted to input the first control signal a, and its output terminal coupled to the input terminal of the fifth NOT gate NOT5.

[0104] The fifth NOT gate NOT5 has its input terminal coupled to the output terminal of the first NAND gate unit NAND1, and its output terminal is adapted to output the second control signal b.

[0105] In a specific implementation, the non-overlapping clock submodule may include: two structurally identical and mutually coupled non-overlapping clock units. As a specific example, the non-overlapping clock unit may include: a third delay unit, a second NAND gate unit, a first NOR gate unit, and a sixth NOT gate, wherein:

[0106] The third delay unit has a first input terminal corresponding to the overlapping clock submodule, which is adapted to receive one of the first latch signal, the first latch inverted signal, the second latch signal, and the second latch inverted signal. Its second input terminal is adapted to be coupled to the output terminal of the third delay unit of another non-overlapping clock unit in the same non-overlapping submodule. It includes two inverted first output terminals and second output terminals. The delay duration of the third delay unit is less than the delay duration of the first delay unit and greater than the delay duration of the second delay unit.

[0107] The second NAND gate unit has a first input terminal adapted to be coupled to the first output terminal of the third delay unit, a second input terminal adapted to input the first control signal, and an output terminal adapted to output a corresponding switch control signal to the control switch coupled thereto, thereby controlling the on / off state of the control switch coupled thereto.

[0108] The first NOR gate unit has a first input terminal adapted to be coupled to the second output terminal of the third delay unit, a second input terminal adapted to input the second control signal, and an output terminal coupled to the output terminal of the sixth NOT gate.

[0109] The sixth NOT gate is adapted to output a corresponding switch control signal to the control switch coupled thereto, so as to control the on / off state of the control switch coupled thereto.

[0110] The seventh NOT gate has its input terminal coupled to the output terminal of the second NAND gate unit, and its output terminal is adapted to output a corresponding switch control signal to the control switch coupled thereto, so as to control the on / off state of the control switch coupled thereto.

[0111] The eighth NOT gate has its input terminal adapted to be coupled to the output terminal of the sixth NOT gate, and its output terminal adapted to output a corresponding switch control signal to the control switch coupled thereto, thereby controlling the on / off state of the control switch coupled thereto.

[0112] As a specific example, the third delay unit may include: an AND gate, a fourth delay unit, and a ninth NOT gate coupled in sequence, wherein: the output terminal of the ninth NOT gate serves as the first output terminal of the third delay unit, and the output terminal of the fourth delay unit serves as the second output terminal of the third delay unit.

[0113] In a specific implementation, the delay duration of the first delay unit is greater than the delay duration of the fourth delay unit.

[0114] To enable those skilled in the art to better understand and implement this method, the following references are provided. Figure 8 The specific circuit structure of the first non-overlapping clock submodule 82 is explained below.

[0115] The first non-overlapping clock submodule 82 includes: two structurally identical and mutually coupled non-overlapping clock units, namely, a first non-overlapping clock unit 82A and a second non-overlapping clock unit 82B, wherein:

[0116] The first non-overlapping clock unit 82A includes: a third delay unit delay3, a second NAND gate unit NAND2, a first NOR gate unit NOR1, a sixth NOT gate NOT6, a seventh NOT gate NOT7, and an eighth NOT gate NOT8, wherein:

[0117] The third delay unit delay3 has a first input terminal corresponding to the overlapping clock submodule, which is adapted to input the first latch signal data1p. Its second input terminal is adapted to be coupled to the output terminal of the third delay unit delay3 of the second non-overlapping clock unit 82B. It includes two inverted first output terminals and second output terminals. The delay duration of the third delay unit delay3 is less than the delay duration of the first delay unit delay1 and greater than the delay duration of the second delay unit delay2.

[0118] The second NAND gate unit NAND2 has its first input terminal adapted to be coupled to the first output terminal of the third delay unit delay3, its second input terminal adapted to input the first control signal a, and its output terminal adapted to output a corresponding switch control signal swp1_o to the control switch coupled thereto, controlling the on / off state of the control switch coupled thereto. Combined with... Figures 6 to 8 It can be seen that after the signal in the first non-overlapping clock unit 82A passes through the NAND gate NAND2, the output switch control signal is suitable for controlling the second P-type transistor P1 in the fully differential complementary circuit module 70. When its output is low, the second P-type transistor P2 is turned on, and the current source Ip1 in the first current source branch I1 can output current through the output terminal ion1.

[0119] The first NOR gate unit NOR1 has its first input terminal adapted to be coupled to the second output terminal of the third delay unit deal3, its second input terminal adapted to input the second control signal b, and its output terminal coupled to the output terminal of the sixth NOT gate NOT6. The sixth NOT gate NOT6 is adapted to output a corresponding switch control signal to the control switch coupled thereto, controlling the on / off state of the control switch coupled thereto. Figure 6 , Figure 7 and Figure 8 It can be seen that the control switch is the eighth P-type transistor P8. When the eighth P-type transistor P8 is turned on, the current source Ip1 in the first current source branch I1 can output current through the output terminal ion2.

[0120] The seventh NOT gate (NOT7) has its input coupled to the output of the second NAND gate (NAND2), and its output is adapted to output a corresponding switch control signal to the control switch coupled to it, controlling the on / off state of the control switch coupled to it. Combined with... Figures 6-8 It can be seen that the control switch is the first N-type transistor N1. When the first N-type transistor N1 is turned on, the current source In1 in the first current source branch I1 can flow into the current through the output terminal iop1.

[0121] The eighth NOT gate (NOT8) has its input terminal adapted to be coupled to the output terminal of the sixth NOT gate (NOT6), and its output terminal adapted to output a corresponding switch control signal to the control switch coupled thereto, controlling the on / off state of the control switch coupled thereto. (Combined with...) Figure 6 , Figure 7 and Figure 8 It can be seen that the control switch is the fifth N-type transistor N5. When the fifth N-type transistor N5 is turned on, the current source In1 in the first current source branch I1 can flow into the current through the output terminal iop2.

[0122] Combination Figures 6-8 It can be seen Figure 8The switching control signals output from each output terminal of the drive circuit module 80 shown are... Figure 7 The control relationship between the switches in the fully differential complementary circuit module shown can be achieved through the drive circuit module 80. Figure 7 The switches connected to any current source in the circuit will not be turned off simultaneously.

[0123] The following is a brief description of the operating characteristics of the current source drive circuit used in the embodiments of this specification.

[0124] In any case (including when the first input signal data1 and the second input signal data2 are both 1, both 0, or one is 0 and the other is 1):

[0125] 1) The N-type transistors N1, N2, N5, and N8 connected to the current source In1 will not be turned off simultaneously, that is, the switch enable control terminals swp1_inv, swn1_inv, ex_swn1_inv, and ex_swp1_inv will not be low at the same time.

[0126] 2) The N-type transistors N3, N4, N6, and N7 connected to the current source In2 will not be turned off simultaneously, that is, the switch enable control terminals swp2_inv, swn2_inv, ex_swp2_inv, and ex_swn2_inv will not be low at the same time.

[0127] 3) The P-type transistors P1, P2, P5, and P8 connected to the current source Ip1 will not be turned off at the same time, that is, the switch enable control terminals swn1, swp1, ex_swn1, and ex_swp1 will not be at a high level at the same time.

[0128] 4) The P-type transistors P3, P4, P6, and P7 connected to the current source Ip2 will not be turned off at the same time, that is, the switch enable control terminals swn2, swp2, ex_swn2, and ex_swp2 will not be at a high level at the same time.

[0129] 5) When the first input signal data1 and the second input signal data2 are the same, the current sources Ip1 and In1 of the first current source branch flow into or out of the output terminals iop1 and ion1, and the current sources Ip2 and In2 of the second current source branch flow into or out of the output terminals iop2 and ion2.

[0130] 6) When the first input signal data1 and the second input signal data2 are different, the current sources Ip1 and In1 of the first current source branch flow into or out of the output terminals iop2 and ion2, and the current sources Ip2 and In2 of the second current source branch flow into or out of the output terminals iop1 and ion1.

[0131] When the signal at the current source switch control terminal changes, the above-mentioned operating characteristics can prevent the switches connected to the current source from being closed simultaneously during the switching process between the first and second paths, which would cause the current source to need to be re-established. The current source circuit described in the embodiments of this specification can avoid this phenomenon, thus improving circuit performance.

[0132] For the first input signal data1 and the second input signal data2, as mentioned above, the possible states are: both are 0 (corresponding to a low level), both are 1 (corresponding to a high level), one of them switches from 0 to 1, and one of them switches from 1 to 0. Correspondingly, the first latch signal data1p and the second latch signal data2p are output after the corresponding delay of the latch circuit module. The first latch signal data1p is consistent with the first input signal data1, and the second latch signal data2p is consistent with the second input signal data2. (Refer to...) Figures 9A-9D The waveform diagrams of the switching control signals of the corresponding switch group submodules during the input signal switching process are shown. The voltage waveform diagrams of the switch enable signals swn1, swp1, ex_swn1 and ex_swp1 corresponding to transistors P1, P2, P5 and P8 under various conditions corresponding to the first latch signal data1p and the second latch signal data2p are shown.

[0133] Specifically, Figure 9A The diagram shows the latch signals and voltage waveforms of the corresponding switches as the first latch signal data1p remains 0 and the second latch signal data2p switches from 0 to 1. (Refer to...) Figures 6-8 and combined Figure 9A ,Depend on Figure 9A It can be seen that when both the first latch signal data1p and the second latch signal data2p are 0, the switch enable signal swn1 corresponding to transistor P1 is 0. Therefore, the first current source Ip1 coupled to it will not be turned off. During the process of the second latch signal data2p switching from 0 to 1, the current source Ip1 connected to it will not be turned off. Figure 9A It can be seen that one of transistors P2, P5, and P8 is always kept at 0, so that the first current source Ip1 coupled with it is always in the conducting state. After the switching is completed, transistor P5 is kept at 0, so that the first current source Ip1 can output current through the output terminal iop2.

[0134] Figure 9B The diagram shows the latch signals and voltage waveforms of the corresponding switches during the process of the first latch signal data1p switching from 0 to 1 and the second latch signal data2p simultaneously switching from 1 to 0, which corresponds to the case of switching current sources. (Refer to...) Figures 6-8 and combined Figure 9B ,Depend on Figure 9BIt can be seen that when the first latch signal data1p is 0 and the second latch signal data2p is 1, the switch enable signal ex_swn1 corresponding to transistor P5 is 0. Therefore, the first current source Ip1 coupled to it will not be turned off. During the process of the second latch signal data2p switching from 0 to 1, the current source Ip1 connected to it will not be turned off. Figure 9B It can be seen that transistor P5 remains at 0, so that the first current source Ip1 coupled with it is still in the conducting state. After the switching is completed, transistor P2 remains at 0, so that the first current source Ip1 can output current through the output terminal ion1.

[0135] Figure 9C The diagram shows the latch signal and voltage waveforms of the corresponding switches as the first latch signal data1p switches from 0 to 1, while the second latch signal data2p remains at 1. (Refer to...) Figures 6-8 and combined Figure 9C ,Depend on Figure 9C It can be seen that when the first latch signal data1p is 0 and the second latch signal data2p is 1, the switch enable signal ex_swn1 corresponding to transistor P5 is 0. Therefore, the first current source Ip1 coupled to it will not be turned off. During the process of the first latch signal data1p switching from 0 to 1, the current source Ip1 connected to it will not be turned off. Figure 9C It can be seen that transistor P5 remains at 0, so that the first current source Ip1 coupled with it is still in the conducting state. After the switching is completed, transistor P8 remains at 0, so that the first current source Ip1 can output current through the output terminal ion2.

[0136] Figure 9D The diagram shows the latch signals and voltage waveforms of the corresponding switches as the first latch signal data1p switches from 1 to 0, and the second latch signal data2p also switches from 1 to 0 simultaneously. (Refer to...) Figures 6-8 and combined Figure 9D ,Depend on Figure 9D It can be seen that when the first latch signal data1p is 1 and the second latch signal data2p is 1, the switch enable signal ex_swp1 corresponding to transistor P8 is 0. Therefore, the first current source Ip1 coupled to it will not be turned off, and current will be output through the output terminal ion2. During the process of the first latch signal data1p and the second latch signal data2p switching synchronously from 1 to 0, the current is generated by... Figure 9D It can be seen that transistor P8 remains at 0, so that the first current source Ip1 coupled to it is always in the conducting state. After the switching is completed, that is, after the first latch signal data1p and the second latch signal data2p are switched to 0 simultaneously, transistor P1 remains at 0, so that the first current source Ip1 can output current through the output terminal iop1.

[0137] As can be seen from the voltage waveforms of the enable switch control signals of transistors P1, P2, P5, and P8, which are respectively coupled between the first current source Ip1 and the four output terminals, as they change with the first latch signal data1p and the second latch signal data2, regardless of the input values ​​of the first latch signal data1p and the second latch signal data2, and regardless of how the first latch signal data1p and the second latch signal data2 change, there is always a switch in the on state between the first current source Ip1 and the output terminals iop1, iop2, ion1, and ion2. Therefore, no matter how the first input signal data1 and the second input signal data2 change, the first current source Ip1 will not be turned off, even during rapid switching.

[0138] Similarly, regardless of how the first input signal data1 and the second input signal data2 change, at least one of the switches coupled to the output terminals iop1, iop2, ion1 and ion2 of the first branch second current source In1, the second branch first current source Ip2 and the second branch second current source In2 will always be in a conducting state. Therefore, under any circumstances, there will be a current inflow or outflow path for the first branch second current source In1, the second branch first current source Ip2 and the second branch second current source In2, which will not be elaborated here.

[0139] In practical implementation, the differential complementary circuit module used can also be a half-differential complementary circuit module, as shown in the reference. Figure 7 The circuit structure diagram of the differential complementary circuit module shown can be implemented as follows: In a specific implementation, the differential complementary circuit module used can be a differential complementary circuit module 7A coupled between the first current source Ip1 of the first branch and the first current source Ip2 of the second branch and multiple output terminals iop1, iop2, ion1 and ion2. In this case, the second current source In1 of the first branch and the second current source In2 of the second branch are directly connected to the multiple output terminals iop1, iop2, ion1 and ion2, and the current values ​​of the first current source Ip1 of the first branch and the first current source Ip2 of the second branch are also shown. Similarly, the differential complementary circuit module used can also be a differential complementary circuit module 7B coupled between the second current source In1 of the first branch and the second current source In2 of the second branch and the output terminals iop1, iop2, ion1 and ion2. In this case, the first current source Ip1 of the first branch and the first current source Ip2 of the second branch are directly connected to the plurality of output terminals iop1, iop2, ion1 and ion2, and the current values ​​of the second current source In1 of the first branch and the second current source In2 of the second branch are doubled.

[0140] Accordingly, the structures of the driving circuit modules corresponding to the above-mentioned semi-differential complementary circuit modules 7A and 7B can be obtained, referring to... Figure 8 If required, the current source drive circuit uses a half-differential complementary circuit module 7A or 7B. The unused control signals in the non-overlapping clock units of the corresponding drive circuit modules can be kept open, that is, they are not connected to other modules. Alternatively, if it is determined that the current source drive circuit is only suitable for half-differential complementary circuit modules, the half-differential complementary circuit module 7A or 7B used may not include the corresponding devices. For example, it may not include the seventh NOT gate (NOT7) and the eighth NOT gate (NOT8).

[0141] As can be seen from the above operating characteristics 1)-4), the switches connected to any current source and each output terminal will not be turned off simultaneously. This means that there is a common conduction time at the edge moment. The magnitude of the common conduction time can be obtained by adjusting the delay duration of the fourth delay unit delay4 and the first delay unit delay1.

[0142] In high-speed applications, the requirements for delay duration are very high. For the delay durations t2, t3, and t1 corresponding to each delay unit delay2, delay3, and delay1, in addition to satisfying t2 < t3 < t1, the absolute delay time should be as short as possible. Therefore, in some embodiments of this specification, a delay detection method is provided that can minimize the absolute delay time while meeting the above conditions.

[0143] Specifically, a time delay calibration module can be coupled to the first delay unit delay1 and the fourth delay unit delay4 respectively. Initially, the delay duration t4 of the fourth delay unit delay4 is set to a fixed value, and the delay duration t1 of the first delay unit delay1 is greater than t4. Furthermore, the adjustment step size of t1 is half the total adjustable delay duration of the first delay unit delay1. N Then, the preset test clock signal is input to the delay calibration module, and the first delay unit delay1 is accumulated and counted until the output of the delay calibration module meets the preset conditions. The duration corresponding to the first delay unit delay1 is the delay duration of the first delay unit delay1 in the current source drive circuit.

[0144] In some embodiments of this specification, such as Figure 10 The schematic diagram of the delay calibration module shown indicates that the delay calibration module 100 may include a clock input unit CK, a first flip-flop D1, a second flip-flop D2, and two identical reset units RS1 and RS2, wherein:

[0145] The clock input unit CK has a first input terminal adapted to input the test clock signal test_clk, a second input terminal adapted to input the test enable signal test_en, and an output terminal adapted to output the first clock signal clk to the first delay unit delay1 and the fourth delay unit delay4.

[0146] The first flip-flop D1 has its D input terminal adapted to be coupled to the power supply VDD, its clock signal input terminal CK coupled to the output terminal of the fourth delay unit delay4, and its output terminal adapted to output the first detection signal q1;

[0147] The second flip-flop D2 has its D input terminal adapted to be coupled to the power supply VDD, its clock signal input terminal CK coupled to the output terminal of the first delay unit delay1, and its output terminal adapted to output the second detection signal q2;

[0148] The reset unit RS1 is adapted to output a reset signal rst1 to the reset terminal RST of the first flip-flop D1 coupled thereto, based on the input reset signal;

[0149] The reset unit RS2 is adapted to output a reset signal rst2 to the reset terminal RST of the second flip-flop D2 coupled thereto, based on the input reset signal.

[0150] The preset condition is that the first detection signal q1 and the second detection signal q2 change abruptly as the delay duration of the first delay unit delay1 accumulates.

[0151] More specifically, continue to refer to Figure 10 The clock input unit CK includes: a third NAND gate unit NAND3 and a tenth NOT gate NOT10 coupled in sequence, wherein:

[0152] The third NAND gate unit NAND3 has a first input terminal adapted to input the test clock signal test_clk, and a second input terminal adapted to input the test enable signal test_en;

[0153] The tenth NOT gate NOT10 is adapted to output the first clock signal clk0 based on the second clock signal clk1 output by the third NAND gate unit NAND3.

[0154] As a specific example, the reset unit RS1 may include: a second NOR gate unit NOR2 and an eleventh NOT gate NOT9, wherein:

[0155] The second NOR gate unit NOR2 has a first input terminal adapted to receive the reset signal rst, a second input terminal adapted to be coupled to the output terminal q2 of the second flip-flop D2 (i.e., the flip-flop not to be reset), and an output terminal adapted to be coupled to the input terminal of the eleventh NOT gate NOT11.

[0156] The eleventh NOT gate (NOT11) is coupled to the reset terminal (RST) of the first flip-flop (D1, the corresponding flip-flop to be reset).

[0157] The reset unit RS2 has the same structure as the reset unit RS1, and will not be described in detail here.

[0158] The following combination Figure 11 ,illustrate Figure 10 The delay calibration module shown is an automatic calibration process that obtains the delay duration of the first delay unit delay1 based on the delay duration t4 of the fourth delay unit delay4.

[0159] Before detection, the first flip-flop D1 and the second flip-flop D2 are reset, and the outputs of q1 and q2 are both 0 (indicating a low level). The delay duration t4 of the fourth delay unit delay4 is fixed, and the initial value of the first delay unit delay1 is adjusted. In a specific implementation, a multi-bit storage unit trim can be used. <x:0>Store the set value of the first delay unit delay1. As a specific example, a 6-bit storage unit stores the set value Trim<5:0> of the delay1. Based on the set value Trim<5:0>, the delay duration t1 of the first delay unit delay1 can be obtained.

[0160] When the set value trim<5:0> = 000000, t1 < t4; when the set value trim<5:0> = 111111, t1 > t4. At this time, the input test clock test_clock is applied. Observe the output. Since the adjusted minimum t1 < t4, q1 = 0 and q2 = 1 (0 is low level, equivalent to ground GND; 1 is high level, equivalent to power supply VDD). Next, increment the Trim<5:0> value by 1 and repeat the above process until q1 = 1 and q2 = 0, then delay2 > delay1 and the absolute delay is minimized. At this time, the calibration value delay1_num is the current cumulative count value of trim<5:0>, that is, delay1_num = trim<5:0>.

[0161] The calibration flowchart is as Figure 11 shown, and specifically may include the following steps:

[0162] Step S10, corresponding to the initial state, the test clock enable signal test_en is set to 0, and the reset signal rst is set to 1;

[0163] Step S11, perform the following settings: reset signal rst = 0, trim<5:0> = 000000, test enable signal test_en = 1.

[0164] Step S12, determine whether the output q1 of the first flip-flop is equal to 1 and whether the output q2 of the second flip-flop is equal to 0. If so, execute step S13; otherwise, execute step S14;

[0165] Step S13, the delay adjustment value delay_num corresponding to the first delay unit delay1 = trim<5:0>;

[0166] Step S14, let trim<5:0> = trim<5:0> + 1, that is, accumulate the count of the set value Trim<5:0>;

[0167] Step S15, reset the test clock enable signal test_en to 0 and the reset signal rst to 1.

[0168] After steps S11 to S13, the absolute value of the difference between the delay duration t1 of the first delay unit delay1 and the delay duration t4 of the fourth delay unit delay4 is minimized. Then, the delay1_num corresponding to the first delay unit delay1 at this time is taken as Trim<5:0>, and step S15 is executed, so that the delay calibration module returns to the initial state.

[0169] In specific implementation, the accuracy of the absolute value of the delay difference between the first delay unit delay1 and the fourth delay unit delay4 is consistent with the set value trim. <x:0>The accuracy is related to the number of bits. The more bits, the higher the relative accuracy and the smaller the absolute delay difference.

[0170] In practical implementation, before the current source drive circuit is working normally, the automatic calibration circuit and calibration process in the above embodiment can be used to perform fully automatic calibration to meet the specific application requirements of the circuit.

[0171] It is understood that the reset units RS1 and RS2 can also be other circuit structures, as long as they can automatically calibrate the delay duration of the first delay unit delay1 based on the delay duration of the fourth delay unit delay4.

[0172] By using the current source drive circuit in the embodiments of this specification, the current source path can be avoided from being shut off for a short time during the switching process.

[0173] The current source drive circuits described in the embodiments of this specification can be applied to analog-to-digital converters. To enable those skilled in the art to better understand and implement these circuits, the embodiments of this specification also provide corresponding analog-to-digital converters, see reference. Figure 12 The diagram shows the structure of an analog-to-digital converter, which can be used as a complex analog-to-digital converter, such as in a complex continuous-time SDADC, and can be specifically applied in a receiver for radio frequency modulation.

[0174] like Figure 12 As shown, the analog-to-digital converter 120 may include: a first input path 12I, a second input path 12Q, and a feedback path 12F, wherein:

[0175] The first input path 12I is adapted to obtain a first output signal outI based on the first input signal inQ and the first feedback signal I output by the feedback path 12F;

[0176] The second input path 12Q is adapted to obtain a second output signal outQ based on the second input signal inQ and the first feedback signal Q output by the feedback path 12F;

[0177] The feedback path 12F is coupled to the first input path 12I and the second input path 12Q respectively, and includes: a first current source branch (not shown), a second current source branch (not shown), a current source drive circuit 12D, and a feedback path analog-to-digital converter, wherein:

[0178] The current source drive circuit 12D has a first input terminal coupled to the output terminal of the first input path, and uses the first output signal outI of the first input path 12I as the first input signal data1 of the feedback path 12F; its second input terminal is coupled to the output terminal of the second input path 12Q, and uses the second output signal outQ of the second input path 12Q as the second input signal data2 of the feedback path 12F. Based on the first input signal data1 and the second input signal data2, the feedback path digital-to-analog converter and the first current source branch are turned on, and the second feedback path digital-to-analog converter and the second current source branch are turned on.

[0179] The feedback path digital-to-analog converter DAI+DACQ is adapted to output the first feedback signal I to the first input path 12I and the second feedback signal Q to the second input path 12Q based on the switching control of the current source drive circuit 12D.

[0180] The current source drive circuit in the feedback path can be any of the current source drive circuits in the foregoing embodiments of this specification. For details, please refer to the foregoing embodiments, which will not be described further here.

[0181] Using the analog-to-digital converter in the above embodiments, the current source driving circuit 12D can drive two DACs simultaneously. As a specific example, one can drive the I-channel DAC, i.e., DCI; and the other can drive the Q-channel DAC, i.e., DACQ.

[0182] In the feedback path 12F, the DAC current sources of the I and Q paths can be swapped according to a certain rule, that is, the current sources of the first current source branch and the second current source branch corresponding to DCI and DACQ can be swapped to reduce or eliminate the mismatch of the feedback DACs (i.e., DCI+DACQ) corresponding to the I and Q paths. For example, when the input signals data1 and data2 corresponding to the two feedback DACs (i.e., DCI+DACQ) are the same, the current sources corresponding to the two paths can be swapped, that is, the corresponding current sources are switched; when the input signals data1 and data2 corresponding to the two feedback DACs (i.e., DCI+DACQ) are different, there is no need to swap the current sources corresponding to the two paths.

[0183] As can be seen from the foregoing embodiments, regardless of the specific data input to the first channel (e.g., I channel) input signal data1 and the second channel (e.g., Q channel) input signal data2, or how they are switched, the I and Q channels corresponding to the DCI are always powered by current sources. Therefore, there will be no situation where the current source is temporarily shut off and needs to be rebuilt. Thus, the mismatch of the feedback path 12F can be reduced. Applying the current source drive circuit 12D to the analog-to-digital converter for signal demodulation can improve demodulation performance.

[0184] In specific implementation, both the first input path 12I and the second input path 12Q may include an adder and a quantizer, wherein: the adder is adapted to accumulate the input signal and the feedback signal of the corresponding path to obtain a continuous signal; the quantizer is adapted to quantize the continuous signal into a discrete signal to complete the basic function of analog-to-digital conversion.

[0185] like Figure 12 As shown, the first input path 12I may include adder 1 and quantizer 1, and the second input path 12Q may include adder 2 and quantizer 2.

[0186] In practical implementation, to filter out quantization noise, both the first input path 12I and the second input path 12Q also include filters, which can be placed between the adder and the quantizer. In the loop, the filter can form a filtering circuit with other modules to filter out in-band quantization noise. Figure 12 As shown, the first input path 12I further includes filter 1, and the second input path 12Q further includes filter 2.

[0187] In a specific implementation, the feedback path 12F may further include: a data weighted averager (DWA), coupled between the output terminal of the corresponding input path and the current source drive circuit 12D, adapted to perform a preset transformation on the discrete signal obtained by quantization of the corresponding input path to obtain the digital signal after DWA transformation. The feedback DAC (i.e., DCI+DACQ) can convert the digital signal after DWA transformation into an analog signal and send it to the input terminal of the modem, i.e., the input terminal of the first input path (I path) and the input terminal of the second input path (Q path).

[0188] like Figure 12 As shown, the feedback path 12F may include DWA1 and DWA2, wherein: DWA1 is coupled between the output terminal of the first input path 12I and the current source drive circuit 12D; and DWA2 is coupled between the output terminal of the second input path 12Q and the current source drive circuit 12D.

[0189] In specific implementation, the feedback path digital-to-analog converter (DAC+DACQ) can use a multi-feedback DAC, that is, multiple DAC units can be used for both the I-channel DAC and the Q-channel DAC. The multiple DAC units are all connected in parallel to the corresponding current source branches and share the current source output terminal.

[0190] In the embodiments of this specification, the latch circuit module, the drive circuit module, the differential complementary circuit module, and the corresponding current source can constitute a basic current source unit, such as... Figure 13 The schematic diagram shown is of a multi-feedback DAC. As a specific example, the multi-feedback DAC 130 includes 32 DAC units 13i, which can be connected in parallel. Each of the 32 DAC units 13i includes the latch circuit module, drive circuit module, and differential complementary circuit module (e.g., the fully differential complementary circuit module) shown in the foregoing embodiments of this specification, and shares the output terminals iop1, ion1, iop2, and ion2 of each current source branch. Figure 13 As shown.

[0191] Furthermore, in the feedback path, the inputs of multiple DAC units and the outputs of the quantizer are in one-to-one correspondence. Even if DWA is set in the feedback path to change the correspondence between the two, the bit depth of the two remains consistent.

[0192] For example, the quantizer outputs a 5-level thermometer code, corresponding to the output: 0000, 0001, 0011, 0111, 1111, which has 4 bits. Since the I and Q channels are integrated, the I channel has 4 bits, and the Q channel also has 4 bits. Assuming the 4 bits for the I channel are bitI3, bitI2, bitI1, and bitI0 from high to low, and the 4 bits for the Q channel are bitQ3, bitQ2, bitQ1, and bitQ0 from high to low, then the bit values ​​of the corresponding bits are the inputs of a latch circuit module. For example, bitI3 and bitQ3 are the inputs of one latch circuit module, bitI2 and bitQ2 are the inputs of another latch circuit module, and so on, for a total of four latch circuit modules. The corresponding drive circuit module, differential complementary circuit module, and corresponding current source are also divided into 4 groups, and these four groups of current sources share the output.

[0193] Using DWA (Digital Waveform Analysis), the digital signal output from the quantizer is transformed before being sent to the DAC. This can be used to eliminate mismatches between multi-bit DAC units, for example, it can eliminate... Figure 13 The mismatch between the 32 DAC units 13i shown.

[0194] In practical implementation, the aforementioned analog-to-digital converter can be applied to a receiver, for example, a low-intermediate frequency receiver. In the embodiments of this specification, reference is made to... Figure 14 The schematic diagram of the receiver shown illustrates that the receiver 140 may include: a demodulation device 141 and an analog-to-digital converter 142, wherein:

[0195] Demodulation device 141 is adapted to demodulate radio frequency input signal RF to obtain in-phase orthogonal first input signal inI and second input signal inQ;

[0196] The analog-to-digital converter 142 is adapted to perform analog-to-digital conversion on the first input signal and the second input signal to obtain a first path output signal outI and a second path output signal outQ.

[0197] The specific implementation of the analog-to-digital converter 142 can be carried out using the aforementioned specific embodiments of the analog-to-digital converter, which will not be described in detail here.

[0198] In specific implementations, to further improve receiver performance, the receiver 140 may also include the following circuit components:

[0199] A low-noise amplifier (LNA) is used to amplify the input signal RF with low noise to obtain a voltage signal.

[0200] A transconductance amplifier gm is adapted to convert the voltage signal, which has been amplified with low noise, into a current signal and output it.

[0201] A transimpedance amplifier (TIA) is adapted to convert the current signal into a voltage signal and output it.

[0202] The positions and connections of the above-mentioned components can be found by referring to Figure 14 As shown.

[0203] In practice, only some of the circuits or devices in the embodiments of this specification may be used as needed, or multiple embodiments may be combined as needed.

[0204] While the embodiments disclosed in this specification are as described above, the embodiments of the present invention are not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A current source driving circuit, suitable for driving a current source, characterized in that, include: The latch circuit module is adapted to output a first latch signal and a first latch inverted signal based on a first input signal, and to output a second latch signal and a second latch inverted signal based on a second input signal; A differential complementary circuit module includes two complementary switch group sub-modules, wherein each switch group sub-module is coupled to one of the first current source branch and the second current source branch, and the switch group sub-module includes multiple coupled switches. The driving circuit module is coupled to the latching circuit module and the differential complementary circuit module respectively, and is adapted to output a multiplexed switch control signal to the switch group submodule of the differential complementary circuit module based on the first latching signal, the first latching inverted signal, the second latching signal and the second latching inverted signal, so that at any time, there is a switch in the switch group submodule corresponding to any current source branch that is in the on state, so as to drive the current source in the corresponding current source branch.

2. The current source drive circuit according to claim 1, characterized in that, The latch circuit module includes two latch sub-modules with identical structures. Each latch sub-module has an input terminal adapted to receive either the first input signal or the second input signal, a first output terminal adapted to output a latch signal in phase with the corresponding input signal, and a second output terminal adapted to output a latch signal out of phase with the corresponding input signal.

3. The current source drive circuit according to claim 2, characterized in that, The latch submodule includes: a first NOT gate and a second NOT gate connected in series.

4. The current source drive circuit according to claim 2, characterized in that, The latch submodule includes: a first NOT gate, a second NOT gate, and a latch connected in sequence, wherein: the first input terminal of the latch is coupled to the output terminal of the first NOT gate, the second input terminal of the latch is coupled to the output terminal of the second NOT gate, the first output terminal of the latch is adapted to output the latch signal of the corresponding path, and the second output terminal of the latch is adapted to output the latch inverted signal of the corresponding path.

5. The current source drive circuit according to claim 1, characterized in that, The driving circuit module includes: a logic control submodule, and a first non-overlapping clock submodule and a second non-overlapping clock submodule, which are coupled to the logic control submodule and have the same structure, respectively, wherein: The logic control submodule is adapted to perform preset logic operations based on the first latch signal and the second latch signal, and output a first control signal and a second control signal. The first non-overlapping clock submodule is adapted to output a multiplexed switch control signal to the switch group submodule corresponding to the first current source branch based on the input first latch signal, the first latch inverted signal, the first control signal and the second control signal, so that at any time, there is a switch in the switch group submodule corresponding to the first current source branch in the on state. The second non-overlapping clock submodule is adapted to output multiple switch control signals to the switch group submodule corresponding to the second current source branch based on the input second latch signal, the second latch inverted signal, the first control signal and the second control signal, so that there is a switch in the switch group submodule corresponding to the second current source branch in the on state at any time.

6. The current source drive circuit according to claim 5, characterized in that, Any of the current source branches includes: a first current source and a second current source coupled between the power supply and ground with opposite current flows, and the output terminal of the current source branch is disposed between the first current source and the second current source, including two output terminals with opposite current flows; The switch group submodule includes: a conducting switch unit and a switching switch unit, wherein: The switching unit includes a current source coupled to the corresponding current source branch and the output terminal of the corresponding current source branch, and is adapted to conduct the current source output path formed by the current source on the corresponding current source branch and the output terminal of the corresponding branch based on the received switch enable control signal. The switching unit is coupled between the output terminals of different current source branches and is adapted to switch the output terminal of the current source coupled to it based on the received switch enable control signal.

7. The current source drive circuit according to claim 6, characterized in that, The logic control submodule includes: an XOR gate unit, a first delay unit, and a second delay unit, wherein: The XOR gate unit has a first input terminal adapted to input the first latch signal, a second input terminal adapted to input the second latch signal, and an output terminal coupled to the input terminal of the first delay unit and the first input terminal of the second delay unit, respectively. The first delay unit has its input terminal coupled to the output terminal of the XOR gate unit, and its output terminal is adapted to output the first control signal and coupled to the second input terminal of the second delay unit. The second delay unit is adapted to output the second control signal; Wherein: the delay duration of the second delay unit is less than the delay duration of the first delay unit.

8. The current source drive circuit according to claim 7, characterized in that, The second delay unit includes: a first NAND gate and a fifth NOT gate, wherein: The first NAND gate unit has a first input terminal adapted to be coupled to the output terminal of the XOR gate unit and the input terminal of the first delay unit, a second input terminal coupled to the output terminal of the first delay unit, adapted to input the first control signal, and an output terminal coupled to the input terminal of the fifth NOT gate. The fifth NOT gate has its input terminal coupled to the output terminal of the first NAND gate unit, and its output terminal is adapted to output the second control signal.

9. The current source drive circuit according to claim 8, characterized in that, The non-overlapping clock submodule includes two structurally identical and coupled non-overlapping clock units. Each non-overlapping clock unit includes a third delay unit, a second NAND gate unit, a first NOR gate unit, and a sixth NOT gate, wherein: The third delay unit has a first input terminal corresponding to the overlapping clock submodule, which is adapted to receive one of the first latch signal, the first latch inverted signal, the second latch signal, and the second latch inverted signal. Its second input terminal is adapted to be coupled to the output terminal of the third delay unit of another non-overlapping clock unit in the same non-overlapping submodule. It includes two inverted first output terminals and second output terminals. The delay duration of the third delay unit is less than the delay duration of the first delay unit and greater than the delay duration of the second delay unit. The second NAND gate unit has a first input terminal adapted to be coupled to the first output terminal of the third delay unit, a second input terminal adapted to input the first control signal, and an output terminal adapted to output a corresponding switch control signal to the conduction control switch coupled thereto, thereby controlling the on / off state of the conduction control switch coupled thereto. The first NOR gate unit has a first input terminal adapted to be coupled to the second output terminal of the third delay unit, a second input terminal adapted to input the second control signal, and an output terminal coupled to the output terminal of the sixth NOT gate. The sixth NOT gate is adapted to output a corresponding switch control signal to the switching control switch coupled thereto, thereby controlling the on / off state of the switching control switch coupled thereto.

10. The current source drive circuit according to claim 9, characterized in that, The non-overlapping clock units further include: a seventh NOT gate and an eighth NOT gate, wherein: The seventh NOT gate has its input terminal coupled to the output terminal of the second NAND gate unit, and its output terminal is adapted to output a corresponding switch control signal to the conduction control switch coupled thereto, so as to control the on / off state of the conduction control switch coupled thereto. The eighth NOT gate has its input terminal adapted to be coupled to the output terminal of the sixth NOT gate, and its output terminal adapted to output a corresponding switch control signal to the switching control switch coupled thereto, thereby controlling the on / off state of the switching control switch coupled thereto.

11. The current source drive circuit according to claim 9 or 10, characterized in that, The third delay unit includes: an AND gate, a fourth delay unit, and a ninth NOT gate coupled in sequence, wherein: the output terminal of the ninth NOT gate serves as the first output terminal of the third delay unit, and the output terminal of the fourth delay unit serves as the second output terminal of the third delay unit.

12. The current source drive circuit according to claim 11, characterized in that, The delay duration of the first delay unit is greater than the delay duration of the fourth delay unit.

13. The current source drive circuit according to claim 12, characterized in that, Also includes: The delay calibration module is coupled to the first delay unit and the fourth delay unit respectively. The initial delay duration of the fourth delay unit is set to a fixed value, and the delay adjustment step size of the first delay unit is half of the total adjustment step size. N Then, a preset test clock signal is input to the delay calibration module, and the first delay unit is accumulated and counted until the output of the delay calibration module meets the preset conditions. At that time, the duration corresponding to the first delay unit is the delay duration of the first delay unit in the current source drive circuit.

14. The current source drive circuit according to claim 13, characterized in that, The time delay calibration module includes: a clock input unit, a first flip-flop, a second flip-flop, and two identical reset units, wherein: The clock input unit has a first input terminal adapted to input the test clock signal, a second input terminal adapted to input the test enable signal, and an output terminal adapted to output the first clock signal to the first delay unit and the fourth delay unit. The first flip-flop has its D input terminal adapted to be coupled to a power supply, its clock signal input terminal coupled to the output terminal of the fourth delay unit, and its output terminal adapted to output a first detection signal. The second flip-flop has its D input terminal adapted to be coupled to a power supply, its clock signal input terminal coupled to the output terminal of the first delay unit, and its output terminal adapted to output a second detection signal; Any of the reset units is adapted to output a reset signal to the reset terminal of the first or second flip-flop coupled thereto, based on the input reset signal; The preset condition is that the first detection signal and the second detection signal change abruptly as the delay duration of the first delay unit accumulates.

15. The current source drive circuit according to claim 14, characterized in that, The clock input unit includes: a third NAND gate and a tenth NOT gate coupled in sequence, wherein: The third NAND gate unit has a first input terminal adapted to input the test clock signal and a second input terminal adapted to input the test enable signal; The tenth NOT gate is adapted to output the first clock signal based on the second clock signal output by the third NAND gate unit.

16. The current source drive circuit according to claim 14, characterized in that, The reset unit includes: a second NOR gate and an eleventh NOT gate, wherein: The second NOR gate unit has a first input terminal adapted to receive the reset signal, a second input terminal adapted to be coupled to the output terminal of the flip-flop not to be reset, and an output terminal adapted to be coupled to the input terminal of the eleventh NOT gate. The eleventh NOT gate is coupled to the reset terminal of the corresponding trigger to be reset.

17. An analog-to-digital converter, characterized in that, include: The system comprises a first input path, a second input path, and a feedback path, wherein: The first input path is adapted to obtain a first output signal based on the first input signal and the first feedback signal output by the feedback path; The second input path is adapted to obtain a second output signal based on the second input signal and the second feedback signal output by the feedback path; The feedback path, coupled to the first input path and the second input path respectively, includes: First current source branch; Second current source branch; The current source driving circuit according to any one of claims 1-16, wherein its first input terminal is coupled to the output terminal of the first input path, and the first output signal output by the first input path is used as the first input signal of the feedback path; its second input terminal is coupled to the output terminal of the second input path, and the second output signal output by the second input path is used as the second input signal of the feedback path; based on the first input signal and the second input signal, the first feedback path digital-to-analog converter and the first current source branch are turned on, and the second feedback path digital-to-analog converter and the second current source branch are turned on. The feedback path digital-to-analog converter is adapted to output the first feedback signal to the first input path and output the second feedback signal to the second input path based on the switching control of the current source drive circuit.

18. The analog-to-digital converter according to claim 17, characterized in that, Both the first input path and the second input path include: an adder and a quantizer, wherein: The adder is adapted to accumulate the input signal and feedback signal of the corresponding input path to obtain a continuous signal; The quantizer is adapted to quantize the continuous signal into a discrete signal.

19. The analog-to-digital converter according to claim 18, characterized in that, Both the first and second input paths include filters, which are positioned between the adder and the quantizer to filter out quantization noise.

20. The analog-to-digital converter according to claim 18, characterized in that, The feedback path digital-to-analog converter includes: multiple digital-to-analog conversion units corresponding to the corresponding input paths. Each of the multiple digital-to-analog conversion units includes the latch circuit module, the drive circuit module, and the differential complementary circuit module, and shares the output terminal of each current source branch.

21. The analog-to-digital converter according to claim 20, characterized in that, The feedback path also includes: A data weighted averager is coupled between the output of the corresponding input path and the current source drive circuit. It is suitable for performing a preset transformation on the discrete signal obtained by quantization of the corresponding input path to eliminate the mismatch between the multiple digital-to-analog conversion units.

22. A receiver, characterized in that, include: The demodulation device is suitable for demodulating radio frequency input signals to obtain in-phase and quadrature first and second input signals; The analog-to-digital converter according to any one of claims 17-21 is adapted to perform analog-to-digital conversion on the first input signal and the second input signal to obtain a first path output signal and a second path output signal.

23. The receiver according to claim 22, characterized in that, Also includes: A low-noise amplifier, suitable for performing low-noise amplification processing on the input signal and outputting a voltage signal; A transconductance amplifier, coupled between the low-noise amplifier and the demodulation device, is adapted to convert the voltage signal output by the low-noise amplifier into a current signal and output it. A transimpedance amplifier, coupled between the demodulation device and the analog-to-digital converter, is adapted to convert the current signal into a voltage signal and output it.

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