Command distribution method, command distributor, chip and electronic device

Abstract

The present disclosure provides a command distribution method, a command distributor, a chip, and an electronic device, wherein the command distribution method includes: determining multiple first target register groups corresponding to the current processing cycle from multiple register groups; wherein the first target register group is different from the second target register group determined in at least one recent historical processing cycle; determining the target threads corresponding to the multiple first target register groups in the current processing cycle from the thread groups corresponding to the multiple first target register groups; and distributing commands corresponding to the determined target threads to the corresponding computing units. In the embodiment of the present disclosure, each thread group will be accessed by at most one computing unit in each processing cycle, so the computing units that receive the command do not need to arbitrate, and can directly access the corresponding register group to obtain the operands required for the command, thereby improving the efficiency of command distribution and command processing efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a command distribution method, a command distributor, a chip, and an electronic device. Background Art

[0002] The structure of command processing devices such as central processing units and graphics processing units usually includes: a controller, a command distributor connected to the controller, and multiple computing units connected to the command distributor. The controller is used to receive commands from the host, and send the commands to the command distributor after preliminary processing, and the command distributor distributes the commands to different computing units for execution. With the continuous increase in intensive computing tasks, hardware multithreading, as a technology that can effectively improve parallel computing capabilities, has been widely used in fields such as image, neural network, and data processing. Hardware multithreading effectively improves computing speed by increasing the number of computing units, maintaining more threads for parallel execution, increasing the capacity of the register stack used to store command operands, and using higher bandwidth external memory.

[0003] The current command distribution method has the problem of low distribution efficiency. Summary of the invention

[0004] The embodiments of the present disclosure at least provide a command distribution method, a command distributor, a chip, and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a command distribution method, comprising: determining a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups; wherein the first target register groups are different from a second target register group determined in at least one recent historical processing cycle;

[0006] Determine target threads corresponding to the plurality of first target register groups in a current processing cycle from thread groups corresponding to the plurality of first target register groups; and distribute commands corresponding to the determined target threads to corresponding computing units.

[0007] In a possible implementation, determining, from the multiple register groups, the multiple first target register groups corresponding to the current processing cycle includes: when the current processing cycle is an odd-numbered cycle, determining the register groups with odd numbers among the multiple register groups as the first target register groups; and when the current processing cycle is an even-numbered cycle, determining the register groups with even numbers among the multiple register groups as the first target register groups.

[0008] In a possible implementation, the method further includes: determining the number of register groups according to the number of operands of the operation unit requiring the largest number of operands, and dividing the registers into the plurality of register groups.

[0009] In a possible implementation, determining, from the thread groups corresponding to the multiple first target register groups respectively, the target threads corresponding to the multiple first target register groups in the current processing cycle includes: determining, from the thread groups corresponding to the multiple first target register groups respectively, the target threads corresponding to the multiple first target register groups in the current processing cycle based on command execution status information of each thread in the thread groups corresponding to the multiple first target register groups respectively.

[0010] In a possible implementation, the determining, based on the command execution status of each thread in the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle from the thread groups corresponding to the plurality of first target register groups includes: determining, from the thread groups corresponding to the plurality of first target register groups, a plurality of candidate threads whose command execution status information is in a ready state; and determining, from the plurality of candidate threads, target threads corresponding to the plurality of first target register groups in a current processing cycle.

[0011] In a possible implementation, determining, from the multiple candidate threads, the target threads that respectively correspond to the multiple first target register groups in the current processing cycle includes: determining, from the multiple candidate threads, the target threads that respectively correspond to the multiple first target register groups in the current processing cycle based on the priorities of the commands to be distributed that respectively correspond to the multiple candidate threads.

[0012] In a possible implementation, determining the target threads corresponding to the multiple first target register groups in the current processing cycle from the multiple candidate threads includes: determining the target threads corresponding to the multiple first target register groups in the current processing cycle from the multiple candidate threads based on the priorities of the commands to be distributed corresponding to the multiple candidate threads and the occupancy status of the computing units corresponding to the commands to be distributed.

[0013] In one possible implementation, in response to the presence of a multi-operand to-be-dispatched command having more than one operand in the to-be-dispatched commands corresponding to the target thread determined for the current processing cycle, the first target register group corresponding to the multi-operand to-be-dispatched command distributes a corresponding operand to the corresponding operation unit of the to-be-dispatched command in each processing cycle from the current processing cycle to the target processing cycle; wherein the difference in the number of cycles between the target processing cycle and the current processing cycle is equal to subtracting one from the number of the multi-operands.

[0014] In a possible implementation, the method further includes: in response to the presence of a multi-operand to-be-dispatched command having two operands in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, for each single-operand to-be-dispatched command in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, determining, in the next processing cycle of the current processing cycle, another single-operand to-be-dispatched command in a ready state for the first target register group where the single-operand to-be-dispatched command is located.

[0015] In a possible implementation, the method further includes: in response to the existence of a multi-operand to-be-distributed command with more than one operand in the to-be-distributed commands corresponding to the target thread determined for the current processing cycle, determining the number of operands of the multi-operand to-be-distributed command with the largest number of operands in the multi-operand to-be-distributed commands; for each other to-be-distributed command with a number of operands less than the largest number of operands in the to-be-distributed commands corresponding to the target thread determined for the current processing cycle, in response to the existence of an idle first target register group where other to-be-distributed commands are located, determining a ready-to-be-distributed command for the first target register group from a thread group corresponding to the first target register group where the command is located; wherein the number of operations of the ready-to-be-distributed command is not greater than the number of processing cycles from the processing cycle where the ready-to-be-distributed command is located to the processing cycle where the first target register group is scheduled again.

[0016] In a possible implementation, the method further includes: obtaining feedback information generated by the computing unit after executing the command; and generating command execution status information corresponding to the thread to which the executed command belongs based on the feedback information.

[0017] In a possible implementation, the method further includes: grouping the currently executing threads based on the number of the register groups and the number of currently executing threads to obtain thread groups corresponding to each of the register groups.

[0018] In a second aspect, an embodiment of the present disclosure provides a command distributor, including: a scheduler, and a distribution interface;

[0019] The scheduler is configured to determine a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups; wherein the first target register group is different from a second target register group determined in at least one recent historical processing cycle; and determine, from thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in the current processing cycle;

[0020] The distribution interface is used to distribute commands corresponding to the determined target threads to the corresponding computing units.

[0021] In a possible implementation, the scheduler, when determining a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups, is configured to:

[0022] In a case where the current processing cycle is an odd-numbered cycle, determining an odd-numbered register group among the multiple register groups as the first target register group;

[0023] When the current processing cycle is an even-numbered cycle, an even-numbered register group among the multiple register groups is determined as the first target register group.

[0024] In a possible implementation manner, the scheduler is further configured to:

[0025] The number of register groups is determined according to the number of operands of the operation unit requiring the largest number of operands, and the registers are divided into the plurality of register groups.

[0026] In a possible implementation manner, the scheduler, when determining, from the thread groups corresponding to the plurality of first target register groups, the target threads corresponding to the plurality of first target register groups in the current processing cycle, is configured to:

[0027] Based on the determined command execution status information of each thread in the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle are determined from the thread groups corresponding to the plurality of first target register groups.

[0028] In a possible implementation manner, the scheduler, when determining, from the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle, is configured to:

[0029] Determine, from the thread groups respectively corresponding to the plurality of first target register groups, a plurality of candidate threads whose command execution status information is in a ready state;

[0030] From the multiple candidate threads, target threads corresponding to the multiple first target register groups respectively in a current processing cycle are determined.

[0031] In a possible implementation manner, when the scheduler determines, from the multiple candidate threads, target threads corresponding to the multiple first target register groups in the current processing cycle, the scheduler is configured to:

[0032] Based on the priorities of the to-be-dispatched commands respectively corresponding to the multiple candidate threads, target threads respectively corresponding to the multiple first target register groups in a current processing cycle are determined from the multiple candidate threads.

[0033] In a possible implementation manner, when the scheduler determines, from the multiple candidate threads, target threads corresponding to the multiple first target register groups in the current processing cycle, the scheduler is configured to:

[0034] Based on the priorities of the commands to be issued respectively corresponding to the multiple candidate threads and the occupation status of the computing units corresponding to the commands to be issued, target threads corresponding to the multiple first target register groups in the current processing cycle are determined from the multiple candidate threads.

[0035] In a possible implementation manner, when the scheduler determines, from the multiple candidate threads, target threads corresponding to the multiple first target register groups in the current processing cycle, the scheduler is configured to:

[0036] Based on the command types of the current commands to be distributed corresponding to the candidate threads respectively and the type of the operation unit, target threads corresponding to the first target register groups respectively in the current processing cycle are determined from the candidate threads.

[0037] In a possible implementation manner, the scheduler is further configured to:

[0038] In response to the existence of a multi-operand to-be-dispatched command with more than one operand in the to-be-dispatched commands corresponding to the target thread determined for the current processing cycle, the first target register group corresponding to the multi-operand to-be-dispatched command distributes a corresponding operand to the computing unit corresponding to the to-be-dispatched command in each processing cycle from the current processing cycle to the target processing cycle;

[0039] The difference between the target processing cycle and the current processing cycle is equal to the number of the multiple operands reduced by one.

[0040] In a possible implementation manner, the scheduler is further configured to:

[0041] In response to the presence of a multi-operand to-be-dispatched command with two operands in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, for each single-operand to-be-dispatched command in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, in the next processing cycle of the current processing cycle, another single-operand to-be-dispatched command in a ready state is determined for the first target register group where the single-operand to-be-dispatched command is located.

[0042] In a possible implementation manner, the scheduler is further used to:

[0043] In response to the existence of a multi-operand to-be-dispatched command having more than one operand among the commands to be distributed corresponding to the target thread determined for the current processing cycle, determining the number of operands of the multi-operand to-be-dispatched command having the largest number of operands among the multi-operand to-be-dispatched commands;

[0044] For each other to-be-dispatched command corresponding to the target thread determined for the current processing cycle and having an operand number less than the maximum operand number, in each processing cycle from the next processing cycle of the current processing cycle to the processing cycle before the first target register group is scheduled again, in response to the first target register group where the other to-be-dispatched command is located being idle, determine a to-be-dispatched command in a ready state for the first target register group from the thread group corresponding to the first target register group;

[0045] The number of operations of the ready-to-be-dispatched command is not greater than the number of processing cycles from the processing cycle where the ready-to-be-dispatched command is located to the processing cycle where the first target register group is scheduled again.

[0046] In a possible implementation manner, the scheduler is further used to: obtain feedback information generated by the computing unit after executing the command;

[0047] Based on the feedback information, command execution status information corresponding to the thread to which the executed command belongs is generated.

[0048] In a possible implementation manner, the scheduler is further configured to:

[0049] Based on the number of the register groups and the number of currently executing threads, the currently executing threads are grouped to obtain thread groups corresponding to each of the register groups.

[0050] In a third aspect, the embodiments of the present disclosure further provide a chip, a controller, a command distributor, and an operator;

[0051] The controller is used to obtain commands corresponding to the multiple threads respectively, and send the commands to the command distributor;

[0052] The command distributor is used to distribute the command to the operator based on the command distribution method according to any one of the first aspects;

[0053] The operator is used to read operands from a target register group corresponding to a command distributed by the command distributor based on the command, and execute the command based on the operands.

[0054] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, comprising the chip described in the third aspect above.

[0055] In a fifth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the command distribution method described in any one of the above-mentioned first aspects are executed.

[0056] For a description of the effects of the above-mentioned command distributor, chip and electronic device, please refer to the description of the above-mentioned command distribution method, which will not be repeated here.

[0057] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0059] Figure 1 A flowchart of a command distribution method provided by an embodiment of the present disclosure is shown;

[0060] Figure 2 A specific example of the command distribution device provided by the embodiment of the present disclosure is shown;

[0061] Figure 3 A schematic diagram showing a specific example of distributing commands using a command distribution device provided in an embodiment of the present disclosure;

[0062] Figure 4 A schematic diagram of the structure of a command distributor provided by an embodiment of the present disclosure is shown;

[0063] Figure 5 A schematic structural diagram of a chip provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0065] After research, it was found that the command processing device includes: a controller, a command distribution unit, and multiple computing units. The controller obtains the command stream, and after preliminary processing of multiple commands in the command stream, transmits it to the command distribution unit; after the command distribution unit distributes the command to the computing unit, the computing units executing different commands obtain the register read permission through arbitration, and after obtaining the register read permission, read the operands required for executing the command from the register, and then based on the read operands, the arbitration of the register stack read permission will also cause a certain delay, affecting the throughput rate of the computing unit to the command, and then leading to the problem of low command distribution efficiency, resulting in low processing efficiency for executing a single command.

[0066] In addition, after the command is distributed to the command distribution unit, if the operands required to execute the command are not ready, the computing unit will switch to executing commands corresponding to other threads; this requires the command distribution unit to distribute new commands to the computing unit, which results in the possibility that some of the commands distributed to the computing unit cannot be executed immediately (they need to wait for the operands to be ready before they can be executed), which will reduce the efficiency of command distribution and cause low command processing efficiency.

[0067] Based on the above research, the present disclosure provides a command distribution method, which divides the registers in the register file into multiple register groups, and different register groups correspond to different thread groups. In each processing cycle, by determining multiple first target register groups, and from the thread groups corresponding to the multiple first target register groups, the target threads corresponding to the multiple first target register groups in the current processing cycle are determined, and the commands corresponding to the determined target threads are distributed to the corresponding operation units, so that in each processing cycle, each thread group will be accessed by at most one operation unit in each processing cycle, so that the operation units that receive the command do not need to arbitrate, and can directly access the corresponding register group to obtain the operands required by the command, thereby improving the efficiency of command distribution and the efficiency of command processing.

[0068] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0069] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0070] To facilitate understanding of this embodiment, a command distribution method disclosed in the embodiment of the present disclosure is first introduced in detail. The executor of the command distribution method provided in the embodiment of the present disclosure is generally a command processing device such as a central processing unit (CPU), a graphics processing unit (GPU), or an artificial intelligence (AI) chip.

[0071] In the embodiments of the present disclosure, the operand of a command is data that needs to be read from an external memory when executing the command; for example, if the command is: multiply data A and data B, then the corresponding command operands are data A and data B; for another example, if the command is to perform a convolution operation on a feature map M to be processed using a convolution kernel F, then the corresponding command operands are the feature map M and the convolution kernel F.

[0072] The command distribution method provided by the embodiment of the present disclosure is described below.

[0073] See also Figure 1 FIG. 1 is a flowchart of a command distribution method provided by an embodiment of the present disclosure, wherein the method includes steps S101 to S103, wherein:

[0074] S101: Determine a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups; wherein the first target register groups are different from a second target register group determined in at least one recent historical processing cycle;

[0075] S102: Determine, from the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle;

[0076] S103: Distribute the commands corresponding to the determined target threads to the corresponding computing units.

[0077] The disclosed embodiment divides registers into multiple register groups, and in each processing cycle, determines multiple first target register groups corresponding to the current processing cycle from the multiple register groups, and then determines target threads corresponding to the multiple first target register groups in the current processing cycle from the thread groups corresponding to the multiple first target register groups. After distributing commands corresponding to the multiple target threads to the operation units, since there is at most one operation unit accessing one register group in one processing cycle, there is no need for arbitration between the operation units that receive the commands. able It can directly access the corresponding register group to obtain the operands required by the command, thereby improving the efficiency of command distribution and the efficiency of command processing.

[0078] The above S101 to S103 are described in detail below.

[0079] In the above S101, for example, multiple registers can be divided into multiple register groups in advance. At the same time, the threads in the host that currently have commands issued are also divided into multiple thread groups. Each register group corresponds to a thread group. For each thread group, the operands corresponding to the commands generated by each thread in the thread group will be stored in the registers in the register group corresponding to the thread group.

[0080] Here, for example, based on the number of register groups and the number of currently executing threads, the currently executing threads may be grouped to obtain thread groups corresponding to each of the register groups.

[0081] When determining multiple first target register groups corresponding to the current processing cycle from multiple register groups, for example, the multiple register groups can be divided into at least two groups, each group including multiple register groups. In each processing cycle, the register groups included in one of the groups are determined as the first target register groups corresponding to the processing cycle. In multiple processing cycles, register groups in different groups are alternately determined as target register groups corresponding to multiple processing cycles.

[0082] Exemplarily, each register group may be numbered, and the processing cycle may be numbered, and the correspondence between the register group number and the processing cycle number may be predetermined. For example, in an even-numbered processing cycle in a processing cycle, the register group numbered with an even number may be determined as the target register group corresponding to the even-numbered processing cycle; in an odd-numbered processing cycle in a processing cycle, the register group numbered with an odd number may be determined as the target register group corresponding to the odd-numbered processing cycle.

[0083] Here, illustratively, the number of register groups may be related to the number of operands required in the executed command; for example, if the number of operands required in each command to be executed is at most 2, the number of register groups to be grouped is also 2; if the number of operands required in each command to be executed is at most 3, the number of register groups to be grouped is 3. Assume that the number of operands required in each command to be executed is at most n, that is, the number of register groups is n; thus, in the i-th processing cycle, if the first register group among the n register groups is used as the target register group, for the operation unit that receives the instruction requiring n operations, after receiving the command in the current i-th processing cycle, it will read an operand from the corresponding first target register group in the current i-th processing cycle, and then in the subsequent i+1 to i+n-1 processing cycles, the remaining n-1 operands from the corresponding first target register; and in the subsequent i+1 to i+n-1 processing cycles, the second to nth register groups will be used as the target register groups corresponding to the i+1 to i+n-1 processing cycles respectively, thereby avoiding conflicts in the operation units' access to the same register group.

[0084] With respect to the above S102, after determining a plurality of first target register groups corresponding to the current processing cycle, for example, at least one of the following methods may be used to determine a plurality of target threads from thread groups respectively corresponding to the plurality of first target register groups:

[0085] (1): For each first target register group, an order is determined for multiple threads in a thread group corresponding to the first target register group in a cyclic manner, and according to the order, different threads in the thread group are determined as target threads corresponding to the first target register group in different processing cycles.

[0086] (2) For each first target register group, in the thread group corresponding to the first target register group, a thread having a command in the current processing cycle is selected as a candidate thread, and according to the priorities of the candidate threads, the candidate thread with the highest priority is selected as the target thread of the first target register group in the current processing cycle.

[0087] (3) Determine target threads corresponding to the plurality of first target register groups in a current processing cycle based on command execution status information of each thread in the thread groups corresponding to the plurality of first target register groups.

[0088] Here, for example, for each first target register group, multiple candidate threads whose command execution status information is in the ready state can be determined from the thread group corresponding to the first target register group; and target threads corresponding to the multiple first target register groups respectively in the current processing cycle can be determined from the multiple candidate threads.

[0089] Here, the command execution status information corresponding to any thread includes, for example, whether the command recently distributed to the computing unit by the thread has been executed, and / or whether the operands required by the command currently to be distributed by the thread have been prepared.

[0090] The operands corresponding to the command are prepared, for example, data generated by other commands that the command depends on have been stored in corresponding registers, and / or operands that need to be read from the external memory have been stored in corresponding registers.

[0091] If the command most recently distributed to the computing unit by the thread has been executed, and / or the operands required by the command currently to be distributed corresponding to the thread have been prepared, the command execution status information corresponding to the thread is considered to be in the ready state, and the thread corresponding to the command can be used as the target thread.

[0092] In this case, in another embodiment of the present disclosure, the method further includes: obtaining feedback information generated by the operation unit after executing the command; and generating command execution status information corresponding to the thread to which the executed command belongs based on the feedback information.

[0093] In this way, the command distributor can learn the execution status of the commands by each computing unit in real time.

[0094] In addition, in a possible implementation, the above-mentioned method (3) can determine a target thread number greater than 1 for a first target register group, and can also determine the target thread from multiple threads that meet the requirements of (3) in combination with the priorities corresponding to each thread, or in a circular manner.

[0095] It should be noted that there may be a situation in which a first target register set does not have a target thread in a certain processing cycle, that is, the number of determined target threads is less than the number of first target register sets.

[0096] When determining the target threads corresponding to the plurality of first target register groups respectively in the current processing cycle from the determined plurality of candidate threads, for example, any one of the following methods ① to ③ may be adopted:

[0097] ①: Based on the priorities of the to-be-dispatched commands respectively corresponding to the multiple candidate threads, target threads respectively corresponding to the multiple first target register groups in the current processing cycle are determined from the multiple candidate threads.

[0098] ②: Based on the priorities of the commands to be distributed corresponding to the multiple candidate threads and the occupation status of the computing units corresponding to the commands to be distributed, determine the target threads corresponding to the multiple first target register groups in the current processing cycle from the multiple candidate threads.

[0099] Here, the occupancy status of the computing unit includes, for example: a specific target thread has been allocated to the computing unit in the current processing cycle; and / or the number of commands received by the computing unit in the historical processing cycle and not yet executed reaches a preset number.

[0100] Exemplarily, the following process is performed in descending order of priority:

[0101] According to the priorities of the commands to be distributed corresponding to the candidate threads, at least one command to be distributed with the highest priority is determined, and then based on the occupation state of the computing unit corresponding to the command to be distributed with the highest priority, it is determined whether the command to be distributed with the highest priority can be distributed to the corresponding computing unit; if it can be distributed to the corresponding computing unit, the candidate thread corresponding to the command to be distributed with the highest priority is determined as the target thread. If it cannot be distributed to the corresponding computing unit, the candidate thread corresponding to the command to be distributed is not used as the target thread.

[0102] Then, at least one command to be distributed with the second highest priority is determined from the candidate threads, and then based on the occupancy status of the computing unit corresponding to the command to be distributed with the second highest priority, it is determined whether the command to be distributed with the second highest priority can be distributed to the corresponding computing unit.

[0103] …

[0104] At least one to-be-distributed command with the lowest priority is determined from the candidate threads, and then based on the occupation status of the computing unit corresponding to the to-be-distributed command with the lowest priority, it is determined whether the to-be-distributed command with the lowest priority can be distributed to the corresponding computing unit.

[0105] Based on the above process, target threads corresponding to the plurality of first target register groups respectively in the current processing cycle are determined from the plurality of candidate threads.

[0106] ③: Based on the command types of the current commands to be distributed corresponding to the multiple candidate threads respectively and the type of the operation unit, determine the target threads corresponding to the multiple first target register groups respectively in the current processing cycle from the multiple candidate threads.

[0107] Here, different types of computing units can process different types of commands.

[0108] Exemplarily, for the arithmetic operation unit, the command type that can be processed is the arithmetic operation command; for the write address operation unit, the command type that can be processed is the write address command; for the read address operation unit, the command type that can be processed is the read address command; and for the transcendental function operation unit, the command type that can be processed is the transcendental function processing.

[0109] When determining the target thread, multiple target threads that can match the types of each computing unit will be determined from the candidate threads according to the types of commands to be distributed corresponding to each candidate thread, and then the current commands to be distributed corresponding to the target thread will be distributed to the computing unit with matching types.

[0110] In another embodiment of the present disclosure, for certain commands, the number of operands required when executing the command may be different.

[0111] After the command to be distributed corresponding to the target thread is distributed to the operation unit, the operation unit needs at least one cycle to read the operand corresponding to the command to be distributed from the corresponding register group; wherein the number of cycles for reading the operand is the same as the number of operands corresponding to the command to be distributed.

[0112] Furthermore, in response to the existence of a multi-operand to-be-dispatched command having more than one operand in the to-be-dispatched commands corresponding to the target thread determined for the current processing cycle, the first target register group corresponding to the multi-operand to-be-dispatched command distributes a corresponding operand to the computing unit corresponding to the to-be-dispatched command in each processing cycle from the current processing cycle to the target processing cycle;

[0113] The difference between the target processing cycle and the current processing cycle is equal to the number of the multiple operands reduced by one.

[0114] For commands to be distributed with fewer operands, the operation unit can read operands corresponding to different commands to be distributed from the same target register group in multiple cycles.

[0115] Further, in response to the existence of a multi-operand to-be-dispatched command having more than one operand in the commands to be distributed corresponding to the target thread determined for the current processing cycle, determining the number of operands of the multi-operand to-be-dispatched command having the largest number of operands in the multi-operand to-be-dispatched commands;

[0116] For each other to-be-dispatched command corresponding to the target thread determined for the current processing cycle and having an operand number less than the maximum operand number, in each processing cycle from the next processing cycle of the current processing cycle to the processing cycle before the first target register group is scheduled again, in response to the first target register group where the other to-be-dispatched command is located being idle, determine a to-be-dispatched command in a ready state for the first target register group from the thread group corresponding to the first target register group;

[0117] The number of operations of the ready-to-be-dispatched command is not greater than the number of processing cycles from the processing cycle where the ready-to-be-dispatched command is located to the processing cycle where the first target register group is scheduled again.

[0118] Exemplarily, for example, in response to the presence of a multi-operand to-be-dispatched command with two operands in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, for each single-operand to-be-dispatched command in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, in the next processing cycle of the current processing cycle, another single-operand to-be-dispatched command in a ready state is determined for the first target register group where the single-operand to-be-dispatched command is located.

[0119] In this way, the operation unit can read multiple operands corresponding to multi-operand instructions to be distributed from the first target register group corresponding to the multi-operand commands to be distributed in multiple processing cycles, and at the same time, the operation unit can read the operands corresponding to different single-operand commands to be distributed from the first target register group to which the single-operand command pair is located in multiple processing cycles, thereby improving the efficiency of data reading while avoiding reading conflicts on the same target register group.

[0120] In one implementation, the number N of register groups can be determined based on the number of operands of the operation unit that requires the largest number of operands, so that in N consecutive processing cycles, the N register groups can be scheduled separately. Then, after the i-th register group is scheduled in the i-th processing cycle, it will take Ni cycles before the i-th register group is scheduled again. Assuming that the command corresponding to the register group scheduled in the i-th processing cycle just requires N operands, then for the i-th register group, the N operands can be distributed to the corresponding operation units in N cycles. If the number of operands required by the command corresponding to the register group scheduled in the i-th processing cycle is less than N, the command whose number of operands matches the number of cycles remaining before the next scheduling can be flexibly scheduled to improve data reading efficiency.

[0121] See also Figure 2 and Figure 3As shown, the embodiment of the present disclosure also provides a command distribution device and a specific example of using the command distribution device to distribute commands. In this example, it includes a command distributor and five computing units connected to the command distributor. The five computing units are:

[0122] Two Arithmetic and Logic Units (ALUs) that process instructions that require two operands.

[0123] A write address operation unit (Store Unit, ST), the instructions processed require two operands.

[0124] A load unit (LD) processes instructions that require an operand.

[0125] A tensor function unit (TFU) processes instructions that require two operands. There are 64 threads, thread 0 to thread 63, 8 register banks, Bank 0 to Bank 7, and 5 operation units. Each register bank is assigned 8 threads.

[0126] Each bank has only one set of read paths. In one processing cycle, conflicts will occur when different arithmetic units access the same register group, but conflicts will not occur when different arithmetic units access different banks.

[0127] For instructions with two operands, the operands need to be read in two cycles in the same bank.

[0128] In odd cycles, the register groups numbered 1, 3, 5, and 7 are used as the first register groups.

[0129] From the 8 threads assigned to each even-numbered bank, select the valid and highest priority ALU, ST, LD, and TFU instructions respectively.

[0130] From these even-numbered banks, the two ALU instructions with the highest priority are selected and distributed first.

[0131] When the bank corresponding to the ALU instruction is occupied, the ST instruction is selected from the remaining bank and distributed.

[0132] When the bank for ALU and ST instructions is occupied, LD instructions are selected from the remaining banks and distributed.

[0133] Since the ALU and ST instructions have two operands, the operands still need to be read from the same bank in the next cycle. Therefore, when the bank of the ALU and ST instructions is occupied, the TFU instruction is selected from the remaining bank and distributed in the next processing cycle.

[0134] The two-operand instructions dispatched in the even cycle need to read the instructions of the same even bank in the next odd cycle, but since only the instructions of the odd bank will be dispatched in the next cycle, there will be no bank conflict problem. The same applies to the scheduling method of the odd cycle.

[0135] like Figure 3 As shown:

[0136] A: In the 0th processing cycle, the determined banks are: Bank0, Bank2, Bank4 and Bank6.

[0137] The command determined for Bank0 is an ALU command, and the arithmetic unit that reads operands from Bank0 is ALU0, and the ALU command is distributed to ALU0 in the 0th processing cycle. In the 0th processing cycle and the 1st processing cycle, the arithmetic unit ALU0 reads the first operand ALU0_R0 and the second operand ALU0_R1 from Bank0 respectively.

[0138] The command determined for Bank2 is the ST command, and in the 0th processing cycle, the ST command is distributed to the ST unit. The operation unit that reads the operand from Bank2 is ST, and in the 0th processing cycle and the 1st processing cycle, the operation unit ST reads the first operand ST_R0 and the second operand ST_R1 from Bank2 respectively.

[0139] The commands determined for Bank4 are LD command and TFU command, and the operation units that read operands from Bank4 are LD and TFU. In the 0th processing cycle, the LD command is distributed to the operation unit LD, and the operation unit LD reads the operand corresponding to the LD command from Bank4; in the 1st processing cycle, the TFU command is distributed to the operation unit TFU, and the operation unit TFU reads the operand corresponding to the TFU command from Bank4.

[0140] The command determined for Bank6 is an ALU command, and the ALU command is distributed to the ALU unit in the 0th processing cycle. The operation unit that reads the operand from Bank6 is ALU, and in the 0th processing cycle and the 1st processing cycle, the operation unit ALU reads the first operand ALU1_R0 and the second operand ALU1_R1 from Bank6 respectively.

[0141] B: In the first processing cycle, the determined banks are: Bank1, Bank3, Bank5 and Bank6.

[0142] The command determined for Bank1 is the ST command, and in the first processing cycle, the ST command is distributed to the ST unit. The operation unit that reads the operand from Bank1 is ST, and in the first processing cycle and the second processing cycle, the operation unit ST reads the first operand ST_R0 and the second operand ST_R1 from Bank1 respectively.

[0143] The command determined for Bank3 is an ALU command, and the arithmetic unit that reads operands from Bank3 is ALU0, and in the first processing cycle, the ALU command is distributed to ALU0. In the second processing cycle and the first processing cycle, the arithmetic unit ALU0 reads the first operand ALU0_R0 and the second operand ALU0_R1 from Bank3 respectively.

[0144] The command determined for Bank5 is an ALU command, and in the first processing cycle, the ALU command is distributed to the ALU units. The arithmetic unit that reads operands from Bank5 is ALU1, and in the first processing cycle and the second processing cycle, the arithmetic unit ALU1 reads the first operand ALU1_R0 and the second operand ALU1_R1 from Bank5 respectively.

[0145] The commands determined for Bank7 are the LD command and the TFU command, and the operation units that read the operands from Bank7 are LD and TFU. In the first processing cycle, the LD command is distributed to the operation unit LD, and the operation unit LD reads the operand corresponding to the LD command from Bank7; in the second processing cycle, the TFU command is distributed to the operation unit TFU, and the operation unit TFU reads the operand corresponding to the TFU command from Bank7.

[0146] Then in the 3rd processing cycle, the 4th processing cycle, and up to the 8th processing cycle, through this method, in the same processing cycle, it is ensured that only one computing unit accesses each register group, thereby avoiding data conflicts caused by multiple computing units accessing the same register group in the same processing cycle, improving the efficiency of command distribution, and thus improving the efficiency of command processing.

[0147] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0148] Based on the same inventive concept, a command distributor corresponding to the command distribution method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the command distributor in the embodiment of the present disclosure is similar to the above-mentioned command distribution method in the embodiment of the present disclosure, the implementation of the command distributor can refer to the implementation of the method, and the repeated parts will not be repeated.

[0149] Reference Figure 4 , which is a schematic diagram of a command distributor provided by an embodiment of the present disclosure, the command distributor includes: a scheduler 41, and a distribution interface 42;

[0150] The scheduler 41 is configured to determine a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups; wherein the first target register group is different from a second target register group determined in at least one recent historical processing cycle; and determine, from thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in the current processing cycle;

[0151] The distribution interface 42 is used to distribute commands corresponding to the determined target threads to the corresponding computing units.

[0152] In a possible implementation manner, when determining a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups, the scheduler 41 is configured to:

[0153] In a case where the current processing cycle is an odd-numbered cycle, determining an odd-numbered register group among the multiple register groups as the first target register group;

[0154] When the current processing cycle is an even-numbered cycle, an even-numbered register group among the multiple register groups is determined as the first target register group.

[0155] In a possible implementation manner, the scheduler 41 is further configured to:

[0156] The number of register groups is determined according to the number of operands of the operation unit requiring the largest number of operands, and the registers are divided into the plurality of register groups.

[0157] In a possible implementation manner, the scheduler 41, when determining, from the thread groups corresponding to the plurality of first target register groups, the target threads corresponding to the plurality of first target register groups in the current processing cycle, is configured to:

[0158] Based on the determined command execution status information of each thread in the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle are determined from the thread groups corresponding to the plurality of first target register groups.

[0159] In a possible implementation manner, the scheduler 41, when determining, from the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle, is configured to:

[0160] Determine, from the thread groups respectively corresponding to the plurality of first target register groups, a plurality of candidate threads whose command execution status information is in a ready state;

[0161] From the multiple candidate threads, target threads corresponding to the multiple first target register groups respectively in a current processing cycle are determined.

[0162] In a possible implementation manner, when the scheduler 41 determines the target threads corresponding to the plurality of first target register groups respectively in the current processing cycle from the plurality of candidate threads, it is configured to:

[0163] Based on the priorities of the to-be-dispatched commands respectively corresponding to the multiple candidate threads, target threads respectively corresponding to the multiple first target register groups in a current processing cycle are determined from the multiple candidate threads.

[0164] In a possible implementation manner, when the scheduler 41 determines the target threads corresponding to the plurality of first target register groups respectively in the current processing cycle from the plurality of candidate threads, it is configured to:

[0165] Based on the priorities of the commands to be issued respectively corresponding to the multiple candidate threads and the occupation status of the computing units corresponding to the commands to be issued, target threads corresponding to the multiple first target register groups in the current processing cycle are determined from the multiple candidate threads.

[0166] In a possible implementation manner, when the scheduler 41 determines the target threads corresponding to the plurality of first target register groups respectively in the current processing cycle from the plurality of candidate threads, it is configured to:

[0167] Based on the command types of the current commands to be distributed corresponding to the candidate threads respectively and the type of the operation unit, target threads corresponding to the first target register groups respectively in the current processing cycle are determined from the candidate threads.

[0168] In a possible implementation manner, the scheduler 41 is further configured to:

[0169] In response to the existence of a multi-operand to-be-dispatched command with more than one operand in the to-be-dispatched commands corresponding to the target thread determined for the current processing cycle, the first target register group corresponding to the multi-operand to-be-dispatched command distributes a corresponding operand to the computing unit corresponding to the to-be-dispatched command in each processing cycle from the current processing cycle to the target processing cycle;

[0170] The difference between the target processing cycle and the current processing cycle is equal to the number of the multiple operands reduced by one.

[0171] In a possible implementation manner, the scheduler 41 is further configured to:

[0172] In response to the presence of a multi-operand to-be-dispatched command with two operands in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, for each single-operand to-be-dispatched command in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, in the next processing cycle of the current processing cycle, another single-operand to-be-dispatched command in a ready state is determined for the first target register group where the single-operand to-be-dispatched command is located.

[0173] In a possible implementation manner, the scheduler 41 is further configured to:

[0174] In response to the existence of a multi-operand to-be-dispatched command having more than one operand among the commands to be distributed corresponding to the target thread determined for the current processing cycle, determining the number of operands of the multi-operand to-be-dispatched command having the largest number of operands among the multi-operand to-be-dispatched commands;

[0175] For each other to-be-dispatched command corresponding to the target thread determined for the current processing cycle and having an operand number less than the maximum operand number, in each processing cycle from the next processing cycle of the current processing cycle to the processing cycle before the first target register group is scheduled again, in response to the first target register group where the other to-be-dispatched command is located being idle, determine a to-be-dispatched command in a ready state for the first target register group from the thread group corresponding to the first target register group;

[0176] The number of operations of the ready-to-be-dispatched command is not greater than the number of processing cycles from the processing cycle where the ready-to-be-dispatched command is located to the processing cycle where the first target register group is scheduled again.

[0177] In a possible implementation manner, the scheduler 41 is further configured to: obtain feedback information generated by the computing unit after executing the command;

[0178] Based on the feedback information, command execution status information corresponding to the thread to which the executed command belongs is generated.

[0179] In a possible implementation manner, the scheduler 41 is further configured to:

[0180] Based on the number of the register groups and the number of currently executing threads, the currently executing threads are grouped to obtain thread groups corresponding to each of the register groups.

[0181] For the description of the processing flow of each module in the command distributor and the interaction flow between each module, reference can be made to the relevant description in the above method embodiment, which will not be described in detail here.

[0182] In addition, the command distributor provided in the embodiment of the present disclosure may be a chip that can implement the command distribution method provided in the embodiment of the present disclosure.

[0183] The present disclosure also provides a chip, such as Figure 5 As shown, it includes: a controller 51, a command distributor 52, and an operator 53;

[0184] The controller 51 is used to obtain commands corresponding to the multiple threads respectively, and send the commands to the command distributor 52;

[0185] The command distributor 52 is used to distribute the command to the operator 53 based on the command distribution method provided by any embodiment of the present disclosure;

[0186] The operator 53 is used to read an operand from a first target register group corresponding to the command, and execute the command based on the operand.

[0187] The specific process of executing commands by the above-mentioned command execution device can refer to the steps of the command distribution method described in the embodiment of the present disclosure, which will not be repeated here.

[0188] An embodiment of the present disclosure also provides an electronic device, comprising the chip provided by any embodiment of the present disclosure.

[0189] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the command distribution method described in the above method embodiment are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0190] The present disclosure also provides a computer program product that carries a program code. The program code includes instructions that can be used to execute the steps of the command distribution method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0191] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0192] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0193] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0194] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one computing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0195] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several commands to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0196] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A command distribution method, characterized in that: include: Determine a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups; wherein the first target register groups are different from a second target register group determined in at least one recent historical processing cycle; Determining, from the thread groups corresponding to the plurality of first target register groups respectively, target threads corresponding to the plurality of first target register groups respectively in a current processing cycle; Distribute commands corresponding to the determined target threads to the corresponding computing units; Also includes: In response to the presence of a multi-operand to-be-dispatched command with two operands in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, for each single-operand to-be-dispatched command in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, in the next processing cycle of the current processing cycle, another single-operand to-be-dispatched command in a ready state is determined for the first target register group where the single-operand to-be-dispatched command is located.

2. The command distribution method according to claim 1, characterized in that: The step of determining a plurality of first target register groups corresponding to the current processing cycle from the plurality of register groups includes: In a case where the current processing cycle is an odd-numbered cycle, determining an odd-numbered register group among the multiple register groups as the first target register group; When the current processing cycle is an even-numbered cycle, an even-numbered register group among the multiple register groups is determined as the first target register group.

3. The command distribution method according to claim 1, characterized in that: Also includes: The number of register groups is determined according to the number of operands of the operation unit requiring the largest number of operands, and the registers are divided into the plurality of register groups.

4. The command distribution method according to any one of claims 1 to 3, characterized in that: The step of determining, from the thread groups corresponding to the plurality of first target register groups respectively, the target threads corresponding to the plurality of first target register groups respectively in the current processing cycle comprises: Based on the determined command execution status information of each thread in the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle are determined from the thread groups corresponding to the plurality of first target register groups.

5. The command distribution method according to claim 4, characterized in that: The step of determining, based on the determined command execution status of each thread in the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle from the thread groups corresponding to the plurality of first target register groups comprises: Determine, from the thread groups respectively corresponding to the plurality of first target register groups, a plurality of candidate threads whose command execution status information is in a ready state; From the multiple candidate threads, target threads corresponding to the multiple first target register groups respectively in a current processing cycle are determined.

6. The command distribution method according to claim 5, characterized in that: The step of determining, from the plurality of candidate threads, target threads corresponding to the plurality of first target register groups in the current processing cycle respectively comprises: Based on the priorities of the to-be-dispatched commands respectively corresponding to the multiple candidate threads, target threads respectively corresponding to the multiple first target register groups in a current processing cycle are determined from the multiple candidate threads.

7. The command distribution method according to claim 5, characterized in that: The step of determining, from the plurality of candidate threads, target threads corresponding to the plurality of first target register groups in the current processing cycle respectively comprises: Based on the priorities of the commands to be issued respectively corresponding to the multiple candidate threads and the occupation status of the computing units corresponding to the commands to be issued, target threads corresponding to the multiple first target register groups in the current processing cycle are determined from the multiple candidate threads.

8. The command distribution method according to claim 5, characterized in that: The step of determining, from the plurality of candidate threads, target threads corresponding to the plurality of first target register groups in the current processing cycle respectively comprises: Based on the command types of the current commands to be distributed corresponding to the candidate threads respectively and the type of the operation unit, target threads corresponding to the first target register groups respectively in the current processing cycle are determined from the candidate threads.

9. The command distribution method according to any one of claims 1 to 3, characterized in that: Also includes: In response to the existence of a multi-operand to-be-dispatched command with more than one operand in the to-be-dispatched commands corresponding to the target thread determined for the current processing cycle, the first target register group corresponding to the multi-operand to-be-dispatched command distributes a corresponding operand to the computing unit corresponding to the to-be-dispatched command in each processing cycle from the current processing cycle to the target processing cycle; The difference between the target processing cycle and the current processing cycle is equal to the number of the multiple operands reduced by one.

10. The command distribution method according to any one of claims 1 to 3, characterized in that: Also includes: In response to the existence of a multi-operand to-be-dispatched command having more than one operand among the commands to be distributed corresponding to the target thread determined for the current processing cycle, determining the number of operands of the multi-operand to-be-dispatched command having the largest number of operands among the multi-operand to-be-dispatched commands; For each other to-be-dispatched command corresponding to the target thread determined for the current processing cycle and having an operand number less than the maximum operand number, in response to the first target register group where other to-be-dispatched commands are located being idle, determining a to-be-dispatched command in a ready state for the first target register group from the thread group corresponding to the first target register group in each processing cycle from the next processing cycle of the current processing cycle to the processing cycle before the first target register group is scheduled again, in response to the first target register group where other to-be-dispatched commands are located being idle, The number of operations of the ready-to-be-dispatched command is not greater than the number of processing cycles from the processing cycle where the ready-to-be-dispatched command is located to the processing cycle where the first target register group is scheduled again.

11. The command distribution method according to claim 4, characterized in that: Also includes: Obtaining feedback information generated by the computing unit after executing the command; Based on the feedback information, command execution status information corresponding to the thread to which the executed command belongs is generated.

12. The command distribution method according to any one of claims 1 to 3, characterized in that: Also includes: Based on the number of the register groups and the number of currently executing threads, the currently executing threads are grouped to obtain thread groups corresponding to each of the register groups.

13. A command distributor, characterized in that: include: Scheduler, and dispatch interface; The scheduler is configured to determine a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups; wherein the first target register group is different from a second target register group determined in at least one recent historical processing cycle; and determine, from thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in the current processing cycle; The distribution interface is used to distribute commands corresponding to the determined target threads to the corresponding computing units; The scheduler is further used for: In response to the presence of a multi-operand to-be-dispatched command with two operands in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, for each single-operand to-be-dispatched command in the commands to-be-dispatched corresponding to the target thread determined for the current processing cycle, in the next processing cycle of the current processing cycle, another single-operand to-be-dispatched command in a ready state is determined for the first target register group where the single-operand to-be-dispatched command is located.

14. The command distributor according to claim 13, characterized in that: The scheduler, when determining a plurality of first target register groups corresponding to a current processing cycle from a plurality of register groups, is configured to: In a case where the current processing cycle is an odd-numbered cycle, determining an odd-numbered register group among the multiple register groups as the first target register group; When the current processing cycle is an even-numbered cycle, an even-numbered register group among the multiple register groups is determined as the first target register group.

15. The command distributor according to claim 13, characterized in that: The scheduler is further used for: The number of register groups is determined according to the number of operands of the operation unit requiring the largest number of operands, and the registers are divided into the plurality of register groups.

16. The command distributor according to any one of claims 13 to 15, characterized in that: The scheduler, when determining, from the thread groups corresponding to the plurality of first target register groups respectively, the target threads corresponding to the plurality of first target register groups in the current processing cycle respectively, is configured to: Based on the determined command execution status information of each thread in the thread groups corresponding to the plurality of first target register groups, target threads corresponding to the plurality of first target register groups in a current processing cycle are determined from the thread groups corresponding to the plurality of first target register groups.

17. The command distributor according to claim 16, characterized in that: The scheduler, when determining, from the thread groups corresponding to the plurality of first target register groups respectively, target threads corresponding to the plurality of first target register groups respectively in a current processing cycle, is configured to: Determine, from the thread groups respectively corresponding to the plurality of first target register groups, a plurality of candidate threads whose command execution status information is in a ready state; From the multiple candidate threads, target threads corresponding to the multiple first target register groups respectively in a current processing cycle are determined.

18. The command distributor according to claim 17, characterized in that: The scheduler, when determining, from the plurality of candidate threads, target threads corresponding to the plurality of first target register groups respectively in a current processing cycle, is configured to: Based on the priorities of the to-be-dispatched commands respectively corresponding to the multiple candidate threads, target threads respectively corresponding to the multiple first target register groups in a current processing cycle are determined from the multiple candidate threads.

19. The command distributor according to claim 17, characterized in that: The scheduler, when determining, from the plurality of candidate threads, target threads corresponding to the plurality of first target register groups respectively in a current processing cycle, is configured to: Based on the priorities of the commands to be issued respectively corresponding to the multiple candidate threads and the occupation status of the computing units corresponding to the commands to be issued, target threads corresponding to the multiple first target register groups in the current processing cycle are determined from the multiple candidate threads.

20. The command distributor according to claim 17, characterized in that: The scheduler, when determining, from the plurality of candidate threads, target threads corresponding to the plurality of first target register groups respectively in a current processing cycle, is configured to: Based on the command types of the current commands to be distributed corresponding to the candidate threads respectively and the type of the operation unit, target threads corresponding to the first target register groups respectively in the current processing cycle are determined from the candidate threads.

21. The command distributor according to any one of claims 13 to 15, characterized in that: The scheduler is further used for: In response to the existence of a multi-operand to-be-dispatched command with more than one operand in the to-be-dispatched commands corresponding to the target thread determined for the current processing cycle, the first target register group corresponding to the multi-operand to-be-dispatched command distributes a corresponding operand to the computing unit corresponding to the to-be-dispatched command in each processing cycle from the current processing cycle to the target processing cycle; The difference between the target processing cycle and the current processing cycle is equal to the number of the multiple operands reduced by one.

22. The command distributor according to any one of claims 13 to 15, characterized in that: The scheduler is also used for: In response to the existence of a multi-operand to-be-dispatched command having more than one operand among the commands to be distributed corresponding to the target thread determined for the current processing cycle, determining the number of operands of the multi-operand to-be-dispatched command having the largest number of operands among the multi-operand to-be-dispatched commands; For each other to-be-dispatched command corresponding to the target thread determined for the current processing cycle and having an operand number less than the maximum operand number, in response to the first target register group where other to-be-dispatched commands are located being idle, determining a to-be-dispatched command in a ready state for the first target register group from the thread group corresponding to the first target register group in each processing cycle from the next processing cycle of the current processing cycle to the processing cycle before the first target register group is scheduled again, in response to the first target register group where other to-be-dispatched commands are located being idle, The number of operations of the ready-to-be-dispatched command is not greater than the number of processing cycles from the processing cycle where the ready-to-be-dispatched command is located to the processing cycle where the first target register group is scheduled again.

23. The command distributor according to claim 16, characterized in that: The scheduler is further used to: obtain feedback information generated by the computing unit after executing the command; Based on the feedback information, command execution status information corresponding to the thread to which the executed command belongs is generated.

24. The command distributor according to any one of claims 13 to 15, characterized in that: The scheduler is further used for: Based on the number of the register groups and the number of currently executing threads, the currently executing threads are grouped to obtain thread groups corresponding to each of the register groups.

25. A chip, characterized in that: include: Controller, command distributor, and operator; The controller is used to obtain commands corresponding to the multiple threads respectively, and send the commands to the command distributor; The command distributor is used to distribute the command to the operator based on the command distribution method according to any one of claims 1 to 12; The operator is used to read operands from a target register group corresponding to a command distributed by the command distributor based on the command, and execute the command based on the operands.

26. An electronic device, characterized in that: Comprising the chip as claimed in claim 25.

27. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the command distribution method according to any one of claims 1 to 12 are executed.

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