A method, device and storage medium for timestamp calibration of multi-channel pulse signals

Abstract

The present application discloses a method, device, and storage medium for timestamp calibration of multi-channel pulse signals. The method includes: dividing a large-capacity SRAM into a first storage area and a second storage area; based on the current storage address of the first storage area, using a DMA peripheral, constructing a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area; when the MCU chip receives a sampling request, controlling the DMA peripheral to collect the port status data of the IO port through a first periodic signal generated by a first crystal oscillator in the MCU chip; adding a timestamp to the port status data and storing it in the first storage area; when the collected port status data reaches a preset threshold, constructing a mapping relationship between the IO port and the second storage area, and controlling the FLASH memory in the MCU chip through a second periodic signal generated by a second crystal oscillator to receive the port status data set in the first storage area. Through the above method, the present application realizes timestamp calibration of sampled high-speed signals using a low-cost general-purpose MCU chip.

Description

Technical Field

[0001] The present application relates to the technical field of logic level time domain pulse signal analysis, and in particular to a timestamp calibration method, device and storage medium for multi-channel pulse signals. Background Art

[0002] In various electronic devices, various physical signals can be converted into logic-level signals through level conversion circuits. When electronic devices are running, they are constantly receiving logic-level signals. For low-speed switching signals, common electronic systems can determine the level of the signal, but the trigger timing of high-speed pulse signals is often unable to be accurately known.

[0003] If you need to analyze the timing of pulse signals over a period of time, accurately calibrating the trigger time of the pulse signals is essential. However, in general-purpose MCU chip applications, the performance of the MCU is limited, making it impossible to sample and timestamp high-speed signals. Adding high-speed sampling circuits and timestamp calibration procedures would increase product costs. Therefore, how to use low-cost general-purpose MCU chips to timestamp sampled high-speed signals has become a pressing technical challenge. Summary of the Invention

[0004] The embodiments of the present application provide a method, device, and storage medium for timestamp calibration of multi-channel pulse signals to solve the following technical problem: how to use a low-cost general-purpose MCU chip to timestamp calibrate sampled high-speed signals.

[0005] In the first aspect, an embodiment of the present application provides a timestamp calibration method for a multi-channel pulse signal, characterized in that the method includes: dividing a large-capacity SRAM into blocks to determine a first storage area and a second storage area; wherein the large-capacity SRAM is a large-capacity static random access memory in the MCU chip; based on the current storage address of the first storage area, a mapping relationship between a multi-channel pulse signal sampling IO port and the first storage area is constructed through a DMA peripheral; wherein the current storage address is a storage address corresponding to the first storage space in the storage space in the first storage area where no data has been stored, and the DMA peripheral is a module in the MCU chip for implementing a DMA data transmission method; when the MCU chip receives a pulse signal sampling request, the DMA peripheral is used to The first periodic signal generated by the first crystal oscillator in the MCU chip is used to control the DMA peripheral to collect the port status data of the multi-channel pulse signal sampling IO port; a timestamp is added to the port status data, and the port status data with the timestamp is stored in the first storage area; wherein the port status data is used to describe all port states of the multi-channel pulse signal sampling IO port; when the collected port status data reaches a preset threshold, the current storage address of the second storage area is sent to the DMA peripheral, a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area is established, and the second periodic signal generated by the second crystal oscillator in the MCU chip is used to control the FLASH memory in the MCU chip to receive the port status data set in the first storage area.

[0006] In one implementation of the present application, before dividing the large-capacity SRAM into blocks to determine the first storage area and the second storage area, the method also includes: determining the power-on time of the system clock source as the time reference zero point; based on the time reference zero point, initializing the first crystal oscillator and the second crystal oscillator so that the time reference zero point of the first periodic signal generated by the first crystal oscillator and the second periodic signal generated by the second crystal oscillator is the power-on time of the system clock source; wherein the period of the second periodic signal is equal to the period of a preset number of first periodic signals.

[0007] In one implementation of the present application, before constructing a mapping relationship between a multi-channel pulse signal sampling IO port and the first storage area through a DMA peripheral based on the current storage address of the first storage area, the method also includes: determining the working mode of the DMA peripheral based on the port number of the multi-channel pulse signal sampling IO port; wherein the working mode is a program for sampling the multi-channel pulse signal sampling IO port with a fixed port number; and determining the first crystal oscillator as the driving clock source of the DMA peripheral.

[0008] In one implementation of the present application, based on the current storage address of the first storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is constructed through a DMA peripheral, specifically including: binding a temporary register address in the DMA peripheral to the multi-channel pulse signal sampling IO port so that the DMA peripheral can collect the initial port status data of each port corresponding to the multi-channel pulse signal sampling IO port; binding a temporary register address in the DMA peripheral to the current storage address of the first storage area so that the DMA peripheral can upload the port status data obtained based on the initial port status data to the first storage area.

[0009] In one implementation of the present application, the first periodic signal generated by the first crystal oscillator in the MCU chip is used to control the DMA peripheral to collect the port status data of the multi-channel pulse signal sampling IO port, specifically including: starting the DMA peripheral based on the first periodic signal to collect the initial port status data of each port corresponding to the multi-channel pulse signal sampling IO port; sorting the initial port status data of each port based on the port number corresponding to each initial port status data, and compressing the initial port status data in the correct order to obtain the port status data.

[0010] In one implementation of the present application, adding a timestamp to the port status data specifically includes: determining the status data acquisition period corresponding to the first cycle signal when acquiring the port status data; determining the period start time corresponding to the status data acquisition period based on the power-on time of the system clock source; compiling the period start time to obtain the timestamp corresponding to the port status data, and calibrating the timestamp with the port status data to achieve adding a timestamp to the port status data.

[0011] In one implementation of the present application, after storing the port status data with the timestamp added in the first storage area, the method also includes: self-incrementing the current storage address of the first storage area, and re-binding the self-incremented current storage address to the temporary register address in the DMA peripheral, so that the DMA peripheral can upload the port status data of the next cycle to the first storage area.

[0012] In one implementation of the present application, after controlling the FLASH memory in the MCU chip and receiving the port status data set in the first storage area, the method also includes: the MCU chip reads the port status data set in the FLASH memory and applies the port status data set; and, based on the external physical interface in the FLASH memory, connects an external physical device so that the external physical device can read the port status data set.

[0013] In the second aspect, an embodiment of the present application also provides a timestamp calibration device for a multi-channel pulse signal, characterized in that the device includes: a processor; and a memory on which executable code is stored, and when the executable code is executed, the processor executes a timestamp calibration method for a multi-channel pulse signal as described in any one of claims 1-8.

[0014] On the third aspect, the embodiment of the present application further provides a non-volatile computer storage medium for timestamp calibration of a multi-channel pulse signal, which stores computer executable instructions, and is characterized in that the computer executable instructions are set to: divide the large-capacity SRAM into blocks to determine the first storage area and the second storage area; wherein the large-capacity SRAM is a large-capacity static random access memory in the MCU chip; based on the current storage address of the first storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is constructed through the DMA peripheral; wherein the current storage address is the storage address corresponding to the first storage space in the storage space in the first storage area where no data has been stored, and the DMA peripheral is a module in the MCU chip for implementing the DMA data transmission method; when the MCU chip receives When a pulse signal sampling request is received, the first periodic signal generated by the first crystal oscillator in the MCU chip is used to control the DMA peripheral to collect the port status data of the multi-channel pulse signal sampling IO port; a timestamp is added to the port status data, and the port status data with the timestamp is stored in the first storage area; wherein the port status data is used to describe all port states of the multi-channel pulse signal sampling IO port; when the collected port status data reaches a preset threshold, the current storage address of the second storage area is sent to the DMA peripheral, a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area is constructed, and the second periodic signal generated by the second crystal oscillator in the MCU chip is used to control the FLASH memory in the MCU chip to receive the port status data set in the first storage area.

[0015] The embodiments of the present application provide a timestamp calibration method, device, and storage medium for multi-channel pulse signals, which can perform high-precision sampling of high-speed pulse signals at low cost and with minimal resources, assign timestamps to the triggering edges of the signals, and have multiple export interfaces for docking and exporting with external devices. The signal acquisition device using this method does not require additional hardware investment and can be integrated into any chip with DMA peripherals. It can complete the sampling, analysis, and timestamp calibration of level signals while occupying minimal resources while realizing the original functions of the device, which can significantly reduce equipment cost and system complexity, improve system stability, and make signal acquisition results more accurate and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A flowchart of a method for timestamp calibration of a multi-channel pulse signal provided in an embodiment of the present application;

[0018] Figure 2 A diagram showing the connection relationship between system working units provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the internal structure of a multi-channel pulse signal timestamp calibration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] The embodiments of the present application provide a method, device, and storage medium for timestamp calibration of multi-channel pulse signals to solve the following technical problem: how to use a low-cost general-purpose MCU chip to timestamp calibrate sampled high-speed signals.

[0022] The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0023] Figure 1 This is a flow chart of a method for timestamp calibration of a multi-channel pulse signal provided by an embodiment of the present application. Figure 1 As shown, the embodiment of the present application provides a method for timestamp calibration of a multi-channel pulse signal, which specifically includes the following steps:

[0024] Step 101: Divide the large-capacity SRAM into blocks to determine a first storage area and a second storage area.

[0025] First of all, it should be noted that the device needs to initialize the system time base when it is powered on. In the embodiment of the present application, the power-on time of the system clock source is determined to be the time base zero point; based on the time base zero point, the first crystal oscillator and the second crystal oscillator are initialized so that the time base zero point of the first periodic signal generated by the first crystal oscillator and the second periodic signal generated by the second crystal oscillator is the power-on time of the system clock source; wherein the period of the second periodic signal is equal to the period of a preset number of first periodic signals.

[0026] It should be noted that the first periodic signal is used to drive the DMA peripheral, and the second periodic signal is used to drive the FLASH memory.

[0027] In one embodiment of the present application, the large-capacity SRAM is a large-capacity static random access memory in the MCU chip. On the one hand, since the first cycle signal will drive the DMA peripheral during operation and continuously store the port status data in the large-capacity SRAM, the large-capacity SRAM may be full; on the other hand, the MCU chip needs to process the port status data in the large-capacity SRAM, but since the port status data needs to be stored continuously, it is not possible to process the port status data in the large-capacity SRAM at the same time. In response to the above two problems, the present application divides the large-capacity SRAM into blocks to determine the first storage area and the second storage area to solve the above two problems. When the first storage area receives the port status data continuously stored in the large-capacity SRAM by the DMA peripheral, the second storage area can be used to process the port status data.

[0028] Step 102: Based on the current storage address of the first storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is constructed through the DMA peripheral.

[0029] In one embodiment of the present application, after the large-capacity SRAM is divided into blocks to determine the first storage area and the second storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is constructed through the DMA peripheral based on the current storage address of the first storage area. It can be understood that while constructing the mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area, the direction of the data flow through the DMA peripheral is also determined. It should also be noted that the current storage address is the storage address corresponding to the first storage space in the storage space of the first storage area where data has not yet been stored. The DMA peripheral is a module in the MCU chip for implementing the DMA data transmission method.

[0030] Specifically, the temporary register address in the DMA peripheral is bound to the multi-channel pulse signal sampling IO port so that the DMA peripheral can collect the initial port status data of each port corresponding to the multi-channel pulse signal sampling IO port; the temporary register address in the DMA peripheral is bound to the current storage address of the first storage area so that the DMA peripheral can upload the port status data obtained based on the initial port status data to the first storage area.

[0031] In one embodiment of the present application, before constructing a mapping relationship between a multi-channel pulse signal sampling IO port and the first storage area through a DMA peripheral based on the current storage address of the first storage area, in addition to determining the working direction of the DMA peripheral, it is also necessary to determine the working mode of the DMA peripheral and set the clock source for starting it to complete the initialization of the DMA peripheral.

[0032] Specifically, based on the port number of the multi-channel pulse signal sampling IO port, the working mode of the DMA peripheral is determined; wherein the working mode is a program for sampling the multi-channel pulse signal sampling IO port with a fixed port number; and the first crystal oscillator is determined as the driving clock source of the DMA peripheral.

[0033] Step 103: When the MCU chip receives a pulse signal sampling request, the DMA peripheral is controlled to collect port status data of the multi-channel pulse signal sampling IO port through the first periodic signal generated by the first crystal oscillator in the MCU chip.

[0034] In one embodiment of the present application, when the MCU chip receives a pulse signal sampling request, the DMA peripheral is started based on the first periodic signal generated by the first crystal oscillator in the MCU chip to collect the initial port status data of each port corresponding to the multi-channel pulse signal sampling IO port; based on the port number corresponding to each initial port status data, the initial port status data of each port is sorted, and the initial port status data in the correct order are compressed to obtain the port status data.

[0035] It should be noted that, assuming that the number of multi-channel pulse signal sampling IO ports is 32, the initial port status data of the DMA peripheral is 32, and each initial port status data only displays the port status of the corresponding port in the corresponding bit. Due to the large amount of data, if the initial port status data is directly stored in a large-capacity SRAM, it will greatly waste storage space and greatly reduce the number of storage times. Therefore, after the DMA peripheral collects the initial port status data of each port in the corresponding cycle, the embodiment of the present application will also compress the initial port status data according to the port number to obtain the port status data.

[0036] Step 104: Add a timestamp to the port status data, and store the timestamped port status data in the first storage area.

[0037] In one embodiment of the present application, after the DMA peripheral collects the port status data of the multi-channel pulse signal sampling IO port, the status data acquisition period corresponding to the first period signal is determined when acquiring the port status data; based on the power-on time of the system clock source, the period start time corresponding to the status data acquisition period is determined; the period start time is compiled to obtain the timestamp corresponding to the port status data, and the timestamp is calibrated with the port status data to achieve the addition of a timestamp to the port status data.

[0038] Furthermore, based on the current storage address of the first storage area bound to the temporary register address in the DMA peripheral, the port status data is uploaded to the storage space where the current storage address is located.

[0039] In one embodiment of the present application, after the port status data is uploaded to the current storage address of the first storage area, the current storage address of the first storage area is self-incremented so that the current storage address points to the next storage space, and the self-incremented current storage address is re-bound to the temporary register address in the DMA peripheral so that the DMA peripheral can upload the port status data of the relative next cycle to the first storage area.

[0040] Step 105: When the collected port status data reaches a preset threshold, the current storage address of the second storage area is sent to the DMA peripheral, a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area is constructed, and the second periodic signal generated by the second crystal oscillator in the MCU chip is used to control the FLASH memory in the MCU chip to receive the port status data set in the first storage area.

[0041] In one embodiment of the present application, when the collected port status data reaches a preset threshold, the current storage address of the second storage area is sent to a DMA peripheral, and a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area is established, so that the DMA peripheral can store subsequent port status data in the second storage area. Then, a second periodic signal generated by a second crystal oscillator in the MCU chip controls the FLASH memory in the MCU chip to receive the port status data set in the first storage area.

[0042] In one embodiment of the present application, after controlling the FLASH memory in the MCU chip and receiving the port status data set in the first storage area, the MCU chip can read the port status data set in the FLASH memory and apply the port status data set; and, based on the external physical interface in the FLASH memory, connect an external physical device so that the external physical device can read the port status data set.

[0043] Figure 2A system working unit connection diagram provided in an embodiment of the present application is shown as follows: Figure 2 As shown, the MCU chip includes: a processor, DMA peripherals, large-capacity SRAM, FLASH memory, a first crystal oscillator, and a second crystal oscillator. The system also includes: a system clock source and a multi-channel pulse signal sampling IO port. The processor is connected to the DMA peripherals, large-capacity SRAM, FLASH memory, first crystal oscillator, and second crystal oscillator, respectively, for initializing the DMA peripherals, analyzing and processing data stored in the large-capacity SRAM, analyzing and processing data in the FLASH memory, and initializing the first and second crystal oscillators based on the power-up time of the system clock source. The processor is also connected to the system clock source, which provides the system clock for the processor.

[0044] Furthermore, the DMA peripheral is respectively connected to the multi-channel pulse signal sampling IO port and the large-capacity SRAM to establish a mapping relationship between the multi-channel pulse signal sampling IO port and the large-capacity SRAM; the first crystal oscillator is connected to the DMA peripheral to drive the DMA peripheral; the second crystal oscillator is connected to the FLASH memory to drive the FLASH memory; the large-capacity SRAM is connected to the FLASH memory to transfer the port status data.

[0045] Based on the same inventive concept, the embodiment of the present application also provides a timestamp calibration device for a multi-channel pulse signal, the internal structure of which is as follows: Figure 3 shown.

[0046] Figure 3 This is a schematic diagram of the internal structure of a multi-channel pulse signal timestamp calibration device provided in an embodiment of the present application. Figure 3 As shown, the device includes: a processor 301; a memory 302, which stores executable instructions. When the executable instructions are executed, the processor 301 executes the above-mentioned method for timestamp calibration of multi-channel pulse signals.

[0047] In one embodiment of the present application, the processor 301 is used to divide the large-capacity SRAM into blocks to determine the first storage area and the second storage area; wherein the large-capacity SRAM is a large-capacity static random access memory in the MCU chip; based on the current storage address of the first storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is constructed through the DMA peripheral; wherein the current storage address is the storage address corresponding to the first storage space in the storage space in the first storage area where no data has been stored, and the DMA peripheral is a module in the MCU chip for implementing the DMA data transmission method; when the MCU chip receives a pulse signal sampling request, the first crystal oscillator in the MCU chip is used to The first periodic signal generated controls the DMA peripheral to collect port status data of the multi-channel pulse signal sampling IO port; adds a timestamp to the port status data, and stores the timestamped port status data in the first storage area; wherein the port status data is used to describe all port states of the multi-channel pulse signal sampling IO port; when the collected port status data reaches a preset threshold, sends the current storage address of the second storage area to the DMA peripheral, establishes a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area, and controls the FLASH memory in the MCU chip through the second periodic signal generated by the second crystal oscillator in the MCU chip to receive the port status data set in the first storage area.

[0048] Some embodiments of the present application provide corresponding Figure 1 A non-volatile computer storage medium for timestamp calibration of a multi-channel pulse signal stores computer executable instructions, wherein the computer executable instructions are set to:

[0049] The large-capacity SRAM is divided into blocks to determine a first storage area and a second storage area; wherein the large-capacity SRAM is a large-capacity static random access memory in the MCU chip;

[0050] Based on the current storage address of the first storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is established through the DMA peripheral; wherein the current storage address is the storage address corresponding to the first storage space in the storage space of the first storage area that has not yet stored data, and the DMA peripheral is a module in the MCU chip for implementing a DMA data transmission method;

[0051] When the MCU chip receives a pulse signal sampling request, the DMA peripheral is controlled to collect port status data of the multi-channel pulse signal sampling IO port through the first periodic signal generated by the first crystal oscillator in the MCU chip;

[0052] Adding a timestamp to the port status data, and storing the timestamped port status data in the first storage area; wherein the port status data is used to describe all port states of the multi-channel pulse signal sampling IO port;

[0053] When the collected port status data reaches a preset threshold, the current storage address of the second storage area is sent to the DMA peripheral, a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area is constructed, and the second periodic signal generated by the second crystal oscillator in the MCU chip is used to control the FLASH memory in the MCU chip to receive the port status data set in the first storage area.

[0054] The various embodiments in this application are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from the other embodiments. In particular, the IoT device and media embodiments are generally similar to the method embodiments, so their description is relatively simple. For relevant portions, refer to the description of the method embodiments.

[0055] The system and medium provided in the embodiments of the present application correspond one-to-one to the method. Therefore, the system and medium also have similar beneficial technical effects to their corresponding methods. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the system and medium will not be repeated here.

[0056] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0057] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0058] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0059] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0060] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0061] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0062] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0063] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0064] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A timestamp calibration method for a multi-channel pulse signal, characterized in that: The method comprises: Divide the large-capacity SRAM into blocks to determine a first storage area and a second storage area; wherein the large-capacity SRAM is a large-capacity static random access memory in the MCU chip; Based on the current storage address of the first storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is established through a DMA peripheral; wherein the current storage address is a storage address corresponding to the first storage space in the storage space of the first storage area that has not yet stored data, and the DMA peripheral is a module in the MCU chip for implementing a DMA data transmission method; When the MCU chip receives a pulse signal sampling request, the DMA peripheral is controlled to collect the port status data of the multi-channel pulse signal sampling IO port through the first periodic signal generated by the first crystal oscillator in the MCU chip; Adding a timestamp to the port status data, and storing the timestamped port status data in the first storage area; wherein the port status data is used to describe all port states of the multi-channel pulse signal sampling IO port; When the collected port status data reaches a preset threshold, the current storage address of the second storage area is sent to the DMA peripheral, a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area is constructed, and the second periodic signal generated by the second crystal oscillator in the MCU chip is used to control the FLASH memory in the MCU chip to receive the port status data set in the first storage area.

2. The method for timestamp calibration of a multi-channel pulse signal according to claim 1, wherein: Before dividing the large-capacity SRAM into blocks to determine the first storage area and the second storage area, the method further includes: Determine the power-on time of the system clock source as the time base zero; Based on the time reference zero point, the first crystal oscillator and the second crystal oscillator are initialized so that the time reference zero point of the first periodic signal generated by the first crystal oscillator and the second periodic signal generated by the second crystal oscillator is the power-on time of the system clock source; wherein the period of the second periodic signal is equal to the period of a preset number of first periodic signals.

3. The method for timestamp calibration of a multi-channel pulse signal according to claim 1, wherein: Before establishing a mapping relationship between a multi-channel pulse signal sampling IO port and the first storage area through a DMA peripheral based on the current storage address of the first storage area, the method further includes: Determining the operating mode of the DMA peripheral based on the number of ports of the multi-channel pulse signal sampling IO port; wherein the operating mode is a program for sampling the multi-channel pulse signal sampling IO port with a fixed number of ports; Determine the first crystal oscillator as a driving clock source for the DMA peripheral.

4. The method for timestamp calibration of a multi-channel pulse signal according to claim 1, wherein: Based on the current storage address of the first storage area, a mapping relationship between a multi-channel pulse signal sampling IO port and the first storage area is established through a DMA peripheral, specifically including: Binding a temporary register address in the DMA peripheral to the multi-channel pulse signal sampling IO port so that the DMA peripheral can collect initial port state data of each port corresponding to the multi-channel pulse signal sampling IO port; A temporary register address in the DMA peripheral is bound to a current storage address of the first storage area, so that the DMA peripheral can upload the port status data obtained based on the initial port status data to the first storage area.

5. The method for timestamp calibration of a multi-channel pulse signal according to claim 4, characterized in that: Controlling the DMA peripheral to collect the port status data of the multi-channel pulse signal sampling IO port by using the first periodic signal generated by the first crystal oscillator in the MCU chip specifically includes: Starting the DMA peripheral based on the first periodic signal to collect initial port status data of each port corresponding to the multi-channel pulse signal sampling IO port; The initial port state data of each port is sorted based on the port number corresponding to each initial port state data, and the initial port state data in the correct order is compressed to obtain the port state data.

6. The method for timestamp calibration of a multi-channel pulse signal according to claim 2, characterized in that: Adding a timestamp to the port status data specifically includes: Determine, when acquiring the port status data, a status data acquisition period corresponding to the first periodic signal; Determining a cycle start time corresponding to the status data acquisition cycle according to a power-on time of the system clock source; The cycle start time is compiled to obtain a timestamp corresponding to the port status data, and the timestamp is calibrated with the port status data to achieve adding a timestamp to the port status data.

7. The method for timestamp calibration of a multi-channel pulse signal according to claim 4, characterized in that: After storing the timestamped port status data in the first storage area, the method further includes: The current storage address of the first storage area is self-incremented, and the self-incremented current storage address is re-bound to the temporary register address in the DMA peripheral, so that the DMA peripheral can upload the port status data of the next cycle to the first storage area.

8. The method for timestamp calibration of a multi-channel pulse signal according to claim 1, wherein: After controlling the FLASH memory in the MCU chip to receive the port status data set in the first storage area, the method further includes: The MCU chip reads the port status data set in the FLASH memory and applies the port status data set; and Based on the external physical interface in the FLASH memory, an external physical device is connected so that the external physical device can read the port status data set.

9. A timestamp calibration device for multi-channel pulse signals, characterized in that: The device comprises: processor; and a memory storing executable code thereon, which, when the executable code is executed, enables the processor to execute the timestamp calibration method for a multi-channel pulse signal according to any one of claims 1 to 8.

10. A non-volatile computer storage medium for timestamp calibration of multi-channel pulse signals, storing computer executable instructions, characterized in that: The computer executable instructions are configured to: Divide the large-capacity SRAM into blocks to determine a first storage area and a second storage area; wherein the large-capacity SRAM is a large-capacity static random access memory in the MCU chip; Based on the current storage address of the first storage area, a mapping relationship between the multi-channel pulse signal sampling IO port and the first storage area is established through a DMA peripheral; wherein the current storage address is a storage address corresponding to the first storage space in the storage space of the first storage area that has not yet stored data, and the DMA peripheral is a module in the MCU chip for implementing a DMA data transmission method; When the MCU chip receives a pulse signal sampling request, the DMA peripheral is controlled to collect the port status data of the multi-channel pulse signal sampling IO port through the first periodic signal generated by the first crystal oscillator in the MCU chip; Adding a timestamp to the port status data, and storing the timestamped port status data in the first storage area; wherein the port status data is used to describe all port states of the multi-channel pulse signal sampling IO port; When the collected port status data reaches a preset threshold, the current storage address of the second storage area is sent to the DMA peripheral, a mapping relationship between the multi-channel pulse signal sampling IO port and the second storage area is constructed, and the second periodic signal generated by the second crystal oscillator in the MCU chip is used to control the FLASH memory in the MCU chip to receive the port status data set in the first storage area.

Images