Display device performing charge sharing

Abstract

A display apparatus includes a display panel, a plurality of switching circuits, and a charge sharing controller. The display panel includes a plurality of pixels connected to a plurality of gate lines and a plurality of source lines. The plurality of source lines is divided into a plurality of source line groups. The plurality of switching circuits electrically connects source lines included in each of the plurality of source line groups based on each of a plurality of group switch control signals to perform charge sharing. The charge sharing controller generates each of the plurality of group switch control signals based on a first most significant bit (MSB) of each of a plurality of (K-1)th digital data groups and a second MSB of each of a plurality of Kth digital data groups.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0037763, filed on March 24, 2021, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to semiconductor integrated circuits, and more specifically, to a display device that performs charge sharing. Background Technology

[0004] Liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs) are widely used as display devices. Recently, with the increase in the size and resolution of display panels included in display devices, the power consumption of display devices has increased. Summary of the Invention

[0005] Some embodiments may provide a display device that can reduce the current consumption and hardware resources required to perform charge sharing.

[0006] According to an embodiment, a display device includes a display panel, a plurality of switching circuits, and a charge-sharing controller. The display panel includes a plurality of pixels connected to a plurality of gate lines and a plurality of source lines and arranged in a plurality of rows and columns. The plurality of source lines are divided into a plurality of source line groups. The plurality of switching circuits electrically connect the source lines included in each of the plurality of source line groups based on each of a plurality of group switching control signals to perform charge sharing. The charge-sharing controller generates each of the plurality of group switching control signals based on a first most significant bit (MSB) of each of a plurality of (K-1)th digital data groups and a second MSB of each of a plurality of Kth digital data groups. The plurality of (K-1)th digital data groups correspond to pixel values ​​in the (K-1)th row of the display panel, and the plurality of Kth digital data groups correspond to pixel values ​​in the Kth row of the display panel, where K is a natural number greater than 1.

[0007] According to an embodiment, a display device includes a display panel and a display driver integrated circuit. The display panel includes a plurality of pixels connected to a plurality of gate lines and a plurality of source lines and arranged in a plurality of rows and columns. The plurality of source lines are divided into a plurality of source line groups. The display driver integrated circuit drives the display panel. The display driver integrated circuit includes a plurality of switching circuits, a data latch circuit, and a charge sharing controller. The plurality of switching circuits electrically connect the source lines included in each of the plurality of source line groups based on each of the plurality of group switching control signals to perform charge sharing. The data latch circuit outputs a plurality of (K-1)th digital data groups corresponding to the pixel values ​​of the (K-1)th row of the display panel and a plurality of Kth digital data groups corresponding to the pixel values ​​of the Kth row of the display panel, where K is a natural number greater than 1. The charge sharing controller generates each of the plurality of group switching control signals based on a first MSB of each of the plurality of (K-1)th digital data groups and a second MSB of each of the plurality of Kth digital data groups.

[0008] According to an embodiment, a display device includes a display panel, a plurality of switching circuits, and a charge-sharing controller. The display panel includes a plurality of pixels connected to a plurality of gate lines and a plurality of source lines and arranged in a plurality of rows and columns. The plurality of source lines are divided into a plurality of source line groups. The plurality of switching circuits electrically connect the source lines included in each of the plurality of source line groups based on each of a plurality of group switch control signals to perform charge sharing. Each of the plurality of switching circuits includes a plurality of first switches for performing charge sharing. The charge-sharing controller generates each of the plurality of group switch control signals based on a first MSB of each of a plurality of (K-1)th digital data groups, a second MSB of each of a plurality of Kth digital data groups, a third MSB as a first MSB corresponding to a selected column of the display panel, and a fourth MSB as a second MSB corresponding to a selected column of the display panel, where K is a natural number greater than 1.

[0009] The display device according to an embodiment can perform charge sharing by electrically connecting the source lines included in each of the plurality of source line groups based on digital data corresponding to each of the plurality of source line groups, the plurality of group switch control signals, and the plurality of switch circuits. Charge sharing can also be performed based on the parasitic capacitance formed in the source lines included in each of the plurality of source line groups. The display device can perform charge sharing without additional data other than the input digital data used to display an image on the display panel. The display device can perform charge sharing using general components for performing the original functions of the display device, without additional components other than a charge sharing controller and a plurality of first switches. Attached Figure Description

[0010] The exemplary embodiments of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0012] Figure 2A and Figure 2B It is shown that it includes Figure 1 A block diagram of an embodiment of the first switching circuit in a display device.

[0013] Figure 3 and Figure 4 It is shown that it includes Figure 1 A circuit diagram of an example of pixels in a display panel.

[0014] Figure 5 and Figure 6 It is shown that it includes Figure 1 A block diagram of an embodiment of a charge-sharing controller in a display device.

[0015] Figure 7 It is shown that, according to the embodiments, it includes Figure 1 A diagram showing the arrangement of multiple pixels in a display panel.

[0016] Figure 8 It is shown that it includes Figure 1 A flowchart illustrating an embodiment of the operation of a charge-sharing controller in a display device.

[0017] Figure 9 It is used to describe including Figure 1 A diagram illustrating the process by which the charge-sharing controller in the display device determines the first and second conditions.

[0018] Figure 10 This illustrates an embodiment. Figure 1 A timing diagram showing the changes in the group switch control signal and the voltage level in the source line of the display device.

[0019] Figure 11 It is used to describe the embodiments according to the provisions of the present invention. Figure 1 A graph showing the change in current consumption when charge sharing is performed in the display device.

[0020] Figure 12 It is shown that, according to the embodiments, it includes Figure 1 A diagram showing the arrangement of multiple pixels in a display panel.

[0021] Figure 13 It is shown that it includes Figure 1 A flowchart illustrating an embodiment of the operation of a charge-sharing controller in a display device.

[0022] Figure 14A and Figure 14B It is shown that it includes Figure 1A block diagram of an embodiment of the first switching circuit in a display device.

[0023] Figure 15 It is used to describe the inclusion of, according to the embodiments Figure 1 A diagram illustrating the process by which the charge-sharing controller in the display device determines the first to fourth conditions.

[0024] Figure 16 This is a block diagram illustrating a display device according to an embodiment.

[0025] Figure 17 It is shown that it includes Figure 16 A block diagram of an embodiment of the first switching circuit in a display device.

[0026] Figure 18 This illustrates an embodiment. Figure 16 A timing diagram showing the changes in the group switch control signal and the voltage level in the source line of the display device.

[0027] Figure 19 This is a block diagram illustrating a display system according to an embodiment.

[0028] Figure 20 This is a block diagram illustrating a display device according to an embodiment. Detailed Implementation

[0029] Various embodiments will be described more fully below with reference to the accompanying drawings, which illustrate some embodiments. All embodiments described herein are exemplary, and therefore the inventive concept is not limited thereto, and may be implemented in various other forms. In the drawings, the same reference numerals always denote the same elements. Repeated descriptions may be omitted.

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0031] Reference Figure 1 The display device 100 may include a display panel, data pads 140, and a display driver integrated circuit (IC). The display panel may be one of an organic light-emitting diode (OLED) panel and a liquid crystal display (LCD) panel, or a combination thereof.

[0032] The display panel may include connections to multiple gate lines GL1, GL2, GL3, ..., GL M-1 GL M and multiple source lines SL1, SL2, SL3, ..., SL N-1 SL NThe display driver IC may include a data latch circuit 110, a digital-to-analog converter (DAC) 120, a drive switch circuit 130, and a charge-sharing controller 170. The drive switch circuit 130 may include a plurality of switch circuits 131 to 13Q. Here, M, N, and Q are each natural numbers greater than 1.

[0033] Multiple pixels can receive pixel data corresponding to the pixel values ​​of multiple pixels under the control of the display driver IC to display an image.

[0034] In some embodiments, multiple pixels can be arranged in multiple rows and columns. For example, a total of M×N pixels P 11 P 21 P 31 ... P (M-1)N P MN It can be arranged in M ​​rows and N columns. In this case, M gate lines corresponding to multiple rows and N source lines corresponding to multiple columns can be formed. Multiple pixels can be connected to multiple gate lines GL1, GL2, GL3, ..., GL M-1 GL M It can be selected in rows and can be connected to multiple source lines SL1, SL2, SL3, ..., SL N-1 SL N To receive pixel data. In some embodiments, each of the plurality of pixels may represent one or more of a plurality of colors. For example, the plurality of colors may represent one of red, green and blue; however, the embodiments are not limited thereto.

[0035] The display driver IC can receive input digital data IDAT from the outside, generate pixel data based on the input digital data IDAT, and provide the pixel data to the display panel.

[0036] In some embodiments, the data latch circuit 110 can latch the input digital data IDAT to store the digital data D1, D2, D3, ..., D corresponding to at least one of the multiple rows. N Provided to the digital-to-analog converter 120. The digital-to-analog converter 120 can convert digital data D1, D2, D3, ..., D... N Convert to analog data A1, A2, A3, ..., A N And the simulated data A1, A2, A3, ..., A N Provided to the drive switch circuit 130. The drive switch circuit 130 can transmit analog data A1, A2, A3, ..., A through the data pads 140. N This data is provided to the display panel as pixel data.

[0037] In some embodiments, the data latch circuit 110 may latch input digital data IDAT to provide digital data RDAT1 and RDAT2 to the charge sharing controller 170. Digital data RDAT1 may be data corresponding to the pixel value of the (K-1)th row in a plurality of rows, and digital data RDAT2 may be data corresponding to the pixel value of the Kth row in a plurality of rows, where K is a natural number greater than 1.

[0038] The charge sharing controller 170 may receive a charge sharing control signal CCS from a timing controller (not shown) and digital data RDAT1 and RDAT2 from a data latch circuit 110. However, the embodiments are not limited thereto. In some embodiments, the charge sharing controller 170 may receive digital data RDAT1 and RDAT2 from the timing controller.

[0039] The charge-sharing controller 170 can partition digital data RDAT1 to generate multiple (K-1)th digital data groups and partition digital data RDAT2 to generate multiple Kth digital data groups. The charge-sharing controller 170 may include multiple line memories for temporarily storing the multiple (K-1)th and multiple Kth digital data groups. In this case, each of the multiple (K-1)th and Kth digital data groups may correspond to multiple source line groups SLG_1, ..., SLG_Q, which will be described later. For example, the number of (K-1)th digital data groups may be substantially the same as the number of multiple source line groups SLG_1, ..., SLG_Q.

[0040] The Kth digital data group can also be generated by partitioning the digital data RDAT2 in the same way as the (K-1)th digital data group. Hereinafter, it is assumed that the number of multiple source line groups SGL_1, ..., SLG_Q is "Q", where Q is a natural number greater than 1; however, the embodiments are not limited to this.

[0041] The charge-sharing controller 170 can extract the most significant bit (MSB) from each of the plurality of (K-1)th digital data groups (referred to herein as the “first MSB”), and extract the MSB from each of the plurality of Kth digital data groups (referred to herein as the “second MSB”).

[0042] The charge sharing controller 170 can generate each of a plurality of group switch control signals CS11 to CS1Q and CS21 to CS2Q based on the first MSB and the second MSB.

[0043] The drive switch circuit 130 may include a plurality of switch circuits (e.g., first switch circuits 131 to Q switch circuits 13Q). Each of the plurality of switch circuits 131 to 13Q may include a plurality of first switches and a plurality of second switches.

[0044] Multiple source lines SL1, SL2, SL3, ..., SL N-1 SL N It can be divided into multiple source line groups SGL_1, ..., SLG_Q, and multiple first switches can electrically connect the source lines included in each of the multiple source line groups SLG_1, ..., SLG_Q to each other based on each of the multiple group switch control signals CS11 to CS1Q to perform charge sharing.

[0045] Multiple second switches can be electrically connected to the source line of each of multiple source line groups SLG_1, ..., SLG_Q based on multiple group switch control signals CS21 to CS2Q.

[0046] According to the above configuration, the display device 100 can electrically connect the source lines included in each of the multiple source line groups SLG_1, ..., SLG_Q to each other based on the digital data RDAT and RDAT2 corresponding to each of the multiple source line groups SLG_1, ..., SLG_Q, the multiple group switch control signals CS11 to CS1Q, and the multiple switch circuits 131 to 13Q, to perform charge sharing. Charge sharing can also be performed based on the parasitic capacitance 150 formed in the source lines included in each of the multiple source line groups SLG_1, ..., SLG_Q. For example, the parasitic capacitance 150 can be formed on the data pad 140 and M×N pixels P. 11 P 21 P 31 ... P (M-1)N P MN The source lines SL1, SL2, SL3, ..., SL between N-1 SL N In part, the display device 100 can perform charge sharing without additional data other than the input digital data IDAT used to display an image on the display panel. The display device 100 can perform charge sharing using general components for performing the original functions of the display device 100, without the need for the charge sharing controller 170 and additional components other than the plurality of first switches included in each of the plurality of switching circuits 131 to 13Q.

[0047] The display device 100 can divide digital data RDAT1 and RDAT2 to correspond to each of a plurality of source line groups SLG_1, ..., SLG_Q, generate each of a plurality of group switch control signals CS11 to CS1Q and CS21 to CS2Q, and electrically connect the source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q to each other. Therefore, each of the plurality of source line groups SLG_1, ..., SLG_Q becomes the basic unit for the display device 100 to perform charge sharing.

[0048] In some embodiments, the number of source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q may be substantially the same. For example, in the plurality of source line groups SLG_1, ..., SLG_Q, the first source line group SLG_1 may include the first source line SL1 to the eighth source line SL8, and the second source line group SLG_2 may include the ninth source line SL9 to the sixteenth source line SL8. 16 The third source line group SLG_3 may include the seventeenth source line SL 17 Up to the twenty-fourth source pole line SL 24 Similarly, the remaining source line groups within multiple source line groups SLG_1, ..., SLG_Q can include multiple source lines SL1, ..., SL... N-1 SL N The remaining source lines. The Qth source line group SLG_Q corresponding to the last source line group may include the (N-7)th source line SL. N-7 To the Nth source pole line SL N However, the number of multiple source line groups SLG_1, ..., SLG_Q and the number of source lines included in each of the multiple source line groups SLG_1, ..., SLG_Q are exemplary and can be varied.

[0049] In some embodiments, the plurality of first switches and the plurality of second switches may be periodically turned on within each row unit time interval for progressively driving the display panel. For example, the plurality of first switches may be periodically turned on after the time points when the plurality of second switches are turned on within the row unit time interval. The plurality of first switches and the plurality of second switches will refer to Figure 2A , Figure 2B , Figure 14A , Figure 14B and Figure 17 To describe.

[0050] exist Figure 1 In this embodiment, the display driver IC is shown as including only a data latch circuit 110, a digital-to-analog converter 120, a drive switch circuit 130, and a charge-sharing controller 170; however, the embodiment is not limited thereto. In some embodiments, the display driver IC may include a timing controller, a source driver, a scan driver, a power supply circuit, and a gamma voltage generation circuit, and the digital-to-analog converter 120, the drive switch circuit 130, and the charge-sharing controller 170 may be included in the source driver.

[0051] Figure 2A and Figure 2B It is shown that it includes Figure 1 A block diagram of an embodiment of the first switching circuit in a display device.

[0052] Reference Figure 1 and Figure 2A ,and Figure 1 The first switching circuit 131a corresponding to the first switching circuit 131 shown can receive analog data A1, A2, A3, ..., A8 converted from digital data D1, D2, D3, ..., D8, and provide the analog data A1, A2, A3, ..., A8 to the first source line SL1 to the eighth source line SL8 included in the first source line group SLG_1, respectively.

[0053] The first switching circuit 131a may include a plurality of first switches 131-1a and a plurality of second switches 131-2.

[0054] Multiple first switches 131-1a can connect the first source lines SL1 to the eighth source line SL8 included in the first source line group SLG_1 to each other. In some embodiments, the multiple first switches 131-1a can respectively connect a reference source line (e.g., SL1) that is one of the source lines included in the first source line group SLG_1 to other source lines SL2 to SL8 included in the first source line group SLG_1. Figure 2A In the diagram, the first source line SL1 is shown as corresponding to the reference source line; however, the embodiment is not limited thereto. Multiple second switches 131-2 can connect the first source line SL1 to the eighth source line SL8, which are included in the first source line group SLG_1, to... Figure 1 The digital-to-analog converter 120 is included.

[0055] The first switching circuit 131a can be from Figure 1 The charge sharing controller 170 in the middle receives group switch control signals CS11 and CS21.

[0056] In some embodiments, a plurality of first switches 131-1a may be turned on or off based on a group switch control signal CS11, and a plurality of second switches 131-2 may be turned on or off based on a group switch control signal CS21.

[0057] In some embodiments, the group switch control signals CS11 and CS21 can be 1-bit signals, and Figure 2A In the embodiments described, multiple first switches 131-1a can be turned on or off simultaneously, and multiple second switches 131-2 can also be turned on or off simultaneously. However, the timing of the on-state of the multiple first switches 131-1a and the multiple second switches 131-2 can be different from each other.

[0058] exist Figure 2A The diagram shows a first switching circuit 131a as included in... Figure 1The embodiment of the plurality of switch circuits 131 to 13Q in the drive switch circuit 130 shown, however, each of the plurality of switch circuits 131 to 13Q may have the same configuration as the first switch circuit 131a.

[0059] In some embodiments, the plurality of first switches included in each of the plurality of first switch circuits may be respectively connected to other source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q, using a reference source line as one of the source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q. However, the embodiments are not limited thereto. In some embodiments, as Figure 2B As shown, with Figure 1 The first switch circuit 131b corresponding to the first switch circuit 131 shown may include a plurality of first switches 131-1b and a plurality of second switches 131-2, and each of the plurality of first switches 131-1b may respectively connect two adjacent source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q to each other.

[0060] Figure 3 and Figure 4 It is shown that it includes Figure 1 A circuit diagram of an example of pixels in a display panel.

[0061] Reference Figure 1 and Figure 3 , Figure 1 The display panel can be implemented using electroluminescent (EL) pixels Pa, including organic light-emitting diodes (OLEDs). EL pixels Pa may include switching transistors ST, storage capacitors CST, driving transistors DT, and the OLED.

[0062] The switching transistor ST may have a first terminal connected to the source line SL or a data line, a second terminal connected to the storage capacitor CST, and a gate terminal connected to the gate line GL or a scan line. The switching transistor ST can transmit analog data provided through the source line SL to the storage capacitor CST in response to a gate drive signal applied through the gate line GL.

[0063] The storage capacitor CST may have a first electrode connected to a high supply voltage ELVDD and a second electrode connected to the gate terminal of the drive transistor DT. The storage capacitor CST may store analog data transmitted through the switching transistor ST.

[0064] The driving transistor DT may have a first terminal connected to a high supply voltage ELVDD, a second terminal connected to the OLED, and a gate electrode connected to a storage capacitor CST. The driving transistor DT can be turned on or off according to the data stored in the storage capacitor CST.

[0065] OLEDs may have an anode electrode connected to a driving transistor DT and a cathode electrode connected to a low supply voltage ELVSS. While the driving transistor DT is turned on, the OLED emits light based on the current flowing from the high supply voltage ELVDD to the low supply voltage ELVSS. This simple structure of the pixel Pa (e.g., a 2T1C structure with two transistors ST and DT and a capacitor CST) may be more suitable for scaling up the display device 100. Figure 3 The EL pixel Pa shown is merely exemplary, and various configurations of EL pixels may be used in the display device 100 according to the embodiment.

[0066] Reference Figure 1 and Figure 4 , Figure 1 The display can be implemented using liquid crystal display (LCD) pixels Pb, which include liquid crystal capacitors CL. The LCD pixel Pb may include a switching element ST, a liquid crystal capacitor CL, and a storage capacitor CST. The switching element ST electrically connects the source line SL, as well as the capacitors CL and CST, in response to a gate drive signal applied via the gate line GL. The liquid crystal capacitor CL is coupled between the switching element ST and a common voltage VCOM, and the storage capacitor CST is coupled between the switching element ST and ground voltage VGND. The liquid crystal capacitor CL can control the amount of transmitted light based on data stored in the storage capacitor CST. Figure 4 The LCD pixel Pb shown is merely exemplary, and various configurations of LCD pixels may be used in the display device 100 according to the embodiment.

[0067] Figure 5 and Figure 6 It is shown that it includes Figure 1 A block diagram of an embodiment of a charge-sharing controller in a display device.

[0068] Reference Figure 1 and Figure 5 ,and Figure 1 The charge sharing controller 170a corresponding to the charge sharing controller 170 shown may include a data partitioning circuit 171a, a first determination circuit (DTC1) 173a, a second determination circuit (DTC2) 175a, and a switch control signal generation circuit 177a.

[0069] The data partitioning circuit 171a can receive digital data RDAT1 corresponding to the pixel values ​​of the (K-1)th row of the display panel and digital data RDAT2 corresponding to the pixel values ​​of the Kth row of the display panel from the data latching circuit 110. The data partitioning circuit 171a can partition the digital data RDAT1 to generate multiple (K-1)th digital data groups GDAT11 to GDAT1Q, and partition the digital data RDAT2 to generate multiple Kth digital data groups.

[0070] In some embodiments, the data partitioning circuit 171a can partition the digital data RDAT1 to generate a plurality of (K-1)th digital data groups GDAT11 to GDAT1Q. In this case, the plurality of (K-1)th digital data groups GDAT11 to GDAT1Q can respectively correspond to a plurality of source line groups SLG_1, ..., SLG_Q. The (K-1)th digital data group GDAT11 may include a plurality of pixels (e.g., P... (K-1)1 P (K-1)2 P (K-1)3 P (K-1)4 P (K-1)5 P (K-1)6 P (K-1)7 and P (K-1)8 The (K-1)th digital data group GDAT12 may include the digital data corresponding to the pixel values ​​of multiple pixels (e.g., P). (K-1)9 P (K-1)10 P (K-1)11 P (K-1)12 P (K-1)13 P (K-1)14 P (K-1)15 and P (K-1)16 The (K-1)th digital data group GDAT1Q may include the digital data corresponding to the pixel values ​​of multiple pixels (e.g., P). (K-1)(N-7) P (K-1)(N-6) P (K-1)(N-5) P (K-1)(N-4) P (K-1)(N-3) P (K-1)(N-2) P (K-1)(N-1) and P (K-1)N The pixel value corresponds to the numerical data.

[0071] In some embodiments, the data partitioning circuit 171a can partition the digital data RDAT2 to generate a plurality of Kth digital data groups GDAT21 to GDAT2Q. In this case, the plurality of Kth digital data groups GDAT21 to GDAT2Q can respectively correspond to a plurality of source line groups SLG_1, ..., SLG_Q. The Kth digital data group GDAT21 may include a plurality of pixels (e.g., P... K1 P K2 P K3 PK4 P K5 P K6 P K7 and P K8 The Kth digital data group GDAT22 may include the digital data corresponding to the pixel values ​​of multiple pixels (e.g., P). K9 P K10 P K11 P K12 P K13 P K14 P K15 and P K16 The (K-1)th digital data group GDAT2Q may include the digital data corresponding to the pixel values ​​of multiple pixels (e.g., P). K(N-7) P K(N-6) P K(N-5) P K(N-4) P K(N-3) P K(N-2) P K(N-1) and P KN The pixel value corresponds to the numerical data.

[0072] The data partitioning circuit 171a can provide multiple (K-1)th digital data groups GDAT11 to GDAT1Q to the first determining circuit 173a, and can provide multiple (K-1)th digital data groups GDAT11 to GDAT1Q and multiple Kth digital data groups GDAT21 to GDAT2Q to the second determining circuit 175a.

[0073] The first determining circuit 173a can receive first reference values ​​TH_MIN and TH_MAX from the outside, and receive multiple (K-1)th digital data groups GDAT11 to GDAT1Q from the data partitioning circuit 171a. The second determining circuit 175a can receive a second reference value TH_TOG from the outside, and receive multiple (K-1)th digital data groups GDAT11 to GDAT1Q and multiple Kth digital data groups GDAT21 to GDAT2Q from the data partitioning circuit 171a.

[0074] In some embodiments, the first determining circuit 173a and the second determining circuit 175a may be referenced above. Figure 1 The timing controller described (not shown) receives first reference values ​​TH_MIN and TH_MAX and a second reference value TH_TOG.

[0075] The first determining circuit 173a can determine, for each of the plurality of source line groups SLG_1, ..., SLG_Q, whether the first most significant bit (MSB) of each of the plurality of (K-1)th digital data groups GDAT11 to GDAT1Q satisfies a first condition.

[0076] The second determining circuit 175a can determine, for each of the plurality of source line groups SLG_1, ..., SLG_Q, whether the first MSB of each of the plurality of (K-1)th digital data groups GDAT11 to GDAT1Q and the second MSB of each of the plurality of Kth digital data groups GDAT21 to GDAT2Q satisfy the second condition.

[0077] Multiple (K-1)th digital data groups GDAT11 to GDAT1Q and multiple Kth digital data groups GDAT21 to GDAT2Q are data corresponding to the pixel values ​​of the (K-1)th and Kth rows of the display panel, and the grayscale of the pixel value is represented by multiple bits, from which the MSB can be extracted.

[0078] In some embodiments, the first determining circuit 173a may further determine, for each of the plurality of source line groups SLG_1, ..., SLG_Q, whether the first MSB of each of the plurality of (K-1)th digital data groups GDAT11 to GDAT1Q satisfies a third condition. The second determining circuit 175a may further determine, for each of the plurality of source line groups SLG_1, ..., SLG_Q, whether the first MSB of each of the plurality of (K-1)th digital data groups GDAT11 to GDAT1Q and the second MSB of each of the plurality of Kth digital data groups GDAT21 to GDAT2Q satisfy a fourth condition.

[0079] In some embodiments, the first determining circuit 173a and the second determining circuit 175a may determine whether the first condition and the second condition are met within each row unit time interval for progressively driving the display panel.

[0080] In some embodiments, when each of the pixel values ​​is represented by multiple bits, the first determining circuit 173a and the second determining circuit 175a may remove the least significant bit (LSB) from the next order of bits of the MSB in the pixel value to extract the first MSB and the second MSB.

[0081] The first determining circuit 173a can determine that a first condition is met for each of the plurality of source line groups SLG_1, ..., SLG_Q in response to the number of first MSBs having a first value being included within a first reference range, and generate first result data RES11 to RES1Q.

[0082] The second determining circuit 175a can determine whether the second condition is satisfied for each of the plurality of source line groups SLG_1, ..., SLG_Q, in response to the number of bit pairs with different values ​​in the bit pairs of the first MSB and the second MSB, which are included in the second reference range, and generate second result data RES21 to RES2Q.

[0083] Furthermore, it is assumed that the source lines included in each of the multiple source line groups SLG_Q, ..., SLG_Q are driven between the maximum and minimum drive voltage levels. In this case, the first determining circuit 173a can determine whether a first condition is met and determine which source line group can adjust the voltage level of the source line to near the intermediate voltage level (which is half of the maximum drive voltage level) when charge sharing is performed. The second determining circuit 175a can determine whether a second condition is met and determine which source line group can change the voltage level of the source line from near the maximum drive voltage level to near the minimum drive voltage level or from near the minimum drive voltage level to near the maximum drive voltage level.

[0084] In some embodiments, the first determining circuit 173a may determine a first reference range based on first reference values ​​TH_MIN and TH_MAX, and the second determining circuit 175a may determine a second reference range based on a second reference value TH_TOG. The first determining circuit 173a may provide first result data RES11 to RES1Q to the switch control signal generation circuit 177a, and the second determining circuit 175a may provide second result data RES21 to RES2Q to the switch control signal generation circuit 177a. (Referring later...) Figure 8 and Figure 9 Describe the operation of the first determining circuit 173a and the second determining circuit 175a.

[0085] The switch control signal generation circuit 177a can, based on the first result data RES11 to RES1Q and the second result data RES21 to RES2Q, enable each of the multiple source line groups SLG_1, ..., SLG_Q in response to the first MSB satisfying a first condition and the first MSB and the second MSB satisfying a second condition, to turn off the multiple first switches described above with reference to FIG2.

[0086] The switch control signal generation circuit 177a can, based on the first result data RES11 to RES1Q and the second result data RES21 to RES2Q, invalidate each of the multiple group switch control signals CS11 to CS1Q for each of the multiple source line groups SLG_1, ..., SLG_Q in response to the first MSB not satisfying the first condition or the first MSB and the second MSB not satisfying the second condition, thereby turning off the multiple first switches.

[0087] As shown above (refer to the reference) Figure 1As described, the drive switch circuit 130 includes a plurality of switch circuits (e.g., first switch circuits 131 to Q switch circuits 13Q), each of the plurality of switch circuits including a plurality of first switches, so that the drive switch circuit 130 may electrically connect the source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q to each other to perform charge sharing based on a plurality of group switch control signals CS11 to CS1Q.

[0088] The switch control signal generation circuit 177a can generate group switch control signals CS21 to CS2Q to enable charge sharing at appropriate intervals for the original function of the display device 100 for displaying images on the display panel. The relationship between the multiple group switch control signals CS11 to CS1Q and the multiple group switch control signals CS21 to CS2Q will be referred to later. Figure 10 Describe it.

[0089] Reference Figure 1 and Figure 6 ,and Figure 1 The charge-sharing controller 170b corresponding to the charge-sharing controller 170 shown may include a data partitioning circuit 171b, multiple determination circuits (DTC12_1) 173b1 to (DTC12_Q) 173bQ, and a switch control signal generation circuit 177b. Figure 5 and Figure 6 In this context, regarding their respective functions, data partitioning circuit 171a corresponds to data partitioning circuit 171b, first determining circuit 173a and second determining circuit 175a correspond to multiple determining circuits (DTC12_1) 173b1 to (DTC12_Q) 173bQ, and switch control signal generation circuit 177a corresponds to switch control signal generation circuit 177b. However, in Figure 6 In this configuration, the charge-sharing controller 170b may include “Q” deterministic circuits 173b1 to 173bQ.

[0090] Each of the decision circuits 173b1 to 173bQ can receive a first reference value TH_MIN and TH_MAX and a second reference value TH_TOG. The first determination circuit 173b1 can receive the (K-1)th digital data group GDAT11 and the Kth digital data group GDAT21 to generate first result data RES11 and second result data RES21, and provide the first result data RES11 and the second result data RES21 to the switch control signal generation circuit 177b. The Qth determination circuit 173bQ can receive the (K-1)th digital data group GDAT1Q and the Kth digital data group GDAT2Q to generate first result data RES1Q and second result data RES2Q, and provide the first result data RES1Q and the second result data RES2Q to the switch control signal generation circuit 177b.

[0091] The switch control signal generation circuit 177b can receive first result data RES11 to RES1Q and second result data RES21 to RES2Q from the first determination circuit 173b1 to the Q determination circuit 173bQ to generate multiple sets of switch control signals CS11 to CS1Q and CS21 to CS2Q.

[0092] Figure 7 It is shown that, according to the embodiments, it includes Figure 1 A diagram showing the arrangement of multiple pixels in a display panel.

[0093] Reference Figure 7 The display panel may include multiple pixels connected to multiple gate lines GL1, GL2, and GL3 and multiple source lines SL1, SL2, SL3, ..., SL6, and arranged in multiple rows and columns. The multiple pixels may include a red pixel R, a green pixel G, and a blue pixel B.

[0094] In some embodiments, multiple gate lines GL1, GL2 and GL3 may extend in a first direction, and multiple source lines SL1, SL2, SL3, ..., SL6 may extend in a second direction that intersects the first direction.

[0095] In some embodiments, red pixels R and blue pixels B can be arranged in odd-numbered columns, and green pixels G can be arranged in even-numbered columns. For example, in each of multiple rows, multiple pixels can have a structure in which red pixels R, green pixels G, and blue pixels B are arranged alternately. This arrangement structure can be referred to as an RGB stripe structure.

[0096] Figure 8 It is shown that it includes Figure 1 A flowchart illustrating an embodiment of the operation of a charge-sharing controller in a display device. Figure 9 It is used to describe including Figure 1 A diagram illustrating the process by which the charge-sharing controller in the display device determines the first and second conditions.

[0097] Reference Figure 1 , Figure 5 , Figure 6 and Figure 8 The charge sharing controller 170 can turn on the plurality of first switches described above with reference to FIG2 (S500) for each of the plurality of source line groups SLG_1, ..., SLG_Q based on the first result data RES11 to RES1Q and the second result data RES21 to RES2Q, in response to the first MSB satisfying a first condition (S100: Yes) and the first MSB and the second MSB satisfying a second condition (S150: Yes).

[0098] The charge sharing controller 170 can turn off multiple first switches for each of multiple source line groups SLG_1, ..., SLG_Q based on first result data RES11 to RES1Q and second result data RES21 to RES2Q in response to a first MSB not satisfying a first condition (S100: No) or a first MSB and a second MSB not satisfying a second condition (S150: No).

[0099] In some embodiments, whether the first condition is met can be determined by referring to the above. Figure 5 and Figure 6 The first determining circuit 173a and determining circuits 173b1 to 173bQ are described. Whether the second condition is satisfied can be determined by referring to the above. Figure 5 and Figure 6 The second determining circuit 175a and determining circuits 173b1 to 173bQ are described.

[0100] exist Figure 9 In this diagram, the first source line group SLG_1 among multiple source line groups SLG_1, ..., SLG_Q may include the first source line SL1 to the eighth source line SL8. For ease of description, the first MSB GDAT11_MSB and the second MSB GDAT21_MSB extracted from multiple (K-1)th digital data groups and multiple Kth digital data groups corresponding to the first source line group SLG_1 are shown. However, the first MSB GDAT12_MSB, ..., GDAT1Q_MSB and the second MSB GDAT22_MSB, ..., GDAT2Q_MSB can be extracted for the remaining source line groups SLG_2, ..., SLG_Q in the same manner as the first source line group SLG_1. Hereinafter, it is assumed that the values ​​of the first MSB GDAT11_MSB and the second MSB GDAT21_MSB are "01101010" and "01011101", respectively.

[0101] In some embodiments, it can be from multiple pixels (e.g., P) (K-1)1 P (K-1)2 P (K-1)3 P (K-1)4 P (K-1)5 P (K-1)6 P (K-1)7 and P (K-1)8 The first MSB GDAT11_MSB is extracted from the digital data corresponding to the pixel value of each pixel in the dataset, and can be extracted from multiple pixels (e.g., P). K1 P K2 P K3 P K4 P K5 P K6 P K7 and PK8 Extract the second MSB GDAT21_MSB corresponding to the pixel value of each pixel in the data.

[0102] The charge-sharing controller 170 may determine that a first condition is met in response to the number of first MSBs having a first value being included within a first reference range. In this case, the first value may be one of "1" and "0", and the first reference range may be determined based on a number corresponding to half the number of the first MSBGDAT11_MSB (or source lines included in each source line group) and a predetermined margin. For example, the first value may be "1", and the first reference range may be determined as a range with a margin of "±1" (e.g., a range greater than or equal to "3" and less than or equal to "5") based on a number corresponding to half the number of the first MSB GDAT11_MSB (e.g., "4").

[0103] The charge-sharing controller 170 can determine that the second condition is satisfied in response to the number of bit pairs with different values ​​in the first MSB GDAT11_MSB and the second MSB GDAT21_MSB being included within a second reference range. In this case, bit pairs can be generated based on the bits at the same number of bits in each of the first MSB GDAT11_MSB and the second MSB GDAT21_MSB. For example, in Figure 9 In this context, bit pairs can be (0,0), (1,1), (1,0), (0,1), (1,1), (0,1), (1,0), and (0,1), and the second reference range can be defined as a range greater than or equal to half the number of the first MSB GDAT11_MSB (e.g., "4").

[0104] Therefore, in Figure 9 In this case, the number of first MSB GDAT11_MSBs with the first value is "4" and is included within the first reference range, thus satisfying the first condition. The number of bit pairs with different values ​​among the bit pairs of the first MSB GDAT11_MSB and the second MSB GDAT21_MSB is "5" and is included within the second reference range, thus satisfying the second condition. In this case, since the first and second conditions are satisfied, the charge sharing controller 170 can turn on multiple first switches. As a result, charge sharing can be performed by electrically connecting the source lines SL1 to SL8 included in the first source line group SLG_1 to each other.

[0105] Figure 10 This illustrates an embodiment. Figure 1 A timing diagram showing the changes in the group switch control signal and the voltage level in the source line of the display device. Figure 11 It is used to describe according to Figure 1A graph showing the change in current consumption when charge sharing is performed in the display device.

[0106] exist Figure 10 In the diagram, when charge sharing is performed before and after driving row (K-1) of the display panel, the changes in the voltage levels of group switch control signals CS11 and CS21, as well as source lines SL3, SL4, SL6, SL7, and SL8, are shown. Each of the time intervals for driving row (K-1) and driving row K can be referred to as the above reference. Figure 1 The term "row unit time interval" is described.

[0107] Reference Figure 10 During the interval where the (K-1)th row of the display panel is driven, while performing the original function of the display device for displaying images on the display panel, the voltage level of the group switch control signal CS21 can be maintained at a logic high level. In this case, the above-mentioned reference can be turned on. Figure 1 The description includes multiple second switches.

[0108] After the image is displayed on the display panel, the voltage level of the group switch control signal CS21 can be changed from logic high to logic low. (Refer to the above...) Figure 8 When multiple first switches are connected, while the voltage level of the group switch control signal CS21 is maintained at a logic low level, the voltage level of the group switch control signal CS11 can be maintained at a logic high level to perform charge sharing.

[0109] exist Figure 9 In the process of performing charge sharing, the source lines SL1 to SL8, which are included in the first source line group SLG_1, are electrically connected to each other, so the voltage level of each source line can be adjusted to a near intermediate voltage level VM (which is half of the maximum drive voltage level).

[0110] For example, source lines SL4, SL6, and SL8 can be adjusted from being close to the minimum drive voltage level VL before charge sharing is performed to being close to the intermediate voltage level VM while charge sharing is performed, and can be adjusted to be close to the maximum drive voltage level VH after charge sharing is performed. Source lines SL3 and SL7 can be adjusted from being close to the maximum drive voltage level VH before charge sharing is performed to being close to the intermediate voltage level VM while charge sharing is performed, and can be adjusted to be close to the minimum drive voltage level VL after charge sharing is performed.

[0111] Reference Figure 10 and Figure 11 ,exist Figure 9In the diagram, without charge sharing, the display panel consumes 22.9 mA. With charge sharing enabled, the display panel consumes 19.5 mA. Therefore, by enabling charge sharing, the current consumption can be reduced by approximately 15%.

[0112] Figure 12 It is shown that, according to the embodiments, it includes Figure 1 A diagram showing the arrangement of multiple pixels in a display panel.

[0113] Reference Figure 12 The display panel may include multiple pixels connected to multiple gate lines GL1, GL2, and GL3 and multiple source lines SL1, SL2, SL3, ..., SL6, arranged in multiple rows and columns. The multiple pixels may include a red pixel R, a green pixel G, and a blue pixel B.

[0114] In some embodiments, multiple gate lines GL1, GL2 and GL3 may extend in a first direction, and multiple source lines SL1, SL2, SL3, ..., SL6 may extend in a second direction that intersects the first direction.

[0115] In some embodiments, red pixels R and blue pixels B may be arranged in odd-numbered columns, and green pixels G may be arranged in even-numbered columns. For example, in each of multiple rows, multiple pixels may have a structure in which red-green pixel pairs and blue-green pixel pairs are arranged alternately. This arrangement structure may be referred to as a pentile structure.

[0116] exist Figure 12 In the pentile structure, the need for charge sharing is likely small because only identical green pixels are arranged in even-numbered columns. However, since different red and blue pixels are arranged alternately in odd-numbered columns, charge sharing is very likely to be required. Therefore, as described later, charge sharing can be performed for odd-numbered source lines using third and fourth conditions.

[0117] Figure 13 It is shown that it includes Figure 1 A flowchart illustrating an embodiment of the operation of a charge-sharing controller in a display device.

[0118] exist Figure 13 In the middle, it can be used for those with the above reference. Figure 12 The described pentile structure of the display panel performs charge sharing.

[0119] Reference Figure 1 , Figure 5 , Figure 6 , Figure 12 and Figure 13The charge sharing controller 170 can turn on the plurality of first switches described above with reference to FIG2 (S500) for each of the plurality of source line groups SLG_1, ..., SLG_Q based on the first result data RES11 to RES1Q and the second result data RES21 to RES2Q, in response to the first MSB satisfying a first condition (S100: Yes) and the first MSB and the second MSB satisfying a second condition (S150: Yes).

[0120] The charge sharing controller 170 can, for each of the multiple source line groups SLG_1, ..., SLG_Q, respond to the first MSB not satisfying a first condition (S100: No) or the first MSB and the second MSB not satisfying a second condition (S150: No) and responding to the third MSB satisfying a third condition (S300: Yes) and the third MSB and the fourth MSB satisfying a fourth condition (S350: Yes), turn on a plurality of first switches corresponding to odd-numbered sequences (S700).

[0121] In some embodiments, the third MSB may be a bit in the first MSB corresponding to a selected column (such as an odd column) of the display panel, and the fourth MSB may be a bit in the second MSB corresponding to a selected column (such as an odd column) of the display panel. In the embodiments described herein, the selected column is an odd column of the display panel. However, according to embodiments, the selected column may not be limited to an odd column.

[0122] The charge sharing controller 170 can turn off multiple first switches for each of multiple source line groups SLG_1, ..., SLG_Q based on first result data RES11 to RES1Q and second result data RES21 to RES2Q in response to a third MSB not satisfying a third condition (S300: No) or a third MSB and a fourth MSB not satisfying a fourth condition (S350: No).

[0123] In some embodiments, whether the first condition or the third condition is met can be determined by referring to the above. Figure 5 and Figure 6 The first determining circuit 173a and determining circuits 173b1 to 173bQ are described. Whether the second or fourth condition is met can be determined by referring to the above. Figure 5 and Figure 6 The second determining circuit 175a and determining circuits 173b1 to 173bQ are described.

[0124] Figure 14A and Figure 14B It is shown that it includes Figure 1 A block diagram of an embodiment of the first switching circuit in a display device.

[0125] exist Figure 14A and Figure 14B The diagram shows the respective operations corresponding to the S700 operation. Figure 1 The first switching circuits 131'a and 131'b are shown. Figure 2A , Figure 2B , Figure 14A and Figure 14B In this context, components with similar labels perform similar functions (e.g., 131-1a and 131'-1a, 131-1b and 131'-1b).

[0126] Reference Figure 2A and Figure 14A The first switching circuit 131'a can receive analog data A1, A2, A3, ..., A8 converted from digital data D1, D2, D3, ..., D8, and provide the analog data A1, A2, A3, ..., A8 to the first source line SL1 to the eighth source line SL8 included in the first source line group SLG_1, respectively.

[0127] The first switching circuit 131'a may include a plurality of first switches 131'-1a and a plurality of second switches 131'-2.

[0128] Multiple first switches 131'-1a can connect the first source lines SL1 to the eighth source line SL8 included in the first source line group SLG_1 to each other. In some embodiments, the multiple first switches 131'-1a can respectively connect a reference source line (e.g., SL1) that is one of the source lines included in the first source line group SLG_1 to other source lines SL2 to SL8 included in the first source line group SLG_1. Figure 14A In the diagram, the first source line SL1 is shown corresponding to the reference source line; however, the embodiment is not limited thereto. Multiple second switches 131'-2 can connect the first source line SL1 to the eighth source line SL8, which are included in the first source line group SLG_1, to... Figure 1 The digital-to-analog converter 120 is included.

[0129] The first switch 131'a can be accessed from Figure 1 The charge sharing controller 170 in the middle receives group switch control signals CS11 and CS21.

[0130] In some embodiments, a plurality of first switches 131'-1a may be turned on or off based on a group switch control signal CS11, and a plurality of second switches 131'-2 may be turned on or off based on a group switch control signal CS21.

[0131] In some embodiments, the group switch control signal CS11[0:6] can be a 7-bit signal, CS21 can be a 1-bit signal, and... Figure 14A In the embodiments described above, the plurality of first switches 131'-1a can be referenced above. Figure 13 The S500 operation described is simultaneously turned on. In this case, the group switch control signal CS11[0:6] may have the value "1111111". Multiple first switches 131'-1a, corresponding only to the odd-numbered columns of the display panel, can be referenced above. Figure 13 The S700 operation described involves simultaneously turning on or off. In this case, the group switch control signal CS11[0:6] may have the value "1010101". Multiple first switches 131'-1a can be referenced above. Figure 13 The S900 operation described herein is simultaneously turned off. In this case, the group switch control signal CS11[0:6] may have the value "0000000". Multiple second switches 131'-2 may also be turned on or off simultaneously. However, the timing of the on-state of multiple first switches 131'-1a and multiple second switches 131'-2 may differ from each other.

[0132] exist Figure 14A In the illustration, the first switching circuit 131'a is shown as an embodiment of a plurality of switching circuits included in the drive switching circuit 130. However, the plurality of switching circuits other than the first switching circuit 131'a may also have the same configuration as the first switching circuit 131'a.

[0133] In some embodiments, the plurality of first switches included in each of the plurality of first switch circuits may be respectively connected to other source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q, using a reference source line as one of the source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q. However, the embodiments are not limited thereto. In some embodiments, as Figure 14B As shown, the first switching circuit 131'b may include a plurality of first switches 131'-1b and a plurality of second switches 131'-2, and each of the plurality of first switches 131'-1b may respectively connect two adjacent source lines included in each of the plurality of source line groups SLG_1, ..., SLG_Q to each other.

[0134] Figure 15 It is used to describe the inclusion of, according to the embodiments Figure 1 A diagram illustrating the process by which the charge-sharing controller in the display device determines the first to fourth conditions.

[0135] Reference Figure 1 , Figure 5 , Figure 6 , Figure 8 , Figure 13 , Figure 14A , Figure 14B and Figure 15 The charge sharing controller 170 can generate each of the multiple group switch control signals based on the first MSB, the second MSB, the third MSB, and the fourth MSB.

[0136] In some embodiments, the charge sharing controller 170 can be used with Figure 5 and Figure 6 The similar components shown determine the first through fourth conditions. In response to the number of first MSBs having a first value falling within a first reference range, the charge-sharing controller 170 can determine that the first condition is met. In this case, the first value can be one of "1" and "0", and the first reference range can be determined based on a number corresponding to half the number of the first MSB GDAT11_MSB (or the source lines included in each source line group) and a predetermined margin. For example, the first value can be "1", and the first reference range can be determined as a range with a margin of "±1" (e.g., greater than or equal to "3" and less than or equal to "5") based on a number corresponding to half the number of the first MSB GDAT11_MSB (e.g., "4").

[0137] The charge-sharing controller 170 can determine that a second condition is satisfied in response to the number of bit pairs with different values ​​in the first MSB GDAT11_MSB and the second MSB GDAT21_MSB, which is included within a second reference range. In this case, bit pairs can be generated based on the bits at the same number of bits in each of the first MSB GDAT11_MSB and the second MSB GDAT21_MSB. For example, in Figure 15 In this context, bit pairs can be (1,0), (0,0), (0,1), (0,0), (1,0), (0,0), (0,1), and (0,0), and the second reference range can be defined as a range greater than or equal to half the number of the first MSB GDAT11_MSB (e.g., "4").

[0138] Therefore, in Figure 15In this case, the number of first MSB GDAT11_MSBs with the first value is "2" and is outside the first reference range, therefore, the first condition is not met. The number of bit pairs with different values ​​among the bit pairs of the first MSB GDAT11_MSB and the second MSB GDAT21_MSB is "4" and is included in the second reference range, therefore, the second condition is met. In this case, since the second condition is met but the first condition is not met, the charge sharing controller 170 can determine that the third condition is met in response to the fact that the number of third MSB GDAT11_MSB_ODDs with the first value is included in the third reference range. For example, the first value can be one of "1" and "0", and the third reference range can be determined based on the number corresponding to half of the number of third MSB GDAT11_MSB_ODDs and a predetermined margin. For example, the first value can be "1", and the third reference range can be determined as a range with a margin of "±1" (e.g., a range greater than or equal to "1" and less than or equal to "3") based on the number corresponding to half of the number of the third MSB GDAT11_MSB_ODD (e.g., "2").

[0139] The number of bit pairs with different values ​​in the bit pairs of the third MSB GDAT11_MSB_ODD and the fourth MSB GDAT21_MSB_ODD is included within the fourth reference range, and the charge sharing controller 170 can determine that the fourth condition is satisfied. In this case, bit pairs can be generated based on the bits at the same number of bits in each of the third MSB GDAT11_MSB_ODD and the fourth MSB GDAT21_MSB_ODD. For example, in Figure 15 In this context, bit pairs can be (1,0), (0,1), (1,0), and (0,1), and the fourth reference range can be defined as a range greater than or equal to half the number of the third MSB GDAT11_MSB_ODD (e.g., "2").

[0140] Therefore, in Figure 15 In this case, the number of third MSB GDAT11_MSB_ODDs with the first value is "2" and is included in the third reference range, thus satisfying the third condition. The number of bit pairs with different values ​​in the bit pairs of the third MSB GDAT11_MSB_ODD and the fourth MSB GDAT21_MSB_ODD is "4" and is included in the fourth reference range, thus satisfying the fourth condition. In this case, since the third and fourth conditions are satisfied, the charge sharing controller 170 can turn on the plurality of first switches corresponding to the odd-numbered columns. As a result, charge sharing can be performed by electrically connecting the odd-numbered source lines SL1, SL3, SL5 and SL7 included in the first source line group SLG_1 to each other.

[0141] Figure 16 This is a block diagram illustrating a display device according to an embodiment. Figure 17 It is shown that it includes Figure 16 A block diagram of an embodiment of the first switching circuit in a display device.

[0142] exist Figure 16 The number of unit digital-to-analog converters included in the digital-to-analog converter 120a included in the display device 100a is only the number of units included in the display device 100a. Figure 1 The number of unit digital-to-analog converters in the digital-to-analog converter 120 of the display device 100 is half.

[0143] Reference Figure 16 The data latch circuit 110a can latch the input digital data IDAT to latch the digital data D1, D2, D3, ..., D1 corresponding to one row of a multi-row array. N / 2 Provided to the digital-to-analog converter 120a. The digital-to-analog converter 120a can convert digital data D1, D2, D3, ..., D... N / 2 Convert to analog data A1, A2, A3, ..., A N / 2 And the simulated data A1, A2, A3, ..., A N / 2 Provided to the drive switch circuit 130a. The drive switch circuit 130a can transmit analog data A1, A2, A3, ..., A through the data pad 140. N / 2 This data is provided to the display panel as pixel data.

[0144] The drive switch circuit 130a may include a plurality of switch circuits (e.g., first switch circuits 131a to Qth switch circuits 13Qa). Each of the plurality of switch circuits 131a to 13Qa may include a plurality of first switches, a plurality of second switches, and a plurality of third switches.

[0145] Multiple source lines SL1, SL2, SL3, ..., SL N-1 SL N It can be divided into multiple source line groups SGL_1, ..., SLG_Q. Multiple first switches can be electrically connected to each other based on each of the multiple group switch control signals CS11 to CS1Q to perform charge sharing.

[0146] Multiple second switches can be electrically connected to the digital-to-analog converter 120a based on each of multiple group switch control signals CS21 to CS2Q, including odd-numbered source lines in each of multiple source line groups SLG_1, ..., SLG_Q.

[0147] Multiple third switches can be electrically connected to the digital-to-analog converter 120a based on each of multiple group switch control signals CS31 to CS3Q, including even-numbered source lines in each of multiple source line groups SLG_1, ..., SLG_Q.

[0148] According to the above configuration, the display device 100a can perform charge sharing by electrically connecting the source lines included in each of the multiple source line groups SLG_1, ..., SLG_Q to each other, based on the digital data RDAT1 and RDAT2 corresponding to each of the multiple source line groups SLG_1, ..., SLG_Q, the multiple group switch control signals CS11 to CS1Q, and the multiple switch circuits 131a to 13Qa. Charge sharing can also be performed based on the parasitic capacitance 150 formed in the source lines included in each of the multiple source line groups SLG_1, ..., SLG_Q. For example, the parasitic capacitance 150 can be formed on the data pad 140 and M×N pixels P. 11 P 21 P 31 ... P (M-1)N P MN The source lines SL1, SL2, SL3, ..., SL between N-1 SL N In part of it.

[0149] exist Figure 2A and Figure 17 In this context, components with similar labels perform similar functions (e.g., 131-1a and 131a-1, 131-2 and 131a-2). However, in... Figure 17 In addition to the first switch circuit 131a, the first switch circuit 131c also includes a plurality of third switches 131a-3.

[0150] Reference Figure 16 and Figure 17 The first switching circuit 131c can receive analog data A1, A2, A3 and A4 converted from digital data D1, D2, D3 and D4, and provide the analog data A1, A2, A3 and A4 to the first source line SL1 to the eighth source line SL8 included in the first source line group SLG_1, respectively.

[0151] The first switching circuit 131c may include a plurality of first switches 131a-1, a plurality of second switches 131a-2, and a plurality of third switches 131a-3.

[0152] Multiple first switches 131a-1 can connect the first source line SL1 to the eighth source line SL8 included in the first source line group SLG_1. Multiple second switches 131a-2 and multiple third switches 131a-3 can respectively connect the first source line SL1 to the eighth source line SL8 to the digital-to-analog converter 120a.

[0153] The first switching circuit 131c can receive group switching control signals CS11, CS21 and CS31 from the charge sharing controller 170a.

[0154] In some embodiments, a plurality of first switches 131a-1 may be turned on or off based on a group switch control signal CS11, a plurality of second switches 131a-2 may be turned on or off based on a group switch control signal CS21, and a plurality of third switches 131a-3 may be turned on or off based on a group switch control signal CS31.

[0155] In some embodiments, each of the group switch control signals CS11, CS21, and CS31 may be a 1-bit signal, and the plurality of first switches 131a-1, the plurality of second switches 131a-2, and the plurality of third switches 131a-3 may be simultaneously turned on or off. However, the timing of the turn-on of the plurality of first switches 131a-1, the plurality of second switches 131a-2, and the plurality of third switches 131a-3 may be different from each other.

[0156] exist Figure 17 The diagram shows a first switching circuit 131c as an example of a plurality of switching circuits included in a drive switching circuit 130a. However, the plurality of switching circuits other than the first switching circuit 131c may also have the same configuration as the first switching circuit 131c.

[0157] Figure 18 This illustrates an embodiment. Figure 16 A timing diagram showing the changes in the group switch control signal and the voltage level in the source line of the display device.

[0158] exist Figure 18 In the diagram, when charge sharing is performed before and after driving row (K-1) of the display panel, the changes in the voltage levels of group switch control signals CS11, CS21, and CS31, as well as source lines SL1, SL3, SL5, and SL7, are shown. Each of the time intervals for driving row (K-1) and row K can be referred to as the above reference. Figure 1 The term "row unit time interval" is described.

[0159] Reference Figure 18During the interval where the (K-1)th row of the display panel is driven, while performing the original function of the display device for displaying images on the display panel, the voltage levels of the group switch control signal CS21 and the group switch control signal CS31 are alternately maintained at a logic high level. In this case, refer to the above. Figure 17 The multiple second switches 131a-2 and multiple third switches 131a-c described can be turned on alternately.

[0160] After the image is displayed on the display panel, the voltage levels of the group switch control signals CS21 and CS31 change from logic high to logic low. (Refer to the above...) Figure 17 When multiple first switches 131a-1 are turned on as described, while the voltage levels of group switch control signals CS21 and CS31 are maintained at logic low, the voltage level of group switch control signal CS11 can be maintained at logic high to perform charge sharing.

[0161] exist Figure 18 In the process of performing charge sharing, the source lines SL1, SL3, SL5 and SL7 corresponding to the odd-numbered columns in the first source line group SLG_1 are electrically connected to each other. Therefore, the voltage level of each of the source lines SL1, SL3, SL5 and SL7 can be adjusted to a level close to the intermediate voltage level VM (which is half of the maximum drive voltage level).

[0162] For example, source lines SL3 and SL7 can be adjusted from being close to the minimum drive voltage level VL before charge sharing is performed to being close to the intermediate voltage level VM while charge sharing is performed, and can be adjusted to be close to the maximum drive voltage level VH after charge sharing is performed. Source lines SL1 and SL5 can be adjusted from being close to the maximum drive voltage level VH before charge sharing is performed to being close to the intermediate voltage level VM while charge sharing is performed, and can be adjusted to be close to the minimum drive voltage level VL after charge sharing is performed.

[0163] Figure 19 This is a block diagram illustrating a display system according to an embodiment.

[0164] Figure 19 The display system 500 can be various electronic devices with image display capabilities (such as mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), wearable devices, portable multimedia players (PMPs), handheld devices, handheld computers, etc.).

[0165] Reference Figure 19The display system 500 may include a host device 520 and a display device 530. The display device 530 may include a display driver integrated circuit (DDI) 540 and a display panel 550.

[0166] The host device 520 controls the overall operation of the display system 500. The host device 500 may be an application processor (AP), baseband processor (BBP), microprocessor unit (MPU), etc. The host device 500 can provide image data IMG, clock signal CLK, and control signal CTRL to the display device 530. For example, the image data IMG may include RGB pixel values ​​and have a resolution of w×h, where w is the number of pixels in the horizontal direction and h is the number of pixels in the vertical direction.

[0167] The control signal CTRL may include command signals, horizontal synchronization signals, vertical synchronization signals, data enable signals, etc. For example, image data IMG and control signal CTRL may be provided to DDI 540 in display device 530 in a grouped manner. Command signals may include control information, image information, and / or display setting information. Image information may include, for example, the resolution of the input image data IMG. Display setting information may include, for example, panel information, brightness setting values, etc. For example, host device 520 may provide information based on user input or predetermined setting values ​​as display setting information, and provide the above reference. Figure 5 and Figure 6 The description includes the first reference values ​​TH_MIN and TH_MAX, and the second reference value TH_TOG.

[0168] The DDI 540 can drive the display panel 550 based on image data IMG and control signal CTRL. The DDI 540 can convert the digital image signal IMG into an analog signal and drive the display panel 550 based on the analog signal. The image data IMG can be as described above. Figure 1 The input digital data IDAT described above, and the control signal CTRL, may include the references above. Figure 1 The charge sharing control signal CCS is described.

[0169] The DDI 540 may include a charge-sharing controller (CSC), which can be the one described above. Figure 1 and Figure 16 The charge-sharing controllers 170 and 170a are described.

[0170] The display device 530 can perform charge sharing for source lines in a first source line group included in a plurality of source line groups, and then perform charge sharing for source lines in a second source line group included in a plurality of source line groups that is different from the first source line group.

[0171] Figure 20This is a block diagram illustrating a display device according to an embodiment.

[0172] Figure 20 An electroluminescent display device, such as an OLED display device, is shown as an example, and the embodiments are not limited to a particular type of display device.

[0173] Reference Figure 20 The electroluminescent display device 530 may include a display panel 550 comprising a plurality of pixel rows 511 and a DDI 540 for driving the display panel 550. The DDI 540 may include a data driver or source driver 600, a scan driver 544, a timing controller 545, a power supply unit 546, and a gamma circuit 547.

[0174] Display panel 550 can be connected to source driver 600 of DDI 540 via multiple source lines, and can be connected to scan driver 544 of DDI 540 via multiple scan lines. Display panel 550 may include pixel rows 511. That is, display panel 550 may include multiple pixels PX arranged in a matrix having multiple rows and columns. A row of pixels PX connected to the same scan line may be referred to as a pixel row 511. In some embodiments, display panel 550 may be a self-emitting display panel that emits light without using a backlight unit. For example, display panel 550 may be an organic light-emitting diode (OLED) display panel.

[0175] Each pixel PX included in the display panel 550 can have various configurations depending on the driving scheme of the display device 530. For example, the electroluminescent display device 530 can be driven using either analog or digital driving methods. While analog driving methods use variable voltage levels corresponding to input data to generate grayscale, digital driving methods use variable durations of LED emitted light to generate grayscale. Analog driving methods are difficult to implement because they use digital disc rendition (DDI), which is complex to manufacture if the display is large and has a high resolution. On the other hand, digital driving methods can easily achieve high resolution with a simpler circuit structure. As the size of the display panel increases and the resolution increases, digital driving methods can have more advantageous characteristics than analog driving methods. The display device according to the embodiment can be applied to both analog and digital driving methods.

[0176] The source driver 600 can apply a data signal to the display panel 550 via the source line based on the display data DDT. The scan driver 544 can apply a scan signal to the display panel 550 via the scan line.

[0177] The timing controller 545 controls the operation of the display device 530. The timing controller 545 provides predetermined control signals to the source driver 600 and the scan driver 544 to control the operation of the display panel 550. In some embodiments, the source driver 600, scan driver 544, and timing controller 545 may be implemented as a single integrated circuit (IC). In other embodiments, the source driver 600, scan driver 544, and timing controller 545 may be implemented as two or more integrated circuits. A drive module that includes at least the timing controller 545 and the source driver 600 may be referred to as a timing controller embedded data driver (TED).

[0178] The timing controller 545 can be obtained from Figure 19 The host device 520 receives image data IMG and input control signals. For example, the image data IMG may include red (R) image data, green (G) image data, and blue (B) image data. According to an embodiment, the image data IMG may include white image data, magenta image data, yellow image data, cyan image data, etc. The input control signals may include a master clock signal, a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, etc.

[0179] Power supply unit 546 can supply a high power supply voltage ELVDD and a low power supply voltage ELVSS to display panel 550. Additionally, power supply unit 546 can supply a regulator voltage VREG to gamma circuit 547. Gamma circuit 547 can generate a gamma reference voltage GRV based on regulator voltage VREG. For example, regulator voltage VREG can be the high power supply voltage ELVDD or another voltage generated based on the high power supply voltage ELVDD.

[0180] As described above, the display device according to the embodiment can perform charge sharing by electrically connecting the source lines included in each of the plurality of source line groups based on digital data corresponding to each of the plurality of source line groups, the plurality of group switch control signals, and the plurality of switch circuits. Charge sharing can be performed based on the parasitic capacitance formed in the source lines included in each of the plurality of source line groups. The display device can perform charge sharing without additional data other than the input digital data used to display an image on the display panel. The display device can perform charge sharing using general components for performing the original functions of the display device without additional components other than a charge sharing controller and a plurality of first switches.

[0181] The embodiments can be usefully used in display devices and systems including such display devices. For example, the embodiments can be more usefully applied to computers, laptops, cellular phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital TVs, digital cameras, portable game consoles, navigation devices, wearable devices, IoT (Internet of Things) devices, IoE (Internet of Everything) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, in-vehicle navigation systems, video phones, monitoring systems, autofocus systems, tracking systems, motion detection systems, etc.

[0182] The above are illustrative examples and should not be construed as limiting them. Although some embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the embodiments. Therefore, all such modifications are intended to be included within the scope of the embodiments defined in the claims. It will therefore be understood that the above are illustrative examples of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: The display panel includes multiple pixels connected to multiple gate lines and multiple source lines and arranged in multiple rows and columns; Multiple switching circuits are configured to electrically connect the source lines in each of the multiple source line groups included in the multiple source lines to each other based on each of the multiple sets of switching control signals to perform charge sharing; as well as A charge-sharing controller is configured to generate each of the plurality of group switching control signals based on a first most significant bit of each of the plurality of (K-1)th digital data groups and a second most significant bit of each of the plurality of Kth digital data groups. Wherein, the plurality of (K-1)th digital data groups correspond to the pixel values ​​of the (K-1)th row of the display panel, and the plurality of Kth digital data groups correspond to the pixel values ​​of the Kth row of the display panel, where K is a natural number greater than 1. Each of the plurality of switching circuits includes a plurality of first switches configured to perform the charge sharing; and The charge-sharing controller is configured to enable each of the plurality of group switch control signals to turn on the plurality of first switches for each of the plurality of source line groups in response to the first most significant bit satisfying a first condition and the first most significant bit and the second most significant bit satisfying a second condition.

2. The display device according to claim 1, wherein: The first condition is satisfied when the number of the first most significant bits having a first value is included within a first reference range. and The number of bit pairs with different values ​​in the bit pairs of the first most significant bit and the second most significant bit is included within the second reference range, satisfying the second condition.

3. The display device according to claim 1, wherein, The charge-sharing controller is configured to invalidate each of the plurality of group switch control signals to turn off the plurality of first switches for each of the plurality of source line groups in response to the first most significant bit not satisfying the first condition or the first most significant bit and the second most significant bit not satisfying the second condition.

4. The display device according to claim 3, wherein: The first condition is satisfied when the number of the first most significant bits having a first value is included within a first reference range. The number of bit pairs with different values ​​in the bit pairs corresponding to the first most significant bit and the second most significant bit is included within the second reference range, satisfying the second condition; and The first reference range and the second reference range are determined based on the number of source lines included in each of the plurality of source line groups.

5. The display device according to claim 1, wherein: The third most significant bit is the first most significant bit corresponding to a pixel in a selected column among the multiple columns, and the fourth most significant bit is the second most significant bit corresponding to a selected column; and The charge-sharing controller is configured to, for each of the plurality of source line groups, activate each of the plurality of group switch control signals to turn on the plurality of first switches corresponding to the selected column, in response to the third most significant bit satisfying a third condition and the third most significant bit and the fourth most significant bit satisfying a fourth condition.

6. The display device according to claim 5, wherein: The first condition is satisfied when the number of the first most significant bits having a first value is included within a first reference range. and The number of bit pairs with different values ​​in the bit pairs of the first most significant bit and the second most significant bit is included within the second reference range, satisfying the second condition.

7. The display device according to claim 6, wherein: The third condition is satisfied when the number of the third most significant bits having the first value is included within the third reference range. and The number of bit pairs with different values ​​in response to the third most significant bit and the fourth most significant bit is included in the fourth reference range, satisfying the fourth condition.

8. The display device according to claim 7, wherein, The selected column is an odd-numbered column.

9. The display device according to claim 8, wherein, The red and blue pixels of the plurality of pixels are arranged in odd-numbered columns, and the green pixels of the plurality of pixels are arranged in even-numbered columns.

10. The display device according to claim 5, wherein, The charge-sharing controller is configured to, for each of the plurality of source line groups, invalidate each of the plurality of group switch control signals to turn off the plurality of first switches corresponding to the selected column in response to the third most significant bit not satisfying the third condition or the third most significant bit and the fourth most significant bit not satisfying the fourth condition.

11. The display device according to claim 10, wherein: The first condition is satisfied when the number of the first most significant bits having a first value is included within a first reference range. The number of bit pairs with different values ​​in response to the first most significant bit and the second most significant bit is included in the second reference range, satisfying the second condition; The third condition is satisfied when the number of the third most significant bits having the first value is included within the third reference range. and The number of bit pairs with different values ​​in response to the third most significant bit and the fourth most significant bit is included in the fourth reference range, satisfying the fourth condition.

12. The display device according to claim 1, wherein, The plurality of first switches are configured to, subject to the first condition and the second condition, respectively connect a reference source line, which is one of the source lines included in each of the plurality of source line groups, to the other source lines included in each of the plurality of source line groups.

13. The display device of claim 12, further comprising a digital-to-analog converter configured to convert digital data into analog data. in, Each of the plurality of switching circuits further includes a plurality of second switches, the plurality of second switches being configured to connect a source line included in each of the plurality of source line groups to the digital-to-analog converter. The charge-sharing controller is configured to determine, in each of a plurality of row-unit time intervals for driving the display panel row by row, whether the first condition and the second condition are satisfied, and In each of the plurality of row unit time intervals, the time point at which the plurality of first switches are turned on is after the time point at which the plurality of second switches are turned on.

14. The display device according to claim 1, wherein, Each of the plurality of switching circuits will connect two adjacent source lines among the source lines included in each of the plurality of source line groups.

15. A display device, comprising: The display panel includes multiple pixels connected to multiple gate lines and multiple source lines and arranged in multiple rows and columns; as well as A display driver integrated circuit configured to drive the display panel, the display driver integrated circuit comprising: Multiple switching circuits are configured to electrically connect the source lines in each of the multiple source line groups included in the multiple source lines to each other based on each of the multiple sets of switching control signals to perform charge sharing; A data latch circuit is configured to output a plurality of (K-1)th digital data groups corresponding to the pixel values ​​of the (K-1)th row of the display panel and a plurality of Kth digital data groups corresponding to the pixel values ​​of the Kth row of the display panel, wherein K is a natural number greater than 1; and A charge-sharing controller is configured to generate each of the plurality of group switching control signals based on a first most significant bit of each of the plurality of (K-1)th digital data groups and a second most significant bit of each of the plurality of Kth digital data groups. Each of the plurality of switching circuits includes a plurality of first switches configured to perform the charge sharing; and The charge-sharing controller is configured to enable each of the plurality of group switch control signals to turn on the plurality of first switches for each of the plurality of source line groups in response to the first most significant bit satisfying a first condition and the first most significant bit and the second most significant bit satisfying a second condition.

16. The display device according to claim 15, wherein, The first condition is satisfied when the number of the first most significant bits having a first value is included within a first reference range. The number of bit pairs with different values ​​in the bit pairs corresponding to the first most significant bit and the second most significant bit is included within the second reference range, satisfying the second condition; and The first reference range and the second reference range are determined based on the number of source lines included in each of the plurality of source line groups.

17. A display device, comprising: The display panel includes multiple pixels connected to multiple gate lines and multiple source lines and arranged in multiple rows and columns; Multiple switching circuits are configured to electrically connect source lines in each of multiple source line groups, including multiple source lines, to each other to perform charge sharing based on each of multiple sets of switch control signals, each of the multiple switching circuits including multiple first switches to perform the charge sharing; as well as A charge-sharing controller is configured to generate each of the plurality of group switch control signals based on a first most significant bit of each of a plurality of (K-1)th digital data groups, a second most significant bit of each of a plurality of Kth digital data groups, a third most significant bit as a first most significant bit corresponding to a selected column of the display panel, and a fourth most significant bit as a second most significant bit corresponding to a selected column of the display panel, where K is a natural number greater than 1. The charge-sharing controller is configured to enable each of the plurality of group switch control signals to turn on the plurality of first switches for each of the plurality of source line groups in response to the first most significant bit satisfying a first condition and the first most significant bit and the second most significant bit satisfying a second condition.

18. The display device according to claim 17, wherein, The selected column is an odd-numbered column.

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