Data driver and display device including the same

Abstract

A data driver and a display apparatus including the same are provided. A data driver for providing a data voltage to a display panel includes a digital-to-analog conversion block, an option storage block, a data exchange block, and an output buffer block. The digital-to-analog conversion block converts line data into the data voltage. The option storage block stores a pixel arrangement option representing a pixel arrangement structure of the display panel. The data exchange block is connected to the digital-to-analog conversion block and the option storage block, and selectively performs a data exchange operation of exchanging the data voltage based on the pixel arrangement option and whether the line data is odd line data or even line data. The output buffer block is connected to the data exchange block and outputs the data voltage on which the data exchange operation is selectively performed to a data line.

Description

TECHNICAL FIELD

[0001] Embodiments of the inventive concept relate to a display apparatus, and more particularly, to a data driver and a display apparatus including the same. BACKGROUND

[0002] The data driver can be coupled with the display panel and can provide data voltages to pixels of the display panel through data lines of the display panel. The pixels of the display panel can display an image based on the data voltages received from the data driver.

[0003] The data driver should have a configuration and operation suitable for a pixel arrangement structure of the display panel. Accordingly, a dedicated data driver suitable for a display panel having a different pixel arrangement structure should be implemented, respectively. SUMMARY

[0004] Some embodiments provide a data driver capable of driving a display panel having different pixel arrangement structures.

[0005] Some embodiments provide a display apparatus capable of driving a display panel having different pixel arrangement structures.

[0006] Some embodiments provide a display apparatus capable of driving a display panel including a first display area having a first pixel arrangement structure and a second display area having a second pixel arrangement structure.

[0007] According to an embodiment, a data driver for providing data voltages to a display panel is provided. The data driver includes a digital-to-analog conversion block configured to convert line data into data voltages, an option storage block configured to store a pixel arrangement option representing a pixel arrangement structure of the display panel, a data exchange block connected to the digital-to-analog conversion block and the option storage block and configured to selectively perform a data exchange operation of exchanging the data voltages based on the pixel arrangement option and whether the line data is odd line data or even line data, and an output buffer block connected to the data exchange block and configured to output the data voltages on which the data exchange operation is selectively performed to data lines.

[0008] In an embodiment, in case that the pixel arrangement option has a first value and the line data is even line data, the data exchange block can perform the data exchange operation for an entire display area of the display panel. In case that the pixel arrangement option has a second value and the line data is even line data, the data exchange block can perform the data exchange operation for a first display area of the display panel and can not perform the data exchange operation for a second display area of the display panel.

[0009] In an embodiment, the first display area can be an RGBG area, and the second display area can be an RGB stripe area.

[0010] In an embodiment, the first display area can be a center area arranged at a center of the display panel, and the second display area can be a pixel on driver (POD) area arranged at both sides of the display panel.

[0011] In an embodiment, the first display area can be a center area arranged at a center of the display panel, and the second display area can include a pixel on driver (POD) area arranged at both sides of the display panel and a corner area arranged at four corners of the display panel.

[0012] In an embodiment, the data exchange operation can be an even line data exchange operation of exchanging odd numbered data voltages adjacent to each other in the even line data.

[0013] In an embodiment, the data exchange block can include a switch block arranged between the digital-to-analog conversion block and the output buffer block, and a switch control block connected to the switch block and the option storage block and configured to control the switch block based on the pixel arrangement option and whether the line data is odd line data or even line data.

[0014] In an embodiment, the digital-to-analog conversion block can include a plurality of digital-to-analog converters, the output buffer block can include a plurality of output buffers, and a plurality of even numbered digital-to-analog converters among the plurality of digital-to-analog converters can be directly coupled to a plurality of even numbered output buffers among the plurality of output buffers, respectively. The switch block can include a plurality of first switches configured to couple a plurality of odd numbered digital-to-analog converters among the plurality of digital-to-analog converters to a plurality of odd numbered output buffers among the plurality of output buffers, respectively, in response to a first switch signal, and a plurality of second switches configured to couple each of the plurality of odd numbered digital-to-analog converters to an odd numbered output buffer arranged adjacent to a column in which the each of the plurality of odd numbered digital-to-analog converters is arranged, in response to a second switch signal.

[0015] In an embodiment, in a case where the pixel arrangement option has a first value and the line data is odd line data, the switch control block can provide the first switch signal to all of the plurality of first switches corresponding to the entire display area of the display panel. In a case where the pixel arrangement option has the first value and the line data is even line data, the switch control block can provide the second switch signal to all of the plurality of second switches corresponding to the entire display area of the display panel.

[0016] In an embodiment, in a case where the pixel arrangement option has the second value and the line data is odd line data, the switch control block can provide the first switch signal to all of the plurality of first switches corresponding to the entire display area of the display panel. In a case where the pixel arrangement option has the second value and the line data is even line data, the switch control block can provide the second switch signal to a part of the plurality of second switches corresponding to the first display area of the display panel and can provide the first switch signal to a part of the plurality of first switches corresponding to the second display area of the display panel.

[0017] In an embodiment, the pixel arrangement option can have two or more bits to represent one of three or more pixel arrangement structures.

[0018] In an embodiment, the pixel arrangement option having the first value can represent that the entire display area of the display panel is RGBG region. The pixel arrangement option having the second value can represent that a first center region arranged at the center of the display panel is RGBG region, and a first POD region arranged at both sides of the display panel and corresponding to the first number of data channels is an RGB stripe region. The pixel arrangement option having the third value can represent that a second center region arranged at the center of the display panel is RGBG region, and a second POD region arranged at both sides of the display panel and corresponding to the second number of data channels is an RGB stripe region. The pixel arrangement option having the fourth value can represent that a third center region arranged at the center of the display panel is RGBG region, and a third POD region arranged at both sides of the display panel and a corner region arranged at four corners of the display panel are RGB stripe regions.

[0019] In an embodiment, the data driver can further include a shift register configured to sequentially generate a sampling signal, a sample latch block configured to sequentially store the line data in response to the sampling signal, and a hold latch block configured to receive the line data from the sample latch block in response to a load signal and provide the line data to the digital-to-analog conversion block.

[0020] According to an embodiment, there is provided a display apparatus including a display panel, a scan driver configured to provide a scan signal to the display panel, a data driver configured to provide a data voltage to the display panel, and a controller configured to control the scan driver and the data driver. The data driver includes a digital-to-analog conversion block configured to convert line data into the data voltage, an option storage block configured to store a pixel arrangement option representing a pixel arrangement structure of the display panel, a data exchange block connected to the digital-to-analog conversion block and the option storage block, and configured to selectively perform a data exchange operation of exchanging the data voltage based on the pixel arrangement option and whether the line data is odd line data or even line data, and an output buffer block connected to the data exchange block, and configured to output the data voltage on which the data exchange operation is selectively performed to a data line.

[0021] In an embodiment, in case that the pixel arrangement option has a first value and the line data is even line data, the data exchange block can perform the data exchange operation with respect to an entire display area of the display panel. In case that the pixel arrangement option has a second value and the line data is even line data, the data exchange block can perform the data exchange operation with respect to a first display area of the display panel and can not perform the data exchange operation with respect to a second display area of the display panel.

[0022] According to an embodiment, there is provided a display apparatus including a display panel including a first display area in which first pixels are arranged in a first pixel arrangement structure and a second display area in which second pixels are arranged in a second pixel arrangement structure different from the first pixel arrangement structure, a scan driver configured to provide a scan signal to the display panel, a data driver configured to provide a data voltage to the display panel, and a controller configured to control the scan driver and the data driver. The data driver performs a data exchange operation of exchanging the data voltage with respect to the first display area and does not perform the data exchange operation with respect to the second display area.

[0023] In an embodiment, the first display area can be an RGBG area, and the second display area can be an RGB stripe area.

[0024] In an embodiment, the first display area can be a center area arranged at a center of the display panel, and the second display area can be a pixel-on-driver (POD) area arranged at both sides of the display panel.

[0025] In an embodiment, the first display area can be a center area arranged at a center of the display panel, and the second display area can include a pixel-on-driver (POD) area arranged at both sides of the display panel and a corner area arranged at four corners of the display panel.

[0026] In an embodiment, the data exchange operation can be an even line data exchange operation of exchanging, among data voltages corresponding to the even line data, the data voltage at the (4N+1)th data lane with the data voltage at the (4N+3)th data lane with each other, where N is an integer greater than or equal to 0.

[0027] According to an embodiment, there is provided a data driver for providing data voltages to a display panel including a plurality of columns. The data driver includes: a digital-to-analog conversion block including a plurality of digital-to-analog converters each arranged in a column; an option storage block configured to store a pixel arrangement option representing a pixel arrangement structure of the display panel; a data exchange block connected to the digital-to-analog conversion block and the option storage block; and an output buffer block connected to the data exchange block and configured to output the data voltages, the output buffer block including a plurality of output buffers each arranged in a corresponding column. The data exchange block can include: a plurality of first switches connecting the plurality of digital-to-analog converters to the plurality of output buffers, respectively, each of the plurality of first switches connecting a digital-to-analog converter to an output buffer arranged in the same column; and a plurality of second switches connecting the plurality of digital-to-analog converters arranged in one of odd-numbered columns and even-numbered columns to the plurality of output buffers arranged in the one of odd-numbered columns and even-numbered columns, respectively, each of the plurality of second switches connecting a digital-to-analog converter located in one column to an output buffer arranged in a different column from the one column in which the digital-to-analog converter is arranged.

[0028] In an embodiment, each of the plurality of second switches can connect a digital-to-analog converter located in one even-numbered column to an output buffer arranged in another even-numbered column.

[0029] In an embodiment, each of the plurality of second switches can connect a digital-to-analog converter located in one even-numbered column to an output buffer arranged in an even-numbered column arranged adjacent to the one even-numbered column.

[0030] In an embodiment, each of the plurality of second switches can connect a digital-to-analog converter located in one odd-numbered column to an output buffer arranged in another odd-numbered column.

[0031] In an embodiment, each of the plurality of second switches can connect a digital-to-analog converter located in one odd-numbered column to an output buffer arranged in an odd-numbered column arranged adjacent to the one odd-numbered column.

[0032] As described above, in the data driver and display apparatus according to the embodiment, the option storage block can store a pixel arrangement option representing a pixel arrangement structure of the display panel, and the data exchange block can selectively perform the data exchange operation of exchanging the data voltages according to the pixel arrangement option. Accordingly, the data driver according to the embodiment can drive various display panels having different pixel arrangement structures, particularly, a hybrid display panel including both the RGBG pixel arrangement structure and the RGB stripe pixel arrangement structure.

[0033] Further, in the display apparatus according to the embodiment, the display panel can include a first display area in which first pixels are arranged in a first pixel arrangement structure (e.g., the RGBG pixel arrangement structure) and a second display area in which second pixels are arranged in a second pixel arrangement structure (e.g., the RGB stripe pixel arrangement structure), and the data driver can perform the data exchange operation of exchanging the data voltages for the first display area and can not perform the data exchange operation for the second display area. Accordingly, the data driver can drive a hybrid display panel including both the RGBG pixel arrangement structure and the RGB stripe pixel arrangement structure. BRIEF DESCRIPTION OF DRAWINGS

[0034] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and by reference to the drawings in which:

[0035] Figure 1 is a block diagram illustrating a data driver according to an embodiment.

[0036] Figure 2 is a diagram for describing an example of a pixel arrangement option according to an embodiment.

[0037] Figure 3 is a diagram illustrating an RGBG pixel arrangement structure in which pixels are arranged in the entire display area. is a diagram illustrating an example of an RGBG display panel.

[0038] Figure 4 is a diagram for describing an example of output image data of a data driver provided to drive Figure 3 an RGBG display panel.

[0039] Figure 5 is a diagram for describing an example of a data exchange operation performed by a data driver of an RGBG Figure 3 display panel.

[0040] Figure 6is a diagram illustrating an example of a hybrid display panel in which pixels are arranged in an RGBG pixel arrangement structure in a first display area and in an RGB stripe pixel arrangement structure in a second display area.

[0041] Figure 7 is a diagram for describing an example of output image data provided to a data driver of a hybrid display panel driving Figure 6 .

[0042] Figure 8 is a diagram for describing an example of a data exchange operation performed by a data driver of a hybrid display panel driving Figure 6 .

[0043] Figure 9 is a diagram for describing another example of a pixel arrangement option according to an embodiment.

[0044] Figure 10 is a diagram illustrating an example of a hybrid display panel in which pixels are arranged in an RGBG pixel arrangement structure in a center area and in an RGB stripe pixel arrangement structure in a pixel on driver (POD) area and a corner area.

[0045] Figure 11 is a diagram for describing an example of output image data provided to a data driver of a hybrid display panel driving Figure 10 .

[0046] Figure 12 is a diagram for describing yet another example of a pixel arrangement option according to an embodiment.

[0047] Figure 13 is a block diagram illustrating a display apparatus including a data driver according to an embodiment.

[0048] Figure 14 is a block diagram illustrating a display apparatus including a data driver according to an embodiment.

[0049] Figure 15 is a block diagram illustrating an electronic apparatus including a display apparatus according to an embodiment. DETAILED DESCRIPTION

[0050] Embodiments are described more fully below with reference to the accompanying drawings. Like or similar components have always been designated with the same reference numerals, and the description will not be repeated.

[0051] Figure 1 is a block diagram illustrating a data driver according to an embodiment.

[0052] Reference will now be made to Figure 1The data driver 100 according to the embodiment to provide data voltages (VD1, VD2, VD3, VD4, …, VD4N+1, VD4N+2, VD4N+3, VD4N+4, …) to the display panel can include a digital-to-analog conversion block 140, an option storage block 150, a data exchange block 160, and an output buffer block 190. In some embodiments, the data driver 100 can further include a shift register 110, a sample latch block 120, and a hold latch block 130.

[0053] The shift register 110 can sequentially generate a sample signal SAMS in response to a data clock signal DCLK. In some embodiments, the shift register 110 can include a plurality of serially connected flip-flops to sequentially generate the sample signal SAMS.

[0054] The sample latch block 120 can sequentially store output image data ODAT received from the controller or line data LDAT for each pixel line (or each pixel row) in response to the sample signal SAMS from the shift register 110. In some embodiments, the sample latch block 120 can include a plurality of sample latches that respectively sample pixel data included in the line data LDAT in response to the sample signal SAMS.

[0055] The hold latch block 130 can receive and store the line data LDAT received from the sample latch block 120 in response to a load signal LOAD received from the controller, and can provide the line data LDAT to the digital-to-analog conversion block 140. In some embodiments, the hold latch block 130 can include a plurality of hold latches that respectively correspond to the plurality of sample latches of the sample latch block 120.

[0056] The digital-to-analog conversion block 140 can convert the line data LDAT received from the hold latch block 130 into data voltages (VD1, VD2, VD3, VD4, …, VD4N+1, VD4N+2, VD4N+3, VD4N+4, …) as analog voltages. In some embodiments, as shown in FIG. 1B, the digital-to-analog conversion block 140 can include a plurality of digital-to-analog converters (DAC1, DAC2, DAC3, DAC4, …, DAC4N+1, DAC4N+2, DAC4N+3, DAC4N+4, …) that respectively correspond to the plurality of hold latches of the hold latch block 130. Figure 1

[0057] ​The output buffer block 190 can output the data voltages (VD1, VD2, VD3, VD4,..., VD4N+1, VD4N+2, VD4N+3, VD4N+4,...) converted by the digital-to-analog conversion block 140 to the data lines, respectively. In some embodiments, the output buffer block 190 can output the data voltages (VD1, VD2, VD3, VD4,..., VD4N+1, VD4N+2, VD4N+3, VD4N+4,...) on which a data swapping operation is selectively performed. In some embodiments, as shown in FIG. 1, the output buffer block 190 can include a plurality of output buffers (OB1, OB2, OB3, OB4,..., OB4N+1, OB4N+2, OB4N+3, OB4N+4,...) connected to a plurality of data channels (CH1, CH2, CH3, CH4,..., CH4N+1, CH4N+2, CH4N+3, CH4N+4,...) respectively. Figure 1

[0058] The option storage block 150 can store a pixel arrangement option PAO representing a pixel arrangement structure of a display panel driven by the data driver 100. In some embodiments, the pixel arrangement option PAO can be stored to the option storage block 150 when the display apparatus including the data driver 100 is manufactured. In this case, the option storage block 150 can be implemented with a non-volatile memory so as to retain the stored pixel arrangement option PAO even after the data driver 100 is not powered. In other embodiments, the option storage block 150 can be implemented with a volatile memory or a register, and the pixel arrangement option PAO can be stored in an external non-volatile memory arranged outside the data driver 100 at the time of manufacturing the display apparatus. The option storage block 150 can receive the pixel arrangement option PAO from the external non-volatile memory through a controller during power-on of the display apparatus, and store the pixel arrangement option PAO in the option storage block 150 included in the data driver 100.

[0059] The pixel arrangement option PAO can represent one of various pixel arrangement structures of a display panel. In some embodiments, as shown in FIG. 1, the pixel arrangement option PAO having a first value (e.g., "0") can represent that the entire display area of the display panel is arranged in a RGBG Figure 2 stripe pixel arrangement structure. The pixel arrangement option PAO having a second value (e.g., "1") can represent that a first area of the display panel is arranged in a RGBG stripe area and a second area of the display panel is arranged in a RGB stripe area in a RGB stripe pixel arrangement structure. In other embodiments, as shown in FIG. 1, the pixel arrangement option PAO having a first value (e.g., "0") can represent that the entire display area of the display panel is arranged in a RGBG stripe pixel arrangement structure. The pixel arrangement option PAO having a second value (e.g., "1") can represent that a first area of the display panel is arranged in a RGBG stripe area and a second area of the display panel is arranged in a RGB stripe area in a RGB stripe pixel arrangement structure. In other embodiments, as shown in FIG. 1, the pixel arrangement option PAO having a first value (e.g., "0") can represent that the entire display area of the display panel is arranged in a RGBG Figure 9 ​As shown, the pixel arrangement option PAO with a first value (e.g., "0") can represent the entire display area of ​​the display panel as RGBG. The pixel arrangement option PAO, which specifies the area and has a second value (e.g., "1"), can indicate that the central area of ​​the display panel is RGBG. The area and the area of ​​the driver on the display panel, the pixel (POD) area, the PODR (see Figure 10 The corner areas are RGB strip-shaped areas. In other embodiments, such as... Figure 12 As shown, the pixel arrangement option PAO can have two or more bits to represent one of three or more pixel arrangement structures. Although Figure 2 , Figure 9 and Figure 12 An example of the pixel arrangement option PAO is shown, but the pixel arrangement option PAO according to the embodiment is not limited to Figure 2 , Figure 9 and Figure 12 Examples.

[0060] The data exchange block 160 can selectively perform data exchange operations that exchange data voltages (VD1, VD2, VD3, VD4, ..., VD4N+1, VD4N+2, VD4N+3, VD4N+4, ...) based on whether the pixel arrangement option PAO and the line data LDAT are odd-numbered line data for odd-numbered pixel lines (or rows of odd-numbered pixels) of the display panel or even-numbered line data for even-numbered pixel lines (or rows of even-numbered pixels) of the display panel. In some embodiments, when the pixel arrangement option PAO has a first value (e.g., "0") and the line data LDAT is even-numbered line data, the data exchange block 160 can perform data exchange operations for the entire display area of ​​the display panel. Furthermore, when the pixel arrangement option PAO has a second value (e.g., "1") and the line data LDAT is even-numbered line data, the data exchange block 160 can perform data exchange operations for a first display area of ​​the display panel and may not perform data exchange operations for a second display area of ​​the display panel. For example, the first display area may be RGBG. The second display area can be an RGB strip area. The data exchange block 160 can be configured for RGBG... The area performs a data exchange operation and can not perform a data exchange operation for an RGB stripe area. Further, in some embodiments, the data exchange operation can be an even line data exchange operation (or even line RB data exchange operation) that exchanges data voltages of an (4N+1)th data channel (CH1, CH5, …, CH4N+1, …) among data voltages (VD1, VD2, VD3, VD4, …, VD4N+1, VD4N+2, VD4N+3, VD4N+4, …) corresponding to even line data and data voltages of an (4N+3)th data channel (CH3, CH7, …, CH4N+3, …), where N is an integer greater than or equal to 0.

[0061] To perform these operations, the data exchange block 160 can include a switch control block 170 that generates first and second switch signals SWS1 and SWS2 based on the pixel arrangement option PAO stored in the option storage block 150 and / or whether the line data LDAT is odd line data or even line data, and a switch block 180 that operates in response to the first and second switch signals SWS1 and SWS2.

[0062] The switch block 180 can be disposed between the digital-to-analog conversion block 140 and the output buffer block 190. In some embodiments, as Figure 1As shown in the middle, the digital-to-analog conversion block 140 can include a plurality of digital-to-analog converters (DAC1, DAC2, DAC3, DAC4, …, DAC4N+1, DAC4N+2, DAC4N+3, DAC4N+4, …), and the output buffer block 190 can include a plurality of output buffers (OB1, OB2, OB3, OB4, …, OB4N+1, OB4N+2, OB4N+3, OB4N+4, …). The even-numbered digital-to-analog converters (DAC2, DAC4, …, DAC4N+2, DAC4N+4, …) can be directly coupled to the even-numbered output buffers (OB2, OB4, …, OB4N+2, OB4N+4, …) at the even-numbered data channels (CH2, CH4, …, CH4N+2, CH4N+4, …), respectively, where N is an integer greater than or equal to 0. In addition, the switch block 180 can include a plurality of first switches SW1 and a plurality of second switches SW2, the plurality of first switches SW1 coupling the odd-numbered digital-to-analog converters (DAC1, DAC3, …, DAC4N+1, DAC4N+3, …) to the odd-numbered output buffers (OB1, OB3, …, OB4N+1, OB4N+3, …) at the odd-numbered data channels (CH1, CH3, …, CH4N+1, CH4N+3, …), respectively, in response to a first switch signal SWS1, and the plurality of second switches SW2 coupling the (4N+1)th digital-to-analog converters (DAC1, …, DAC4N+1, …) to the (4N+3)th output buffers (OB3, …, OB4N+3, …) and the (4N+3)th digital-to-analog converters (DAC3, …, DAC4N+3, …) to the (4N+1)th output buffers (OB1, …, OB4N+1, …), respectively, in response to a second switch signal SWS2. Thus, in the case where the first switch signal SWS1 is applied to the switch block 180, the odd-numbered digital-to-analog converters (DAC1, DAC3, …, DAC4N+1, DAC4N+3, …) can be coupled to the odd-numbered output buffers (OB1, OB3, …, OB4N+1, OB4N+3, …) at the odd-numbered data channels (CH1, CH3, …, CH4N+1, CH4N+3, …), respectively.Further, in a case where the second switch signal SWS2 is applied to the switch block 180, the (4N+1)th digital-to-analog converter (DAC1, …, DAC4N+1, …) at the (4N+1)th data channel (CH1, …, CH4N+1, …) can be respectively coupled to the (4N+3)th output buffer (OB3, …, OB4N+3, …) at the (4N+3)th data channel (CH3, …, CH4N+3, …), and the (4N+3)th digital-to-analog converter (DAC3, …, DAC4N+3, …) at the (4N+3)th data channel (CH3, …, CH4N+3, …) can be respectively coupled to the (4N+1)th output buffer (OB1, …, OB4N+1, …) at the (4N+1)th data channel (CH1, …, CH4N+1, …), respectively.

[0063] The switch control block 170 can control the switch block 180 based on the pixel arrangement option PAO stored in the option storage block 150 and / or whether the line data LDAT is odd line data or even line data. The switch control block 170 can output one of the first switch signal SWS1 and the second switch signal SWS2 to the switch block 180.

[0064] In some embodiments, in a case where the pixel arrangement option PAO has a first value (e.g., "0") and the line data LDAT is odd line data, the switch control block 170 can provide the first switch signal SWS1 to all of the first switches SW1 corresponding to the entire display area of the display panel, and in a case where the pixel arrangement option PAO has the first value (e.g., "0") and the line data LDAT is even line data, the switch control block 170 can provide the second switch signal SWS2 to all of the second switches SW2 corresponding to the entire display area of the display panel. For example, the pixel arrangement option PAO having the first value (e.g., "0") can indicate that the entire display area is RGBG area or the display panel is RGBG , and the switch control block 170 can provide the first switch signal SWS1 to all of the first switches SW1 while receiving odd line data for the RGBG display panel, and the switch control block 170 can provide the second switch signal SWS2 to all of the second switches SW2 while receiving even line data for the RGBG display panel. Accordingly, in receiving odd line data for the RGBG While displaying odd-numbered line data from the display panel, odd-numbered digital-to-analog converters (DAC1, DAC3, ..., DAC4N+1, DAC4N+3, ...) can be connected to odd-numbered output buffers (OB1, OB3, ..., OB4N+1, OB4N+3, ...) respectively via the first switch SW1. This allows them to output odd-numbered data voltages (VD1, VD3, ..., VD4N+1, VD4N+3, ...) at the odd-numbered data channels (CH1, CH3, ..., CH4N+1, CH4N+3, ...), without performing line data exchange operations. Furthermore, when receiving data for RGBG... Simultaneously with displaying the even-numbered lines of data on the display panel, the (4N+1)th digital-to-analog converter (DAC1, ..., DAC4N+1, ...) can be connected to the (4N+3)th output buffer (OB3, ..., OB4N+3, ...), and the (4N+3)th digital-to-analog converter (DAC3, ..., DAC4N+3, ...) can be connected to the (4N+1)th output buffer (OB1, ..., OB4N+1, ...), and the (4N+3)th data channel (CH3, ..., CH4N+3, ...) is connected to the... The (4N+3) data voltages (VD3, ..., VD4N+3, ...) can be output to the (4N+1)th data channel (CH1, ..., CH4N+1, ...), and the (4N+1)th data voltage (VD1, ..., VD4N+1, ...) at the (4N+1)th data channel (CH1, ..., CH4N+1, ...) can be output to the (4N+3)th data channel (CH3, ..., CH4N+3, ...), and data exchange operations (or even-numbered line data exchange operations) can be performed. That is, in an RGBG display panel... In the case of a display panel, the data driver 100 according to the embodiment can perform an even-line data exchange operation relative to the entire display area (or relative to the data voltage for the entire display area).

[0065] When the pixel arrangement option PAO has a second value (e.g., "1") and the line data LDAT is an odd number of line data, the switch control block 170 can provide a first switch signal SWS1 to all the first switches SW1 corresponding to the entire display area of ​​the display panel. Furthermore, when the pixel arrangement option PAO has a second value (e.g., "1") and the line data LDAT is an even number of line data, the switch control block 170 can provide a first switch signal SWS1 to all the first switches SW1 corresponding to the entire display area of ​​the display panel (e.g., RGBG). The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG The switch control block 170 can provide the second switch signal SWS2 to a portion of the second switches SW2 corresponding to the second display area (e.g., the RGB stripe area) of the display panel, and can provide the first switch signal SWS1 to a portion of the first switches SW1 corresponding to the first display area (e.g., the RGBG

[0066] Conventional data drivers may have configurations and operations suitable for a specific display panel, but cannot drive display panels different from the corresponding display panel. However, the data driver 100 according to an embodiment can store pixel arrangement options (PAOs) representing one of the different pixel arrangement structures of various display panels, and can drive various display panels with different pixel arrangement structures by selectively performing even-number line data exchange operations according to the pixel arrangement options (PAOs). In particular, conventional data drivers cannot drive display panels including RGBG... A hybrid display panel combining both RGB area and RGB strip area features, or a hybrid display panel that provides compatibility with RGBG... The data voltage of the display panel. Correspondingly, in a hybrid display panel driven by a conventional data driver, in RGBG... Color differences and / or brightness differences may occur between the regions and the RGB bar regions. However, the data driver 100 according to the embodiment can be relative to RGBG. The region performs even-number line data exchange operations and may not perform even-number line data exchange operations relative to the RGB bar region. Accordingly, the data driver 100 according to the embodiment can provide a data voltage suitable for the hybrid display panel and can normally drive the RGBG region. A display panel that combines both area and RGB strip area displays.

[0067] Figure 2 This is a diagram used to illustrate an example of pixel arrangement options according to an embodiment. Figure 3 It shows the pixels in RGBG format across the entire display area. RGBG arranged by pixel arrangement structure An example image of the display panel. Figure 4 It is used to describe what is provided to the driver Figure 3 RGBG A diagram showing an example of the output image data from the display panel's data driver. Figure 5 It is used to describe the driver Figure 3 RGBG A diagram illustrating an example of data exchange operations performed by the display panel's data driver. Figure 6 It shows the pixels in the first display area in RGBG. An example diagram of a hybrid display panel in which pixels are arranged in a pixel arrangement structure and in an RGB strip pixel arrangement structure in the second display area. Figure 7 It is used to describe what is provided to the driver Figure 6 An example diagram of the output image data of the data driver of the hybrid display panel, and Figure 8 It is used to describe the driver Figure 6 A diagram illustrating an example of data exchange operations performed by the data driver of a hybrid display panel.

[0068] Reference Figure 1 and Figure 2 According to the embodiment, the pixel arrangement option PAO stored in the option storage block 150 of the data driver 100 can represent the entire display area of ​​the display panel as RGBG. The area, or the first display area of ​​the display panel, is RGBG. The second display area of ​​the display panel is an RGB strip area.

[0069] The pixel arrangement option PAO, with a first value (e.g., "0"), can represent the entire display area of ​​the display panel as RGBG. Area, or indicating the display panel as such Figure 3 The RGBG shown Display panel 200. In RGBG In display panel 200, pixels RP, GP, and BP can support RGBG. Arranged by pixel arrangement structure. For example, such as Figure 3 As shown, red pixel RP, green pixel GP, blue pixel BP, and green pixel GP can be arranged repeatedly in RGBG. In the odd-numbered pixel lines LINE1, LINE3, ... (or odd-numbered pixel rows) of the display panel 200, the blue pixel BP, green pixel GP, red pixel RP, and green pixel GP can be repeatedly arranged in RGBG. In the even-numbered pixel lines LINE2, LINE4, ... (or even-numbered pixel rows) of the display panel 200.

[0070] Drive RGBG The data driver 100 of the display panel 200 can receive data from the controller of the display device including the data driver 100. Figure 4 The output image data ODAT is shown in the image. (As shown in the image data ODAT) Figure 4 As shown, the frame period FP defined by the vertical synchronization signal VSYNC can include multiple horizontal time periods HT defined by the horizontal synchronization signal HSYNC. For example, the number of multiple horizontal time periods HT included in a frame period FP can be substantially the same as that of RGBG. The number of pixel lines LINE1, LINE2, LINE3, LINE4, … (or pixel rows) of the display panel 200 is the same. The data driver 100 can receive line data LDAT for the corresponding pixel lines LINE1, LINE2, LINE3, LINE4, … from the controller as output image data ODAT in each horizontal time period HT. The line data LDAT can include pixel data RGD, GPD, and BPD for the pixels RP, GP, and BP included in the corresponding pixel lines LINE1, LINE2, LINE3, LINE4, …. As Figure 4 shown in FIG. 2B, in the line data LDAT for the RGBG In the line data LDAT for each pixel line LINE1, LINE2, LINE3, LINE4, … of the display panel 200, the red pixel data RPD for the red pixels RP, the green pixel data GPD for the green pixels GP, the blue pixel data BPD for the blue pixels BP, and the green pixel data GPD for the green pixels GP can be repeated.

[0071] In Figure 5 , to describe the data exchange operation (e.g., the even line data exchange operation or the even line RB data exchange operation) performed by the data driver 100 of the display panel 200, Tables 220 and 240 are shown, Table 220 is used to describe the operation of the data driver 100 when receiving the odd line data ODD LDAT for the RGBG The operation of the data driver 100 when receiving the even line data EVEN LDAT for each even pixel line LINE2, LINE4, … of the display panel 200 is described in Table 240.

[0072] As Figure 5 ​​As shown in Table 220, when the data driver 100 receives the odd line data ODD LDAT, the plurality of digital-to-analog converters (DAC1, DAC2, DAC3, DAC4, …, DAC4N+1, DAC4N+2, DAC4N+3, DAC4N+4, …) at the plurality of data channels (CH1, CH2, CH3, CH4, …, CH4N+1, CH4N+2, CH4N+3, CH4N+4, …) can respectively convert the plurality of pixel data (RPD1, GPD2, BPD3, GPD4, …, RPD4N+1, GPD4N+2, BPD4N+3, GPD4N+4, …) of the odd line data ODD LDAT into a plurality of data voltages (RVD1, GVD2, BVD3, GVD4, …, RVD4N+1, GVD4N+2, BVD4N+3, GVD4N+4, …). Thus, as shown in Table 220, the data voltages VD@140 output at the digital-to-analog conversion block 140 can include a first red data voltage RVD1 corresponding to the first red pixel data RPD1 at the first channel CH1, a second green data voltage GVD2 corresponding to the second green pixel data GPD2 at the second channel CH2, a third blue data voltage BVD3 corresponding to the third blue pixel data BPD3 at the third channel CH3, a fourth green data voltage GVD4 corresponding to the fourth green pixel data GPD4 at the fourth channel CH4, …, a (4N+1)th red data voltage RVD4N+1 corresponding to the (4N+1)th red pixel data RPD4N+1 at the (4N+1)th channel CH4N+1, a (4N+2)th green data voltage GVD4N+2 corresponding to the green pixel data GPD4N+2 at the (4N+2)th channel CH4N+2, a (4N+3)th blue data voltage BVD4N+3 corresponding to the (4N+3)th blue pixel data BPD4N+3 at the (4N+3)th channel CH4N+3, a (4N+4)th green data voltage GVD4N+4 corresponding to the (4N+4)th green pixel data GPD4N+4 at the (4N+4)th channel CH4N+4, …. Figure 5 As shown in Table 220, the data voltages VD@140 output at the digital-to-analog conversion block 140 can include a first red data voltage RVD1 corresponding to the first red pixel data RPD1 at the first channel CH1, a second green data voltage GVD2 corresponding to the second green pixel data GPD2 at the second channel CH2, a third blue data voltage BVD3 corresponding to the third blue pixel data BPD3 at the third channel CH3, a fourth green data voltage GVD4 corresponding to the fourth green pixel data GPD4 at the fourth channel CH4, …, a (4N+1)th red data voltage RVD4N+1 corresponding to the (4N+1)th red pixel data RPD4N+1 at the (4N+1)th channel CH4N+1, a (4N+2)th green data voltage GVD4N+2 corresponding to the green pixel data GPD4N+2 at the (4N+2)th channel CH4N+2, a (4N+3)th blue data voltage BVD4N+3 corresponding to the (4N+3)th blue pixel data BPD4N+3 at the (4N+3)th channel CH4N+3, a (4N+4)th green data voltage GVD4N+4 corresponding to the (4N+4)th green pixel data GPD4N+4 at the (4N+4)th channel CH4N+4, …. The entire display area of the display panel 200 does not perform the data exchange operation. For example, the switch control block 170 can output the data voltages VD@170 to the data lines DL1, DL2, DL3, DL4, …, DL4N+1, DL4N+2, DL4N+3, DL4N+4, … in the order of RGBG All the first switches SW1 corresponding to the entire display area of the display panel 200 are provided with the first switch signal SWS1, and the switch block 180 can couple the (4N+1)th digital-to-analog converter and the (4N+3)th digital-to-analog converter (DAC1, DAC3, …, DAC4N+1, DAC4N+3, …) to the (4N+1)th output buffer and the (4N+3)th output buffer (OB1, OB3, …, OB4N+1, OB4N+3, …) respectively. Correspondingly, a plurality of data voltages (RVD1, GVD2, BVD3, GVD4, …, RVD4N+1, GVD4N+2, BVD4N+3, GVD4N+4, …) can be respectively output at a plurality of data channels (CH1, CH2, CH3, CH4, …, CH4N+1, CH4N+2, CH4N+3, CH4N+4, …). Therefore, as shown in Table 220, Figure 5 As shown in Table 220, the data voltages VD@140 output at the digital-to-analog conversion block 140 and the data voltages VD@190 output at the output buffer block 190 can include the same data voltages, i.e., the first red data voltage RVD1 at the first channel CH1, the second green data voltage GVD2 at the second channel CH2, the third blue data voltage BVD3 at the third channel CH3, the fourth green data voltage GVD4 at the fourth channel CH4, …, the (4N+1)th red data voltage RVD4N+1 at the (4N+1)th channel CH4N+1, the (4N+2)th green data voltage GVD4N+2 at the (4N+2)th channel CH4N+2, the (4N+3)th blue data voltage BVD4N+3 at the (4N+3)th channel CH4N+3, the (4N+4)th green data voltage GVD4N+4 at the (4N+4)th channel CH4N+4, ….

[0073] As shown in Table 240, when the data driver 100 receives the even line data EVEN LDAT, the plurality of digital-to-analog converters (DAC1, DAC2, DAC3, DAC4, …, DAC4N+1, DAC4N+2, DAC4N+3, DAC4N+4, …) at the plurality of data channels (CH1, CH2, CH3, CH4, …, CH4N+1, CH4N+2, CH4N+3, CH4N+4, …) can respectively convert a plurality of pixel data (RPD1, GPD2, BPD3, GPD4, …, RPD4N+1, GPD4N+2, BPD4N+3, GPD4N+4, …) of the even line data EVEN LDAT into a plurality of data voltages (RVD1, GVD2, BVD3, GVD4, …, RVD4N+1, GVD4N+2, BVD4N+3, GVD4N+4, …). Therefore, as shown in Table 240, the data voltages VD@140 output at the digital-to-analog conversion block 140 and the data voltages VD@190 output at the output buffer block 190 can include the same data voltages, i.e., the first red data voltage RVD1 at the first channel CH1, the second green data voltage GVD2 at the second channel CH2, the third blue data voltage BVD3 at the third channel CH3, the fourth green data voltage GVD4 at the fourth channel CH4, …, the (4N+1)th red data voltage RVD4N+1 at the (4N+1)th channel CH4N+1, the (4N+2)th green data voltage GVD4N+2 at the (4N+2)th channel CH4N+2, the (4N+3)th blue data voltage BVD4N+3 at the (4N+3)th channel CH4N+3, the (4N+4)th green data voltage GVD4N+4 at the (4N+4)th channel CH4N+4, …. Figure 5 As shown in Table 240, when the data driver 100 receives the even line data EVEN LDAT, the plurality of digital-to-analog converters (DAC1, DAC2, DAC3, DAC4, …, DAC4N+1, DAC4N+2, DAC4N+3, DAC4N+4, …) at the plurality of data channels (CH1, CH2, CH3, CH4, …, CH4N+1, CH4N+2, CH4N+3, CH4N+4, …) can respectively convert a plurality of pixel data (RPD1, GPD2, BPD3, GPD4, …, RPD4N+1, GPD4N+2, BPD4N+3, GPD4N+4, …) of the even line data EVEN LDAT into a plurality of data voltages (RVD1, GVD2, BVD3, GVD4, …, RVD4N+1, GVD4N+2, BVD4N+3, GVD4N+4, …). Therefore, as shown in Table 240, the data voltages VD@140 output at the digital-to-analog conversion block 140 and the data voltages VD@190 output at the output buffer block 190 can include the same data voltages, i.e., the first red data voltage RVD1 at the first channel CH1, the second green data voltage GVD2 at the second channel CH2, the third blue data voltage BVD3 at the third channel CH3, the fourth green data voltage GVD4 at the fourth channel CH4, …, the (4N+1)th red data voltage RVD4N+1 at the (4N+1)th channel CH4N+1, the (4N+2)th green data voltage GVD4N+2 at the (4N+2)th channel CH4N+2, the (4N+3)th blue data voltage BVD4N+3 at the (4N+3)th channel CH4N+3, the (4N+4)th green data voltage GVD4N+4 at the (4N+4)th channel CH4N+4, ….Figure 5 As shown in Table 240, the data voltage VD@140 output at the digital-to-analog conversion block 140 can include a first red data voltage RVD1 corresponding to the first red pixel data RPD1 at the first channel CH1, a second green data voltage GVD2 corresponding to the second green pixel data GPD2 at the second channel CH2, a third blue data voltage BVD3 corresponding to the third blue pixel data BPD3 at the third channel CH3, a fourth green data voltage GVD4 corresponding to the fourth green pixel data GPD4 at the fourth channel CH4, …, a (4N+1)th red data voltage RVD4N+1 corresponding to the (4N+1)th red pixel data RPD4N+1 at the (4N+1)th channel CH4N+1, a (4N+2)th green data voltage GVD4N+2 corresponding to the (4N+2)th green pixel data GPD4N+2 at the (4N+2)th channel CH4N+2, a (4N+3)th blue data voltage BVD4N+3 corresponding to the (4N+3)th blue pixel data BPD4N+3 at the (4N+3)th channel CH4N+3, a (4N+4)th green data voltage GVD4N+4 corresponding to the (4N+4)th green pixel data GPD4N+4 at the (4N+4)th channel CH4N+4, …, with respect to the RGBG The data exchange operation is performed on the entire display area of the display panel 200. For example, the switch control block 170 can provide the second switch signal SWS2 to all the second switches SW2 corresponding to the entire display area of the display panel 200, and the switch block 180 can couple the (4N+1)th digital-to-analog converter (DAC1, …, DAC4N+1, …) to the (4N+3)th output buffer (OB3, …, OB4N+3, …) respectively, and couple the (4N+3)th digital-to-analog converter (DAC3, …, DAC4N+3, …) to the (4N+1)th output buffer (OB1, …, OB4N+1, …) respectively. Accordingly, the data voltage BVD3, …, BVD4N+3, … at the (4N+3)th data channel (CH3, …, CH4N+3, …) can be output at the (4N+1)th data channel (CH1, …, CH4N+1, …) respectively, and the data voltage RVD1, …, RVD4N+1, … at the (4N+1)th data channel (CH1, …, CH4N+1, …) can be output at the (4N+3)th data channel (CH3, …, CH4N+3, …) respectively. Thus, as shown in Table 240, the data voltage VD@140 output at the digital-to-analog conversion block 140 can include a first red data voltage RVD1 corresponding to the first red pixel data RPD1 at the first channel CH1, a second green data voltage GVD2 corresponding to the second green pixel data GPD2 at the second channel CH2, a third blue data voltage BVD3 corresponding to the third blue pixel data BPD3 at the third channel CH3, a fourth green data voltage GVD4 corresponding to the fourth green pixel data GPD4 at the fourth channel CH4, …, a (4N+1)th red data voltage RVD4N+1 corresponding to the (4N+1)th red pixel data RPD4N+1 at the (4N+1)th channel CH4N+1, a (4N+2)th green data voltage GVD4N+2 corresponding to the (4N+2)th green pixel data GPD4N+2 at the (4N+2)th channel CH4N+2, a (4N+3)th blue data voltage BVD4N+3 corresponding to the (4N+3)th blue pixel data BPD4N+3 at the (4N+3)th channel CH4N+3, a (4N+4)th green data voltage GVD4N+4 corresponding to the (4N+4)th green pixel data GPD4N+4 at the (4N+4)th channel CH4N+4, …, with respect to the RGBG Figure 5 ​As shown in Table 240, unlike the data voltages VD@140 output at the digital-to-analog conversion block 140, the data voltages VD@190 output at the output buffer block 190 can include a third blue data voltage BVD3 at the first channel CH1, a second green data voltage GVD2 at the second channel CH2, a first red data voltage RVD1 at the third channel CH3, a fourth green data voltage GVD4 at the fourth channel CH4, a (4N+3)th blue data voltage BVD4N+3 at the (4N+1)th channel CH4N+1, a (4N+2)th green data voltage GVD4N+2 at the (4N+2)th channel CH4N+2, a (4N+1)th red data voltage RVD4N+1 at the (4N+3)th channel CH4N+3, a (4N+4)th green data voltage GVD4N+4 at the (4N+4)th channel CH4N+4, and so on.

[0074] Therefore, the driving RGBG The data driver 100 of the display panel 200 can store the pixel arrangement option PAO having the first value (e.g., "0"), and can arrange the pixels RP, GP, and BP in the RGBG The data driver 100 of the display panel 200 can store the pixel arrangement option PAO having the first value (e.g., "0"), and can arrange the pixels RP, GP, and BP in the RGBG

[0075] The pixel arrangement option PAO having the second value (e.g., "1") can indicate that the first display region of the display panel is RGBG The region and the second display region of the display panel is a RGB stripe region, and indicates that the display panel is a hybrid display panel 300 as shown in Figure 6 The first display region DR1 of the hybrid display panel 300 can be a RGBG Figure 6 The region, and the second display region DR2 of the hybrid display panel 300 can be a RGB stripe region in which the pixels RP, GP, and BP are arranged in a RGB stripe pixel arrangement structure. For example, as shown in The first display region DR1 of the hybrid display panel 300 can be a RGBG The region, and the second display region DR2 of the hybrid display panel 300 can be a RGB stripe region in which the pixels RP, GP, and BP are arranged in a RGB stripe pixel arrangement structure. For example, as shown in Figure 6As illustrated in FIG. 1, in the first display area DR1 of the hybrid display panel 300, red pixels RP, green pixels GP, blue pixels BP, and green pixels GP can be repeatedly arranged in odd pixel lines LINE1, LINE3, … (or odd pixel lines), and blue pixels BP, green pixels GP, red pixels RP, and green pixels GP can be repeatedly arranged in even pixel lines LINE2, LINE4, …. Also, in the second display area DR2 of the hybrid display panel 300, red pixels RP, green pixels GP, and blue pixels BP can be repeatedly arranged in each pixel line LINE1, LINE2, LINE3, LINE4, ….

[0076] In some embodiments, the first display area DR1 of the hybrid display panel 300 can be a center area arranged at the center of the hybrid display panel 300, and the second display area DR2 of the hybrid display panel 300 can be a pixel on driver (POD) area arranged at both sides of the hybrid display panel 300. Here, the POD area can be an area in which a driver (e.g., a scan driver) is formed together with the pixels RP, GP, and BP.

[0077] The data driver 100 driving the hybrid display panel 300 can receive output image data ODAT illustrated in FIG. 1 from a controller of a display apparatus including the data driver 100. Figure 7 As illustrated in FIG. 1, the data driver 100 can receive line data LDAT for a corresponding pixel line LINE1, LINE2, LINE3, LINE4, … from the controller as the output image data ODAT in each horizontal time period HT. The line data LDAT can sequentially include RGB data for an RGB stripe area arranged on one side of an RGBG Figure 7 As illustrated in FIG. 1, the data driver 100 can receive line data LDAT for a corresponding pixel line LINE1, LINE2, LINE3, LINE4, … from the controller as the output image data ODAT in each horizontal time period HT. The line data LDAT can sequentially include RGB data for an RGB stripe area arranged on one side of an RGBG As illustrated in FIG. 1, the data driver 100 can receive line data LDAT for a corresponding pixel line LINE1, LINE2, LINE3, LINE4, … from the controller as the output image data ODAT in each horizontal time period HT. The line data LDAT can sequentially include RGB data for an RGB stripe area arranged on one side of an RGBG As illustrated in FIG. 1, the data driver 100 can receive line data LDAT for a corresponding pixel line LINE1, LINE2, LINE3, LINE4, … from the controller as the output image data ODAT in each horizontal time period HT. The line data LDAT can sequentially include RGB data for an RGB stripe area arranged on one side of an RGBG As illustrated in FIG. 1, the data driver 100 can receive line data LDAT for a corresponding pixel line LINE1, LINE2, LINE3, LINE4, … from the controller as the output image data ODAT in each horizontal time period HT. The line data LDAT can sequentially include RGB data for an RGB stripe area arranged on one side of an RGBG As illustrated in FIG. 1, the data driver 100 can receive line data LDAT for a corresponding pixel line LINE1, LINE2, LINE3, LINE4, … from the controller as the output image data ODAT in each horizontal time period HT. The line data LDAT can sequentially include RGB data for an RGB stripe area arranged on one side of an RGBG

[0078] In Figure 8In the middle, in order to describe an example of a data exchange operation performed by the data driver 100 that drives the hybrid display panel 300, Table 320 for describing an operation of the data driver 100 when receiving odd line data ODD LDAT for each odd pixel line LINE1, LINE3, … of the hybrid display panel 300 and Table 340 for describing an operation of the data driver 100 when receiving even line data EVEN LDAT for each even pixel line LINE2, LINE4, … of the hybrid display panel 300 are shown.

[0079] As Figure 8 As shown in Table 320, when the data driver 100 receives the odd line data ODD LDAT, the digital-to-analog conversion block 140 can convert a plurality of pixel data (RPD1, GPD2, BPD3, RPD4, …, RPDK+1, GPDK+2, BPDK+3, GPDK+4, …, RPDL+1, GPDL+2, BPDL+3, RPDL+4, …) of the odd line data ODD LDAT into a plurality of data voltages (RVD1, GVD2, BVD3, RVD4, …, RVDK+1, GVDK+2, BVDK+3, GVDK+4, …, RVDL+1, GVDL+2, BVDL+3, RVDL+4, …) at a plurality of data channels (CH1, CH2, CH3, CH4, …, CHK+1, CHK+2, CHK+3, CHK+4, …, CHL+1, CHL+2, CHL+3, CHL+4, …), respectively. Accordingly, as Figure 8As shown in Table 320, the data voltage VD@140 output at the digital-to-analog conversion block 140 can include a first red data voltage RVD1 corresponding to a first red pixel data RPD1 at a first channel CH1 for the second display area DR2, a second green data voltage GVD2 corresponding to a second green pixel data GPD2 at a second channel CH2 for the second display area DR2, a third blue data voltage BVD3 corresponding to a third blue pixel data BPD3 at a third channel CH3 for the second display area DR2, a fourth red data voltage RVD4 corresponding to a fourth red pixel data RPD4 at a fourth channel CH4 for the second display area DR2, …, an (K+1)th red data voltage RVDK+1 corresponding to an (K+1)th red pixel data RPDK+1 at an (K+1)th channel CHK+1 for the first display area DR1, an (K+2)th green data voltage GVDK+2 corresponding to an (K+2)th green pixel data GPDK+2 at an (K+2)th channel CHK+2 for the first display area DR1, an (K+3)th blue data voltage BVDK+3 corresponding to an (K+3)th blue pixel data BPDK+3 at an (K+3)th channel CHK+3 for the first display area DR1, an (K+4)th green data voltage GVDK+4 corresponding to an (K+4)th green pixel data GPDK+4 at an (K+4)th channel CHK+4 for the first display area DR1, …, an (L+1)th red data voltage RVDL+1 corresponding to an (L+1)th red pixel data RPDL+1 at an (L+1)th channel CHL+1 for the second display area DR2, an (L+2)th green data voltage GVDL+2 corresponding to an (L+2)th green pixel data GPDL+2 at an (L+2)th channel CHL+2 for the second display area DR2, an (L+3)th blue data voltage BVDL+3 corresponding to an (L+3)th blue pixel data BPDL+3 at an (L+3)th channel CHL+3 for the second display area DR2, an (L+4)th red data voltage RVDL+4 corresponding to an (L+4)th red pixel data RPDL+4 at an (L+4)th channel CHL+4 for the second display area DR2, …, as shown in Table 320. The data exchange block 160 can not perform the data exchange operation with respect to the entire display area of the hybrid display panel 300, or the first display area DR1 and the second display area DR2.For example, the switch control block 170 can provide the first switch signal SWS1 to all the first switches SW1 corresponding to the entire display area of the hybrid display panel 300, and the switch block 180 can couple the (4N+1)th digital-to-analog converter and the (4N+3)th digital-to-analog converter (DAC1, DAC3, …, DAC4N+1, DAC4N+3, …) to the (4N+1)th output buffer and the (4N+3)th output buffer (OB1, OB3, …, OB4N+1, OB4N+3, …), respectively. Accordingly, a plurality of data voltages (RVD1, GVD2, BVD3, RVD4, …, RVDK+1, GVDK+2, BVDK+3, GVDK+4, …, RVDL+1, GVDL+2, BVDL+3, RVDL+4, …) can be output at a plurality of data channels (CH1, CH2, CH3, CH4, …, CHK+1, CHK+2, CHK+3, CHK+4, …, CHL+1, CHL+2, CHL+3, CHL+4, …), respectively. Thus, as. Figure 8 As shown in Table 320, the data voltages VD@140 output at the digital-to-analog conversion block 140 and the data voltages VD@190 output at the output buffer block 190 can include the same data voltages, i.e., a first red data voltage RVD1 at a first channel CH1 for a second display area DR2, a second green data voltage GVD2 at a second channel CH2 for the second display area DR2, a third blue data voltage BVD3 at a third channel CH3 for the second display area DR2, a fourth red data voltage RVD4 at a fourth channel CH4 for the second display area DR2, …, a (K+1)th red data voltage RVDK+1 at a (K+1)th channel CHK+1 for a first display area DR1, a (K+2)th green data voltage GVDK+2 at a (K+2)th channel CHK+2 for the first display area DR1, a (K+3)th blue data voltage BVDK+3 at a (K+3)th channel CHK+3 for the first display area DR1, a (K+4)th green data voltage GVDK+4 at a (K+4)th channel CHK+4 for the first display area DR1, …, a (L+1)th red data voltage RVDL+1 at a (L+1)th channel CHL+1 for the second display area DR2, a (L+2)th green data voltage GVDL+2 at a (L+2)th channel CHL+2 for the second display area DR2, a (L+3)th blue data voltage BVDL+3 at a (L+3)th channel CHL+3 for the second display area DR2, a (L+4)th red data voltage RVDL+4 at a (L+4)th channel CHL+4 for the second display area DR2, ….

[0080] As Figure 8 As shown in Table 340, when the data driver 100 receives the even line data EVEN LDAT, the digital-to-analog conversion block 140 can convert a plurality of pixel data (RPD1, GPD2, BPD3, RPD4, …, RPDK+1, GPDK+2, BPDK+3, GPDK+4, …, RPDL+1, GPDL+2, BPDL+3, RPDL+4, …) of the even line data EVEN LDAT into a plurality of data voltages (RVD1, GVD2, BVD3, RVD4, …, RVDK+1, GVDK+2, BVDK+3, GVDK+4, …, RVDL+1, GVDL+2, BVDL+3, RVDL+4, …) at a plurality of data channels (CH1, CH2, CH3, CH4, …, CHK+1, CHK+2, CHK+3, CHK+4, …, CHL+1, CHL+2, CHL+3, CHL+4, …), respectively. Accordingly, as shown in Table 340, the data driver 100 can output the plurality of data voltages (RVD1, GVD2, BVD3, RVD4, …, RVDK+1, GVDK+2, BVDK+3, GVDK+4, …, RVDL+1, GVDL+2, BVDL+3, RVDL+4, …) to the plurality of data lines (D1, D2, D3, D4, …, DK+1, DK+2, DK+3, DK+4, …, DL+1, DL+2, DL+3, DL+4, …). Figure 8As shown in Table 340, the data voltage VD@140 output at the digital-to-analog conversion block 140 can include a first red data voltage RVD1 corresponding to a first red pixel data RPD1 at a first channel CH1 for the second display area DR2, a second green data voltage GVD2 corresponding to a second green pixel data GPD2 at a second channel CH2 for the second display area DR2, a third blue data voltage BVD3 corresponding to a third blue pixel data BPD3 at a third channel CH3 for the second display area DR2, a fourth red data voltage RVD4 corresponding to a fourth red pixel data RPD4 at a fourth channel CH4 for the second display area DR2, …, an (K+1)th red data voltage RVDK+1 corresponding to an (K+1)th red pixel data RPDK+1 at an (K+1)th channel CHK+1 for the first display area DR1, an (K+2)th green data voltage GVDK+2 corresponding to an (K+2)th green pixel data GPDK+2 at an (K+2)th channel CHK+2 for the first display area DR1, an (K+3)th blue data voltage BVDK+3 corresponding to an (K+3)th blue pixel data BPDK+3 at an (K+3)th channel CHK+3 for the first display area DR1, an (K+4)th green data voltage GVDK+4 corresponding to an (K+4)th green pixel data GPDK+4 at an (K+4)th channel CHK+4 for the first display area DR1, …, an (L+1)th red data voltage RVDL+1 corresponding to an (L+1)th red pixel data RPDL+1 at an (L+1)th channel CHL+1 for the second display area DR2, an (L+2)th green data voltage GVDL+2 corresponding to an (L+2)th green pixel data GPDL+2 at an (L+2)th channel CHL+2 for the second display area DR2, an (L+3)th blue data voltage BVDL+3 corresponding to an (L+3)th blue pixel data BPDL+3 at an (L+3)th channel CHL+3 for the second display area DR2, an (L+4)th red data voltage RVDL+4 corresponding to an (L+4)th red pixel data RPDL+4 at an (L+4)th channel CHL+4 for the second display area DR2, …. The data exchange block 160 can perform a data exchange operation with respect to the first display area DR1 of the hybrid display panel 300 and can not perform a data exchange operation with respect to the second display area DR2 of the hybrid display panel 300. For example, the switch control block 170 can provide the second switch signal SWS2 to a portion of the second switch SW2 corresponding to the first display area DR1 of the hybrid display panel 300 and can provide the first switch signal SWS1 to a portion of the first switch SW1 corresponding to the second display area DR2 of the hybrid display panel 300.Therefore, at the data channels (CHK+1, CHK+2, CHK+3, CHK+4, ...) connected to the first display area DR1, the switch block 180 can connect the (4N+1)th digital-to-analog converter DAC4N+1 to the (4N+3)th output buffer OB4N+3, and can also connect the (4N+3)th digital-to-analog converter DAC4N+3 to the (4N+1)th output buffer OB4N+1. Furthermore, at the data channels (CH1, CH2, CH3, CH4, ..., CHL+1, CHL+2, CHL+3, CHL+4, ...) connected to the second display area DR2, the switch block 180 can connect the (4N+1)th digital-to-analog converter DAC4N+1 and the (4N+3)th digital-to-analog converter DAC4N+3 to the (4N+1)th output buffer OB4N+1 and the (4N+3)th output buffer OB4N+3, respectively. Accordingly, data voltages (BVDK+3, GVDK+2, RVDK+1, GVDK+4, ...) that have undergone data exchange operations can be output at the data channels (CHK+1, CHK+2, CHK+3, CHK+4, ...) connected to the first display area DR1, and data voltages (RVD1, GVD2, BVD3, RVD4, ..., RVDL+1, GVDL+2, BVDL+3, RVDL+4, ...) that have not undergone data exchange operations can be output at the data channels (CH1, CH2, CH3, CH4, ..., CHL+1, CHL+2, CHL+3, CHL+4, ...) connected to the second display area DR2. Therefore, as... Figure 8 As shown in Table 340, the data voltage VD@140 output at the digital-to-analog converter block 140 relative to the second display area DR2 and the data voltage VD@190 output at the output buffer block 190 relative to the second display area DR2 may include the same data voltage, namely, the first red data voltage RVD1 at the first channel CH1, the second green data voltage GVD2 at the second channel CH2, the third blue data voltage BVD3 at the third channel CH3, the fourth red data voltage RVD4 at the fourth channel CH4, ..., the (L+1) red data voltage RVDL+1 at the (L+1) channel CHL+1, the (L+2) green data voltage GVDL+2 at the (L+2) channel CHL+2, the (L+3) blue data voltage BVDL+3 at the (L+3) channel CHL+3, the (L+4) red data voltage RVDL+4 at the (L+4) channel CHL+4, ... However, as Figure 8As shown in Table 340, unlike the data voltages VD@140 output with respect to the first display area DR1 at the digital-to-analog conversion block 140, the data voltages VD@190 output with respect to the first display area DR1 at the output buffer block 190 can include the (K+3)th blue data voltage BVDK+3 at the (K+1)th channel CHK+1, the (K+2)th green data voltage GVDK+2 at the (K+2)th channel CHK+2, the (K+1)th red data voltage RVDK+1 at the (K+3)th channel CHK+3, the (K+4)th green data voltage GVDK+4 at the (K+4)th channel CHK+4, and so on.

[0081] Accordingly, the data driver 100 driving the hybrid display panel 300 can store the pixel arrangement option PAO having the second value (e.g., "1"), can perform the even line data exchange of exchanging the data voltage (e.g., RVDK+1) at the (4N+1)th data channel (e.g., CHK+1) with the data voltage (e.g., BVDK+3) at the (4N+3)th data channel (e.g., CHK+3) from among the data voltages (RVDK+1, GVDK+2, BVDK+3, GVDK+4,...) corresponding to the even line data EVEN LDAT with respect to the first display area DR1 of the hybrid display panel 300, and can not perform the even line data exchange operation with respect to the second display area DR2 of the hybrid display panel 300.

[0082] As described above, the data driver 100 according to an embodiment can store the pixel arrangement option PAO indicating the RGBG display panel 200 or the hybrid display panel 300, and can perform the operation suitable for the RGBG display panel 200 or the hybrid display panel 300 according to the pixel arrangement option PAO. Accordingly, the data driver 100 can drive the various display panels including the RGBG display panel 200 and the hybrid display panel 300.

[0083] Figure 9 is a diagram for describing another example of a pixel arrangement option according to an embodiment, Figure 10 is a diagram showing that pixels are arranged in an RGBG pixel arrangement structure in a center area and pixels are arranged in an RGB stripe pixel arrangement structure in a pixel-on-driver (POD) area PODR and a corner area CR of a hybrid display panel, and Figure 11 is a diagram for describing an example of output image data of a data driver provided to a hybrid display panel according to an embodiment. Figure 10 is a diagram for describing an example of output image data of a data driver provided to a hybrid display panel according to an embodiment.

[0084] Referring toFigure 1 and Figure 9 According to the embodiment, the pixel arrangement option PAO stored in the option storage block 150 of the data driver 100 can represent the entire display area of ​​the display panel as RGBG. The area, or the first display area of ​​the display panel (e.g., the center area), is RGBG. The second display area of ​​the display panel (e.g., the POD area and the corner area) is an RGB strip area.

[0085] The pixel arrangement option PAO, with a first value (e.g., "0"), can represent the entire display area of ​​the display panel as RGBG. Area, or indicating the display panel as such Figure 3 The RGBG shown Display panel 200. (Refer to the above.) Figures 3 to 5 As described, driving RGBG The data driver 100 of the display panel 200 can store pixel arrangement options PAO with a first value (e.g., "0"), and can be relative to RGBG. The entire display area of ​​the display panel 200 performs even-numbered line data exchange operations.

[0086] The pixel arrangement option PAO, with a second value (e.g., "1"), can represent the first display area (e.g., the center area) of the display panel as RGBG. The area and the second display area of ​​the display panel (e.g., the POD area and the corner area) are RGB strip areas, or indicate that the display panel is as follows: Figure 10 The hybrid display panel 400 shown is an example. Figure 10 The hybrid display panel 400 can be referred to as a corner display panel. For example... Figure 10 As shown, the central region NPR arranged at the center of the hybrid display panel 400 can be pixels in RGBG format. RGBG arranged by pixel arrangement structure The POD area (PODR) located on both sides of the hybrid display panel 400 and the corner area (CR) located at the four corners of the hybrid display panel 400 can be RGB strip areas with pixels arranged in an RGB strip pixel arrangement structure.

[0087] The data driver 100 that drives the hybrid display panel 400 can receive data from the controller of the display device including the data driver 100. Figure 11 The output image data ODAT is shown in the image. (As shown in the image data ODAT) Figure 11As shown, the data driver 100 can receive line data (LDAT1, LDAT2, LDAT3, ..., LDATP-2, HTP-1, and HTP) for the corresponding pixel lines from the controller as output image data (ODAT@HT1, ODAT@HT2, ODAT@HT3, ..., ODAT@HTP-2, ODAT@HTP-1, and ODAT@HTP) in each horizontal time period (HT1, HT2, LDAT3, ..., LDATP-2, LDATP-1, and LDATP). Each line data (LDAT1, LDAT2, LDAT3, ..., LDATP-2, LDATP-1, and LDATP) can sequentially include RGB data, RGBG data, and RGB data. Figure 10 and Figure 11 As shown, in the line data LDAT1, LDAT2, and LDAT3 of the upper region where the width of the corner area CR of the hybrid display panel 400 gradually decreases, the size of the RGB data can gradually decrease, and the size of the RGBG data can increase. Furthermore, in the line data LDATP-2, LDATP-1, and LDATP of the lower region where the width of the corner area CR of the hybrid display panel 400 gradually increases, the size of the RGB data can gradually increase, and the size of the RGBG data can decrease.

[0088] Therefore, the data driver 100 driving the hybrid display panel 400 (e.g., a corner display panel) can store pixel arrangement options PAO with a second value (e.g., "1"), can perform even-line data exchange operations relative to the center region NPR of the hybrid display panel 400, and can not perform even-line data exchange operations relative to the POD region PODR and the corner region CR of the hybrid display panel 400. Therefore, the data driver 100 can drive RGBG... Various display panels, including display panel 200 and hybrid display panel 400 (e.g., corner display panel).

[0089] Figure 12 This is a diagram illustrating yet another example of pixel arrangement options according to an embodiment.

[0090] Reference Figure 1 and Figure 12 The pixel arrangement option PAO stored in the option storage block 150 of the data driver 100 according to the embodiment may have two or more bits to represent one of three or more pixel arrangement structures.

[0091] For example, such as Figure 12 As shown, the pixel arrangement option PAO with a first value (e.g., "0") can represent the entire display area of ​​the display panel as RGBG. region, and a first POD region arranged at both sides of the display panel and corresponding to the first number of data channels is an RGB stripe region. In addition, the pixel arrangement option PAO having a third value (e.g., "2") can represent that a second center region arranged at the center of the display panel is RGBG region, and a first POD region arranged at both sides of the display panel and corresponding to the first number of data channels is an RGB stripe region. In addition, the pixel arrangement option PAO having a third value (e.g., "2") can represent that a second center region arranged at the center of the display panel is RGBG region, and a first POD region arranged at both sides of the display panel and corresponding to the first number of data channels is an RGB stripe region. In addition, the pixel arrangement option PAO having a third value (e.g., "2") can represent that a second center region arranged at the center of the display panel is RGBG region, and a first POD region arranged at both sides of the display panel and corresponding to the first number of data channels is an RGB stripe region. In addition, the pixel arrangement option PAO having a third value (e.g., "2") can represent that a second center region arranged at the center of the display panel is RGBG Figure 12 The example of the pixel arrangement option PAO having two bits is shown, but the number of bits of the pixel arrangement option PAO and the pixel arrangement structure corresponding to the value of the pixel arrangement option PAO are not limited to Figure 12 The example of the pixel arrangement option PAO having two bits is shown, but the number of bits of the pixel arrangement option PAO and the pixel arrangement structure corresponding to the value of the pixel arrangement option PAO are not limited to

[0092] As described above, the data driver 100 according to an embodiment can store a pixel arrangement option PAO having two or more bits, and can drive various display panels having different pixel arrangement structures according to the pixel arrangement option PAO.

[0093] Figure 13 is a block diagram showing a display apparatus including a data driver according to an embodiment.

[0094] Referring to Figure 13 , the display apparatus 500 according to an embodiment can include a display panel 510, a scan driver 530 providing a scan signal SS to the display panel 510, a data driver 550 providing a data voltage VD to the display panel 510, and a controller 570 controlling the scan driver 530 and the data driver 550.

[0095] The display panel 510 can include a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the plurality of scan lines and the plurality of data lines. In some embodiments, each pixel can include at least two transistors, at least one capacitor, and a light emitting diode, and the display panel 510 can be a light emitting display panel. For example, the display panel 510 can be an organic light emitting diode (OLED) display panel. In other embodiments, each pixel can include a switching transistor and a liquid crystal capacitor coupled to the switching transistor, and the display panel 510 can be a liquid crystal display (LCD) panel. However, the display panel 510 can not be limited to the light emitting display panel and the LCD panel, and can be any suitable display panel.

[0096] The scan driver 530 can generate scan signals SS based on a scan control signal SCTRL received from the controller 570, and can sequentially provide the scan signals SS to the plurality of pixels through the plurality of scan lines, row by row. In some embodiments, the scan control signal SCTRL can include, but is not limited to, a scan start signal, a scan clock signal, and the like. In some embodiments, the scan driver 530 can be integrated or formed in a peripheral portion of the display panel 510. In other embodiments, the scan driver 530 can be integrated or formed in at least a portion of a display area (e.g., a POD area) of the display panel 510. In still other embodiments, the scan driver 530 can be implemented in the form of an integrated circuit.

[0097] The data driver 550 can generate data voltages VD based on output image data ODAT and a data control signal DCTRL received from the controller 570, and can provide the data voltages VD to the plurality of pixels through the plurality of data lines. In some embodiments, the output image data ODAT can include a plurality of line data LDAT for a plurality of pixel lines (or a plurality of pixel rows) of the display panel 510. Further, in some embodiments, the data control signal DCTRL can include, but is not limited to, a data clock signal DCLK and a load signal LOAD as illustrated in FIG. 1. Figure 1 In addition, in some embodiments, the data driver 550 can be a data driver 100 or the like of FIG. 1. Figure 1

[0098] ​The data driver 550 can store a pixel arrangement option PAO representing a pixel arrangement structure of the display panel 510, and can perform an operation suitable for the pixel arrangement structure of the display panel 510 according to the pixel arrangement option PAO. In some embodiments, the data driver 550 can include a digital-to-analog conversion block converting the line data LDAT into a data voltage VD, an option storage block storing the pixel arrangement option PAO representing the pixel arrangement structure of the display panel 510, a data exchange block selectively performing a data exchange operation of exchanging the data voltage VD based on the pixel arrangement option PAO and whether the line data LDAT is odd line data or even line data, and an output buffer block outputting the data voltage VD on which the data exchange operation is selectively performed to the plurality of data lines. Accordingly, the data driver 550 can drive various display panels having different pixel arrangement structures.

[0099] In some embodiments, the data driver 550 can be mounted on a substrate of the display panel 510 in a chip on glass (COG) manner or a chip on plastic (COP) manner. In other embodiments, the data driver 550 can be mounted on a flexible film coupled with the display panel 510 in a chip on film (COF) manner. Further, in some embodiments, the data driver 500 can be implemented in the form of an integrated circuit. For example, the data driver 550 and the controller 570 can be implemented with a single integrated circuit, and the single integrated circuit can be referred to as a timing controller embedded data driver (TED).

[0100] The controller 570 (e.g., a timing controller (TCON)) can receive input image data IDAT and a control signal CTRL from an external main processor (e.g., an application processor (AP), a graphics processing unit (GPU), a graphics card, etc.). For example, the input image data IDAT can be, but is not limited to, RGB data including red pixel data, green pixel data, and blue pixel data. In some embodiments, in a case where the display panel 510 is an RGBG In a case where the display panel is an RGBG In the case of a hybrid display panel of a first display area of the area and a second display area of the RGB strip area, the controller 570 can generate the output image data ODAT by converting the RGB data for the first display area of the display panel 510 into RGBG data and by not converting the RGB data for the second display area of the display panel 510. Also, in some embodiments, the control signal CTRL can include, but is not limited to, a data enable signal, a main clock signal, etc. The controller 570 can control the operation of the scan driver 530 by providing the scan control signal SCTRL to the scan driver 530, and can control the operation of the data driver 550 by providing the output image data ODAT and the data control signal DCTRL to the data driver 550.

[0101] As described above, in the display apparatus 500 according to an embodiment, the data driver 550 can store the pixel arrangement option PAO representing the pixel arrangement structure of the display panel 510, and can selectively perform the data exchange operation according to the pixel arrangement option PAO. Accordingly, in the display apparatus 500 according to an embodiment, the data driver 550 can drive the display panel 510 as any one of various display panels having different pixel arrangement structures.

[0102] Figure 14 is a block diagram illustrating a display apparatus including a data driver according to an embodiment.

[0103] Referring to Figure 14 , the display apparatus 600 according to an embodiment can include a display panel 610, a scan driver 630, a data driver 650, and a controller 670.

[0104] The display panel 610 can include a first display area DR1 and a second display area DR2, in the first display area DR1, first pixels PX1 are arranged in a first pixel arrangement structure (e.g., an RGBG pixel arrangement structure), in the second display area DR2, second pixels PX2 are arranged in a second pixel arrangement structure (e.g., an RGB strip pixel arrangement structure) different from the first pixel arrangement structure. For example, as shown in Figure 14 , the first display area DR1 can be an RGBG area, and the second display area DR2 can be an RGB strip area. Also, in some embodiments, the first display area DR1 can be a center area arranged at the center of the display panel 610, and the second display area DR2 can be a POD area arranged at both sides of the display panel 610. In other embodiments, as shown in Figure 10As illustrated in the middle, the first display area DR1 can be a center area NPR arranged at the center of the display panel 400, and the second display area DR2 can include a POD area PODR arranged at both sides of the display panel 400 and a corner area CR arranged at four corners of the display panel 400.

[0105] The data driver 650 can perform a data swapping operation of swapping the data voltages VD with respect to the first display area DR1, and can not perform the data swapping operation with respect to the second display area DR2. In some embodiments, the data swapping operation can be an even line data swapping operation of swapping the data voltage VD at the (4N+1)th data channel with the data voltage VD at the (4N+3)th data channel with each other among the data voltages VD corresponding to the even line data, where N is an integer greater than or equal to 0. Accordingly, the data driver 650 can drive the RGBG The hybrid display panel 610 of both the pixel arrangement structure and the RGB stripe pixel arrangement structure.

[0106] Figure 15 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0107] Referring to Figure 15 The electronic device 1100 can include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 can further include a plurality of ports for communication with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electrical devices, etc.

[0108] The processor 1110 can perform various computing functions or tasks. The processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 can be coupled to other components via an address bus, a control bus, a data bus, etc. Also, in some embodiments, the processor 1110 can be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0109] The memory device 1120 can store data for operation of the electronic device 1100. For example, the memory device 1120 can include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0110] The storage device 1130 can be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 can be an input device such as a keyboard, a keypad, a mouse, a touchpad, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 can supply power for operation of the electronic device 1100. The display device 1160 can be coupled to the other components via a bus or other communication link.

[0111] In the display device 1160, the data driver can store a pixel arrangement option representing a pixel arrangement structure of the display panel, and can selectively perform a data swapping operation of swapping data voltages according to the pixel arrangement option. Accordingly, in the display device 1160, the data driver can drive the display panel as any one of various display panels having different pixel arrangement structures. In particular, in the display device 1160, the data driver can drive the display panel having the RGBG pixel arrangement structure as the pixel arrangement option. a hybrid display panel of both the pixel arrangement structure and the RGB stripe pixel arrangement structure.

[0112] According to an embodiment, the electronic device 1100 can be any electronic device including the display device 1160, such as a digital television, a 3D television, a personal computer (PC), a home appliance, a laptop computer, a cellular phone, a smart phone, a tablet computer, a wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0113] The foregoing is a detailed description of embodiments and is not to be interpreted as limiting. While a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the application concepts described. Accordingly, all such modifications are intended to be included within the scope of the application concepts as defined in the claims. Therefore, it is to be understood that the foregoing is a description of various embodiments and is not to be interpreted as limiting. Modifications to the disclosed embodiments, as well as other embodiments, will be obvious to persons skilled in the art upon reading the above description. It is intended that the scope of the application concepts disclosed in the appended claims should include all such modifications and alterations.

Claims

1. A data driver for providing a data voltage to a display panel, the data driver comprising: A digital-to-analog converter block, configured to convert line data into the data voltage; An option storage block is configured to store pixel arrangement options representing the pixel arrangement structure of the display panel; A data exchange block, connected to the digital-to-analog conversion block and the option storage block, is configured to selectively perform a data exchange operation to exchange the data voltages based on the pixel arrangement option and whether the line data is odd-numbered or even-numbered, wherein the data exchange operation is an even-numbered line data exchange operation that exchanges adjacent odd-numbered data voltages in the even-numbered line data. as well as An output buffer block is connected to the data exchange block and configured to output the data voltage, which has been selectively subjected to the data exchange operation, to the data line.

2. The data driver as claimed in claim 1, wherein, When the pixel arrangement option has a first value and the line data is the even-numbered line data, the data exchange block performs the data exchange operation for the entire display area of ​​the display panel, and Specifically, when the pixel arrangement option has a second value and the line data is the even-numbered line data, the data exchange block performs the data exchange operation for the first display area of ​​the display panel and does not perform the data exchange operation for the second display area of ​​the display panel.

3. The data driver as claimed in claim 2, wherein, The first display area is RGBG PENTILE ® The second display area is an RGB strip area.

4. The data driver as claimed in claim 2, wherein, The first display area is a central area located at the center of the display panel, and the second display area is a driver-based pixel area located on both sides of the display panel.

5. The data driver as claimed in claim 2, wherein, The first display area is a central area located at the center of the display panel, and the second display area includes driver-on-pixel areas located on both sides of the display panel and corner areas located at the four corners of the display panel.

6. The data driver as claimed in claim 1, wherein, The data exchange block includes: A switching block is arranged between the digital-to-analog converter block and the output buffer block; and A switch control block, connected to the switch block and the option storage block, is configured to control the switch block based on the pixel arrangement option and whether the line data is odd-numbered or even-numbered.

7. The data driver as claimed in claim 6, wherein, The digital-to-analog converter block includes multiple digital-to-analog converters. The output buffer block includes multiple output buffers. Among them, the even-numbered digital-to-analog converters of the plurality of digital-to-analog converters are directly connected to the even-numbered output buffers of the plurality of output buffers, and The switch block includes: A plurality of first switches, configured to, in response to a first switch signal, respectively connect a plurality of odd-numbered digital-to-analog converters among the plurality of digital-to-analog converters to a plurality of odd-numbered output buffers among the plurality of output buffers; and A plurality of second switches are configured to, in response to a second switch signal, connect each of the plurality of odd-numbered digital-to-analog converters to an odd-numbered output buffer arranged adjacent to a column in which each of the plurality of odd-numbered digital-to-analog converters is arranged.

8. The data driver as claimed in claim 7, wherein, When the pixel arrangement option has a first value and the line data is the odd number of line data, the switch control block provides the first switch signal to all of the plurality of first switches corresponding to the entire display area of ​​the display panel, and Wherein, when the pixel arrangement option has the first value and the line data is the even number of line data, the switch control block provides the second switch signal to all of the plurality of second switches corresponding to the entire display area of ​​the display panel.

9. The data driver as claimed in claim 7, wherein, When the pixel arrangement option has a second value and the line data is the odd number of line data, the switch control block provides the first switch signal to all of the plurality of first switches corresponding to the entire display area of ​​the display panel, and Wherein, when the pixel arrangement option has the second value and the line data is the even number of line data, the switch control block provides the second switch signal to a portion of the plurality of second switches corresponding to the first display area of ​​the display panel, and provides the first switch signal to a portion of the plurality of first switches corresponding to the second display area of ​​the display panel.

10. The data driver as claimed in claim 1, wherein, The pixel arrangement option has two or more bits to represent one of three or more pixel arrangement structures.

11. The data driver of claim 10, wherein, The pixel arrangement option with the first value indicates that the entire display area of ​​the display panel is RGBG PENTILE. ® area, The pixel arrangement option having the second value indicates that the first central region arranged at the center of the display panel is the RGBG PENTILE. ® The pixel areas on the first driver, located on both sides of the display panel and corresponding to the first number of data channels, are RGB strip-shaped areas. Wherein, the pixel arrangement option having the third value indicates that the second central region arranged at the center of the display panel is the RGBG PENTILE. ® The area, and the pixel area on the second driver corresponding to the second number of data channels on both sides of the display panel, is the RGB strip area, and Wherein, the pixel arrangement option having the fourth value indicates that the third central region arranged at the center of the display panel is the RGBG PENTILE. ® The RGB strip area is defined as the pixel area on the third driver arranged on both sides of the display panel and the corner area arranged at the four corners of the display panel.

12. The data driver of claim 1, further comprising: A shift register configured to sequentially generate sampled signals; A sampling latch block is configured to sequentially store the line data in response to the sampling signal; as well as The latch block is configured to receive the line data from the sampling latch block in response to a load signal and to provide the line data to the digital-to-analog converter block.

13. A display device, comprising: Display panel; A scan driver configured to provide a scan signal to the display panel; A data driver configured to provide data voltage to the display panel; as well as The controller is configured to control the scan driver and the data driver. The data driver includes: A digital-to-analog converter block, configured to convert line data into the data voltage; An option storage block is configured to store pixel arrangement options representing the pixel arrangement structure of the display panel; A data exchange block, connected to the digital-to-analog conversion block and the option storage block, is configured to selectively perform a data exchange operation to exchange the data voltages based on the pixel arrangement option and whether the line data is odd-numbered or even-numbered, wherein the data exchange operation is an even-numbered line data exchange operation that exchanges adjacent odd-numbered data voltages in the even-numbered line data; and An output buffer block is connected to the data exchange block and configured to output the data voltage, which has been selectively subjected to the data exchange operation, to the data line.

14. The display device as claimed in claim 13, wherein, When the pixel arrangement option has a first value and the line data is the even-numbered line data, the data exchange block performs the data exchange operation for the entire display area of ​​the display panel, and Specifically, when the pixel arrangement option has a second value and the line data is the even-numbered line data, the data exchange block performs the data exchange operation for the first display area of ​​the display panel and does not perform the data exchange operation for the second display area of ​​the display panel.

15. A data driver for providing data voltage to a display panel comprising a plurality of columns, the data driver comprising: A digital-to-analog converter block includes multiple digital-to-analog converters, each arranged in a column and configured to convert line data into the data voltage; An option storage block is configured to store pixel arrangement options representing the pixel arrangement structure of the display panel; A data exchange block, connected to the digital-to-analog conversion block and the option storage block, is configured to selectively perform a data exchange operation to exchange the data voltages based on the pixel arrangement option and whether the line data is odd-numbered or even-numbered, wherein the data exchange operation is an even-numbered line data exchange operation that exchanges adjacent odd-numbered data voltages in the even-numbered line data; and An output buffer block, connected to the data exchange block and configured to output the data voltage, includes multiple output buffers, each arranged in a corresponding column. The data exchange block includes: A plurality of first switches connect the plurality of digital-to-analog converters to the plurality of output buffers respectively, each of the plurality of first switches connecting the digital-to-analog converter to an output buffer arranged in the same column, and A plurality of second switches connect a plurality of digital-to-analog converters arranged in one of the odd or even columns to a plurality of output buffers arranged in one of the odd or even columns, wherein each of the plurality of second switches connects a digital-to-analog converter located in one column to an output buffer arranged in a column different from the column in which the digital-to-analog converter is arranged.

16. The data driver of claim 15, wherein, Each of the plurality of second switches connects a digital-to-analog converter located in one even-numbered column to an output buffer arranged in another even-numbered column.

17. The data driver of claim 16, wherein, Each of the plurality of second switches connects the digital-to-analog converter located in the even-numbered column to the output buffer arranged in the even-numbered column adjacent to the even-numbered column.

18. The data driver of claim 15, wherein, Each of the plurality of second switches connects a digital-to-analog converter located in one odd column to an output buffer arranged in another odd column.

19. The data driver of claim 18, wherein, Each of the plurality of second switches connects the digital-to-analog converter located in the odd-numbered column to the output buffer arranged in the odd-numbered column adjacent to the odd-numbered column.

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