Open block management using stored charge loss margin check

Abstract

This application relates to open block management using storage charge loss margin checks. A system includes a memory device; and a processing means operatively coupled to the memory device to perform operations including: identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages; determining that the SCL amount satisfies a threshold criterion corresponding to an acceptable SCL amount that will occur on the open block; and, in response to determining that the SCL amount satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to open block management using storage charge loss (SCL) margin checks. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this application provides a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages; determining that the SCL amount satisfies a threshold criterion corresponding to an acceptable SCL amount that would occur on the open block; and, in response to determining that the SCL amount satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

[0004] In another aspect, this application provides a method comprising: identifying an amount of storage charge loss (SCL) that has occurred on an open block of a memory device, the open block having one or more erased pages; determining that the SCL amount satisfies a threshold criterion corresponding to an acceptable SCL amount that would occur on the open block; and, in response to determining that the SCL amount satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

[0005] In another aspect, this application provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: identifying an amount of storage charge loss (SCL) that has occurred on an open block of a memory device, the open block having one or more erased pages; determining that a second SCL amount does not satisfy a threshold criterion corresponding to an acceptable SCL amount that will occur on the open block; and discarding the open block in response to determining that the second SCL amount does not satisfy the threshold criterion. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of a method for open block management using storage charge loss (SCL) margin checks according to some embodiments of this disclosure.

[0009] Figure 3 These are diagrams illustrating open blocks according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0011] This disclosure relates to open block storage charge loss (SCL) margin checks. The memory subsystem can be a storage device, a memory module, or a combination of both. The following is combined with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0012] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0013] A memory device may contain multiple bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and may contain a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of the memory device to allow concurrent operation on each plane. The memory device may contain circuitry for performing concurrent memory page accesses on two or more memory planes. For example, the memory device may include corresponding access line driver circuitry and power circuitry for each plane of the memory device to facilitate concurrent access to pages in two or more memory planes containing different page types.

[0014] Memory cells can be programmed (written) by applying a specific voltage to them, which creates a charge held by the memory cell. For example, a voltage signal V can be applied... CG A control electrode is applied to the cell to open the cell to current flow across the cell between the source and drain electrodes. More specifically, for each individual memory cell (with a charge Q stored thereon), a threshold control gate voltage V may exist. T (Also referred to herein as the “threshold voltage” or simply the “threshold”), such that for a given control gate voltage (V0), CG () below the threshold voltage, i.e. V CG <V T The source-drain current is low. Once the control gate voltage exceeds the threshold voltage, i.e., V... CG >V T The current increases significantly. Because the actual geometry of the electrodes and gate varies between cells, the threshold voltage can differ even for cells implemented on the same die. Therefore, a memory cell can be characterized as a distribution of threshold voltage P, P(Q,V). T )=dW / dV T , where dW represents the threshold voltage of any given cell in the interval [V] when charge Q is placed on the cell. T V T +dV T The probability within ] .

[0015] Memory devices may have a narrow distribution P(Q,V) compared to the operating range of the control voltages allowed by the cells of the device. T Therefore, multiple non-overlapping distributions P(Q) k V TThe valley value can be fitted to the working range, thus allowing the storage and reliable detection of multiple charge values ​​Q. k k = 1, 2, 3… The distribution (valleys) is interspersed with voltage intervals (valley margins), in which the memory cells of the device have no (or very few) their threshold voltages. Therefore, such valley margins can be used to separate various charge states Q. k The corresponding threshold voltage V of the detection unit can be detected during the read operation. T The logic state of a cell is determined by the range between which two valley margins exist. This effectively allows a single memory cell to store multiple bits of information: a memory cell operating under 2N-1 well-defined valley margins and 2N valleys can reliably store N bits of information. Specifically, this can be achieved by comparing the measured threshold voltage V exhibited by the memory cell. T Read operations are performed with one or more reference voltage levels (read levels) corresponding to a known valley margin (e.g., the center of the margin) of the memory device.

[0016] One phenomenon observed in memory devices is V t Distributed shift, also referred to herein as time-voltage shift (TVS). For example, regarding a programmed page of a block, as the charge decreases with, for example, time and / or temperature, the stored charge loss (SCL) can cause V... t The distribution shifts towards the lower voltage. That is, SCL and the corresponding V shifted towards the lower voltage. t Distributed shift can be proportional to the time elapsed from programming to reading. Conversely, for erased pages of a block, the storage charge gain (SCG) can cause V to increase as the charge increases with, for example, time and / or temperature. t The distribution shifts towards higher voltages. That is, similar to SCL, SCG, and the corresponding V shifting towards higher voltages. t Distributed shift can be proportional to the time elapsed from the erase operation to the programming operation. If too many SCGs occur on the erased page, reliability issues may arise when data is programmed into the erased page. This is because SCGs can be difficult to track and / or predict due to the memory cell being in an erased state. When the SCG to the erased page is large enough to be detected, the amount of the SCG and the corresponding V... t Distributed shifting may have become a problem hindering the achievement of reliable programming.

[0017] One approach to address the SCG problem when programming erased blocks is to erase the block immediately before programming and then allow the erased block to remain in an open state (i.e., currently being programmed) for filling within a time limit (e.g., approximately one hour). After the time limit expires, the erased block is discarded, and a new block can subsequently be opened for data writing within the time limit. By doing this, the erased block can be discarded before being fully filled. This is attributable to the need for more frequent partial filling of blocks compared to fully filling the block, resulting in redundant block consumption and thus an overall reduction in the total bytes written (TBW) capacity of the storage device. Furthermore, this approach is attributable to the performance degradation caused by the need to erase new blocks before data writing.

[0018] This disclosure addresses the above and other shortcomings by providing a memory subsystem that manages open blocks using Storage Charge Loss (SCL) margin checks. As discussed above, it can be difficult to detect the amount of SCG that has occurred on erased pages of a block. However, the amount of SCL that has occurred on programmed pages of a block is generally related to the amount of SCG that has occurred on erased pages of a block. Therefore, the memory subsystem can use the amount of SCL that has occurred on programmed pages of a block as a proxy for the amount of SCG that has occurred on erased pages of a block.

[0019] To determine the SCL quantity, the memory subsystem can use any suitable scan method to scan the programmed word lines of the programmed pages of the open block to measure a value, and then compare that value with a known reference to determine the SCL quantity on the programmed pages of the open block. Examples of suitable scan methods include, but are not limited to, direct V... t Measurement, reading level calibration, reading sensed current, etc. Since SCL increases over time, a scan can occur on the earliest programmed data (e.g., TLC / QLC data) contained in the earliest programmed page of the open block to ensure that the SCL amount is the highest possible SCL that can be determined for the open block, and the scan can be performed at a set time frequency since the earliest programmed page in the open block was programmed. The memory subsystem can then determine whether the SCL amount meets a threshold criterion. For example, the SCL amount can be compared to a threshold corresponding to an acceptable SCL amount to determine whether the open block should continue to be used after a previously allocated time has elapsed. More specifically, if the SCL amount is less than or equal to the threshold (the SCL amount is acceptable), then the threshold criterion is met, and the open block will remain open for programming the remaining erased pages. If the SCL amount exceeds the threshold and is therefore unacceptable, then the threshold criterion is not met, and the open block is discarded. After discarding, a new block can then be opened for programming.

[0020] The methods performed by the memory subsystem described above can be implemented according to any suitable memory device architecture based on the embodiments described herein. In one embodiment, the methods can be implemented using a memory device that implements Replacement Gate NAND (RG NAND) technology. A Replacement Gate (RG) NAND device is a NAND device that implements an RG architecture instead of a Floating Gate (FG) architecture. The RG NAND architecture eliminates the cell gaps common in the FG NAND architecture, thereby reducing or eliminating the capacitance generated by these cell gaps. More specifically, the RG NAND architecture corresponds to a single insulator structure. Compared to the FGNAND architecture, the RG NAND architecture can achieve smaller size, improved read and write latency, and higher transfer rates.

[0021] The advantages of this disclosure include, but are not limited to, preventing excessive programming / erasing cycles, allowing accurate prediction of TBW (Block Tolerance), and improved performance due to the reduced need for erasing of new blocks.

[0022] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device that includes memory and processing means (e.g., a processor).

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] The memory subsystem 110 includes an Open Block Management (OBM) component 113 that can perform open block storage charge loss (SCL) margin checks. The OBM component 113 can scan the data programmed on an open block having one or more erased pages to determine the amount of SCL that has occurred on the open block, obtain a threshold corresponding to an acceptable SCL amount that will occur on the open block, and determine whether the SCL amount exceeds the threshold. Since the SCL can be used as a proxy for the SCG, the determination made by the OBM component 113 can be used to determine whether to keep the block open for programming one or more erased pages. Therefore, if the SCL amount meets the threshold criterion (e.g., less than or equal to the threshold), then the OBM component 113 keeps the open block open for programming one or more erased pages. Otherwise, the OBM component 113 discards the open block. The OBM component 113 can then open a new block for programming.

[0039] In some embodiments, the memory subsystem controller 115 includes at least a portion of the PV component 113. In some embodiments, the OBM component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the OBM component 113 and is configured to perform the functionality described herein. References below Figure 2 and 3 Further details regarding the operation of OBM component 113 are described.

[0040] Figure 2 This is a flowchart of a method 200 for open block management using a storage charge loss (SCL) margin check according to some embodiments of the present disclosure. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The OBM component 113 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0041] At operation 210, processing logic identifies the amount of storage charge loss (SCL) that has occurred on an open block of the memory device, wherein the open block has one or more erased pages. For example, the open block may be a NAND block. In some embodiments, determining the SCL amount involves scanning one or more programmed pages of the open block and determining the SCL amount as the amount of SCL that has occurred on the one or more programmed pages based on the scan. More specifically, one or more programmed word lines of one or more programmed pages may be scanned to measure a value, and the value may then be compared with a known reference to determine the amount of SCL on the programmed pages of the open block. Any suitable method may be used to identify the SCL amount (e.g., during scanning). Examples of such methods include, but are not limited to, direct V t Measurements include reading level calibration and reading sensed current. For example, a first measurement can be performed immediately after programming, and a second measurement can be performed at a later time. The difference between the first and second measurements is a measure of SCL.

[0042] The scan can occur at a set time frequency on the earliest programmed data (e.g., TLC / QLC data) contained within the earliest programmed page of the open block, starting from the time the earliest programmed page in the open block was programmed. Various methods can be implemented to determine the age of the data. For example, the programming time can be maintained in the page metadata and / or a separate metadata table. The scan can be set to run once per hour from the time the earliest programmed data (e.g., TLC / QLC data) was programmed into the block until the time when the block is fully programmed or discarded due to storage charge gain (SCG). References will follow below. Figure 3 Describe further details about the structure of open blocks.

[0043] At operation 220, the processing logic obtains a threshold corresponding to the acceptable SCL (Solution Classification Rate) that will occur on the open block. Obtaining the threshold may involve determining the threshold based on characterization data. Several levels of characterization data may be required. One level of characterization data includes a measurement of the ratio of SCL to SCG, allowing the relationship between SCL and SCG to be obtained. Another level of characterization data includes identifying pass / fail points by performing reliability tests on various SCG quantities before data programming (e.g., understanding how much SCG is acceptable before the block should be discarded).

[0044] The relationship between SCL and SCG can vary based on several factors. Examples of such factors include, but are not limited to, the temperature at which the block has been found and the programming / erase cycle. In one instance, the SCL to SCG ratio could be approximately 1.23:1. Another way to illustrate this ratio is that every 123 mV of SCL corresponds to 100 mV of SCG.

[0045] At operation 230, the processing logic determines whether the SCL amount meets a threshold criterion regarding a threshold. This determination is performed to decide whether to continue using the open block after a previously allocated time (e.g., 1 hour). In one embodiment, if the SCL amount is less than or equal to the threshold, then the threshold criterion is met, and if the SCL amount exceeds the threshold, then the threshold criterion is not met.

[0046] If the SCL amount that has occurred on the open block meets the threshold criterion (e.g., less than or equal to the threshold), then this means that the SCL amount that has occurred on the open block is acceptable. Therefore, given the relationship between SCL and SCG, the SCG amount that has occurred on one or more erased pages of the open block should similarly be acceptable. Therefore, the processing logic keeps the open block open for programming one or more erased pages at operation 240.

[0047] In response to the determination that a threshold criterion is not met (e.g., the SCL amount already occurring on the open block exceeds a threshold), it is determined that this SCL amount already occurring on the open block is unacceptable. Therefore, given the relationship between SCL and SCG, the SCG amount already occurring on one or more erased pages of the open block should similarly be unacceptable (e.g., too high to reliably program) and the open block should be closed for programming. Therefore, at operation 250, the processing device discards the open block. The subsequent processing logic may then open a new block for programming at operation 260.

[0048] After keeping the open block open at operation 240 or after opening a new block at operation 260, the processing logic can repeat operations 210-230 to identify the second SCL amount that has occurred on the newly opened block, obtain a threshold, and determine whether the SCL amount that has occurred on the newly opened block meets the threshold criterion.

[0049] Figure 3 Diagram 300 illustrates an example of an open block 310. For example, open block 310 may be a NAND block. As shown, block 310 includes a set of programmed pages 320 and a set of erased pages 330. The set of programmed pages 320 includes programmed pages 320-1 to 320-5, where programmed page 320-1 corresponds to the earliest programmed page with the earliest programmed data, and programmed page 320-5 corresponds to the latest programmed page with the latest programmed data. The set of erased pages 330 includes erased page 332. The programming order proceeds upwards from the earliest programmed data (e.g., from page 322-1).

[0050] As referenced above Figure 2To describe in further detail, there exists a relationship between the SCL of a programmed page and the SCG of an erased page, such that the SCL amount can be used as a proxy for the SCG. Therefore, if it is determined that the SCL amount that has occurred on open block 310 (e.g., the SCL amount that has occurred on page 320-1) satisfies a threshold criterion (e.g., because it is less than or equal to a threshold corresponding to an acceptable SCL amount), then open block 310 remains open for at least programming erased page 332. Otherwise, open block 310 is discarded and a new open block can be opened for programming.

[0051] Figure 4 An example machine is described as representing computer system 400, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 400 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform corresponding... Figure 1 (Operation of OBM component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0052] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0053] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0054] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may additionally include a network interface device 408 for communication on network 420.

[0055] Data storage system 418 may include machine-readable storage medium 424 (also referred to as computer-readable medium) on which one or more sets of instructions 426 or software embodying any one or more methods or functions described herein are stored. The instructions 426 may also reside wholly or at least partially within main memory 404 and / or processing device 402 during execution by computer system 400, the main memory 404 and processing device 402 also constituting machine-readable storage medium. Machine-readable medium 424, data storage system 418 and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0056] In one embodiment, instruction 426 includes instructions for implementing a component corresponding to a PV component (e.g., Figure 1 The OBM component 113) contains functional instructions. Although machine-readable storage medium 424 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0057] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0058] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0059] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0060] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0061] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0062] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: a replacement gate memory device comprising an open block, the open block comprising a set of programmed pages and a set of erased pages; and a processing device operatively coupled with the replacement gate memory device to perform operations comprising: identifying an amount of storage charge loss (SCL) that has occurred on an oldest programmed page of the set of programmed pages; determining whether the amount of SCL that has occurred on the oldest programmed page satisfies a threshold criterion, the threshold criterion corresponding to an acceptable amount of SCL that will occur on the oldest programmed page and an acceptable amount of charge gain that will occur on one or more erased pages of the set of erased pages; and in response to determining that the amount of SCL that has occurred on the oldest programmed page satisfies the threshold criterion, causing the open block to remain open for programming the one or more erased pages of the set of erased pages.

2. The system of claim 1, wherein identifying the amount of SCL that has occurred on the oldest programmed page comprises: scanning the oldest programmed page of the open block; and determining the amount of SCL that has occurred on the oldest programmed page based on the scanning.

3. The system of claim 1, wherein identifying the amount of SCL that has occurred on the oldest programmed page comprises performing at least one of a direct threshold voltage measurement, a read level calibration, or a read sense current.

4. The system of claim 2, wherein the oldest programmed page is scanned at a set time frequency since the oldest programmed page was programmed.

5. The system of claim 1, wherein the operations further comprise: in response to determining that the amount of SCL that has occurred on the oldest programmed page does not satisfy the threshold criterion, discarding the open block.

6. The system of claim 5, wherein the operations further comprise opening a new block for programming after discarding the open block.

7. A method comprising: identifying, by a processing device, an amount of storage charge loss (SCL) that has occurred on an oldest programmed page of a set of programmed pages of an open block of a replacement gate memory device, the open block further comprising a set of erased pages; determining, by the processing device, whether the amount of SCL that has occurred on the oldest programmed page satisfies a threshold criterion, the threshold criterion corresponding to an acceptable amount of SCL that will occur on the oldest programmed page and an acceptable amount of charge gain that will occur on one or more erased pages of the set of erased pages; and in response to determining that the amount of SCL that has occurred on the oldest programmed page satisfies the threshold criterion, causing, by the processing device, the open block to remain open for programming the one or more erased pages of the set of erased pages.

8. The method of claim 7, wherein identifying the amount of SCL that has occurred on the oldest programmed page comprises: scanning the oldest programmed page; and determining the amount of SCL that has occurred on the oldest programmed page based on the scanning. ​ ​ ​ 9. The method of claim 7, wherein identifying the amount of SCL that has occurred on the oldest programmed page comprises performing at least one of a direct threshold voltage measurement, a read level calibration, or a read sense current.

10. The method of claim 8, wherein the oldest programmed page is scanned at a set time frequency since the oldest programmed page was programmed.

11. The method of claim 7, further comprising: in response to determining that the amount of SCL that has occurred on the oldest programmed page does not satisfy the threshold criteria, discarding, by the processing device, the open block.

12. The method of claim 11, further comprising opening, by the processing device, a new block for programming after discarding the open block.

13. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying an amount of storage charge loss (SCL) that has occurred on an oldest programmed page of a set of programmed pages of an open block of a replacement gate memory device, the open block additionally comprising a set of erased pages; determining whether the amount of SCL that has occurred on the oldest programmed page does not satisfy a threshold criteria, the threshold criteria corresponding to an acceptable amount of SCL that will occur on the oldest programmed page and an acceptable amount of charge gain that will occur on the set of erased pages; and in response to determining that the amount of SCL does not satisfy the threshold criteria, discarding the open block.

14. The non-transitory computer-readable storage medium of claim 13, wherein identifying the amount of SCL comprises: scanning the oldest programmed page; and determining, based on the scanning, the amount of SCL that has occurred on the oldest programmed page.

15. The non-transitory computer-readable storage medium of claim 13, wherein identifying the amount of SCL that has occurred on the oldest programmed page comprises performing at least one of a direct threshold voltage measurement, a read level calibration, or a read sense current.

16. The non-transitory computer-readable storage medium of claim 14, wherein the oldest programmed page is scanned at a set time frequency since the oldest programmed page was programmed.

17. The non-transitory computer-readable storage medium of claim 13, wherein the operations additionally comprise opening a new block for programming after discarding the open block.

18. The non-transitory computer-readable storage medium of claim 13, wherein the operations further comprise: in response to determining that the amount of SCL that has occurred on the oldest programmed page satisfies the threshold criteria, causing the open block to remain open for programming one or more of the set of erased pages.

18. A method comprising: identifying an amount of storage charge loss (SCL) that has occurred on an oldest programmed page of a set of programmed pages of an open block of a replacement gate memory device, the open block additionally comprising a set of erased pages; determining whether the amount of SCL that has occurred on the oldest programmed page does not satisfy a threshold criteria, the threshold criteria corresponding to an acceptable amount of SCL that will occur on the oldest programmed page and an acceptable amount of charge gain that will occur on the set of erased pages; and in response to determining that the amount of SCL does not satisfy the threshold criteria, discarding the open block.

19. The method of claim 18, wherein identifying the amount of SCL comprises: scanning the oldest programmed page; and determining, based on the scanning, the amount of SCL that has occurred on the oldest programmed page.

20. The method of claim 18, wherein identifying the amount of SCL that has occurred on the oldest programmed page comprises performing at least one of a direct threshold voltage measurement, a read level calibration, or a read sense current.

21. The method of claim 19, wherein the oldest programmed page is scanned at a set time frequency since the oldest programmed page was programmed.

22. The method of claim 18, wherein the method additionally comprises opening a new block for programming after discarding the open block. in response to determining that the amount of SCL that has occurred on the oldest programmed page satisfies the threshold criteria, causing the open block to remain open for programming one or more of the set of erased pages.

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