Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: forming an interlayer dielectric layer on a substrate, forming a gate opening in the interlayer dielectric layer, forming sidewalls on the sidewalls of the gate opening, and forming a gate dielectric layer on the top and sidewalls of the sidewalls, the top of the interlayer dielectric layer, and the bottom of the gate opening; forming a work function layer conformally covering the gate dielectric layer, the work function layer in the first region filling the gate opening, and the work function layer in the second region covering the sidewalls and the bottom of the gate dielectric layer; forming a gate electrode material layer on top of the work function layer; forming a sacrificial layer on top of the gate electrode material layer in the second region, the top of the sacrificial layer in the second region being flush with the top of the gate electrode material layer in the first region; removing the gate electrode material layer and the sacrificial layer higher than the top of the work function layer, and using the remaining gate electrode material layer in the gate opening in the second region as a gate electrode layer. The height uniformity and the top surface flatness of the first metal gate structure and the second metal gate structure are improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's Law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] During the development of integrated circuits, usually while the functional density (i.e., the number of internal wiring structures per chip) gradually increases, the geometric size (i.e., the minimum element size that can be produced using process steps) gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, in the case of continuously shrinking technology nodes, how to improve the high consistency of devices in different regions of a wafer and the flatness of the wafer top surface has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region and a second region, an interlayer dielectric layer being formed on the substrate, a gate opening being formed in the interlayer dielectric layer, sidewalls being formed on sidewalls of the gate opening, a gate dielectric layer being formed on tops and sidewalls of the sidewalls, on a top of the interlayer dielectric layer, and on a bottom of the gate opening, in a direction perpendicular to an extending direction of the gate opening, a width of the gate opening in the first region being smaller than a width of the gate opening in the second region; forming a work function layer conformally covering the gate dielectric layer, the work function layer in the first region filling a remaining space in the gate opening, the work function layer in the second region covering sidewalls of the gate dielectric layer and exposing the remaining space of the gate opening; forming a gate electrode material layer on a top of the work function layer, the gate electrode material layer further filling the remaining space in the gate opening in the second region, and a top of the gate electrode material layer in the first region being higher than a top of the gate electrode material layer in the second region; forming a sacrificial layer on a top of the gate electrode material layer in the second region, a top of the sacrificial layer in the second region being flush with a top of the gate electrode material layer in the first region; after forming the sacrificial layer, removing the gate electrode material layer, the sacrificial layer, the work function layer, and the gate dielectric layer that are higher than a top of the interlayer dielectric layer, a remaining gate electrode material layer in the gate opening in the second region serving as a gate electrode layer, a remaining gate dielectric layer and work function layer in the gate opening in the first region serving as a first metal gate structure, and a remaining gate dielectric layer, work function layer, and gate electrode layer in the gate opening in the second region serving as a second metal gate structure.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a method for forming a semiconductor structure. An interlayer dielectric layer is formed on a substrate. A gate opening is formed in the interlayer dielectric layer. Sidewalls are formed on the sidewalls of the gate opening. A gate dielectric layer is formed on the top and sidewalls of the sidewalls, the top of the interlayer dielectric layer, and the bottom of the gate opening. In a direction perpendicular to the extending direction of the gate opening, the width of the gate opening in the first region is smaller than the width of the gate opening in the second region. A work function layer is formed to conformally cover the gate dielectric layer. The work function layer in the first region also fills the remaining space in the gate opening. The work function layer in the second region covers the sidewalls and the bottom of the gate dielectric layer and exposes the remaining space of the gate opening. A gate electrode material layer is formed on the top of the work function layer. The gate electrode material layer also fills the remaining space in the gate opening of the second region, and the top of the gate electrode material layer in the first region is higher than the top of the gate electrode material layer in the second region. A sacrificial layer is formed on the top of the gate electrode material layer in the second region. The top of the sacrificial layer in the second region is flush with the top of the gate electrode material layer in the first region. After forming the sacrificial layer, the gate electrode material layer, the sacrificial layer, the work function layer, and the gate dielectric layer above the top of the interlayer dielectric layer are removed. The remaining gate electrode material layer in the gate opening in the second region serves as the gate electrode layer. The remaining gate dielectric layer and work function layer in the gate opening in the first region serve as the first metal gate structure. The remaining gate dielectric layer, work function layer, and gate electrode layer in the gate opening in the second region serve as the second metal gate structure. Compared with the existing solution of directly removing all the gate electrode material layer in the first region after forming the gate electrode material layer in the first region and the second region, in the embodiment of the present invention, after forming the gate electrode material layer in the first region and the second region, a sacrificial layer is first formed on the top of the gate electrode material layer in the second region, and the top of the sacrificial layer in the second region is flush with the top of the gate electrode material layer in the first region. Therefore, when removing the gate electrode material layer and the sacrificial layer above the top of the work function layer subsequently, the sacrificial layer in the second region serves as a thickness compensation layer, making the thickness of the film layers to be removed in the first region and the second region equal, which is beneficial to improving the height uniformity of the remaining gate electrode material layer in the first region and the second region, and further improving the height uniformity and top surface flatness of the first metal gate structure and the second metal gate structure, reducing the probability that the top surface of the second metal gate structure is damaged or indented, and correspondingly improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

[0010] Figure 4 is a schematic structural diagram corresponding to the step of providing a substrate in an embodiment of the present invention;

[0011] Figure 5 It is a schematic structural diagram corresponding to the step of forming a work function layer of a conformal capping gate dielectric layer in an embodiment of the present invention;

[0012] Figure 6 It is a schematic structural diagram corresponding to the step of forming a gate electrode material layer in an embodiment of the present invention;

[0013] Figure 7 It is a schematic structural diagram corresponding to the step of forming a sacrificial material layer on top of the gate electrode material layer in an embodiment of the present invention;

[0014] Figure 8 It is a schematic structural diagram corresponding to the step of forming a sacrificial layer on top of the gate electrode material layer in the second region in an embodiment of the present invention;

[0015] Figure 9 It is a schematic structural diagram corresponding to the step of removing the sacrificial layer in the second region and a part of the thickness of the gate electrode material layer in the first region in an embodiment of the present invention;

[0016] Figure 10 It is a schematic structural diagram corresponding to the step of removing the gate electrode material layer, the sacrificial layer, the work function layer, and the gate dielectric layer above the top of the interlayer dielectric layer in an embodiment of the present invention. Detailed implementation manners

[0017] Currently, the performance of semiconductor structures still needs to be improved. Now, in combination with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed. Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0018] Reference Figure 1 , a substrate is provided, the substrate includes a first region A and a second region B, an interlayer dielectric layer 13 is formed on the substrate, a gate opening 12 is formed in the interlayer dielectric layer 13, sidewalls 31 are formed on the sidewalls of the gate opening 12, a gate dielectric layer 30 is formed on the sidewalls and the top of the sidewalls 31, the top of the interlayer dielectric layer 13, and the bottom of the gate opening 12. In a direction perpendicular to the extending direction of the gate opening 12, the width of the gate opening 12 in the first region A is smaller than the width of the gate opening 12 in the second region; a work function layer 14 that conformally covers the gate dielectric layer 30 is formed. The work function layer 14 in the first region A fills the gate opening 12, and the work function layer 114 in the second region B covers the sidewalls of the gate dielectric layer 30 and exposes the remaining space of the gate opening 12.

[0019] Reference Figure 2, a gate electrode material layer 15 is formed on the top of the work function layer 14. The gate electrode material layer 15 also fills the remaining space of the gate opening 12 in the second region B, and the top of the gate electrode material layer 15 in the first region A is higher than the top of the gate electrode material layer 15 in the second region B.

[0020] Reference Figure 3 , taking the top of the interlayer dielectric layer 13 in the first region A as the stop position, the gate electrode material layer 15, the work function layer 14 and the gate dielectric layer 30 above the top of the interlayer dielectric layer 13 are removed. The remaining gate electrode material layer 15 in the gate opening 12 of the second region B serves as the gate electrode layer 16, the work function layer 17 and the gate dielectric layer 30 in the gate opening 12 of the first region A serve as the first metal gate structure 50, and the work function layer 14, the gate electrode layer 16 and the gate dielectric layer 30 in the gate opening 12 of the second region B serve as the second metal gate structure 18.

[0021] It is found through research that during the process of forming the gate electrode material layer 15 in the first region A and the second region B, since the gate opening 12 in the first region A is completely filled by the work function layer 14 while there is still some remaining space in the gate opening of the second region B, it is prone to be affected by the film thickness loading effect during the formation of the gate electrode material layer 15. The top of the gate electrode material layer 15 in the first region A is higher than the top of the gate electrode material layer 15 in the second region B, that is, there is a height difference H1 between the top of the gate electrode material layer 15 in the first region A and the top of the gate electrode material layer 15 in the second region B.

[0022] Due to the existence of the height difference H1, during the process of removing the gate electrode material layer 15 above the top of the interlayer dielectric layer 13 in the first region A with the top of the interlayer dielectric layer 13 in the first region A as the stop position of the planarization process, in order to completely remove the gate electrode material layer 15 above the top of the interlayer dielectric layer 13 in the first region A, the planarization process is likely to cause losses to the gate dielectric layer 30, the work function layer 14 and the gate electrode material layer 15 in the second region, resulting in a decrease in the effective height of the gate dielectric layer 30, the work function layer 14 and the gate electrode layer 16 in the second region. Correspondingly, there is a height difference H2 between the first metal gate structure 50 and the second metal gate structure 18, reducing the top surface flatness of the first metal gate structure 50 and the second metal gate structure 18, and at the same time, it is also likely to cause the gate electrode layer 16 in the second region to be sunken, thus affecting the performance of the semiconductor structure.

[0023] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, an interlayer dielectric layer being formed on the substrate, a gate opening being formed in the interlayer dielectric layer, a spacer being formed on sidewalls of the gate opening, a gate dielectric layer being formed on a top and sidewalls of the spacer, a top of the interlayer dielectric layer, and a bottom of the gate opening, in a direction perpendicular to an extending direction of the gate opening, a width of the gate opening in the first region being smaller than a width of the gate opening in the second region; forming a work function layer conformally covering the gate dielectric layer, the work function layer in the first region filling a remaining space in the gate opening, the work function layer in the second region covering sidewalls of the gate dielectric layer and exposing the remaining space in the gate opening; forming a gate electrode material layer on a top of the work function layer, the gate electrode material layer further filling the remaining space in the gate opening in the second region, and a top of the gate electrode material layer in the first region being higher than a top of the gate electrode material layer in the second region; forming a sacrificial layer on a top of the gate electrode material layer in the second region, a top of the sacrificial layer in the second region being flush with a top of the gate electrode material layer in the first region; after forming the sacrificial layer, removing the gate electrode material layer, the sacrificial layer, the work function layer, and the gate dielectric layer that are higher than a top of the interlayer dielectric layer, a remaining gate electrode material layer in the gate opening in the second region serving as a gate electrode layer, a remaining gate dielectric layer and work function layer in the gate opening in the first region serving as a first metal gate structure, and a remaining gate dielectric layer, work function layer, and gate electrode layer in the gate opening in the second region serving as a second metal gate structure.

[0024] In the solution disclosed in the embodiments of the present invention, an interlayer dielectric layer is formed on a substrate, a gate opening is formed in the interlayer dielectric layer, sidewalls are formed on the sidewalls of the gate opening, a gate dielectric layer is formed on the top and sidewalls of the sidewalls, the top of the interlayer dielectric layer, and the bottom of the gate opening. In a direction perpendicular to the extending direction of the gate opening, the width of the gate opening in the first region is smaller than the width of the gate opening in the second region; a work function layer is formed to conformally cover the gate dielectric layer, and the work function layer in the first region also fills the remaining space in the gate opening. The work function layer in the second region covers the sidewalls and the bottom of the gate dielectric layer and exposes the remaining space of the gate opening; a gate electrode material layer is formed on the top of the work function layer, and the gate electrode material layer also fills the remaining space in the gate opening in the second region, and the top of the gate electrode material layer in the first region is higher than the top of the gate electrode material layer in the second region; a sacrificial layer is formed on the top of the gate electrode material layer in the second region, and the top of the sacrificial layer in the second region is flush with the top of the gate electrode material layer in the first region; after forming the sacrificial layer, the gate electrode material layer, the sacrificial layer, the work function layer, and the gate dielectric layer higher than the top of the interlayer dielectric layer are removed. The remaining gate electrode material layer in the gate opening in the second region serves as a gate electrode layer, the remaining gate dielectric layer and work function layer in the gate opening in the first region serve as a first metal gate structure, and the remaining gate dielectric layer, work function layer, and gate electrode layer in the gate opening in the second region serve as a second metal gate structure. Compared with the existing solution of directly removing all the gate electrode material layer in the first region after forming the gate electrode material layer in the first region and the second region, in the embodiments of the present invention, after forming the gate electrode material layer in the first region and the second region, a sacrificial layer is first formed on the top of the gate electrode material layer in the second region, and the top of the sacrificial layer in the second region is flush with the top of the gate electrode material layer in the first region. Therefore, when removing the gate electrode material layer and the sacrificial layer higher than the top of the work function layer subsequently, the sacrificial layer in the second region functions as a thickness compensation layer, making the thickness of the film layers to be removed in the first region and the second region equal, which is beneficial to improving the height uniformity of the remaining gate electrode material layer in the first region and the remaining gate electrode material layer in the second region, thereby improving the height uniformity and the top surface flatness of the first metal gate structure and the second metal gate structure, reducing the probability that the top surface of the second metal gate structure is damaged or dented, and correspondingly improving the performance of the semiconductor structure.

[0025] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0026] Figures 4 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of the manufacturing method of the semiconductor structure of the present invention.

[0027] Reference Figure 4 , a substrate is provided, the substrate includes a first region a and a second region b, an interlayer dielectric layer 103 is formed on the substrate, a gate opening 102 is formed in the interlayer dielectric layer 103, a spacer 161 is formed on the sidewall of the gate opening 102, and a gate dielectric layer 160 is formed on the top and sidewalls of the spacer 161, the top of the interlayer dielectric layer 103, and the bottom of the gate opening 102. In a direction perpendicular to the extending direction of the gate opening 102 (as shown by the X direction in Figure 4 ), the width W1 of the gate opening 102 in the first region a is smaller than the width W2 of the gate opening 102 in the second region b.

[0028] The substrate is used to provide a process platform for subsequent process steps.

[0029] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100.

[0030] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0031] In this embodiment, the material of the fins 101 is the same as the material of the substrate 100, and the material of the fins 101 is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide.

[0032] The spacer 161 is used to protect the sidewalls of the subsequently formed first metal gate structure and second metal gate structure. The spacer 161 can be a single-layer structure or a stacked structure, and the material of the spacer 161 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, and boron carbonitride. In this embodiment, the spacer 161 is a single-layer structure, and the material of the spacer 109 is silicon nitride.

[0033] In this embodiment, the material of the gate dielectric layer 160 is a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 160 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0034] In this embodiment, the substrate includes a first region a and a second region b, and the width W1 of the gate opening 102 in the first region a is smaller than the width W2 of the gate opening 102 in the second region b.

[0035] In this embodiment, the region of the substrate exposed by the gate opening 102 is the channel region, and the gate opening 102 is used to form a metal gate structure. Therefore, the width of the gate opening 102 is equal to the width of the metal gate structure to be formed (i.e., the gate width). Correspondingly, the width of the gate opening 102 is equal to the channel length of the device to be formed.

[0036] In this embodiment, the first region a is used to form a short channel device, and the second region b is used to form a long channel device. Among them, the gate width of the short channel device is smaller than that of the long channel device, that is, the channel length of the short channel device is smaller than that of the long channel device.

[0037] The gate opening 102 provides a spatial position for the subsequent formation of the first metal gate structure and the second metal gate structure.

[0038] In this embodiment, the gate opening 102 straddles the fin 101 and exposes part of the top and part of the sidewall of the fin 101.

[0039] In this embodiment, a metal gate structure is formed by a process of forming a high-k gate dielectric layer first and then a gate electrode layer (high k last metal gate last). Therefore, before forming the interlayer dielectric layer 103, it further includes: forming a dummy gate structure (not shown in the figure) on the substrate 100, and the dummy gate structure straddles the fin 101 and covers part of the top and part of the sidewall of the fin 101.

[0040] The dummy gate structure occupies a spatial position for the subsequent formation of the metal gate structure.

[0041] In this embodiment, the material of the dummy gate structure is amorphous silicon. In some other embodiments, the material of the dummy gate structure is polysilicon. In other embodiments, the material of the dummy gate structure can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, or amorphous carbon.

[0042] In this embodiment, after forming the dummy gate structure, an interlayer dielectric layer 103 is formed on the substrate, and the interlayer dielectric layer 103 covers the sidewalls of the dummy gate structure.

[0043] The interlayer dielectric layer 103 is used to isolate adjacent devices in the first region a and the second region b. The material of the interlayer dielectric layer 103 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 103 is silicon oxide.

[0044] Correspondingly, in this embodiment, the gate opening 102 is formed by removing the dummy gate structure.

[0045] It should be noted that after forming the dummy gate structure and before forming the interlayer dielectric layer 103, it further includes: forming source / drain doping layers (not shown in the figure) in the fins 101 on both sides of the dummy gate structure.

[0046] When the formed semiconductor device is a PMOS transistor, the material of the source / drain doping layer 105 is silicon germanide doped with P-type ions, and the P-type ions include B, Ga, or In. When the formed semiconductor device is an NMOS transistor, the material of the source / drain doping layer 105 is silicon carbide or silicon doped with N-type ions, and the N-type ions include P, As, or Sb.

[0047] Refer to Figure 5 , a work function layer 104 is formed to conformally cover the gate dielectric layer 160. The work function layer 104 in the first region a also fills the remaining space of the gate opening 102. The work function layer 104 in the second region b covers the sidewalls and the bottom of the gate dielectric layer 160 and exposes the remaining space of the gate opening 102.

[0048] The work function layer 104 is used to adjust the threshold voltage of the formed device.

[0049] According to the performance requirements of the device, the material of the work function layer 104 includes one or more of TiAl, TiAlC, TiN, TaN, TaSiN, TaAlN, and TiAlN.

[0050] Specifically, when forming a PMOS, the work function layer 104 is a P-type work function layer, and the material of the P-type work function layer includes one or several of TiN, TaN, TaSiN, TaAlN, and TiAlN. When forming an NMOS, the work function layer 104 is an N-type work function layer, and the material of the N-type work function layer includes one or several of TiAl, Mo, MoN, AlN, and TiAlC. As an example, in this embodiment, the material of the work function layer 104 includes one or two of TiN, TaN, TaSiN, TaAlN, and TiAlN.

[0051] In this embodiment, the steps of forming the work function layer 104 include: forming a work function material layer (not shown in the figure) with a preset thickness at the bottom and sidewalls of the gate opening 102 and on the top of the interlayer dielectric layer 103; removing the work function material layer that is higher than the top of the interlayer dielectric layer 103, and the remaining work function material layer serves as the work function layer 104.

[0052] Due to the continuous shrinking of the process node, in order to meet the requirement of improving the device electrical performance, the gate opening 102 in the first region a is continuously shrunk, while the work function layer 104 needs to reach a certain preset thickness to meet the electrical performance requirement. Therefore, the gate opening 102 in the first region a is filled with the work function layer 104.

[0053] Reference Figure 6 , a gate electrode material layer 105 is formed on the top of the work function layer 104. The gate electrode material layer 105 also fills the remaining space in the gate opening 102 of the second region b, and the top of the gate electrode material layer 105 in the first region a is higher than the top of the gate electrode material layer 105 in the second region b.

[0054] It should be noted that since the work function layer 104 occupies all the space of the gate opening 102 in the first region a, and the work function layer 104 in the second region b covers the sidewalls and the bottom of the gate dielectric layer 160 and exposes the remaining space of the gate opening 102, and when forming the gate electrode material layer 105, the gate electrode material layer 105 will be formed in both the first region a and the second region b simultaneously. Therefore, during the process of forming the gate electrode material layer 105, affected by the film thickness load effect, the top of the gate electrode material layer 105 in the first region a is higher than the top of the gate electrode material layer 105 in the second region b.

[0055] The gate electrode material layer 105 provides a process basis for forming the subsequent gate electrode layer.

[0056] The subsequently formed gate electrode layer is used for subsequent electrical connection with the external structure.

[0057] In this embodiment, the material of the gate electrode material layer 105 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

[0058] The materials TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC have excellent electrical conductivity characteristics. As an example, the material of the gate electrode material layer 105 is W.

[0059] Reference Figures 7 to 8, a sacrificial layer 107 is formed on top of the gate electrode material layer 105 in the second region b, and the top of the sacrificial layer 107 in the second region b is flush with the top of the gate electrode material layer 105 in the first region a.

[0060] In this embodiment, after the gate electrode material layer 105 is formed in the first region a and the second region b, a sacrificial layer 107 is first formed on top of the gate electrode material layer 105 in the second region b. The top of the sacrificial layer 107 in the second region b is flush with the top of the gate electrode material layer 105 in the first region a. Therefore, when subsequently removing the gate electrode material layer 105, the sacrificial layer 107, the work function layer 104, and the gate dielectric layer 160 that are higher than the top of the interlayer dielectric layer 103, the sacrificial layer 107 in the second region b acts as a thickness compensation layer, making the film layer thicknesses to be removed in the first region a and the second region b equal. This is conducive to improving the height uniformity of the remaining gate electrode material layer 105 in the first region a and the remaining gate electrode material layer 105 in the second region b, thereby improving the height uniformity and top surface flatness of the first metal gate structure and the second metal gate structure formed subsequently, reducing the probability that the top surface of the second metal gate structure is damaged or indented, and correspondingly improving the performance of the semiconductor structure.

[0061] In this embodiment, the step of forming the sacrificial layer 107 on top of the gate electrode material layer 105 in the second region b includes: as Figure 7 shown, a sacrificial material layer 106 is formed on top of the gate electrode material layer 105, and the top of the sacrificial material layer 106 in the first region a is higher than the top of the sacrificial material layer 106 in the second region b; as Figure 8 shown, the sacrificial material layer 106 in the first region a and a part of the thickness of the sacrificial material layer 106 in the second region b are removed, so that the top of the remaining sacrificial material layer 106 in the second region b is flush with the top of the gate electrode material layer 105 in the first region a, and the remaining sacrificial material layer 106 serves as the sacrificial layer 107.

[0062] The top of the sacrificial layer 107 in the second region b is flush with the top of the gate electrode material layer 105 in the first region a, improving the height uniformity and top surface flatness of the first metal gate structure and the second metal gate structure formed subsequently.

[0063] In this embodiment, in the step of forming the sacrificial layer 107, the material of the sacrificial layer 107 includes one or more of silicon oxide, silicon oxynitride, and silicon carbon oxynitride.

[0064] The silicon oxide, silicon oxynitride, and silicon carbon oxynitride have characteristics such as high material hardness and etching resistance. Moreover, the material of the gate electrode material layer 105 also has a relatively high hardness, which is beneficial for uniformly and effectively controlling the etching rate of the gate electrode material layer 105 and the sacrificial layer 107 above the top of the interlayer dielectric layer 103 in subsequent steps, so as to greatly improve the height uniformity and top surface flatness of the first metal gate structure and the second metal gate structure formed subsequently.

[0065] Furthermore, in the subsequent step of removing the gate electrode material layer 105 and the sacrificial layer 107 above the top of the gate electrode material layer 105 in the second region b, different etching gases have different etching selectivity ratios for the gate electrode material layer 105 and the sacrificial layer 107. By selecting a suitable etching gas and suitable etching parameters, the etching selectivity ratios between the gate electrode material layer 105 and the sacrificial layer 107 are made close to each other, thereby greatly improving the height uniformity and top surface flatness of the first metal gate structure and the second metal gate structure formed subsequently.

[0066] Reference Figures 7 to 8 , in this embodiment, the step of removing the sacrificial material layer 106 in the first region a and a part of the thickness of the sacrificial material layer 106 in the second region b includes: performing planarization on the sacrificial material layer 106 in the first region a and the second region b with the top of the gate electrode material layer 105 in the first region a as the stop position.

[0067] Since the top of the gate electrode material layer 105 in the first region a is higher than the top of the gate electrode material layer 105 in the second region b, after performing planarization with the top of the gate electrode material layer 105 in the first region a as the stop position, there is still a part of the thickness of the sacrificial material layer 106 remaining on the top of the gate electrode material layer 105 in the second region b, which is easy to make the top of the gate electrode material layer 105 in the first region a flush with the top of the sacrificial layer 107 in the second region b.

[0068] Moreover, the material of the gate electrode material layer 105 is a metal material, and the material of the gate electrode material layer 105 usually has a relatively high hardness. Therefore, it is easy for the top of the gate electrode material layer 105 in the first region a to be used as the stop position for planarization.

[0069] In this embodiment, the process of the planarization includes a chemical mechanical polishing process.

[0070] The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing. It can obtain a relatively flat surface while ensuring the material removal efficiency, and has the characteristics of high surface accuracy, good integrity, and high polishing efficiency. This is beneficial for making the remaining sacrificial material layer 106 (i.e., sacrificial layer 107) flush with the top of the gate electrode material layer 105 in the first region a during the process of removing the sacrificial material layer 106 in the first region a and a part of the thickness of the sacrificial material layer 106 in the second region b, thereby improving the top surface flatness of the first region a and the second region b.

[0071] In this embodiment, the thickness of the sacrificial material layer 106 is 100 nanometers to 300 nanometers.

[0072] It should be noted that the thickness of the sacrificial material layer 106 should not be too large or too small. If the thickness of the sacrificial material layer 106 is too large, it will increase the difficulty of removing the sacrificial material layer 106 subsequently, increase the process cost, and at the same time make the height of the transistor too high, increasing the probability of tipping over and reducing the reliability of the semiconductor structure, thus affecting the performance of the semiconductor structure; if the thickness of the sacrificial material layer 106 is too small, it will be difficult to provide sufficient thickness margin during the planarization process of the sacrificial material layer 106 in the first region a and the second region b, easily resulting in poor top surface flatness between the top of the sacrificial layer 107 in the second region b and the top of the gate electrode material layer 105 in the first region a subsequently, and correspondingly making it difficult for the sacrificial layer 107 to play the role of a thickness compensation layer well, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the sacrificial material layer 106 is 100 nanometers to 300 nanometers. For example, the thickness of the sacrificial material layer 106 is 150 nanometers, 200 nanometers, and 250 nanometers.

[0073] In this embodiment, the process of forming the sacrificial material layer 106 on the top of the gate electrode material layer 105 includes a chemical vapor deposition process.

[0074] The chemical vapor deposition process has the characteristics of simple operation, low process cost, and good filling performance, which is beneficial for making the sacrificial material layer 106 formed on the top of the gate electrode material layer 105 meet the process requirements.

[0075] Reference Figures 9 to 10, after forming the sacrificial layer 107, the gate electrode material layer 105, the sacrificial layer 107, the work function layer 104, and the gate dielectric layer 160 above the top of the interlayer dielectric layer 103 are removed. The remaining gate electrode material layer 105 in the gate opening 102 in the second region b serves as the gate electrode layer 108, and the remaining gate dielectric layer 160 and work function layer 104 in the gate opening 102 in the first region a serve as the first metal gate structure 200 (as Figure 10 shown), and the remaining gate dielectric layer 160, work function layer 104, and gate electrode layer 108 in the gate opening 102 in the second region b serve as the second metal gate structure 109.

[0076] The first metal gate structure 200 and the second metal gate structure 109 are used to control the opening or closing of the conductive channel.

[0077] In this embodiment, the steps of removing the gate electrode material layer 105, the sacrificial layer 107, the work function layer 104, and the gate dielectric layer 160 above the top of the interlayer dielectric layer 103 include: as Figure 9 shown, removing the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a, so that the top of the remaining gate electrode material layer 105 in the second region b is flush with the top of the remaining gate electrode material layer 105 in the first region a; as Figure 10 shown, after removing the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a, removing the remaining gate electrode material layer 105, the work function layer 104, and the gate dielectric layer 160 above the top of the interlayer dielectric layer 103.

[0078] Removing the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a makes the top of the remaining gate electrode material layer 105 in the second region b flush with the top of the remaining gate electrode material layer 105 in the first region a, thus preparing for the subsequent removal of the remaining gate electrode material layer 105, the work function layer 104, and the gate dielectric layer 160 above the top of the interlayer dielectric layer 103, and making the top surfaces of the gate electrode layers in the second region b and the first region a have high flatness.

[0079] In this embodiment, the steps of removing the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a include: using the top of the gate electrode material layer 105 in the second region b as the stop position, etching to remove the sacrificial layer 107 and a part of the thickness of the gate electrode material layer 105 in the first region a.

[0080] Compared with using a planarization process, using an etching method is easier to control the etching selectivity between the gate electrode material layer 105 and the sacrificial layer 107, making the etching rates of the two close to each other, so that the height uniformity of the remaining gate electrode material layer 105 in the first region a and the gate electrode material layer 105 in the second region b can be better achieved.

[0081] Specifically, an etching method without a mask is used for etching, so as to etch the gate electrode material layer 105 and the sacrificial layer 107 simultaneously.

[0082] In this embodiment, the process of removing the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a includes a dry etching process.

[0083] The dry etching has a good etching effect and can accurately control the etching uniformity, making the top surface flatness of the first region a and the second region b better, thereby improving the performance of the semiconductor structure.

[0084] It should be noted that the dry etching process is a plasma dry etching process. That is, in the process of removing the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a, the plasma dry etching process directly reacts physically with the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a, so as to remove the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a.

[0085] In this embodiment, the etching gas of the dry etching process includes one or more of CF4, CHF3, C4F6 and Cl2.

[0086] The etching gases CF4, CHF3, C4F6 and Cl2 can etch the gate electrode material layer 105 and the sacrificial layer 107 simultaneously, and during the process of removing the sacrificial layer 107 in the second region b and a part of the thickness of the gate electrode material layer 105 in the first region a, the etching selectivity between the sacrificial layer 107 and the gate electrode material layer 105 is adjustable.

[0087] In this embodiment, the radio frequency power of the dry etching process includes 900W to 1100W.

[0088] Specifically, the RF power of the dry etching process should not be too large or too small. If the RF power of the dry etching process is too large, it is easy to cause the etching rate to be too fast in the process of removing the sacrificial layer 107 in the second region b and the gate electrode material layer 105 of a partial thickness in the first region a, thereby increasing the difficulty of improving the height uniformity of the remaining gate electrode material layer 105 in the first region a and the gate electrode material layer 105 in the second region b; if the RF power of the dry etching process is too small, it is easy to cause the etching rate to be too slow, thereby reducing the process efficiency and affecting the production capacity. For this reason, in this embodiment, the RF power of the dry etching process includes 900W to 1100W.

[0089] In this embodiment, in the step of etching away the sacrificial layer 107 and a portion of the gate electrode material layer 105 in the first region a, the etching selectivity ratio between the sacrificial layer 107 and the gate electrode material layer 105 is 0.5:1 to 2:1.

[0090] It should be noted that, since the material of the gate electrode material layer 105 is inconsistent with the material of the sacrificial layer 107, the etching selectivity between the sacrificial layer 107 and the gate electrode material layer 105 is too large or too small, which may easily lead to the thickness of the sacrificial layer 107 removed being inconsistent with the thickness of the gate electrode material layer 105 removed in the first area a, thereby affecting the top surface flatness of the first metal gate structure 200 and the second metal gate structure 109, thereby affecting the performance of the semiconductor structure. In order to make the thickness of the sacrificial layer 107 removed consistent with the thickness of the gate electrode material layer 105 removed in the first area a, in this embodiment, the etching selectivity between the sacrificial layer 107 and the gate electrode material layer 105 is 0.5:1 to 2:1.

[0091] refer to Figure 10 In this embodiment, the step of removing the remaining gate electrode material layer 105, the work function layer 104 and the gate dielectric layer 160 above the top of the interlayer dielectric layer 103 includes: taking the top of the interlayer dielectric layer 103 as the stopping position, and performing a planarization process on the gate electrode material layer 105, the work function layer 104 and the gate dielectric layer 160.

[0092] Specifically, with the top of the interlayer dielectric layer 103 as the stopping position, the gate electrode material layer 105, the work function layer 104 and the gate dielectric layer 160 are planarized, which not only meets the process requirements of the preset height of the first metal gate structure 200 and the second metal gate structure 109, but also improves the top surface flatness of the first metal gate structure and the second metal gate structure.

[0093] The planarization process includes a chemical mechanical polishing process.

[0094] The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing. It can obtain a relatively flat surface while ensuring the material removal efficiency, and has the characteristics of high surface accuracy, good integrity and high polishing efficiency. This is beneficial for improving the height uniformity and top surface flatness of the first metal gate structure 200 and the second metal gate structure 109 during the process of removing the gate electrode material layer 105, the work function layer 104 and the gate dielectric layer 160 on the top of the interlayer dielectric layer 103. At the same time, it also reduces the probability of damage or depression on the top surface of the second metal gate structure 109, thereby improving the performance of the semiconductor structure.

[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate includes a first region and a second region, an interlayer dielectric layer is formed on the substrate, a gate opening is formed in the interlayer dielectric layer, sidewalls are formed on the sidewalls of the gate opening, a gate dielectric layer is formed on the top and sidewalls of the sidewalls, the top of the interlayer dielectric layer, and the bottom of the gate opening. In a direction perpendicular to the extending direction of the gate opening, the width of the gate opening in the first region is smaller than the width of the gate opening in the second region; Forming a work function layer that conformally covers the gate dielectric layer. The work function layer in the first region also fills the remaining space in the gate opening. The work function layer in the second region covers the sidewalls and the bottom of the gate dielectric layer and exposes the remaining space of the gate opening; Forming a gate electrode material layer on the top of the work function layer. The gate electrode material layer also fills the remaining space in the gate opening of the second region, and the top of the gate electrode material layer in the first region is higher than the top of the gate electrode material layer in the second region; Forming a sacrificial layer on the top of the gate electrode material layer in the second region. The top of the sacrificial layer in the second region is flush with the top of the gate electrode material layer in the first region; After forming the sacrificial layer, removing the gate electrode material layer, the sacrificial layer, the work function layer, and the gate dielectric layer that are higher than the top of the interlayer dielectric layer. The remaining gate electrode material layer in the gate opening in the second region serves as the gate electrode layer. The remaining gate dielectric layer and work function layer in the gate opening in the first region serve as the first metal gate structure. The remaining gate dielectric layer, work function layer, and gate electrode layer in the gate opening in the second region serve as the second metal gate structure.

2. The method for forming a semiconductor structure according to claim 1, wherein The step of forming a sacrificial layer on the top of the gate electrode material layer in the second region includes: Forming a sacrificial material layer on the top of the gate electrode material layer, and the top of the sacrificial material layer in the first region is higher than the top of the sacrificial material layer in the second region; Removing the sacrificial material layer in the first region and a part of the thickness of the sacrificial material layer in the second region, so that the top of the remaining sacrificial material layer in the second region is flush with the top of the gate electrode material layer in the first region, and the remaining sacrificial material layer serves as the sacrificial layer.

3. The method for forming a semiconductor structure according to claim 2, wherein The step of removing the sacrificial material layer in the first region and a part of the thickness of the sacrificial material layer in the second region includes: Using the top of the gate electrode material layer in the first region as the stop position, performing planarization processing on the sacrificial material layers in the first region and the second region.

4. The method for forming a semiconductor structure according to claim 1, wherein The step of removing the gate electrode material layer, the sacrificial layer, the work function layer, and the gate dielectric layer that are higher than the top of the interlayer dielectric layer includes: Removing the sacrificial layer in the second region and a part of the thickness of the gate electrode material layer in the first region, so that the top of the gate electrode material layer in the second region is flush with the top of the remaining gate electrode material layer in the first region; After removing the sacrificial layer in the second region and a part of the thickness of the gate electrode material layer in the first region, removing the remaining gate electrode material layer, work function layer, and gate dielectric layer that are higher than the top of the interlayer dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein, The steps of removing the sacrificial layer in the second region and the gate electrode material layer with a partial thickness in the first region include: etching to remove the sacrificial layer and the gate electrode material layer with a partial thickness in the first region, with the top of the gate electrode material layer in the second region as the stopping position.

6. The method for forming a semiconductor structure according to claim 4 or 5, characterized in that, The process of removing the sacrificial layer in the second region and the gate electrode material layer with a partial thickness in the first region includes a dry etching process.

7. The method for forming a semiconductor structure according to claim 4, wherein, The steps of removing the remaining gate electrode material layer, work function layer, and gate dielectric layer above the top of the interlayer dielectric layer include: planarizing the gate electrode material layer, work function layer, and gate dielectric layer with the top of the interlayer dielectric layer as the stopping position.

8. The method for forming a semiconductor structure according to claim 3 or 7, wherein The process of the planarization treatment includes a chemical mechanical polishing process.

9. The method for forming a semiconductor structure according to claim 5, wherein In the step of etching to remove the sacrificial layer and the gate electrode material layer with a partial thickness in the first region, the etching selectivity between the sacrificial layer and the gate electrode material layer is 0.5:1 to 2:

1.

10. The method for forming a semiconductor structure according to claim 6, wherein, The parameters of the dry etching process include: the etching gas includes one or more of CF4, CHF3, C4F6, and Cl2; the radio frequency power is 900 W to 1100 W.

11. The method for forming a semiconductor structure according to claim 2, wherein In the step of forming a sacrificial material layer on the top of the gate electrode material layer, the thickness of the sacrificial material layer is 100 nanometers to 300 nanometers.

12. The method for forming a semiconductor structure according to claim 2, wherein, The process of forming a sacrificial material layer on the top of the gate electrode material layer includes a chemical vapor deposition process.

13. The method for forming a semiconductor structure as claimed in claim 1, wherein In the step of forming the sacrificial layer, the material of the sacrificial layer includes one or more of silicon oxide, silicon oxynitride, and carbon oxynitride.

14. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the work function layer, the material of the work function layer includes one or more of TiAl, TiAlC, TiN, TaN, TaSiN, TaAlN, and TiAlN.

15. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the gate electrode material layer, the material of the gate electrode material layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

16. The method for forming a semiconductor structure according to claim 1, wherein, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

17. The method for forming a semiconductor structure according to claim 1, wherein, The material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon carbide, carbon silicon nitride, carbon oxynitride, silicon oxynitride, boron nitride, and carbon boron nitride.

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