Semiconductor memory device
By setting a wide portion and a narrow portion in the charge accumulation layer and setting a high dielectric constant layer in between, the problem of insufficient electrostatic capacitance in semiconductor memory devices is solved, thereby improving the reliability and speed of the memory.
CN115132744BActive Publication Date: 2026-06-09KIOXIA CORP
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2021-08-13
- Publication Date
- 2026-06-09
AI Technical Summary
Technical Problem
In the integration process of existing semiconductor memory devices, the electrostatic capacitance between the charge storage layer and the semiconductor layer is insufficient, which affects the reliability and speed of the memory.
Method used
The design incorporates a wide and narrow section within the charge accumulation layer, with a high dielectric constant layer placed between them. This increases the area of the charge accumulation layer relative to the semiconductor layer, thereby improving the electrostatic capacitance.
Benefits of technology
By increasing the electrostatic capacitance, the efficiency of write and erase operations in the memory is improved, thereby enhancing the reliability and speed of the memory.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN115132744B_ABST
Abstract
Embodiments provide a semiconductor memory device capable of achieving high integration. The semiconductor memory device of the embodiments includes: a first conductive layer extending in a first direction; a second conductive layer extending in the first direction and arranged side by side with the first conductive layer in a second direction; a first insulating layer provided between the first conductive layer and the second conductive layer; a semiconductor layer extending in the second direction and arranged opposite the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge accumulation layer provided between the first conductive layer and the semiconductor layer; a second charge accumulation layer provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer provided between the first conductive layer and the first charge accumulation layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge accumulation layer. At least a portion of the first charge accumulation layer is arranged opposite the second charge accumulation layer in the second direction without the second high dielectric constant layer therebetween.
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