Display panel and manufacturing method of display panel

Abstract

This application discloses a display panel and a method for manufacturing the display panel. The thin-film transistor includes: a first gate disposed on a substrate; a first gate insulating layer disposed on the first gate; a semiconductor layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the semiconductor layer; a second gate disposed on the second gate insulating layer; a source and a drain disposed on the second gate; wherein the semiconductor layer includes a channel region corresponding to the second gate, a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region; the first transport region and the second transport region are made of the same material as the channel region, and the electrical signals of the first gate and the second gate have the same potential. In the display panel of this application embodiment, the first transport region and the second transport region are exempt from ion implantation, reducing the manufacturing time of the display panel and simplifying the process.

Description

Technical Field

[0001] This application relates to the field of displays, specifically to a display panel and a method for manufacturing the display panel. Background Technology

[0002] With the development of display technology, display panels have been widely used in people's lives, such as the display screens of mobile phones and computers. In the manufacturing process of thin-film transistors in display panels, it is necessary to perform heavy doping (N+) and light doping (N-) processes on the semiconductor layer, which requires ion implantation.

[0003] However, the doping or ion implantation process of thin-film transistors in existing display panels is time-consuming and generally ineffective. Furthermore, the lightly doped areas limit the current in the thin-film transistors, which is not conducive to driving current-driven display devices such as miniature light-emitting diodes (Min-LED, Mico-LED, etc.). Summary of the Invention

[0004] This application provides a display panel and a method for manufacturing the display panel, which can solve the problems of long time and mediocre effect of doping or ion implantation process of thin film transistors in existing display panels. In addition, the light doping site limits the current in the thin film transistor, which is not conducive to driving current-driven display devices such as micro light-emitting diodes (Min-LED, Micro-LED, etc.).

[0005] This application provides a display panel, including a substrate and a plurality of thin-film transistors disposed on the substrate, the thin-film transistors including:

[0006] A first gate is disposed on the substrate;

[0007] A first gate insulating layer is disposed on the first gate;

[0008] A semiconductor layer is disposed on the first gate insulating layer;

[0009] A second gate insulating layer is disposed on the semiconductor layer;

[0010] The second gate is disposed on the second gate insulating layer;

[0011] The source and drain are disposed on the second gate;

[0012] The semiconductor layer includes a channel region corresponding to the second gate, a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region.

[0013] The first transmission region and the second transmission region are made of the same material as the channel region. The orthographic projection of the first gate on the substrate covers the orthographic projections of the source region, the drain region, the first transmission region, the channel region, and the second transmission region on the substrate. The electrical signals of the first gate and the second gate have the same potential.

[0014] Optionally, in some embodiments of this application, both the source region and the drain region include doped elements.

[0015] Optionally, in some embodiments of this application, the source region and the drain region are made of the same material as the channel region.

[0016] Optionally, in some embodiments of this application, it further includes:

[0017] An interlayer insulating layer is disposed between the source, the drain and the second gate;

[0018] The connecting electrode is disposed in the same layer as the source electrode and the drain electrode and is made of the same material;

[0019] The first through-hole penetrates the interlayer insulation layer;

[0020] The second via penetrates the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. The connection electrode is electrically connected to the second gate and the first gate through the first via and the second via, respectively.

[0021] Optionally, in some embodiments of this application, the material of the semiconductor layer includes polycrystalline silicon or semiconductor oxide.

[0022] Optionally, in some embodiments of this application, the orthogonal projection of the semiconductor layer on the substrate covers the orthogonal projection of the second gate on the substrate, and the display panel further includes:

[0023] The third via penetrates the interlayer insulating layer and the second gate insulating layer, and the source is electrically connected to the semiconductor layer through the third via;

[0024] The fourth via penetrates the interlayer insulating layer and the second gate insulating layer, and the drain is electrically connected to the semiconductor layer through the fourth via.

[0025] Optionally, in some embodiments of this application, the display panel further includes a plurality of micro light-emitting diodes electrically connected to the thin-film transistor.

[0026] Accordingly, embodiments of this application also provide a method for manufacturing a display panel, comprising:

[0027] Provide a base;

[0028] A first gate is formed on the substrate;

[0029] A first gate insulating layer is formed on the first gate;

[0030] A semiconductor layer is formed on the first gate insulating layer;

[0031] A second gate insulating layer is formed on the semiconductor layer;

[0032] A second gate is formed on the second gate insulating layer, and the semiconductor layer includes a channel region corresponding to the second gate;

[0033] An interlayer insulating layer is formed on the second gate;

[0034] A source and a drain are formed on the interlayer insulating layer to obtain a thin-film transistor. The semiconductor layer further includes a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region. The first transport region and the second transport region are made of the same material as the channel region. The orthographic projection of the first gate on the substrate covers the orthographic projections of the source region, the drain region, the first transport region, the channel region, and the second transport region on the substrate. The first gate and the second gate are electrically connected.

[0035] Optionally, in some embodiments of this application, it further includes:

[0036] The process of forming the interlayer insulating layer further includes: forming a first via through the interlayer insulating layer, and a second via through the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer;

[0037] In forming the source and the drain, a connection electrode is also formed simultaneously, wherein the connection electrode is electrically connected to the second gate and the first gate through the first via and the second via, respectively.

[0038] Optionally, in some embodiments of this application, both the source region and the drain region include doped elements; or both the source region and the drain region are made of the same material as the channel region.

[0039] This application provides a display panel and a method for manufacturing the display panel. The display panel includes a substrate and a plurality of thin-film transistors disposed on the substrate. The thin-film transistors include: a first gate disposed on the substrate; a first gate insulating layer disposed on the first gate; a semiconductor layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the semiconductor layer; a second gate disposed on the second gate insulating layer; a source and a drain disposed on the second gate; wherein the semiconductor layer includes a channel region corresponding to the second gate, a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region; the first transport region and the second transport region are made of the same material as the channel region; the orthographic projection of the first gate on the substrate covers the orthographic projections of the source region, the drain region, the first transport region, the channel region, and the second transport region on the substrate; and the electrical signals of the first gate and the second gate have the same potential. In the display panel of this application embodiment, the first transmission region and the second transmission region are made of the same material as the channel region, that is, the first transmission region and the second transmission region are exempt from ion implantation, which reduces the manufacturing time of the display panel and simplifies the process. The conduction current and leakage current of the first transmission region and the second transmission region are controlled by the first gate. The orthogonal projection of the first gate on the substrate covers the orthogonal projections of the source region, the drain region, the first transmission region, the channel region and the second transmission region on the substrate. The electrical signals of the first gate and the second gate have the same potential. The first gate can control the opening and closing of the current in the first transmission region and the second transmission region, which can improve the current magnitude or mobility in the thin film transistor. This makes the thin film transistor in this application embodiment have good opening and closing performance at the same time, which is beneficial to the driving of current-driven display devices. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a first cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0042] Figure 2 This is a second cross-sectional schematic diagram of a display panel provided in one embodiment of this application;

[0043] Figure 3 A schematic flowchart illustrating the manufacturing steps of a display panel according to an embodiment of this application;

[0044] Figure 4A schematic diagram of a first intermediate process of a method for manufacturing a display panel according to an embodiment of this application;

[0045] Figure 5 A schematic diagram of a second intermediate process of a method for manufacturing a display panel according to an embodiment of this application;

[0046] Figure 6 A schematic diagram of a third intermediate process in a method for manufacturing a display panel according to an embodiment of this application;

[0047] Figure 7 A schematic diagram of the fourth intermediate process of a method for manufacturing a display panel according to an embodiment of this application;

[0048] Figure 8 A schematic diagram of the fifth intermediate process of a method for manufacturing a display panel according to an embodiment of this application;

[0049] Figure 9 This is a schematic diagram of the sixth intermediate process of a method for manufacturing a display panel according to an embodiment of this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0051] This application provides a display panel, which includes a substrate and a plurality of thin-film transistors disposed on the substrate. The thin-film transistors include: a first gate disposed on the substrate; a first gate insulating layer disposed on the first gate; a semiconductor layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the semiconductor layer; a second gate disposed on the second gate insulating layer; a source and a drain disposed on the second gate; wherein the semiconductor layer includes a channel region corresponding to the second gate, a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region; the first transport region and the second transport region are made of the same material as the channel region, and the orthographic projection of the first gate on the substrate covers the orthographic projections of the source region, the drain region, the first transport region, the channel region, and the second transport region on the substrate, and the electrical signals of the first gate and the second gate have the same potential.

[0052] This application also provides a method for manufacturing a display panel. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0053] Example 1

[0054] Please see Figure 1 and Figure 2 , Figure 1 This is a first cross-sectional schematic diagram of a display panel provided in an embodiment of this application; Figure 2 This is a second cross-sectional schematic diagram of a display panel provided in an embodiment of this application. Figure 2 and Figure 1 The same, the difference is Figure 2 The diagram illustrates two locations of the connecting electrode 183, which is connected to other locations in the plan view or top view.

[0055] This application provides a display panel 100, which includes a substrate 11 and a plurality of thin-film transistors 101 disposed on the substrate 11. Each thin-film transistor 101 includes a first gate 12, a first gate insulating layer 13, a semiconductor layer 14, a second gate insulating layer 15, and a second gate 16. The first gate 12 is disposed on the substrate 11; the first gate insulating layer 13 is disposed on the first gate 12; the semiconductor layer 14 is disposed on the first gate insulating layer 13; the second gate insulating layer 15 is disposed on the semiconductor layer 14; the second gate 16 is disposed on the second gate insulating layer 15; a source 181 and a drain 182 are disposed on the second gate 16; wherein the semiconductor layer 14 includes a channel region 141 corresponding to the second gate 16, a source region 142 corresponding to the source 181, a drain region 143 corresponding to the drain 182, and a channel region 141 located on the second gate 16. The first transmission region 144 is located between the source region 142 and the channel region 141, and the second transmission region 145 is located between the drain region 143 and the channel region 141. The first transmission region 144 and the second transmission region 145 are made of the same material as the channel region 141. The orthogonal projection of the first gate 12 on the substrate 11 covers the orthogonal projections of the source region 142, the drain region 143, the first transmission region 144, the channel region 141 and the second transmission region 145 on the substrate 11. The electrical signals of the first gate 12 and the second gate 16 have the same potential.

[0056] Specifically, the thin-film transistor 101 includes a first gate 12, a first gate insulating layer 13, a semiconductor layer 14, a second gate insulating layer 15, and a second gate 16. The thin-film transistor 101 may also include other structures, which are not limited here.

[0057] Specifically, a first gate 12 is disposed on a substrate 11; a first gate insulating layer 13 is disposed on the first gate 12; a semiconductor layer 14 is disposed on the first gate insulating layer 13; a second gate insulating layer 15 is disposed on the semiconductor layer 14; a second gate 16 is disposed on the second gate insulating layer 15; and a source 181 and a drain 182 are disposed on the second gate 16. That is, the first gate 12, the first gate insulating layer 13, the semiconductor layer 14, the second gate insulating layer 15, the second gate 16, and the source 181 / drain 182 are stacked sequentially.

[0058] Specifically, the semiconductor layer 14 includes a channel region 141 corresponding to the second gate 16, a source region 142 corresponding to the source 181, a drain region 143 corresponding to the drain 182, a first transport region 144 located between the source region 142 and the channel region 141, and a second transport region 145 located between the drain region 143 and the channel region 141. That is, the channel region 141 refers to the region where the semiconductor layer 14 overlaps with the second gate 16; the source 181 at least partially overlaps with the source region 142; the drain 182 at least partially overlaps with the drain region 143; the portion between the source region 142 and the channel region 141 of the semiconductor layer 14 is the first transport region 144; and the portion between the drain region 143 and the channel region 141 of the semiconductor layer 14 is the second transport region 145.

[0059] Specifically, the source 181 and the drain 182 are formed by patterning the source and drain metal layers 18.

[0060] Specifically, the orthogonal projection of the first gate 12 on the substrate 11 covers the orthogonal projections of the source region 142, drain region 143, first transport region 144, channel region 141, and second transport region 145 on the substrate 11, that is, the first gate 12 is completely overlapped with the source region 142, drain region 143, first transport region 144, channel region 141, and second transport region 145.

[0061] Specifically, further, the orthogonal projection of the first gate 12 on the substrate 11 covers the orthogonal projection of the semiconductor layer 14 on the substrate 11.

[0062] Specifically, the electrical signals of the first gate 12 and the second gate 16 have the same potential, that is, the first gate 12 and the second gate 16 are electrically connected, or the first gate 12 and the second gate 16 are supplied with the same electrical signal through different traces.

[0063] Specifically, the electrical signals of the first gate 12 and the second gate 16 have the same potential. That is, when the thin-film transistor 101 is turned on, the electrical signals of the first gate 12 and the second gate 16 have the same potential, and when the thin-film transistor 101 is turned off, the electrical signals of the first gate 12 and the second gate 16 have the same potential.

[0064] Specifically, the first transport region 144 and the second transport region 145 are made of the same material as the channel region 141, that is, the first transport region 144 and the second transport region 145 are not lightly doped, thus avoiding the ion implantation process.

[0065] In this embodiment, the first transmission region 144 and the second transmission region 145 are made of the same material as the channel region 141, meaning that the first transmission region 144 and the second transmission region 145 are exempt from ion implantation. The conduction current and leakage current of the first transmission region 144 and the second transmission region 145 are controlled by the first gate 12. The orthogonal projection of the first gate 12 on the substrate 11 covers the orthogonal projections of the source region 142, the drain region 143, the first transmission region 144, the channel region 141, and the second transmission region 145 on the substrate 11. The electrical signals of the first gate 12 and the second gate 16 have the same potential. The first gate 12 can control the opening and closing of the current in the first transmission region 144 and the second transmission region 145, which can increase the current in the thin film transistor 101. This allows the thin film transistor 101 in this embodiment to have good opening and closing performance, which is beneficial for driving current-driven display devices.

[0066] Specifically, the first transmission area 144 and the second transmission area 145 are made of the same material as the channel area 141, that is, the first transmission area 144 and the second transmission area 145 are exempt from ion implantation, which can also simplify the manufacturing process of the display panel 100.

[0067] Specifically, a current-driven display device can be a display device with a backlight including miniature light-emitting diodes (Min-LED, Micro-LED, etc.), or a display device with display pixels including miniature light-emitting diodes (Min-LED, Micro-LED, etc.), without limitation.

[0068] Example 2

[0069] This embodiment is the same as or similar to Embodiment 1, except that the features of the display panel 100 are further defined.

[0070] In some embodiments, both the source region 142 and the drain region 143 include doped elements.

[0071] Specifically, the source region 142 and the drain region 143 can reduce the contact resistance or on-resistance between the source 181 and the source region 142, and can reduce the contact resistance or on-resistance between the drain 182 and the drain region 143.

[0072] Specifically, the second gate 16 and the semiconductor layer 14 do not need to undergo ion implantation using the self-aligned process of the second gate 16, which can save one process step.

[0073] Example 3

[0074] This embodiment is the same as or similar to Embodiment 1, except that the features of the display panel 100 are further defined.

[0075] In some embodiments, the source region 142 and the drain region 143 are made of the same material as the channel region 141.

[0076] Specifically, the source region 142 and the drain region 143 are made of the same material as the channel region 141, that is, the source region 142 and the drain region 143 are not heavily doped (N+), and the source region 142 and the drain region 143 are exempt from the ion implantation process, which further reduces the manufacturing process of the display panel 100.

[0077] Specifically, in the prior art, when the ion implantation process of the first transmission region 144 and the second transmission region 145 is the same as the ion implantation process of the source region 142 and the drain region 143, this embodiment reduces one process or photomask and simplifies the manufacturing process.

[0078] Specifically, in the prior art, when the ion implantation process of the first transmission region 144 and the second transmission region 145 is different from the ion implantation process of the source region 142 and the drain region 143, this embodiment reduces two processes or photomasks, simplifying the manufacturing process.

[0079] Specifically, since the first transmission region 144 and the second transmission region 145 are made of the same material as the channel region 141, the conduction current and turn-off leakage current performance of the first transmission region 144 and the second transmission region 145 can be controlled by the first gate 12, which can improve the current magnitude in the thin film transistor 101. Therefore, the source region 142 and the drain region 143 do not need to undergo ion implantation. At the same time, the first gate 12 can also control or improve the current magnitude of the source region 142 and the drain region 143 when the thin film transistor 101 is turned on.

[0080] Example 4

[0081] This embodiment is the same as or similar to the display panel 100 in any of the above embodiments, except that the features of the display panel 100 are further defined.

[0082] In some embodiments, the display panel 100 further includes an interlayer insulating layer 17, a connecting electrode 183, a first through-hole 1831, and a second through-hole 1832. The interlayer insulating layer 17 is disposed between the source electrode 181, the drain electrode 182, and the second gate electrode 16. The connecting electrode 183 is disposed in the same layer as the source electrode 181 and the drain electrode 182 and is made of the same material. The first through-hole 1831 penetrates the interlayer insulating layer 17. The second through-hole 1832 penetrates the interlayer insulating layer 17, the second gate insulating layer 15, and the first gate insulating layer 13. The connecting electrode 183 is electrically connected to the second gate electrode 16 and the first gate electrode 12 through the first through-hole 1831 and the second through-hole 1832, respectively.

[0083] Specifically, the interlayer insulating layer 17 is disposed between the source 181, the drain 182 and the second gate 16, so that the source 181, the drain 182 and the second gate 16 are insulated from each other.

[0084] Specifically, the connecting electrode 183 is disposed in the same layer as the source electrode 181 and the drain electrode 182 and is made of the same material. That is, the connecting electrode 183 is formed in the same process as the source electrode 181 and the drain electrode 182, for example, by patterning the same metal layer.

[0085] Specifically, the connecting electrode 183, source 181 and drain 182 are formed by patterning the source and drain metal layers 18.

[0086] Specifically, the connecting electrode 183 is electrically connected to the second gate 16 and the first gate 12 through the first through hole 1831 and the second through hole 1832 respectively, so that the second gate 16 and the first gate 12 are electrically connected, and the second gate 16 and the first gate 12 can be supplied with electrical signals of the same potential through the scan line.

[0087] In some embodiments, the material of the semiconductor layer 14 includes polycrystalline silicon or semiconductor oxide.

[0088] Specifically, polycrystalline silicon (e.g., low-temperature polycrystalline silicon) or semiconductor oxide is suitable for the structure of the thin-film transistor 101 in the embodiments of this application.

[0089] In some embodiments, the orthogonal projection of the semiconductor layer 14 on the substrate 11 covers the orthogonal projection of the second gate 16 on the substrate 11. The display panel 100 further includes a third via 1811 and a fourth via 1821. The third via 1811 penetrates the interlayer insulating layer 17 and the second gate insulating layer 15, and the source 181 is electrically connected to the semiconductor layer 14 through the third via 1811. The fourth via 1821 penetrates the interlayer insulating layer 17 and the second gate insulating layer 15, and the drain 182 is electrically connected to the semiconductor layer 14 through the fourth via 1821.

[0090] Specifically, the source 181 and the source region 142 overlap at least partially, the drain 182 and the drain region 143 overlap at least partially, and the source 181 is electrically connected to the semiconductor layer 14 through the third via 1811, and the drain 182 is electrically connected to the semiconductor layer 14 through the fourth via 1821.

[0091] Example 5

[0092] This embodiment is the same as or similar to the display panel 100 in any of the above embodiments, except that the display panel also includes a miniature light-emitting diode.

[0093] In some embodiments, the display panel 100 further includes a plurality of micro light-emitting diodes electrically connected to the thin-film transistor 101.

[0094] Specifically, a first insulating layer 19 is provided on the source 181 and the drain 182, and a pixel electrode layer 20 is provided on the first insulating layer 19. The pixel electrode layer 20 may include multiple pads, and the micro light-emitting diode is connected to the corresponding pad. At least some of the pads are connected to the source 181 or the drain 182 of the thin film transistor. The micro light-emitting diode is electrically connected to the thin film transistor through the pixel electrode layer 20.

[0095] Example 5

[0096] This embodiment also provides a method for manufacturing a display panel 100. The display panel 100 of any of the above embodiments can be manufactured using the manufacturing method of the display panel in this embodiment.

[0097] Please see Figures 3 to 9 , Figure 3 A schematic flowchart illustrating the manufacturing steps of a display panel according to an embodiment of this application; Figure 4 A schematic diagram of a first intermediate process of a method for manufacturing a display panel according to an embodiment of this application; Figure 5 A schematic diagram of a second intermediate process of a method for manufacturing a display panel according to an embodiment of this application; Figure 6 A schematic diagram of a third intermediate process in a method for manufacturing a display panel according to an embodiment of this application; Figure 7 A schematic diagram of the fourth intermediate process of a method for manufacturing a display panel according to an embodiment of this application; Figure 8 A schematic diagram of the fifth intermediate process of a method for manufacturing a display panel according to an embodiment of this application; Figure 9 This is a schematic diagram of the sixth intermediate process of a method for manufacturing a display panel according to an embodiment of this application.

[0098] Specifically, the manufacturing method of the display panel in this embodiment includes the following steps: S100, S200, S300, S400, S500, S600, S700, and S800. The numbering of the steps in the manufacturing method is for the purpose of more clearly explaining the manufacturing method of the display panel and is not a limitation on the order of steps.

[0099] Step S100: Provide a substrate.

[0100] Specifically, a base 11 is provided.

[0101] Step S200: Form a first gate on the substrate.

[0102] Specifically, such as Figure 4 As shown, a first gate 12 is formed on the substrate 11.

[0103] Step S300: A first gate insulating layer is formed on the first gate.

[0104] Specifically, such as Figure 5 As shown, a first gate insulating layer 13 is formed on the first gate 12.

[0105] In step S400, a semiconductor layer is formed on the first gate insulating layer.

[0106] Specifically, such as Figure 5 As shown, a semiconductor layer 14 is formed on the first gate insulating layer 13.

[0107] In step S500, a second gate insulating layer is formed on the semiconductor layer.

[0108] Specifically, such as Figure 6 As shown, a second gate insulating layer 15 is formed on the semiconductor layer 14.

[0109] In step S600, a second gate is formed on the second gate insulating layer, and the semiconductor layer includes a channel region corresponding to the second gate.

[0110] Specifically, such as Figure 6 As shown, a second gate 16 is formed on the second gate insulating layer 15, and the semiconductor layer 14 includes a channel region 141 corresponding to the second gate 16.

[0111] In step S700, an interlayer insulating layer is formed on the second gate.

[0112] Specifically, such as Figure 7 As shown, an interlayer insulating layer 17 is formed on the second gate 16.

[0113] In step S800, a source and a drain are formed on the interlayer insulating layer to obtain a thin-film transistor. The semiconductor layer further includes a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region. The first transport region and the second transport region are made of the same material as the channel region. The orthogonal projection of the first gate on the substrate covers the orthogonal projections of the source region, the drain region, the first transport region, the channel region, and the second transport region on the substrate. The first gate and the second gate are electrically connected.

[0114] Specifically, such as Figure 8As shown, a source 181 and a drain 182 are formed on the interlayer insulating layer 17 to obtain a thin film transistor 101. The semiconductor layer 14 further includes a source region 142 corresponding to the source 181, a drain region 143 corresponding to the drain 182, a first transport region 144 located between the source region 142 and the channel region 141, and a second transport region 145 located between the drain region 143 and the channel region 141. The first transport region 144 and the second transport region 145 are made of the same material as the channel region 141. The orthogonal projection of the first gate 12 on the substrate 11 covers the orthogonal projections of the source region 142, the drain region 143, the first transport region 144, the channel region 141, and the second transport region 145 on the substrate 11. The first gate 12 and the second gate 16 are electrically connected.

[0115] In some embodiments, the method of manufacturing the display panel 100 further includes: when forming an interlayer insulating layer, forming a first through-hole penetrating the interlayer insulating layer, a second through-hole penetrating the interlayer insulating layer, a second gate insulating layer, and a first gate insulating layer; when forming the source and drain, forming a connection electrode simultaneously, wherein the connection electrode is electrically connected to the second gate and the first gate through the first through-hole and the second through-hole, respectively.

[0116] Specifically, the manufacturing method of the display panel 100 further includes: when forming the interlayer insulating layer 17, forming a first through hole 1831 penetrating the interlayer insulating layer 17, and a second through hole 1832 penetrating the interlayer insulating layer 17, the second gate insulating layer 15, and the first gate insulating layer 13; when forming the source electrode 181 and the drain electrode 182, forming a connection electrode 183 simultaneously, wherein the connection electrode 183 is electrically connected to the second gate electrode 16 and the first gate electrode 12 through the first through hole 1831 and the second through hole 1832, respectively.

[0117] In some embodiments, both the source region 142 and the drain region 143 include doped elements; or both the source region 142 and the drain region 143 are made of the same material as the channel region 141, as described in detail in the above embodiments and will not be repeated here.

[0118] The above provides a detailed description of a display panel and a method for manufacturing the display panel according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, Includes a substrate and a plurality of thin-film transistors disposed on the substrate, the thin-film transistors comprising: A first gate is disposed on the substrate; A first gate insulating layer is disposed on the first gate; A semiconductor layer is disposed on the first gate insulating layer; A second gate insulating layer is disposed on the semiconductor layer; The second gate is disposed on the second gate insulating layer; The source and drain are disposed on the second gate; The semiconductor layer includes a channel region corresponding to the second gate, a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region; the source region and the drain region are made of the same material as the channel region, and both the source region and the drain region are exempt from ion implantation process; The first transmission region and the second transmission region are made of the same material as the channel region. The orthographic projection of the first gate on the substrate covers the orthographic projections of the source region, the drain region, the first transmission region, the channel region, and the second transmission region on the substrate. The electrical signals of the first gate and the second gate have the same potential. The orthogonal projection of the first gate onto the substrate completely covers the orthogonal projection of the semiconductor layer onto the substrate.

2. The display panel as described in claim 1, characterized in that, Also includes: An interlayer insulating layer is disposed between the source, the drain and the second gate; The connecting electrode is disposed in the same layer as the source electrode and the drain electrode and is made of the same material; The first through-hole penetrates the interlayer insulation layer; The second via penetrates the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. The connection electrode is electrically connected to the second gate and the first gate through the first via and the second via, respectively.

3. The display panel as described in claim 1, characterized in that, The semiconductor layer is made of polycrystalline silicon or semiconductor oxide.

4. The display panel as described in claim 2, characterized in that, The orthographic projection of the semiconductor layer on the substrate overlaps the orthographic projection of the second gate on the substrate, and the display panel further includes: The third via penetrates the interlayer insulating layer and the second gate insulating layer, and the source is electrically connected to the semiconductor layer through the third via; The fourth via penetrates the interlayer insulating layer and the second gate insulating layer, and the drain is electrically connected to the semiconductor layer through the fourth via.

5. The display panel as described in claim 1, characterized in that, The display panel also includes a plurality of miniature light-emitting diodes, which are electrically connected to the thin-film transistors.

6. A method for manufacturing a display panel, characterized in that, include: Provide a base; A first gate is formed on the substrate; A first gate insulating layer is formed on the first gate; A semiconductor layer is formed on the first gate insulating layer; A second gate insulating layer is formed on the semiconductor layer; A second gate is formed on the second gate insulating layer, and the semiconductor layer includes a channel region corresponding to the second gate; An interlayer insulating layer is formed on the second gate; A source and a drain are formed on the interlayer insulating layer to obtain a thin-film transistor. The semiconductor layer further includes a source region corresponding to the source, a drain region corresponding to the drain, a first transport region located between the source region and the channel region, and a second transport region located between the drain region and the channel region. The source region and the drain region are made of the same material as the channel region, and both are exempt from ion implantation. The first transport region and the second transport region are made of the same material as the channel region. The orthogonal projection of the first gate onto the substrate covers the orthogonal projections of the source region, the drain region, the first transport region, the channel region, and the second transport region onto the substrate. The first gate and the second gate are electrically connected. The orthogonal projection of the first gate onto the substrate completely covers the orthogonal projection of the semiconductor layer onto the substrate.

7. The method for manufacturing a display panel as described in claim 6, characterized in that, Also includes: The process of forming the interlayer insulating layer further includes: forming a first via through the interlayer insulating layer, and a second via through the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; In forming the source and the drain, a connection electrode is also formed simultaneously, wherein the connection electrode is electrically connected to the second gate and the first gate through the first via and the second via, respectively.

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