Image sensor and method of manufacturing the same

Abstract

The application relates to an image sensor and a preparation method thereof. The preparation method of the image sensor comprises the following steps: providing a substrate, forming a plurality of isolation grooves on a first side of the substrate, and isolating a plurality of pixel units in the substrate by the plurality of isolation grooves; performing first-type ion implantation on the bottom and the sidewall of the isolation groove, so as to form a bottom doped part on the bottom of the isolation groove and a sidewall doped part on the sidewall of the isolation groove; and performing thermal annealing on the obtained structure after the bottom doped part is formed, so that the plurality of bottom doped parts are diffused and connected into a first-type bottom semiconductor layer. The application can improve the production yield and imaging quality of the image sensor.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to an image sensor and a method for fabricating the same. Background Technology

[0002] Image sensors are used in various electronic devices, such as digital cameras and optical imaging devices, for image acquisition. Image sensors have the function of converting optical images into digital images. Currently, commonly used image sensors include Complementary Metal Oxide Semiconductor (CMOS) image sensors. CMOS image sensors offer advantages such as lower power consumption, smaller size, faster data processing capabilities, and lower manufacturing costs. Summary of the Invention

[0003] This application provides an image sensor and its fabrication method, which can effectively improve the production yield of the image sensor and ensure that the image sensor has good imaging quality.

[0004] On the one hand, some embodiments of this application provide a method for fabricating an image sensor, including the following steps.

[0005] A substrate is provided, and a plurality of isolation trenches are formed on a first side of the substrate, wherein the plurality of isolation trenches isolate a plurality of pixel units within the substrate.

[0006] Type I ion implantation is performed on the bottom and sidewalls of the isolation trench to form a bottom doped portion at the bottom of the isolation trench and a sidewall doped portion at the sidewalls of the isolation trench.

[0007] The resulting structure after forming the bottom doped portion is thermally annealed to diffuse and connect multiple bottom doped portions into a first-type bottom semiconductor layer.

[0008] In some embodiments, the method for fabricating the image sensor further includes the following steps.

[0009] A portion within the pixel unit is subjected to type II ion implantation to form a pixel doped portion; the pixel doped portion is located between adjacent sidewall doped portions.

[0010] The resulting structure after forming the pixel doped portion is thermally annealed to diffuse and form a second type semiconductor layer within the pixel unit.

[0011] In some embodiments, a first buffer semiconductor layer is provided between the second type semiconductor layer and the adjacent sidewall doped portion and the first type bottom semiconductor layer.

[0012] In some embodiments, the method for fabricating the image sensor further includes: performing a first type of ion implantation on the top of the pixel unit to form an active region doped layer; the active region doped layer is located on the side of the second type semiconductor layer opposite to the first type bottom semiconductor layer.

[0013] In some embodiments, a second buffer semiconductor layer is provided between the second type semiconductor layer and the active region doped layer.

[0014] In some embodiments, the method for fabricating the image sensor further includes: forming a vertical gate on the active region doped layer and the second buffer semiconductor layer; the bottom of the vertical gate is connected to the second type semiconductor layer.

[0015] In some embodiments, the method for fabricating the image sensor further includes: polishing a second side of the substrate to expose the first type bottom semiconductor layer; wherein the second side is the back side of the first side; forming a buffer oxide layer on the polished surface of the substrate; and forming a color resist layer on the buffer oxide layer.

[0016] In some embodiments, the method for fabricating the image sensor further includes forming a lens layer on the side of the color resist layer opposite to the substrate.

[0017] On the other hand, some embodiments of this application provide an image sensor, including: a substrate and a plurality of pixel units disposed within the substrate; a deep trench isolation structure is provided between adjacent pixel units. Each pixel unit includes: a first type semiconductor layer and a second type semiconductor layer; the first type semiconductor layer includes a sidewall doped portion and a bottom doped portion disposed connected together; the second type semiconductor layer is located between adjacent sidewall doped portions and above the bottom doped portion; wherein the bottom doped portions of the plurality of pixel units are diffusely connected to form a first type bottom semiconductor layer.

[0018] In some embodiments, the pixel unit further includes a first buffer semiconductor layer located between the second type semiconductor layer and the adjacent sidewall doped portion and the first type bottom semiconductor layer.

[0019] In some embodiments, the pixel unit further includes an active region doped layer located on the side of the second type semiconductor layer opposite to the first type bottom semiconductor layer.

[0020] In some embodiments, the pixel unit further includes a second buffer semiconductor layer located between the second type semiconductor layer and the active region doped layer.

[0021] In some embodiments, the pixel unit further includes: a vertical gate penetrating the active region doped layer and the second buffer semiconductor layer; the bottom of the vertical gate is connected to the second type semiconductor layer.

[0022] In some embodiments, the image sensor further includes a color resist layer located on the side of the first type bottom semiconductor layer opposite to the second type semiconductor layer.

[0023] In some embodiments, the image sensor further includes a lens layer located on the side of the color resist layer opposite to the first type bottom semiconductor layer.

[0024] In this embodiment, a first-type ion implantation process can be used to simultaneously form bottom doped portions and sidewall doped portions at the bottom and sidewalls of the isolation trench. Then, a thermal annealing process is used to diffuse and connect the bottom doped portions in multiple pixel units to form a first-type bottom semiconductor layer. In this way, the corresponding portions of each sidewall doped portion and the first-type bottom semiconductor layer are connected to form a first-type semiconductor layer, which can achieve the first-type semiconductor layer surrounding the portion of the pixel unit except for the top. Thus, in this embodiment, the entire fabrication of the first-type semiconductor layer can be completed before the fabrication of the second-type semiconductor layer of the pixel unit, ensuring that the first-type semiconductor layer can surround the portion of the pixel unit except for the top. During the processing of the second side (i.e., the back side) of the substrate, the first-type semiconductor layer can be used to protect the pixel unit, effectively preventing damage, contamination, or potential partial discharge or leakage caused by mechanical stress or other processes (such as polishing). This effectively improves the production yield of the image sensor and ensures that the image sensor has good imaging quality. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic flowchart of a method for fabricating an image sensor according to one embodiment;

[0027] Figure 2 This is a schematic flowchart of another method for fabricating an image sensor provided in one embodiment;

[0028] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming the isolation trench in one embodiment;

[0029] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming the bottom doped portion and the sidewall doped portion in one embodiment;

[0030] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming a first-type bottom semiconductor layer in one embodiment;

[0031] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the pixel doped portion in one embodiment;

[0032] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming a second type semiconductor layer in one embodiment;

[0033] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the active region doped layer in one embodiment;

[0034] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming a vertical gate in one embodiment;

[0035] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming a vertical gate, as provided in one embodiment; and... Figure 10 This is also a schematic diagram of the structure of an image sensor provided in one embodiment.

[0036] Explanation of reference numerals in the attached figures:

[0037] 1-Substrate, T-Isolation trench, DTI-Deep trench isolation structure;

[0038] 2-Pixel unit, 21-First type semiconductor layer, 22-Second type semiconductor layer, 21A-Bottom doped portion, 211-First type bottom semiconductor layer, 21B-Sidewall doped portion, 22A-Pixel doped portion, 23-First buffer semiconductor layer, 24-Second buffer semiconductor layer, 25-Active region doped layer, 26-Vertical gate, 27-Gate dielectric layer;

[0039] 3-Buffer oxide layer; 4-Color resist layer; 41-Light-shielding mesh; 42-Color filter film; 5-Lens layer. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0045] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0046] This application provides a method for fabricating an image sensor, which can be used to fabricate a back-side illumination (BSI) image sensor. BSI image sensors are a common application of CMOS image sensors. In a BSI image sensor, a deep trench isolation (DTI) structure can be used to isolate photodiodes (PDs) in adjacent pixels to avoid optical crosstalk between adjacent pixels. The image sensor fabrication method provided in some embodiments of this application can effectively improve the production yield of image sensors and ensure that the image sensor has good imaging quality.

[0047] Please see Figure 1 The image sensor fabrication method provided in some embodiments of this application includes the following steps.

[0048] S100 provides a substrate, on which a plurality of isolation trenches are formed on a first side, the plurality of isolation trenches isolating a plurality of pixel units within the substrate.

[0049] S200, type I ion implantation is performed on the bottom and sidewalls of the isolation trench to form a bottom doped portion at the bottom of the isolation trench and a sidewall doped portion at the sidewalls of the isolation trench.

[0050] S300, the structure obtained after forming the bottom doped portion is thermally annealed so that multiple bottom doped portions are diffusely connected to form a first type bottom semiconductor layer.

[0051] In this embodiment, a first-type ion implantation process can be used to simultaneously form bottom doped portions and sidewall doped portions at the bottom and sidewalls of the isolation trench. Then, a thermal annealing process is used to diffuse and connect the bottom doped portions in multiple pixel units to form a first-type bottom semiconductor layer. In this way, the corresponding portions of each sidewall doped portion and the first-type bottom semiconductor layer are connected to form a first-type semiconductor layer, which can achieve the first-type semiconductor layer surrounding the portion of the pixel unit except for the top. Thus, in this embodiment, the entire fabrication of the first-type semiconductor layer can be completed before the fabrication of the second-type semiconductor layer of the pixel unit, ensuring that the first-type semiconductor layer can surround the portion of the pixel unit except for the top. During the processing of the second side (i.e., the back side) of the substrate, the first-type semiconductor layer can be used to protect the pixel unit, effectively preventing damage, contamination, or potential partial discharge or leakage caused by mechanical stress or other processes (such as polishing). This effectively improves the production yield of the image sensor and ensures that the image sensor has good imaging quality.

[0052] In some embodiments, please refer to Figure 2 The image sensor fabrication method provided in some embodiments of this application further includes steps S400 to S500.

[0053] S400 performs type II ion implantation on a portion within a pixel unit to form a pixel doped portion; the pixel doped portion is located between adjacent sidewall doped portions.

[0054] S500 involves thermally annealing the structure obtained after forming the pixel doped portion to diffuse and form a second type semiconductor layer within the pixel unit.

[0055] In this embodiment, the pixel unit can first undergo type II ion implantation to form a pixel doped portion, and then a thermal annealing process can be used to diffuse the pixel doped portion to form a type II semiconductor layer. This not only helps ensure a simple and stable fabrication process for the type II semiconductor layer, but also further ensures the uniformity of the type I semiconductor layer and restores the lattice damage to the pixel unit caused by ion implantation.

[0056] It is understood that in some embodiments, a first buffer semiconductor layer is provided between the second type semiconductor layer and the adjacent sidewall doped portion and the first type bottom semiconductor layer.

[0057] Here, after the second type semiconductor layer is formed, the portion of the substrate located between the second type semiconductor layer and the adjacent sidewall doped portion and the first type bottom semiconductor layer can constitute a first buffer semiconductor layer.

[0058] In some embodiments, please continue reading Figure 2 The method for preparing the image sensor further includes step S600.

[0059] S600 performs type I ion implantation on the top of the pixel unit to form an active region doped layer; the active region doped layer is located on the side of the type II semiconductor layer away from the bottom type I semiconductor layer.

[0060] In some embodiments, a second buffer semiconductor layer is provided between the second type semiconductor layer and the active region doped layer.

[0061] Here, after the active region doped layer is formed, the portion of the substrate located between the second type semiconductor layer and the active region doped layer can constitute a second buffer semiconductor layer.

[0062] In this embodiment, after forming the second type semiconductor layer, first type ion implantation can be performed on the top of the pixel unit to form an active region doped layer, ensuring that a second buffer semiconductor layer exists between the active region doped layer and the second type semiconductor layer. Thus, the pixel unit prepared by the above method in this embodiment can achieve deep embedding of the first and second type semiconductor layers, and ensure complete isolation between the first and second type semiconductor layers and the two sides of the substrate, effectively avoiding numerous surface and lattice defects in the pixel unit, thereby improving the performance of the pixel unit.

[0063] In some embodiments, please continue reading Figure 2 The method for preparing the image sensor further includes step S700.

[0064] S700, a vertical gate is formed on the active region doped layer and the second buffer semiconductor layer; the bottom of the vertical gate is connected to the second type semiconductor layer.

[0065] In this embodiment, the vertical gate is connected to the second type semiconductor layer, which helps to increase the distribution density of pixel units and thus effectively improve the resolution of the image sensor.

[0066] In some embodiments, please continue reading Figure 2 The method for preparing the image sensor further includes step S800.

[0067] S800, the second side of the polished substrate exposes the first type bottom semiconductor layer; wherein the second side is the back side of the first side. A buffer oxide layer is formed on the polished surface of the substrate; a color resist layer is formed on the buffer oxide layer.

[0068] Optionally, the color resist layer includes: a light-shielding grid for defining pixel areas and a color filter film disposed in each grid area of ​​the light-shielding grid.

[0069] In this embodiment, after the pixel unit is fabricated, a polishing process can be used to thin the second side of the substrate until a uniform first-type bottom semiconductor layer is exposed. Then, a buffer oxide layer and a color resist layer are sequentially formed on the polished surface of the substrate. This enables color imaging by the image sensor and avoids defects such as stress damage and contamination of the pixel unit caused by subsequent polishing and the formation processes of the buffer oxide and color resist layers, thereby improving the imaging quality of the image sensor.

[0070] In some embodiments, please continue reading Figure 2 The method for preparing the image sensor further includes step S900.

[0071] S900 forms a lens layer on the side of the color resist layer that faces away from the substrate.

[0072] Thus, embodiments of this application can utilize a lens layer to improve the efficiency of light incident on the pixel unit, thereby ensuring the imaging quality of the image sensor.

[0073] To more clearly illustrate the fabrication method of the image sensor in the embodiments of this application, the following is combined with... Figures 3 to 10 The preparation method is described in detail.

[0074] In step S100, please refer to Figure 3 A substrate 1 is provided, and a plurality of isolation trenches T are formed on a first side of the substrate 1. The plurality of isolation trenches T isolate a plurality of pixel units 2 within the substrate 1.

[0075] Here, substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multi-layer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0076] Furthermore, the number and distribution density of pixel units 2 can be designed to match the resolution requirements of the image sensor. Accordingly, isolation trenches T are used to isolate pixel units 2, and the formation area of ​​the isolation trenches T can be determined based on pixel units 2.

[0077] Optionally, the isolation trench T can be formed based on a patterned hard mask layer, which can be directly formed on the surface of the first side of the substrate 1 using a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0078] Optionally, the isolation trench T is a deep trench, and the depth of the isolation trench T can be selected and set according to actual needs, for example, its depth ranges from 2μm to 10μm. In one example, the isolation trench T does not penetrate the substrate 1.

[0079] Optionally, the opening shape of the isolation trench T can be rectangular, trapezoidal, circular, elliptical, or similar geometric shapes.

[0080] In step S200, please refer to Figure 4 Type I ion implantation is performed on the bottom and sidewalls of the isolation trench T to form a bottom doped portion 21A at the bottom of the isolation trench T and a sidewall doped portion 21B at the sidewalls of the isolation trench T.

[0081] Optionally, the first type of ion can be a P-type ion; for example, boron (B) or indium (In) can be used for ion implantation.

[0082] Optionally, the implantation dose of type I ions can be: 1 × 10⁻⁶ 13 ~1×10 14 Here, the injection dose refers to the total number of ions injected per unit area of ​​the sample surface.

[0083] Optionally, the ion energy during type I ion implantation can be 10 KeV to 50 KeV.

[0084] Optionally, the first type of ion implantation can be performed in multiple stages, for example, first ion implantation is performed at the bottom of the isolation trench T, and then ion implantation is performed at the sidewall of the isolation trench T.

[0085] Optionally, the first type of ion implantation can be performed once, that is, the bottom doped portion 21A and the sidewall doped portion 21B are formed simultaneously.

[0086] In step S300, please refer to Figure 4 and Figure 5 The structure obtained after forming the bottom doped portion 21A is thermally annealed so that the multiple bottom doped portions 21A are diffusely connected to form a first type bottom semiconductor layer 211.

[0087] Here, the temperature for hot annealing can be selected and set according to actual needs.

[0088] In this embodiment, after forming a bottom doped portion 21A at the bottom of each isolation trench T, a thermal annealing process is used to diffuse and connect the bottom doped portions 21A of multiple pixel units 2 into a uniform first-type bottom semiconductor layer 211. This ensures that the corresponding portions of each sidewall doped portion 21B and the first-type bottom semiconductor layer 211 are connected to form the first-type semiconductor layer 21, thereby achieving the first-type semiconductor layer 21 surrounding the portion of the pixel unit 2 except for the top. Thus, in this embodiment, the entire fabrication of the first-type semiconductor layer can be completed before fabricating the second-type semiconductor layer of the pixel unit 2, ensuring that the first-type semiconductor layer 21 effectively surrounds the portion of the pixel unit 2 except for the top.

[0089] In step S400, please refer to Figure 6 A second type of ion implantation is performed on a portion within the pixel unit 2 to form a pixel doped portion 22A; the pixel doped portion 22A is located between adjacent sidewall doped portions 21B.

[0090] Alternatively, the second type ion can be an N-type ion; for example, arsenic (As) or phosphorus (P31) can be used for ion implantation.

[0091] Optionally, the pixel doped portion 22A is formed between adjacent sidewall doped portions 21B and is located at the center of the pixel unit 2; that is, there is a distance between the pixel doped portion 22A and any surface of the pixel unit 2. This can also be understood as the second type of ions using a high-energy ion implantation method to form the pixel doped portion 22A embedded inside the pixel unit 2.

[0092] In step S500, please refer to Figure 6 and Figure 7 The structure obtained after forming the pixel doped portion 22A is thermally annealed to diffuse and form a second type semiconductor layer 22 within the pixel unit 2.

[0093] It is understood that in some of the aforementioned examples, the high-energy ion implantation method used to form the pixel doped portion 22A means that the high-energy ions, after entering the pixel unit 2, remain within a certain depth of the semiconductor lattice. Based on this, high-energy ion implantation is also prone to lattice breakage or damage due to ion collisions. Therefore, in this embodiment, the structure obtained after forming the pixel doped portion 22A is thermally annealed to allow the pixel doped portion 22A to diffuse and form the second type semiconductor layer 22. This not only helps ensure a simple and stable fabrication process for the second type semiconductor layer 22, but also further ensures the uniformity of the second type semiconductor layer 22 and the first type semiconductor layer 21, and effectively restores the lattice damage to the pixel unit 2 caused by ion implantation.

[0094] It is understood that after the second type semiconductor layer 22 is formed using the aforementioned method, a first buffer semiconductor layer 23 is provided between the second type semiconductor layer 22 and the adjacent sidewall doped portion 21B and the first type bottom semiconductor layer 211. Here, the first buffer semiconductor layer 23 may be formed by the portion of the substrate 1 located between the second type semiconductor layer 22 and the adjacent sidewall doped portion 21B and the first type bottom semiconductor layer 211.

[0095] In step S600, please refer to Figure 8 A first-type ion implantation is performed on the top of the pixel unit 2 to form an active region doped layer 25; the active region doped layer 25 is located on the side of the second-type semiconductor layer 22 away from the first-type bottom semiconductor layer 211.

[0096] It is understood that after the active region doped layer 25 is formed using the aforementioned method, a second buffer semiconductor layer 24 is present between the second type semiconductor layer 22 and the active region doped layer 25. Here, the second buffer semiconductor layer 24 may be formed by the portion of the substrate 1 located between the second type semiconductor layer 22 and the active region doped layer 25.

[0097] In this embodiment, after forming the second type semiconductor layer 22, a first type ion implantation can be performed on the top of the pixel unit 2 to form an active region doped layer 25, ensuring that a second buffer semiconductor layer 24 exists between the active region doped layer 25 and the second type semiconductor layer 22. Thus, the pixel unit 2 prepared by the above method in this embodiment can achieve deep embedding of the first type semiconductor layer 21 and the second type semiconductor layer 22, and ensure complete isolation between the first type semiconductor layer 21 and the second type semiconductor layer 22 and the two side surfaces of the substrate 1, effectively avoiding numerous surface and lattice defects in the pixel unit 2, thereby improving the performance of the pixel unit 2.

[0098] As described above, the first type semiconductor layer 21, the second type semiconductor layer 22, and the first buffer semiconductor layer 23 located between the first type semiconductor layer 21 and the second type semiconductor layer 22 can form a PN junction at adjacent interfaces to jointly constitute the optoelectronic device of the pixel unit 2.

[0099] Please refer to the following for further information. Figure 8 In some embodiments, before performing type-1 ion implantation on the top of pixel unit 2 to form active region doped layer 25, the fabrication method of the image sensor further includes: forming a deep trench isolation structure (DTI) within the isolation trench T.

[0100] Optionally, the deep trench isolation (DTI) structure can be formed by dielectric filling, such as using oxides or other high-k dielectric materials. For example, the material of the deep trench isolation (DTI) structure can be one or any combination of the following: silicon oxide (SiO2), hafnium oxide (HfO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y ), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), ytterbium oxide (Yb2O3), yttrium oxide (Y2O3), etc.

[0101] Optionally, the deep trench isolation structure (DTI) can have light-absorbing regions or light-reflecting regions. The light-absorbing regions can be formed using light-absorbing materials such as tungsten, titanium, titanium nitride, or nickel, while the light-reflecting regions can be formed using light-reflecting materials such as aluminum, copper, silver, or platinum. In this way, stray light can be absorbed by the light-absorbing regions or incident light can be retained within the pixel unit 2 by the light-reflecting regions, thereby effectively avoiding light crosstalk between adjacent pixel units 2 and improving the quantum efficiency of the optoelectronic devices in the pixel unit 2.

[0102] In step S700, please refer to Figure 9A vertical gate 26 is formed on the active region doped layer 25 and the second buffer semiconductor layer 24; the bottom of the vertical gate 26 is connected to the second type semiconductor layer 22.

[0103] It is understandable that the vertical gate 26 and the active region doped layer 25 need to be effectively isolated by the gate dielectric layer 27.

[0104] Optionally, a gate trench is formed on the active region doped layer 25 and the second buffer semiconductor layer 24 to expose a portion of the second type semiconductor layer 22. Then, a gate dielectric layer 27 and a vertical gate 26 covering the sidewalls are formed in the gate trench, and the bottom of the vertical gate 26 is made in contact with the second type semiconductor layer 22.

[0105] In this embodiment, the vertical gate 26 is connected to the second type semiconductor layer 22, which helps to increase the distribution density of the pixel unit 2, thereby effectively improving the resolution of the image sensor.

[0106] In step S800, please refer to Figure 10 On the second side of the polished substrate, a first-type bottom semiconductor layer 211 is exposed; wherein the second side is the back side of the first side. A buffer oxide layer 3 is formed on the polished surface of the substrate; a color resist layer 4 is formed on the buffer oxide layer 3.

[0107] Optionally, the second side of the substrate is polished using a chemical mechanical polishing process.

[0108] In this embodiment, during the polishing of the second side (i.e., the back side of the substrate) of the substrate, the first type semiconductor layer 21 can be used to protect the pixel unit 2, effectively preventing damage, contamination, or potential partial discharge to the pixel unit 2 caused by mechanical stress or other processes (such as polishing and grinding). This effectively improves the production yield of the image sensor and ensures that the image sensor has good imaging quality.

[0109] Optionally, the color resist layer 4 includes: a light-shielding grid 41 for defining pixel areas and a color filter film 42 disposed in each grid area of ​​the light-shielding grid 41.

[0110] Here, the light-shielding grid 41 is, for example, a metal grid layer. The color filter film 42 includes, for example, three different colored filter films, specifically a red filter film, a green filter film, and a blue filter film.

[0111] Optionally, the red filter, green filter, and blue filter can be arranged in the pixel areas defined by the light-shielding grid 41 according to the pixel arrangement principle.

[0112] In this embodiment, a buffer oxide layer 3 and a color resist layer 4 are sequentially formed on the polished surface of the substrate (i.e., the exposed surface of the first type bottom semiconductor layer 211), which can effectively realize the colorization of the image sensor imaging.

[0113] In step S900, please refer to Figure 10 A lens layer 5 is formed on the side of the color resist layer 4 facing away from the substrate. In this way, the lens layer 5 can be used to improve the efficiency of light incident on the pixel unit 2, thereby ensuring the imaging quality of the image sensor.

[0114] Alternatively, the lens layer 5 can be formed by spin coating or by depositing a lens material layer and then patterning it.

[0115] Optionally, the lens layer 5 can be an on-chip lens (OCL) or a microlens array formed by patterning.

[0116] Some embodiments of this application also provide an image sensor, which can be prepared using the fabrication methods provided in the above embodiments. This image sensor also possesses all the technical advantages achieved by the foregoing embodiments, and will not be detailed here.

[0117] Please continue reading. Figure 10 The image sensor includes a substrate and a plurality of pixel units 2 disposed within the substrate; a deep trench isolation structure (STI) is provided between adjacent pixel units 2. Each pixel unit 2 includes a first type semiconductor layer 21 and a second type semiconductor layer 22; the first type semiconductor layer 21 includes a sidewall doped portion 21B and a bottom doped portion 21A disposed together; the second type semiconductor layer 22 is located between adjacent sidewall doped portions 21B and above the bottom doped portion 21A; wherein the bottom doped portions 21A of the plurality of pixel units 2 are diffusely connected to form a first type bottom semiconductor layer 211.

[0118] Here, pixel units 2 can be arranged in an array on the substrate. The number and distribution density of pixel units 2 can be designed to match the resolution requirements of the image sensor. It is understandable that... Figure 10 Only a portion of the cross-sectional structure of pixel unit 2 is shown in the diagram; therefore, the substrate is not shown. Figure 10 As shown in the figure, but as can be seen from the fabrication method of the image sensor in some of the foregoing embodiments, the substrate retained in the image sensor is only located at the peripheral edge of each pixel unit 2; that is, the substrate is the part retained after thinning the back side of the initial substrate to expose the first type bottom semiconductor layer 211.

[0119] Optionally, the first type semiconductor layer 21 is a P-type semiconductor layer. The second type semiconductor layer 22 is an N-type semiconductor layer.

[0120] Optionally, the deep trench isolation structure (DTI) can be formed by filling the isolation trench with a dielectric material, such as an oxide or other high-k dielectric material. For example, the material of the deep trench isolation structure (DTI) can be one or any combination of the following: silicon oxide (SiO2), hafnium oxide (HfO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y ), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), ytterbium oxide (Yb2O3), yttrium oxide (Y2O3), etc.

[0121] Optionally, the deep trench isolation structure (DTI) can have light-absorbing regions or light-reflecting regions. The light-absorbing regions can be formed using light-absorbing materials such as tungsten, titanium, titanium nitride, or nickel, while the light-reflecting regions can be formed using light-reflecting materials such as aluminum, copper, silver, or platinum. In this way, stray light can be absorbed by the light-absorbing regions or incident light can be retained within the pixel unit 2 by the light-reflecting regions, thereby effectively avoiding light crosstalk between adjacent pixel units 2 and improving the quantum efficiency of the optoelectronic devices in the pixel unit 2.

[0122] In some embodiments, please continue reading Figure 10 The pixel unit 2 further includes a first buffer semiconductor layer 23 located between the second type semiconductor layer 22 and the adjacent sidewall doped portion 21B and the first type bottom semiconductor layer 211.

[0123] Here, the first buffer semiconductor layer 23 may be composed of a portion of the substrate located between the second type semiconductor layer 22 and the adjacent sidewall doped portion 21B and the first type bottom semiconductor layer 211.

[0124] In some embodiments, please continue reading Figure 10 The pixel unit 2 also includes an active region doped layer 25 located on the side of the second type semiconductor layer 22 away from the first type bottom semiconductor layer 211.

[0125] Optionally, the doping type of the active region doped layer 25 is the same as that of the first type semiconductor layer 21; for example, both are P-type.

[0126] In some embodiments, please continue reading Figure 10 The pixel unit 2 further includes a second buffer semiconductor layer 24 located between the second type semiconductor layer 22 and the active region doped layer 25.

[0127] Here, the second buffer semiconductor layer 24 may be formed by the portion of the substrate 1 located between the second type semiconductor layer 22 and the active region doped layer 25.

[0128] As described above, the first type semiconductor layer 21, the second type semiconductor layer 22, and the first buffer semiconductor layer 23 located between the first type semiconductor layer 21 and the second type semiconductor layer 22 can form a PN junction at adjacent interfaces to jointly constitute the optoelectronic device of the pixel unit 2.

[0129] In some embodiments, please continue reading Figure 10 The pixel unit 2 further includes a vertical gate 26 that penetrates the active region doped layer 25 and the second buffer semiconductor layer 24; the bottom of the vertical gate 26 is connected to the second type semiconductor layer 22.

[0130] Alternatively, please continue reading Figure 10 The pixel unit 2 further includes a gate dielectric layer 27 disposed between the vertical gate 26 and the active region doped layer 25.

[0131] In some embodiments, please continue reading Figure 10 The image sensor also includes a color resist layer 4 located on the side of the first type bottom semiconductor layer 211 opposite to the second type semiconductor layer 22.

[0132] Alternatively, please continue reading Figure 10 The image sensor also includes a buffer oxide layer 3 located between the first type semiconductor layer 211 and the color resist layer 4.

[0133] Optionally, the color resist layer 4 includes: a light-shielding grid 41 for defining pixel areas and a color filter film 42 disposed in each grid area of ​​the light-shielding grid 41.

[0134] Here, the light-shielding grid 41 is, for example, a metal grid layer. The color filter film 42 includes, for example, three different colored filter films, specifically a red filter film, a green filter film, and a blue filter film.

[0135] Optionally, the red filter, green filter, and blue filter can be arranged in the pixel areas defined by the light-shielding grid 41 according to the pixel arrangement principle.

[0136] In some embodiments, please continue reading Figure 10 The image sensor also includes a lens layer 5 located on the side of the color resist layer 4 opposite to the first type bottom semiconductor layer 211.

[0137] Alternatively, the lens layer 5 can be formed by spin coating or by depositing a lens material layer and then patterning it.

[0138] Optionally, the lens layer 5 can be an on-chip lens (OCL) or a microlens array formed by patterning.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating an image sensor, characterized in that, include: A substrate is provided, and a plurality of isolation trenches are formed on a first side of the substrate, wherein the plurality of isolation trenches isolate a plurality of pixel units within the substrate; Type I ion implantation is performed on the bottom and sidewalls of the isolation trench to form a bottom doped portion at the bottom of the isolation trench and a sidewall doped portion at the sidewalls of the isolation trench. The structure obtained after forming the bottom doped portion is thermally annealed to diffuse and connect the multiple bottom doped portions into a first-type bottom semiconductor layer. A portion within the pixel unit is subjected to type II ion implantation to form a pixel doped region; The pixel doped portion is located between adjacent sidewall doped portions; The resulting structure after forming the pixel doped portion is thermally annealed to diffuse and form a second type semiconductor layer within the pixel unit; Also includes: Type I ion implantation is performed on the top of the pixel unit to form an active region doped layer; The active region doped layer is located on the side of the second type semiconductor layer away from the bottom semiconductor layer of the first type; A second buffer semiconductor layer is provided between the second type semiconductor layer and the active region doped layer.

2. The method for fabricating an image sensor according to claim 1, characterized in that, A first buffer semiconductor layer is provided between the second type semiconductor layer and the adjacent sidewall doped portion and the first type bottom semiconductor layer.

3. The method for fabricating an image sensor according to claim 1, characterized in that, Also includes: A vertical gate is formed on the active region doped layer and the second buffer semiconductor layer; The bottom of the vertical gate is connected to the second type of semiconductor layer.

4. The method for fabricating an image sensor according to any one of claims 1 to 3, characterized in that, Also includes: Polishing a second side of the substrate exposes the first type bottom semiconductor layer; wherein the second side is the back side of the first side; A buffer oxide layer is formed on the polished surface of the substrate; A color resist layer is formed on the buffer oxide layer.

5. The method for fabricating an image sensor according to claim 4, characterized in that, Also includes: A lens layer is formed on the side of the color resist layer that is away from the substrate.

6. An image sensor, characterized in that, include: A substrate and a plurality of pixel units disposed within the substrate; A deep trench isolation structure is provided between adjacent pixel units; The pixel unit includes: a first type semiconductor layer and a second type semiconductor layer; the first type semiconductor layer includes a sidewall doped portion and a bottom doped portion disposed together; the second type semiconductor layer is located between adjacent sidewall doped portions and above the bottom doped portion; The bottom doped portions of the plurality of pixel units are diffusely connected to form a first type bottom semiconductor layer; The pixel unit further includes: an active region doped layer located on the side of the second type semiconductor layer opposite to the bottom semiconductor layer of the first type; The pixel unit further includes a second buffer semiconductor layer located between the second type semiconductor layer and the active region doped layer.

7. The image sensor according to claim 6, characterized in that, The pixel unit further includes a first buffer semiconductor layer located between the second type semiconductor layer and the adjacent sidewall doped portion and the first type bottom semiconductor layer.

8. The image sensor according to claim 6, characterized in that, The pixel unit further includes: a vertical gate penetrating the active region doped layer and the second buffer semiconductor layer; the bottom of the vertical gate is connected to the second type semiconductor layer.

9. The image sensor according to any one of claims 6 to 8, characterized in that, The image sensor further includes a color resist layer located on the side of the first type bottom semiconductor layer opposite to the second type semiconductor layer.

10. The image sensor according to claim 9, characterized in that, The image sensor further includes a lens layer located on the side of the color resist layer opposite to the first type bottom semiconductor layer.

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