Average current controller and BUCK constant current circuit

Abstract

The present invention provides an average current controller and a BUCK constant current circuit. The controller includes: a first current generation module, a current mirror, a second current generation module, a capacitor charge / discharge module, a MOS transistor turn-off signal control module, and a logic control module. It can implement a control method of 2 times Δt control + constant turn-off time Toff for the switching state of the MOS transistor in the BUCK circuit operating in the CCM mode. Only the switching current during the Ton time needs to be sampled, and the load output current does not change with the output voltage Vout and the inductance L, which can well solve the problem of the constant current accuracy of the load output. Moreover, a high-voltage differential sampling circuit is not required, which can solve the problems of high process requirements and high cost. Additionally, through the first current generation module, the current mirror, and the second current generation module, the voltage difference is converted into a current difference to achieve precise control of the charging and discharging of the capacitor in the subsequent capacitor charge / discharge module, thereby further improving the constant current accuracy of the entire system.

Description

Technical Field

[0001] The present invention relates to the technical field of constant current drive power supplies, and particularly to an average current controller and a BUCK constant current circuit. Background Art

[0002] LED lighting sources have the advantages of environmental protection, energy saving, long lifespan, etc., and are regarded as the most promising lighting sources in the 21st century. In recent years, with the development of LED lighting technology, LED lighting sources have begun to replace traditional light sources and are widely used in various lighting fixtures. To obtain an ideal lighting effect, LEDs require constant current drive power supplies.

[0003] The core of DC LED drive technology is to solve the problem of constant current control, that is, when various external conditions change, the LED driver can also ensure the stability of the output current. Currently, for the methods of constant current control, there are generally two classification methods. The first is to distinguish according to different circuit topologies. Different topologies have different constant current control methods due to different conversion ratios, such as linear, buck (step-down conversion), buckboost (buck-boost conversion), etc. The second is to distinguish according to different control principles, which are divided into open-loop control and closed-loop feedback control. Since the buck topology is simple and has strong adaptability, and the open-loop control has a lower cost, the BUCK architecture with open-loop constant current control (as Figure 1 shown) is one of the mainstream topologies of DC LED drivers.

[0004] As Figure 2 shown, it is the topology of the existing BUCK architecture with open-loop constant current control, where the current sampling resistor Rcs is at the high voltage end. Figure 3 For its common control method (also known as Bang-bang control), the inductor L current is sampled through a differential operational amplifier. The internal set current peak given value Ipk and the current valley given value Iva are set. When the inductor current touches Ipk, the Mos tube N turns off; when the inductor current touches Iva, the Mos tube N turns on, and so on, controlling the average value of the inductor current at (Ipk + Iva) / 2, and the output LED current is equal to the inductor current, thereby controlling the constancy of the output current.

[0005] As Figure 4 shown, it is the topology of the existing BUCK architecture with open-loop constant current control, where the current sampling resistor Rcs is at the low voltage end. Figure 5Its common control method (also known as Constant Toff control) samples the current when Mos transistor N is turned on through the single-ended current sampling resistor Rcs. The internal set current peak given value Ipk and fixed Toff time are set. When the inductor current reaches Ipk, Mos transistor N turns off; when the fixed Toff time arrives, Mos transistor N turns on, and so on, controlling the average value of the inductor L current at Ipk - 0.5 * Vout * Toff / L. And the output LED lamp voltage Vout and the inductance L are basically unchanged, thus controlling the constancy of the output current.

[0006] For the Bang-bang control method, a high-voltage differential sampling circuit is required, which has relatively high requirements for the process. Currently, the highest can reach about 60V, and the cost will be very high if it is made higher; while using the Constant Toff control method, the requirements for system consistency are relatively high. Because there are differences in the output lamp voltage and inductance among individuals, it will affect the constant current accuracy of the system, and it is very difficult to achieve below ±5% in practice. Therefore, for the medium-voltage BUCK LED driver market with a breakdown voltage above 60V, if there are relatively high requirements for constant current consistency, neither of the above two control methods can meet the requirements well. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an average current controller and a BUCK constant current circuit, which are used to solve the problems that in the prior art, for the medium-voltage BUCK drive market, if there are relatively high requirements for constant current consistency, neither the Bang-bang control method nor the Constant Toff control method can meet the market demand, etc.

[0008] To achieve the above purpose and other related purposes, the present invention provides an average current controller, which is applied to a BUCK circuit. Among them, the BUCK circuit operates in the CCM mode and the current sampling resistor is set at the low-voltage end. The average current controller includes:

[0009] A first current generation module, a current mirror, a second current generation module, a capacitor charge / discharge module, a MOS transistor turn-off signal control module, and a logic control module;

[0010] The first current generation module is connected to the current sampling resistor and receives a first reference voltage, and generates a current comparison signal based on the sampling voltage of the current sampling resistor and the first reference voltage;

[0011] The current mirror is connected to the output end of the first current generation module, and mirrors the current comparison signal into a charge / discharge current comparison signal;

[0012] The second current generation module is connected to the output terminal of the current mirror and receives a second reference voltage, and generates a charge / discharge current reference signal based on the second reference voltage;

[0013] The capacitor charge / discharge module is connected to the current mirror and the second current generation module, and controls the charging / discharging of the capacitor in the capacitor charge / discharge module based on the current difference between the charge / discharge current comparison signal and the charge / discharge current reference signal;

[0014] The MOS transistor turn-off signal control module is connected to the output terminal of the capacitor charge / discharge module, and generates a turn-off control signal based on the voltage of the capacitor in the capacitor charge / discharge module;

[0015] The logic control module is connected to the output terminal of the MOS transistor turn-off signal control module, generates a turn-off signal for the MOS transistor in the BUCK circuit based on the turn-off control signal, and generates a turn-on signal for the MOS transistor after a preset time.

[0016] Optionally, the BUCK circuit includes: the current sampling resistor, the MOS transistor, the freewheeling diode, the capacitor and the inductor; the first end of the current sampling resistor is connected to the first end of the MOS transistor, and the second end is connected to the low-voltage end of the DC power supply; the second end of the MOS transistor is connected to the anode of the freewheeling diode and the first end of the inductor; the second end of the inductor is connected to the first end of the capacitor; the high-voltage end of the DC power supply is connected to the cathode of the freewheeling diode and the second end of the capacitor.

[0017] Optionally, the first current generation module includes:

[0018] A first operational amplifier, a first resistor and a fifth MOS transistor;

[0019] The sampled voltage is connected to the first input terminal of the first operational amplifier and the first end of the fifth MOS transistor through the first resistor;

[0020] The second input terminal of the first operational amplifier is connected to the first reference voltage, and the output terminal is connected to the second end of the fifth MOS transistor;

[0021] The third end of the fifth MOS transistor is connected to the input terminal of the current mirror.

[0022] Optionally, the current mirror is a cascode current mirror, including:

[0023] A first MOS transistor and a third MOS transistor connected in series and a second MOS transistor and a fourth MOS transistor connected in series;

[0024] The drain of the third MOS transistor is connected to the third end of the fifth MOS transistor;

[0025] The drain of the fourth MOS transistor is connected to the capacitor charging / discharging module and the second current generation module;

[0026] The source of the first MOS transistor and the source of the second MOS transistor are connected and commonly connected to the operating voltage; the gate of the first MOS transistor and the gate of the second MOS transistor are connected.

[0027] Optionally, the second current generation module includes:

[0028] A second operational amplifier, a second resistor, and a sixth MOS transistor;

[0029] The reference ground terminal is connected to the first input terminal of the second operational amplifier and the first terminal of the sixth MOS transistor through the second resistor;

[0030] The second input terminal of the second operational amplifier is connected to the second reference voltage, and the output terminal is connected to the second terminal of the sixth MOS transistor;

[0031] The third terminal of the sixth MOS transistor is connected to the drain of the fourth MOS transistor and the capacitor charging / discharging module.

[0032] Optionally, the fifth MOS transistor is an N-type MOS transistor; the first terminal of the fifth MOS transistor is the source, the second terminal of the fifth MOS transistor is the gate, and the third terminal of the fifth MOS transistor is the drain; the first input terminal of the first operational amplifier is the inverting input terminal, and the second input terminal of the first operational amplifier is the non-inverting input terminal; the sixth MOS transistor is an N-type MOS transistor; the first terminal of the sixth MOS transistor is the source, the second terminal of the sixth MOS transistor is the gate, and the third terminal of the sixth MOS transistor is the drain; the first input terminal of the second operational amplifier is the inverting input terminal, and the second input terminal of the second operational amplifier is the non-inverting input terminal.

[0033] Optionally, the capacitor charging / discharging module includes a first capacitor, the first terminal of the first capacitor is connected to the reference ground terminal, and the second terminal of the first capacitor is connected to the drain of the fourth MOS transistor and the MOS transistor turn-off signal control module.

[0034] Optionally, the MOS transistor turn-off signal control module includes:

[0035] A comparator, a second capacitor, a first switch, and a second switch;

[0036] The second capacitor is connected to the first input terminal of the comparator and is connected to the second input terminal of the comparator through the second switch;

[0037] The first bias voltage is connected to the second input terminal of the comparator through the first switch;

[0038] The second input terminal of the comparator is connected to the second end of the first capacitor, and the output terminal outputs the turn-off control signal.

[0039] The present invention also provides a BUCK constant current circuit, which is connected to a DC power supply and outputs a constant current to a load. The BUCK constant current circuit includes the average current controller described in any one of the above.

[0040] Optionally, the load is an LED.

[0041] As described above, the average current controller and the BUCK constant current circuit of the present invention are directed to the BUCK architecture that uses open-loop constant current control in the prior art, and the current sampling resistor Rcs is sampled at the low-voltage end. The control method of 2 times of Δt control + constant turn-off time Toff can be used to achieve the constant current output of the BUCK architecture. As long as the system operates in CCM, only the MOS transistor switching current at the Ton moment can be sampled to control the magnitude of the load output current, and the load output current does not change with the output voltage Vout and the inductance L. It can well solve the problem of the constant current accuracy of the load output, and does not require a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost. Description of the Drawings

[0042] Figure 1 It shows a schematic diagram of a BUCK architecture that uses open-loop constant current control in the prior art.

[0043] Figure 2 It shows a schematic diagram of the topology of the BUCK architecture that uses open-loop constant current control in the prior art, where the current sampling resistor is at the high-voltage end.

[0044] Figure 3 It shows Figure 2 The method for implementing open-loop constant current control of the BUCK architecture.

[0045] Figure 4 It shows a schematic diagram of the topology of the BUCK architecture that uses open-loop constant current control in the prior art, where the current sampling resistor is at the low-voltage end.

[0046] Figure 5 It shows Figure 4 The method for implementing open-loop constant current control of the BUCK architecture.

[0047] Figure 6 It shows the method for implementing open-loop constant current control of the BUCK architecture by the average current controller of the present invention.

[0048] Figure 7Schematic diagram of the average current controller of the present invention.

[0049] Description of component labels

[0050] 100 First current generation module

[0051] 200 Current mirror

[0052] 300 Second current generation module

[0053] 400 Capacitor charge / discharge module

[0054] 500 MOS transistor turn-off signal control module

[0055] 600 Logic control module Detailed implementation manners

[0056] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please refer to Figures 6 to 7 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0058] As Figure 6 and Figure 7 shown, the average current controller provided in this embodiment is for the BUCK architecture that uses open-loop constant current control in the prior art, and the current sampling resistor Rcs is sampled at the low-voltage end. It can implement a control method of 2 times Δt control (i.e., on-time Ton) + constant off-time Toff (or constant frequency f) to achieve constant current output of the BUCK architecture. As long as it is ensured that the system operates in CCM (Continuous Conduction Mode), the MOS transistor switch current at Ton time can be sampled to control the magnitude of the load output current, and the load output current does not change with the output voltage Vout and the inductance L. It can well solve the problem of constant current accuracy of the load output, and does not require a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost.

[0059] The average current controller includes:

[0060] The first current generation module 100, current mirror 200, second current generation module 300, capacitor charge / discharge module 400, MOS transistor turn-off signal control module 500, and logic control module 600;

[0061] The first current generation module 100 is connected to the current sampling resistor Rcs and receives a first reference voltage Vref1, and generates a current comparison signal based on the sampling voltage Vcs of the current sampling resistor Rcs and the first reference voltage Vref1;

[0062] The current mirror 200 is connected to the output end of the first current generation module 100, and mirrors the current comparison signal into a charge / discharge current comparison signal;

[0063] The second current generation module 300 is connected to the output end of the current mirror 200 and receives a second reference voltage Vref2, and generates a charge / discharge current reference signal based on the second reference voltage Vref2;

[0064] The capacitor charge / discharge module 400 is connected to the current mirror 200 and the second current generation module 300, and controls the charge / discharge of the capacitor (such as the first capacitor C1 in Figure 7 the capacitor charge / discharge module 400) based on the current difference between the charge / discharge current comparison signal and the charge / discharge current reference signal;

[0065] The MOS transistor turn-off signal control module 500 is connected to the output end of the capacitor charge / discharge module 400, and generates a turn-off control signal based on the voltage of the capacitor in the capacitor charge / discharge module 400;

[0066] The logic control module 600 is connected to the output end of the MOS transistor turn-off signal control module 500, generates a turn-off signal of the MOS transistor N in the BUCK circuit based on the turn-off control signal, and generates a turn-on signal of the MOS transistor N after a preset time Toff (Toff is the constant turn-off time of the MOS transistor N).

[0067] Such as Figure 6As shown, during the Ton time, the charging / discharging current difference between the charging / discharging current comparison signal Ichg generated by the current mirror 200 and the charging / discharging current reference signal Idis generated by the second current generation module 300 controls the charging and discharging of the capacitor in the capacitor charging / discharging module 400. The capacitor is charged through the Δt time and then discharged through the Δt time, thereby achieving the precise replication of the Δt time. In addition, the MOS transistor turn-off signal control module 500 generates a turn-off control signal based on the voltage of the capacitor in the capacitor charging / discharging module 400, so that the logic control module 600 generates a turn-off signal for the MOS transistor N based on this turn-off control signal, thereby achieving the turn-off of the MOS transistor N after 2 times the Δt time. Finally, the logic control module 400 generates a turn-on signal for the MOS transistor N after a preset time Toff and enters the next Ton time, repeating this process, thereby realizing the control method of 2 times the Δt control + constant turn-off time Toff. This control method can control the magnitude of the output current by only sampling the current of the MOS transistor N during the Ton time, and the output current is always constant at Vref / Rcs, where Vref is the reference voltage. This output current does not change with the output voltage Vout and the inductance L, thereby effectively solving the problem of output constant current accuracy, and does not require a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost.

[0068] As Figure 4 shown, as an example, the BUCK circuit includes: the current sampling resistor Rcs, the MOS transistor N, the freewheeling diode D, the capacitor C, and the inductor L; the first end of the current sampling resistor Rcs is connected to the first end of the MOS transistor N, and the second end is connected to the low-voltage end of the DC power supply DC; the second end of the MOS transistor N is connected to the anode of the freewheeling diode D and the first end of the inductor L; the second end of the inductor L is connected to the first end of the capacitor C; the high-voltage end of the DC power supply DC is connected to the cathode of the freewheeling diode D and the second end of the capacitor C. It should be noted here that Figure 4 this is only a schematic of the BUCK circuit, and those skilled in the art know that the BUCK circuit can also have other forms of deformation, and all of them can use the average current controller of this embodiment to achieve open-loop constant current control.

[0069] As Figure 7 shown, as an example, the first current generation module 100 includes: the first operational amplifier OP1, the first resistor R1, and the fifth MOS transistor Q5;

[0070] The sampled voltage Vcs is connected to the first input terminal of the first operational amplifier OP1 and the first end of the fifth MOS transistor Q5 through the first resistor R1;

[0071] The second input terminal of the first operational amplifier OP1 is connected to the first reference voltage Vref1, and the output terminal is connected to the second terminal of the fifth MOS transistor Q5;

[0072] The third terminal of the fifth MOS transistor Q5 is connected to the input terminal of the current mirror 200.

[0073] As a further example, the fifth MOS transistor Q5 is an N-type MOS transistor; the first terminal of the fifth MOS transistor Q5 is the source electrode, the second terminal of the fifth MOS transistor Q5 is the gate electrode, and the third terminal of the fifth MOS transistor Q5 is the drain electrode; the first input terminal of the first operational amplifier OP1 is the inverting input terminal, and the second input terminal of the first operational amplifier OP1 is the non-inverting input terminal.

[0074] The first current generation module 100 converts the sampled voltage signal into a current signal through a transconductance operational amplifier circuit, and provides a current comparison signal for the subsequent charging / discharging of the capacitor. During the Ton time, the current flowing through the fifth MOS transistor Q5 (i.e., the current comparison signal) is (Vref1 - Vcs) / R1.

[0075] As Figure 7 shown, as an example, the current mirror 200 is a cascode current mirror, and the current mirror 200 is used to mirror the current comparison signal generated by the first current generation module 100 into a charging / discharging current comparison signal Ichg. The current mirror adopting the cascode mode can improve the accuracy of current mirroring. The cascode current mirror includes:

[0076] The first MOS transistor Q1 and the third MOS transistor Q3 connected in series and the second MOS transistor Q2 and the fourth MOS transistor Q4 connected in series;

[0077] The drain electrode of the third MOS transistor Q3 is connected to the third terminal of the fifth MOS transistor Q5, and receives the current comparison signal output by the first current generation module 100;

[0078] The drain electrode of the fourth MOS transistor Q4 is connected to the capacitor charging / discharging module 400 and the second current generation module 300, and is used to provide the charging / discharging current comparison signal Ichg for the second current generation module 300, so as to compare with the charging / discharging current reference signal Idis generated by the second current generation module 300 to control the charging / discharging of the capacitor in the capacitor charging / discharging module 400;

[0079] The source of the first MOS transistor Q1 and the source of the second MOS transistor Q2 are connected and commonly connected to the working voltage VDD; the gates of the first MOS transistor Q1 and the second MOS transistor Q2 are connected, so that the first MOS transistor Q1 and the second MOS transistor Q2 adopt a cascode structure, mirror the current in the branch where the first MOS transistor Q1 is located to the branch where the second MOS transistor Q2 is located, and output through the fourth MOS transistor Q4.

[0080] As Figure 7 shown, as an example, the second current generation module 300 includes: a second operational amplifier OP2, a second resistor R2, and a sixth MOS transistor Q6;

[0081] The reference ground terminal is connected to the first input terminal of the second operational amplifier OP2 and the first terminal of the sixth MOS transistor Q6 through the second resistor R2;

[0082] The second input terminal of the second operational amplifier OP2 is connected to the second reference voltage Vref2, and the output terminal is connected to the second terminal of the sixth MOS transistor Q6;

[0083] The third terminal of the sixth MOS transistor Q6 is connected to the current mirror 200 and the capacitor charge / discharge module 400; when the current mirror 200 is a cascode current mirror, the third terminal of the sixth MOS transistor Q6 is connected to the drain of the fourth MOS transistor Q4 of the cascode current mirror.

[0084] As a further example, the first terminal of the sixth MOS transistor Q6 is the source, the second terminal of the sixth MOS transistor Q6 is the gate, and the third terminal of the sixth MOS transistor Q6 is the drain; the first input terminal of the second operational amplifier OP2 is the inverting input terminal, and the second input terminal of the second operational amplifier OP2 is the non-inverting input terminal.

[0085] The second current generation module 300 converts the second reference voltage Vref2 into a current signal through a transconductance operational amplifier circuit, provides a current reference signal for the subsequent charging and discharging of the capacitor, and within the Ton time, the current flowing through the sixth MOS transistor Q6 (i.e., the current reference signal) is Vref2 / R2.

[0086] Due to efficiency issues, the current sampling resistor Rcs is generally very small, and the obtained sampling voltage Vcs is also very small. If the sampling voltage Vcs is directly input to the comparator to control the charging / discharging of the capacitor, the delay is relatively large, and the delay of the comparator will affect the constant current accuracy of the system. In this embodiment, through the first current generation module 100, the current mirror 200, and the second current generation module 300, especially the first current generation module 100 and the second current generation module 300 both adopt a transconductance operational amplifier circuit to achieve the conversion of voltage to current, ensuring the control accuracy of the average current, generating a current difference, and realizing the precise control of the charging / discharging of the capacitor in the subsequent capacitor charging / discharging module 400, thereby ensuring the constant current accuracy of the entire system.

[0087] As Figure 7 shown, as an example, the capacitor charging / discharging module 400 includes a first capacitor C1. The first end of the first capacitor C1 is connected to the reference ground terminal, and the second end of the first capacitor C1 is connected to the current mirror 200 and the MOS transistor turn-off signal control module 500; when the current mirror 200 is a cascode current mirror, the second end of the first capacitor C1 is connected to the drain of the fourth MOS transistor Q4 of the cascode current mirror.

[0088] As Figure 7 shown, as an example, the MOS transistor turn-off signal control module 500 includes:

[0089] Comparator Cp1, second capacitor C2, first switch SW1, and second switch SW2;

[0090] The second capacitor C2 is connected to the first input terminal of the comparator Cp1 and is connected to the second input terminal of the comparator Cp1 through the second switch SW2;

[0091] The first bias voltage Vbias is connected to the second input terminal of the comparator Cp1 through the first switch SW1;

[0092] The second input terminal of the comparator Cp1 is connected to the second end of the first capacitor C1, and the output terminal outputs the turn-off control signal.

[0093] It is not limited that the first input terminal of the comparator Cp1 is the positive input terminal or the negative input terminal, and the second input terminal is the negative input terminal or the positive input terminal. In this embodiment, the first input terminal of the comparator Cp1 is selected as the negative input terminal, and the second input terminal is selected as the positive input terminal.

[0094] Next, in combination with Figure 7 For Figure 6 this embodiment of the average current controller, the control method will be described: In the MOS transistor N (refer to Figure 4)During Ton time, the first switch SW1 and the second switch SW2 are turned off, and the initial voltages of the first capacitor C1 and the second capacitor C2 are the same, which is the first bias voltage Vbias. In the first half of Ton for the first capacitor C1, that is, during the generation time of Δt, based on Ichg = (Vref1 - Vcs) / R1, Idis = Vref2 / R2, and since Vcs is relatively small, Ichg > Idis. Then the first capacitor C1 in the capacitor charge / discharge module 400 is charged, and the voltage V of the first capacitor C1 C1 rises parabolically based on the first bias voltage Vbias (as Figure 7 shown); afterwards, as Vcs continues to rise until Ichg = Idis, that is, (Vref1 - Vcs) / R1 = Vref2 / R2. For the simplicity of the circuit, R1 = R2 and Vref1 = 2*Vref2 can be designed. Then when Ichg = Idis, the equation can be simplified to: Vcs = Vref2. That is, during Ton time, the average value of Vcs is controlled to be Vref2; then Vcs continues to rise until Ichg < Idis, entering the second half of Ton, that is, the replication time of Δt. At this time, the first capacitor C1 discharges to the second current generation module 300, and the voltage V of the first capacitor C1 C1 starts to decline parabolically until it returns to the Vbias value, the comparator Cp1 flips, generating a turn-off control signal. The logic control module 600 generates a turn-off signal for the MOS transistor based on this turn-off control signal, thus completing the constant current control of Vref2 for Vcs during the Ton time period; during the Toff time, that is, during the turn-off time of the MOS transistor, the first switch SW1 and the second switch SW2 are turned on. Although there is a charging current for the first capacitor C1 at this time, the voltages of the first capacitor C1 and the second capacitor C2 will be clamped to the first bias voltage Vbias value. After the Toff time, the logic control module generates a turn-on signal for the MOS transistor, entering the next Ton time, and so on, working in a cycle to achieve a control method of 2 times Δt control + constant turn-off time Toff. Because the system operates in the CCM mode, the average value of the switch current of the MOS transistor during the Ton time period is equal to the average value of the inductor current, which is also equal to the average value of the load output current. Therefore, this circuit controls the average value of the switch current during the Ton time period through Vref2, indirectly achieving the purpose of controlling the load output current. Moreover, the load output current does not change with the output voltage Vout and the inductance L, which can well solve the problem of the constant current accuracy of the load output, and does not require a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost.

[0095] As Figure 4As shown, by way of example, the MOS transistor N is an N-channel enhancement-mode MOS transistor. However, this is not limiting, and the MOS transistor N can also be other types of MOS transistors.

[0096] By way of example, there is no limitation here on how the logic control module 600 implements the preset time Toff, that is, the turn-off time Toff of the MOS transistor N. For example, it can be implemented by a constant time method (such as a clock circuit) or a constant frequency method.

[0097] Based on the average current controller of the above example, the present embodiment further provides a BUCK constant current circuit that is connected to a DC power supply and outputs a constant current to a load. The BUCK constant current circuit includes the above-mentioned average current controller.

[0098] By way of example, the BUCK constant current circuit can achieve a constant current output for an LED.

[0099] In summary, for the average current controller and the BUCK constant current circuit of the present invention, for the BUCK architecture that uses open-loop constant current control in the prior art and the current sampling resistor Rcs sampling topology at the low-voltage end, a control method of 2-fold Δt control + constant turn-off time Toff can be used to achieve a constant current output of the BUCK architecture. As long as it is ensured that the system operates in CCM, the MOS transistor switching current at only the Ton moment can be sampled to control the magnitude of the load output current, and the load output current does not change with the output voltage Vout and the inductance L, which can well solve the problem of the constant current accuracy of the load output, and there is no need for a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0100] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An average current controller is applied to a BUCK circuit. Wherein, The BUCK circuit operates in the CCM mode and the current sampling resistor is set at the low voltage end. It is characterized in that the average current controller includes: A first current generation module, a current mirror, a second current generation module, a capacitor charge / discharge module, a MOS tube turn-off signal control module and a logic control module; The first current generation module is connected to the current sampling resistor and receives a first reference voltage, and generates a current comparison signal based on the sampling voltage of the current sampling resistor and the first reference voltage; The current mirror is connected to the output end of the first current generation module, and mirrors the current comparison signal into a charge / discharge current comparison signal; The second current generation module is connected to the output end of the current mirror and receives a second reference voltage, and generates a charge / discharge current reference signal based on the second reference voltage; The capacitor charge / discharge module is connected to the current mirror and the second current generation module, and controls the charge / discharge of the capacitor in the capacitor charge / discharge module based on the current difference between the charge / discharge current comparison signal and the charge / discharge current reference signal; The MOS tube turn-off signal control module is connected to the output end of the capacitor charge / discharge module, and generates a turn-off control signal based on the voltage of the capacitor in the capacitor charge / discharge module; The logic control module is connected to the output end of the MOS tube turn-off signal control module, generates a turn-off signal of the MOS tube in the BUCK circuit based on the turn-off control signal, and generates a turn-on signal of the MOS tube after a preset time; Wherein, the first current generation module includes: A first operational amplifier, a first resistor and a fifth MOS tube; The sampling voltage is connected to the first input end of the first operational amplifier and the first end of the fifth MOS tube through the first resistor; The second input end of the first operational amplifier is connected to the first reference voltage, and the output end is connected to the second end of the fifth MOS tube; The third end of the fifth MOS tube is connected to the input end of the current mirror; The second end of the fifth MOS tube is the gate, the first input end of the first operational amplifier is the inverting input end, and the second input end of the first operational amplifier is the non-inverting input end; The second current generation module includes: A second operational amplifier, a second resistor and a sixth MOS tube; The reference ground terminal is connected to the first input end of the second operational amplifier and the first end of the sixth MOS tube through the second resistor; The second input end of the second operational amplifier is connected to the second reference voltage, and the output end is connected to the second end of the sixth MOS tube; The third end of the sixth MOS tube is connected to the current mirror and the capacitor charge / discharge module; The second end of the sixth MOS tube is the gate, the first input end of the second operational amplifier is the inverting input end, and the second input end of the second operational amplifier is the non-inverting input end.

2. The average current controller according to claim 1, It is characterized in that, The BUCK circuit includes: the current sampling resistor, the MOS transistor, the freewheeling diode, the capacitor and the inductor; a first end of the current sampling resistor is connected to a first end of the MOS transistor, and a second end thereof is connected to a low-voltage end of the DC power supply; a second end of the MOS transistor is connected to an anode of the freewheeling diode and a first end of the inductor; a second end of the inductor is connected to a first end of the capacitor; a high-voltage end of the DC power supply is connected to a cathode of the freewheeling diode and a second end of the capacitor.

3. The average current controller according to claim 2, wherein, the current mirror is a cascode current mirror, and includes: a first MOS transistor and a third MOS transistor connected in series, and a second MOS transistor and a fourth MOS transistor connected in series; a drain of the third MOS transistor is connected to a third end of the fifth MOS transistor; a drain of the fourth MOS transistor is connected to the capacitor charging / discharging module and the second current generating module; a source of the first MOS transistor and a source of the second MOS transistor are connected and commonly connected to the operating voltage; a gate of the first MOS transistor and a gate of the second MOS transistor are connected.

4. The average current controller according to claim 3, wherein: the fifth MOS transistor is an N-type MOS transistor; a first end of the fifth MOS transistor is the source, and a third end thereof is the drain; the sixth MOS transistor is an N-type MOS transistor; a first end of the sixth MOS transistor is the source, and a third end thereof is the drain.

5. The average current controller according to claim 3, wherein: the capacitor charging / discharging module includes a first capacitor, a first end of the first capacitor is connected to the reference ground terminal, and a second end thereof is connected to a drain of the fourth MOS transistor and the MOS transistor turn-off signal control module.

6. The average current controller according to claim 5, wherein, the MOS transistor turn-off signal control module includes: a comparator, a second capacitor, a first switch and a second switch; the second capacitor is connected to a first input terminal of the comparator and is connected to a second input terminal of the comparator through the second switch; a first bias voltage is connected to the second input terminal of the comparator through the first switch; the second input terminal of the comparator is connected to a second end of the first capacitor, and an output terminal outputs the turn-off control signal.

7. A BUCK constant current circuit is connected to a DC power supply and outputs a constant current to a load, wherein, the BUCK constant current circuit includes the average current controller according to any one of claims 1 to 6.

8. The BUCK constant current circuit according to claim 7, wherein: the load is an LED.

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