Cameras and electronic equipment

Abstract

Provided are an image pickup device and an electronic device capable of reducing the delay of a control signal according to the horizontal position of a pixel. A time code generation unit (104) is arranged on the first side of a pixel array (150), a signal processing unit (105) is arranged on the second side of the pixel array opposite to the first side, a timing generation circuit (120) is arranged on the second side of the pixel array, each of a plurality of transmission units (110) is arranged from the first side to the second side through the pixel array, and a control line (130) is arranged in each of two or more of the plurality of transmission units, the control line being used to transmit the timing signal generated by the timing signal generation unit to the time code generation unit.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and an electronic device. Background Art

[0002] An image pickup element using an in-pixel ADC structure is known, which includes an ADC (analog to digital converter) in a pixel that converts a pixel signal (i.e., an analog signal) into a digital signal. In this in-pixel ADC structure, a control signal line for a control circuit is connected from a timing generation circuit provided at both ends of a pixel array in the horizontal direction to a circuit block for performing pixel control such as an ADC and a time code generator.

[0003] Citation list

[0004] Patent Literature

[0005] Patent document 1: WO 16 / 136448 A Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the prior art, a linear sensor that detects movement in a specific direction is known. In the case where the linear sensor is configured to include an image pickup device, the image pickup element has a structure in which, for example, the number of pixels in the horizontal direction in which a control signal is transmitted to each pixel is greater than in the vertical direction in which a pixel signal is transmitted. In the case where the above-mentioned in-pixel ADC structure is applied to such an image pickup device, a control signal line wired from a timing generation circuit becomes longer, and a load on the control signal line increases. Therefore, a propagation delay is generated in the control signal line with respect to the horizontal direction of the image pickup element.

[0008] The delay time due to propagation delay increases as the distance from the timing generation circuit increases. Therefore, at the timing of the control signal propagating to the control signal line, a perspective difference occurs according to the distance from the timing generation circuit, and the perspective difference causes a shadow of the captured image. In addition, since the delay time itself increases, high-speed responsiveness deteriorates, and it is difficult to increase the frame rate.

[0009] An object of the present disclosure is to provide an imaging device and an electronic device capable of suppressing a delay of a control signal according to a horizontal position of a pixel.

[0010] Technical solutions to the problem

[0011] According to the present disclosure, the camera device includes: a pixel array, in which pixels are arranged in a matrix array; a time code generation unit, which generates a time code; a signal processing unit, which performs signal processing on pixel data; a timing signal generation unit, which generates a timing signal for controlling at least the timing of generating the time code in the time code generation unit; and a plurality of transmission units, which transmit the time code to each of the pixels and transmit the pixel data to the signal processing unit, wherein the time code generation unit is arranged toward a first side of the pixel array, the signal processing unit is arranged toward a second side of the pixel array opposite to the first side, the timing generation circuit is arranged toward the second side of the pixel array, and the plurality of Each of the transmission units is arranged from the first side to the second side through the pixel array, and a control line is set in each of two or more of the multiple transmission units, and the control line is used to transmit the timing signal generated by the timing signal generating unit to the time code generating unit, each pixel includes: a light receiving element, which generates an electric charge through photoelectric conversion according to received light; a pixel circuit, which reads the electric charge from the light receiving element and outputs an analog signal corresponding to the electric charge; and a conversion circuit, which compares the analog signal with a reference signal whose voltage changes with time, and according to the comparison result, based on the time code whose value is updated per unit time, converts the analog signal into pixel data as a digital signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram showing the configuration of an example of an electronic device applicable to an embodiment of the present disclosure.

[0013] Figure 2 It is a schematic diagram for explaining a usage example of an electronic device applicable to the embodiment.

[0014] Figure 3 1 is a diagram showing an example of a stacked structure of a solid-state imaging element as an imaging device applicable to the embodiment.

[0015] Figure 4 is a block diagram showing the configuration of an example of a pixel applicable to the embodiment.

[0016] Figure 5 is a schematic diagram showing the layout of an example of a solid-state imaging element according to the embodiment.

[0017] Figure 6 is a schematic diagram showing a configuration of an example of a solid-state image pickup element according to the embodiment.

[0018] Figure 7 is a block diagram showing the configuration of an example of the timing generation circuit according to the embodiment in more detail.

[0019] Figure 8 is a block diagram showing a configuration of an example of a timing generation circuit including a delay amount adjustment unit that adjusts delay according to an embodiment.

[0020] Fig. 9 is a circuit diagram showing a configuration of an example of a transmission circuit applicable to the embodiment.

[0021] Fig. 10A is a schematic diagram showing an example of accessing a pixel array unit through a transfer circuit applicable to the embodiment.

[0022] Fig. 10B is a schematic diagram showing a state where a time code is written.

[0023] Fig.11A is a schematic diagram showing a state of reading a time code.

[0024] Fig. 11B is a timing chart showing an example of the timing related to the reading of the time code.

[0025] Fig.12 is a schematic diagram showing an example of the layout of control lines according to the embodiment.

[0026] Fig.13 is a diagram showing an example of shielding for the control line 130 provided in the transmission circuit 110 according to the embodiment.

[0027] Fig.14A is a diagram showing an example of the layout of a solid-state imaging element according to the related art.

[0028] Fig. 14B is a diagram showing an example of the layout of a solid-state imaging element according to the embodiment.

[0029] Fig.15 is a schematic diagram showing a configuration of an example of a solid-state image pickup element according to a first modification of the embodiment.

[0030] Fig.16A is a schematic diagram showing a configuration of an example of a solid-state image pickup element according to a second modification of the embodiment.

[0031] Fig. 16B is a block diagram showing the configuration of any of the units according to the second modification example of the embodiment in more detail. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. Note that in the following embodiments, the same parts are denoted by the same reference numerals, and thus repeated descriptions will be omitted.

[0033] Hereinafter, embodiments of the present disclosure will be described in the following order.

[0034] 1. Configuration applicable to the embodiment

[0035] 2. Configuration according to the embodiment

[0036] 2-1. Timing generation circuit

[0037] 2-2. Transmission circuit

[0038] 2-3. Shielding structure

[0039] 2-4. Effects of the Embodiments

[0040] 3. First Modification of the Embodiment

[0041] 4. Second Modification of the Embodiment

[0042] [1. Configuration applicable to the embodiment]

[0043] First, a configuration applicable to an embodiment of the present disclosure will be described. Figure 1 1 is a block diagram showing a configuration of an example of an electronic device 1000 applicable to an embodiment of the present disclosure. The electronic device 1000 is a device that captures image data, and includes an optical unit 2000, a solid-state imaging element 10, a storage unit 2001, a control unit 2002, and a communication unit 2003.

[0044] The optical unit 2000 converges incident light and guides the light to the solid-state imaging element 10. The solid-state imaging element 10 includes a pixel array in which pixels are arranged in a matrix array, and performs imaging based on the incident light to output image data. The solid-state imaging element 10 provides the image data output by imaging to the storage unit 2001 via the signal line 2005.

[0045] The storage unit 2001 can store image data supplied from the solid-state imaging element 10. The control unit 2002 causes the solid-state imaging element 10 to perform imaging processing. For example, the control unit 2002 supplies various synchronization signals for controlling imaging timing and the like to the solid-state imaging element 10 via the signal line 2004.

[0046] The communication unit 2003 performs communication between the electronic device 1000 and an external device, and can transmit, for example, image data read from the storage unit 2001 to the outside.

[0047] Figure 2 1 is a schematic diagram for explaining an example of use of the electronic device 1000 applicable to the embodiment. Figure 2As shown, the electronic device 1000 can be used in a factory provided with a belt conveyor 510 .

[0048] The belt conveyor 510 moves the object 511 in a predetermined direction at a constant speed. The electronic device 1000 is fixed near the belt conveyor 510 and captures an image of the object 511 to generate image data. For example, the image data is used to check for defects. As a result, factory automation (FA) is achieved.

[0049] Note that Figure 2 In the example in which the electronic device 1000 captures an image of the subject 511 moving at a constant speed, the use example of the electronic device 1000 is not limited to this example. For example, the electronic device 1000 may be configured to move at a constant speed relative to the subject and perform imaging, such as aerial imaging.

[0050] Figure 3 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 10 as an imaging device applicable to the embodiment. The solid-state imaging element 10 includes a circuit chip 301 and a light receiving chip 300 bonded to the circuit chip 301 in a stacked structure. The light receiving chip 300 and the circuit chip 301 are electrically connected via a connection portion such as a through hole. Note that the electrical connection between the light receiving chip 300 and the circuit chip 301 can also be achieved by Cu-Cu bonding or bumps instead of through holes.

[0051] Figure 4 1 is a block diagram showing a configuration of an example of a pixel 11 applicable to the embodiment. Figure 4 As shown, the pixel 11 includes a pixel circuit 100 and an ADC (analog to digital converter) 102 .

[0052] The pixel circuit 100 outputs a charge signal corresponding to the amount of received light as an analog pixel signal SIG to the ADC 102. The pixel circuit 100 includes a photodiode as a light receiving element, a discharge transistor that discharges the charge accumulated in the photodiode and adjusts the exposure time according to a signal OFG, a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion layer (FD) according to a signal TRG, and a reset transistor that resets the FD according to a signal RST.

[0053] When the discharge transistor is turned on by the signal OFG, the pixel circuit 100 discharges the charge accumulated in the photodiode, thereby starting exposure. After the FD is reset by turning on the reset transistor by the signal RST, the transfer transistor is turned on by the signal TRG, and the charge accumulated in the photodiode by exposure is transferred to the FD and accumulated in the FD. The charge accumulated in the FD is converted into a voltage by reading out from the FD, and is output from the pixel circuit 100 as an analog pixel signal SIG.

[0054] The ADC 102 converts the analog pixel signal SIG supplied from the pixel circuit 100 into a digital signal. The ADC 102 includes a comparison circuit 51 and a data storage unit 52. The comparison circuit 51 compares the reference signal REF supplied from the DAC (digital to analog converter) 101 with the pixel signal SIG, and outputs an output signal VCO as a comparison result signal indicating a comparison result. When the reference signal REF and the pixel signal SIG become the same (the same voltage), the comparison circuit 51 inverts the output signal VCO.

[0055] The comparison circuit 51 includes a differential input circuit 61, a voltage conversion circuit 62, and a positive feedback circuit 63. The differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 100 in the pixel 11 with the reference signal REF output from the DAC 101, and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF. The voltage conversion circuit 62 converts the current of the signal output from the differential input circuit 61 into a voltage signal. Based on the signal output from the voltage conversion circuit 62, a comparison result signal inverted when the pixel signal SIG is higher than the reference signal REF is output. The output of the positive feedback circuit 63 as the above-mentioned output signal VCO is provided to the data storage unit 52.

[0056] The data storage unit 52 receives the output signal VCO from the comparison circuit 51 and also receives the output signal VCO from the later reference circuit 51. Figure 5 The pixel drive circuit 103 described above provides the data storage unit 52 with a signal WR indicating a write operation of a pixel signal, a signal RD indicating a read operation of a pixel signal, and a signal WORD controlling the read timing of the pixel 11 during the read operation of the pixel signal. In addition, the time code transmission unit 23 also provides the data storage unit 52 with a signal WR indicating a write operation of a pixel signal, a signal RD indicating a read operation of a pixel signal, and a signal WORD controlling the read timing of the pixel 11 during the read operation of the pixel signal. Figure 5 The time code generated by the time code generator 104 is described.

[0057] The data storage unit 52 includes a latch control circuit 71 that controls a write operation and a read operation of a time code based on signals WR and RD, and a latch storage unit 72 that stores the time code.

[0058] In the time code writing operation, when the output signal VCO in the High state is input from the comparison circuit 51, the latch control circuit 71 causes the latch storage unit 72 to store the time code supplied from the time code transmission unit 23 and updated every unit time. When the reference signal REF and the pixel signal SIG become the same (voltage) and the output signal VCO supplied from the comparison circuit 51 is inverted to the Low state, the latch control circuit 71 stops writing (updating) the supplied time code and causes the latch storage unit 72 to hold the time code finally stored in the latch storage unit 72. The time code stored in the latch storage unit 72 indicates the time when the pixel signal SIG and the reference signal REF become equal, and indicates data showing that the pixel signal SIG is the reference voltage at this time, that is, the digitized light amount value.

[0059] After the sweeping out of the reference signal REF is completed and the time code is stored in the latch storage unit 72 of all the pixels 11 in the pixel array, the operation of the pixel 11 changes from a write operation to a read operation.

[0060] In the time code reading operation, when the pixel 11 becomes its own reading timing based on the signal WORD for controlling the reading timing, the latch control circuit 71 outputs the time code (digital pixel signal SIG) stored in the latch storage unit 72 to the time code transmission unit 23. The time code transmission unit 23 sequentially transmits the supplied time code in the column direction (vertical direction), and supplies the time code to a reference later. Figure 5 The signal processing circuit 105 is described.

[0061] Note that Figure 4 In the configuration of the pixel 11, the portion related to the analog signal, that is, the pixel circuit 100 and a portion of the ADC 102 (for example, a portion of the differential input circuit 61) are arranged in Figure 3 In addition, a portion related to a digital signal included in the pixel 11, for example, another portion of the comparison circuit 51 including another portion of the differential input circuit 61, the DAC 101, and the time code transmission unit 23 are provided. Figure 3 In the circuit chip 301 shown.

[0062] Figure 5 1 is a schematic diagram showing the layout of an example of the solid-state imaging element 10 according to the embodiment. More specifically, Figure 5 FIG. 3 shows an example of the layout of the circuit chip 301 of the solid-state imaging element 10. Figure 5 In the subsequent similar drawings, the left-right direction is defined as the horizontal direction, and the up-down direction is defined as the vertical direction.

[0063] exist Figure 5 In the example of FIG. 3 , in the circuit chip 301, the output interface 106, the signal processing circuit 105, and the timing generation circuit 120 are arranged from the bottom to the top. In addition, the DAC 101, the pixel driving circuit 103, and the time code generator 104 are arranged from the top to the bottom. The pixel array unit 150 is arranged between the timing generation circuit 120 and the time code generator 104.

[0064] The pixel array unit 150 includes a plurality of pixels 11 arranged in a matrix array. At this time, on the circuit chip 301, as described above, a part of the ADC 102 in the pixel 11 is provided, for example, except for a part of the differential input circuit 61 provided on the light receiving chip 300. Figure 5 As ADC 102, it is shown Figure 4 The configuration of the ADC 102 excluding a part of the differential input circuit 61 provided on the light receiving chip 300 . This also applies to the following similar figures.

[0065] With the pixel array unit 150, a plurality of transfer circuits 110 are arranged at predetermined intervals in the horizontal direction from the upper end side (first side) toward the lower end side (second side) of the pixel array unit 150. That is, in the pixel array unit 150, assuming that the arrangement of the ADCs 102 (pixels 11) in the horizontal direction is a row and the arrangement of the ADCs (pixels 11) in the vertical direction is a column, the transfer circuits 110 are arranged along the column direction in the pixel array unit 150.

[0066] exist Figure 5 In the example of FIG. 1 , each transmission circuit 110 has the following configuration: the transmission circuit 110 is connected to one ADC 102 on the left and one on the right in each row. Figure 5 In the example of FIG. 1 , in the pixel array unit 150 , the number of transfer circuits 110 is equal to “(the number of pixels in the row direction) / 2”.

[0067] Each transmission circuit 110 includes the above-mentioned time code transmission unit 23. In addition, each transmission circuit 110 also serves as a path for transmitting image data output from each pixel 11 of the pixel array unit 150 to the signal processing circuit 105.

[0068] In addition, the pixel array unit 150 according to the embodiment has a very elongated shape in the horizontal direction, for example, thousands of pixels in the row direction and tens of pixels in the column direction, that is, the pixel array unit 150 has a very large aspect ratio.

[0069] Note that Figure 5In the examples of 1 and subsequent similar figures, each transmission circuit 110 is shown as being provided between two ADCs 102, but this is for illustrative purposes. In reality, the ADCs 102 (pixels 11) are arranged in a lattice pattern with equal intervals, and the transmission circuits 110 are provided in a layer different from the ADCs 102. That is, each transmission circuit 110 is provided in a stacked structure with a portion overlapping with each ADC 102 (pixel 11) in the layer direction.

[0070] (2. Configuration according to the embodiment)

[0071] Next, the configuration of an embodiment according to the present disclosure will be described. Figure 6 1 is a schematic diagram showing a configuration of an example of a solid-state imaging element 10 according to an embodiment. Figure 6 As shown, in the embodiment, a control line 130 is provided in each transfer circuit 110, and a configuration of a timing generation circuit 120 and a pixel array unit 150 which are provided away from the timing generation circuit 120 are connected through each control line 130. The timing generation circuit 120 generates various timing signals for driving the solid-state imaging element 10. The timing generation circuit 120 has a function as a timing signal generating unit which generates a timing signal which controls at least the timing at which the time code generator 104 generates a time code.

[0072] More specifically, the control line 130 includes a plurality of control lines 130a, 130b, 130c, and 130d. The timing generation circuit 120 can output different timing signals to the control lines 130a, 130b, 130c, and 130d.

[0073] exist Figure 6 In the example of , the control line 130a is a control line for providing the timing signal generated by the timing generation circuit 120 to the pixel driving circuit 103. The pixel driving circuit 103 generates a driving signal (for example, the above-mentioned signal OFG, signal TRG, and signal RST) for driving each pixel 11 in the pixel circuit 100 based on the timing signal provided via the control line 130a. The pixel driving circuit 103 provides the generated driving signal to each pixel 11 via the transmission circuit 110.

[0074] The control line 130b is a control line for supplying the timing signal generated by the timing generation circuit 120 to the time code generator 104. The time code generator 104 generates a time code whose value is updated per unit time based on the timing signal supplied via the control line 130b. The time code generator 104 supplies the generated time code to each pixel 11 via the transmission circuit 110.

[0075] The control line 130c is a control line for supplying the timing signal generated by the timing generation circuit 120 to each ADC 102. The timing signal includes, for example, the above-mentioned signal WR, signal RD, and signal WORD, and the ADC 102 is driven by the timing signal.

[0076] In addition, the control line 130d is a control line for supplying the timing signal generated by the timing generation circuit 120 to the DAC 101. The DAC 101 starts scanning of the reference signal REF, for example, according to the timing signal.

[0077] In the embodiment, the timing generation circuit 120 is configured to be able to suppress delays between the transmission circuits 110 in the timing signals respectively output to the control lines 130 a , 130 b , 130 c , and 130 d provided in each transmission circuit 110 .

[0078] Note that hereinafter, in the case where there is no need to particularly distinguish the control lines 130 a , 130 b , 130 c , and 130 d , these control lines 130 a , 130 b , 130 c , and 130 d will be collectively referred to as control lines 130 .

[0079] (2-1. Timing Generation Circuit)

[0080] Next, the timing generation circuit 120 according to the embodiment will be described in more detail.

[0081] Figure 7 1 is a block diagram showing a configuration of an example of the timing generation circuit 120 according to the embodiment in more detail. Figure 7 In the embodiment, the timing generation circuit 120 includes a plurality of timing generation circuits 120 1 , 120 2 , ..., 120 N .exist Figure 7 In the example of 1 , 120 2 , ..., 120 N Each of the two transmission circuits 110 provides a timing signal to each control line 130. In this way, the timing signal can be transmitted from one timing generation circuit 120 to the other timing generation circuit 120, while the influence of the delay between the control lines 130 on the characteristics can be ignored. 1 Provided to a plurality of control lines 130 .

[0082] Here, if Figure 7 As shown, it will be considered that, for example, a plurality of timing generation circuits 120 1 , 120 2 , ..., 120 N The timing generation circuit 120 at the end of 1When an external synchronization signal used as a reference for the timing signal is input.

[0083] Timing generation circuit 120 1 A timing signal is generated based on the input external synchronization signal, and the timing signal is output to the control line 130, and a synchronization signal 121 based on the external synchronization signal is output to the control line 130. 1 Sent to the next stage timing generation circuit 120 2 . Timing generation circuit 120 2 Based on the input synchronization signal 121 1 Generates a timing signal and outputs the timing signal to the control line 130, and transmits the synchronization signal 121 1 As the synchronization signal 121 2 In this way, the synchronization signal 121 based on the external synchronization signal 1 ,121 2 , ...are sent to the next timing generation circuit in sequence.

[0084] In this case, for example, Figure 7 In the figure, the timing generation circuit 120 at the left end 1 Sent to the timing generation circuit 120 2 The synchronization signal 121 1 and sent to the timing generation circuit 120 at the right end N The synchronization signal is out of sync due to the delay.

[0085] When each timing generation circuit 120 1 , 120 2 , ... and 120 N When the synchronization signal provided in the embodiment is not synchronized, the timing generating circuits 120 connected to each other are connected to each other according to the synchronization deviation. 1 , 120 2 , ... and 120 N The timing of the timing signal propagated by each control line 130 generates a perspective difference, and the perspective difference causes a shadow in the captured image.

[0086] Therefore, in an embodiment, the timing generation circuit 120 1 , 120 2 , ..., each pair is based on the input synchronization signal 121 1 ,121 2 ,....the respective timing signals generated provide a predetermined delay.

[0087] Figure 8 1 is a block diagram showing a configuration of an example of a timing generation circuit including a delay amount adjustment unit for adjusting delay according to an embodiment. Figure 8In the timing generation circuit 120 1 Including a timing generation unit 122 1 and delay amount adjustment unit 123 1 Similarly, the timing generation circuit 120 2 , ... and 120 N Each includes a timing generation unit 122 2 , ... and 122 N , and a delay amount adjustment unit 123 2 , ... and 123 N .

[0088] Here, it is assumed that an external synchronization signal is input to the timing generation circuit 120 provided at the left end. 1 The delay amount adjustment unit 123 in 1 In this case, if only the distance in the horizontal direction is considered, the timing generation circuit 120 at the left end of the input external synchronization signal 1 The delay is approximately 0, and the timing generation circuit 120 arranged at the right end away from the input position of the external synchronization signal N Therefore, the timing generation circuit 120 is given 1 , 120 2 , ..., 120 N The delay amount of each of the timing generation circuits 120 on the left side provided with the external synchronization signal used as a reference 1 The timing generation circuit 120 is the largest and is located at the right end farthest from the position where the external synchronization signal is provided. N The smallest among them.

[0089] exist Figure 8 In the example, the external synchronization signal is provided to the timing generation circuit 120 at the left end. 1 , and input to the delay amount adjustment unit 123 1 Delay amount adjustment unit 123 1 Provides a synchronization signal based on the input external synchronization signal to the next stage timing generation circuit 120 2 , and supplies the synchronization signal delayed by giving a predetermined delay amount to the external synchronization signal to the timing generation unit 122 1 Here, each timing generation circuit 120 included in the timing generation circuit 120 1 , 120 2 , ... and 120 N In the delay amount given, the delay amount adjustment unit 123 1 The delay amount assigned is the maximum delay amount.

[0090] Timing generation unit 122 1Based on the delay amount adjustment unit 123 1 The synchronization signal to which the delay amount is given generates a timing signal, and the timing signal is output to the control line 130 .

[0091] In the timing generation circuit 120 2 In the delay amount adjustment unit 123 2 Further, the input synchronization signal 121 1 As the synchronization signal 121 2 Provided to the next stage timing generation circuit (not shown), and the synchronization signal 121 1 The delayed synchronization signal with a predetermined delay amount is provided to the timing generation unit 122. 2 Here, the timing generation circuit 120 2 Ratio timing generation circuit 120 1 Therefore, in the timing generation circuit 120 2 The delay amount adjustment unit 123 2 The delay amount given is smaller than that of the timing generation circuit 120 at the previous stage. 1 The delay amount adjustment unit 123 1 The amount of delay to assign.

[0092] In addition, in the timing generation circuit 120 1 , 120 2 , ... and 120 N In the timing generation circuit 120 farthest from the position where the external synchronization signal is supplied, N The delay amount adjustment unit 123 N The amount of delay imparted is minimal.

[0093] As described above, in the timing generation circuit 120 1 , 120 2 , ... and 120 N In each of the timing signals to be output, a delay amount corresponding to the distance from the position where the external synchronization signal is supplied is given, thereby generating a delay signal from the timing generation circuit 120. 1 , 120 2 , ... and 120 N The delay amount of each output timing signal is made uniform. As a result, the generation of a near-far difference due to a synchronization deviation is suppressed, and the generation of a shadow in a captured image can be prevented.

[0094] (2-2. Transmission circuit)

[0095] Next, the transmission circuit 110 according to the embodiment will be described in more detail.

[0096] Fig. 91 is a circuit diagram showing the configuration of an example of a transmission circuit 110 applicable to the embodiment. The transmission circuit 110 applicable to the embodiment is a shift register with a D-FF (flip-flop) 1110 as a core, and includes an MCK clock transmission unit 1101, an FF data transmission unit 1102, and a REN (read enable) signal transmission unit 1103. In order to transmit the read enable signal RENL on the left side of the figure and the read enable signal RENR on the right side, the REN signal transmission unit 1103 is provided on the left and right sides of the transmission circuit 110, respectively.

[0097] Circuit block 1100 at the level of D-FF 1110 1 , 1100 2 , ... and 1100 M In each of the FFs, read / write bidirectional buffers 1111L and 1111R (hereinafter referred to as bidirectional buffers 1111L and 1111R) are provided on the left and right sides of the FF output stage data line (hereinafter referred to as MBL) connected to the output of the D-FF 1110, and an nMOS (n-metal oxide semiconductor: n metal oxide semiconductor) transistor 1112 for initializing the MBL and initializing the low-level fixed transmission circuit (REPINI) is connected to the line.

[0098] In addition, Fig. 9 In the example, the transmission circuit 110 includes a transmission circuit 110 for each bit. 1 , 110 2 , ..., 110 n-1 , and the bit includes M circuit blocks 1100 1 , 1100 2 , ..., 1100 M In each pixel 11 included in the pixel array unit 150, the circuit block 1100 is controlled in a unit called a cluster including a predetermined number of pixels 11. 1 to 1100 M Each pixel in the read access.

[0099] The signal MCK is an operation clock signal of the D-FF 1110. The D-FF 1110 is used for the circuit block 1100. 1 Each bit line is set, that is, each transmission circuit 110 is set for each bit. 1 , 110 2 , ..., 110 n-1 The bidirectional buffers 1111L and 1111R are controlled by the write enable signal WEN and the read enable signal REN, thereby 1 to 1100M Each of them acts as a buffer when a write operation is performed from the MBL to a local bit line (hereinafter, LBL) or a buffer operation when a read operation is performed from the LBL to the MBL.

[0100] The signal WEN is fixed to a high level when the transfer circuit 110 is used as a transfer circuit for writing, and is fixed to a low level when the transfer circuit is used as a transfer circuit for reading. With this circuit configuration, the transfer circuit 110 can be used as both a transfer circuit for writing and a transfer circuit for reading.

[0101] By providing LBLL and LBLR, bidirectional buffers 1111L and 1111R on the left and right sides of the MBL, it is possible to hide a signal transition of data read by the signal WORD at the timing of operating the D-FF 1110. Therefore, the read enable signal REN as the read enable signal REN-L and REN-R is also input to the left and right sides of the MBL.

[0102] Fig. 10A 1 is a schematic diagram showing an example of a transmission circuit 110 applicable to an embodiment accessing a pixel array unit 150. The pixel array unit 150 is divided into units called clusters 140, each of which includes a predetermined number of pixels 11, and a circuit block 1100 of the transmission circuit 110 1 , 1100 2 , ..., 1100 M There is a one-to-one correspondence with each cluster 140 .

[0103] For example, Fig. 10A As shown on the right side of FIG. 1 , it is assumed that the cluster 140 includes 64 pixels of 4 horizontal pixels×16 vertical pixels, and the transfer circuit 110 is arranged along the central portion 110′ in the row direction of the cluster 140. In one circuit block of the transfer circuit 110 (for example, the circuit block 1100 of 64 pixels) 1 ), for example, for the pixels 11 on the left and right sides of the central portion 110', the pixels 11 are designated in the order of the numbers shown for the pixels 11 in the figure, and the time code is transmitted (written) and the pixel data is transmitted (read).

[0104] Note that Fig. 10A In FIG. 1 , for the sake of explanation, the transmission circuit 110 is provided for the column of the cluster 140 at the right end of the pixel array unit 150 , but in reality, the transmission circuit 110 is provided for each column of the cluster 140 included in the pixel array unit 150 .

[0105] Fig. 10B 1 is a schematic diagram showing how to write a time code. The time code generated by the time code generator 104 is transmitted through the circuit blocks 1100. 1, 1100 2 , ..., 1100 M The shift register is propagated to each pixel 11 of the corresponding cluster 140.

[0106] Fig.11A is a schematic diagram showing how to read the time code. Fig. 11B 1 is a timing diagram showing an example of the timing related to the reading of the time code. By a predetermined read pixel selection signal, the read pixel to be read is selected from the pixels 11 included in the cluster 140, and the time code of the selected read pixel stored in the latch storage unit 72 is read and transmitted to the signal processing circuit 105.

[0107] For example, when the pixel 11 with the number “0” is designated by the readout pixel selection signal, since the pixel 11 with the number “0” is the pixel on the left side of the cluster 140, the readout enable signal RENL on the left side is set to a high state, and for example, Fig. 11B As shown in the block B of FIG. 1 , the clock MCK strikes 4 clocks, so that the transmission circuit 110 performs a shift register operation. The time code read out from the pixel 11 with the number “0” is transferred to MBL via the bidirectional buffer 1111L and transmitted to the signal processing circuit 105 .

[0108] The same applies to the case where the pixel 11 numbered "1" is designated by the readout pixel selection signal. Since the pixel 11 numbered "1" is a pixel on the right side of the cluster 140, the right readout enable signal RENR is set to a high state, and the clock MCK strikes 4 clocks, for example, so that the transmission circuit 110 performs a shift register operation. The time code read out from the pixel 11 numbered "1" is transferred to the MBL via the bidirectional buffer 1111R and transmitted to the signal processing circuit 105.

[0109] The embodiment has a layout in which each of the control lines 130 a to 130 d is provided in the transmission circuit 110 for performing such an operation. Fig.12 1 is a schematic diagram showing an example of the layout of each of the control lines 130a to 130d according to the embodiment. Fig.12 In the example of , the control line 130a is provided in the REN signal transmission unit 1103 on the left side of the figure, and the control line 130b is provided in the MCK clock transmission unit 1101. In addition, the control line 130d is provided in the REN signal transmission unit 1103 on the right side of the figure. In addition, the control line 130c is further provided in the control line 130d.

[0110] Among the control lines 130a to 130d, the control lines 130a, 130b, and 130d pass through the transmission circuit 110 so as to respectively supply the timing signals generated by the timing generation circuit 120 to the pixel driving circuit 103, the time code generator 104, and the DAC 101 provided outside the pixel array unit 150. On the other hand, the control line 130c for supplying the timing signals to the respective ADCs 102 branches left and right in the region of the transmission circuit 110, for example.

[0111] (2-3. Shielding structure)

[0112] Next, a shielding structure for the control line 130 according to the embodiment will be described. In the case where the control line 130 is provided in the transmission circuit 110, that is, in the case where there is a portion overlapping with the transmission circuit 110 in the layer direction of the stacking, it is necessary to consider the interference between the digital signal transmitted through the control line 130 and the analog signal processed in the pixel circuit 100 or the differential input circuit 61. In the embodiment, the control line 130 provided in the transmission circuit 110 is shielded using a low-resistance wiring (for example, a power supply wiring). As a result, the interference of the digital signal transmitted through the control line 130 with the analog signal such as the output of the pixel circuit 100 or the differential input circuit 61 can be suppressed.

[0113] Fig.13 is a schematic diagram showing an example of shielding for the control line 130 provided in the transmission circuit 110 according to the embodiment. Fig.13 Part (a) is along Fig.13 An example of a cross-sectional view taken along line AA′ shown in part (b) of FIG.

[0114] The light receiving chip 300 includes a first substrate 13 and a wiring layer 14 provided on the first substrate 13. In the light receiving chip 300, a pixel circuit 100 and a part of a differential input circuit 61 in the ADC 102 are provided on the first substrate 13. In the wiring layer 14, each wiring 17 is provided.

[0115] As in the light receiving chip 300, the circuit chip 301 includes a second substrate 15 and a wiring layer 16 provided on the second substrate. In the circuit chip 301, each element 19 is provided on the second substrate 15, and another part of the differential input circuit 61 in the ADC 102, the data storage unit 52, the voltage conversion circuit 62, and the positive feedback circuit 63 are provided. In the wiring layer 16, each wiring 17 is provided, and the control line 130 is provided.

[0116] The light receiving chip 300 and the circuit chip 301 are bonded to each other via the surface of the wiring layer 14 and the surface of the wiring layer 16. More specifically, the light receiving chip 300 and the circuit chip 301 are bonded to each other with the surface of the wiring layer 14 facing the first substrate 13 and the surface of the wiring layer 16 facing the second substrate 15 as bonding surfaces, thereby forming the solid-state imaging element 10.

[0117] At this time, the light receiving chip 300 and the circuit chip 301 are electrically connected through the wiring 17 in the wiring layers 14 and 16 via the bonding portion 18 by Cu-Cu bonding or the like.

[0118] Here, in the solid-state imaging element 10 according to the embodiment, in the circuit chip 301, a shield 1200 is provided between the control line 130 and the bonding surface. As described above, the shield 1200 is formed using a low-resistance wiring such as a power line, and a predetermined potential is applied. The shield 1200 between the control line 130 and the bonding surface can suppress the interference of the digital signal sent to the control line 130 with the analog signal in the light receiving chip 300.

[0119] In addition, the shield 1200 between the control line 130 and the bonding surface also functions as a light shielding film that shields the light emitted from the second substrate 15 in the circuit chip 301 .

[0120] In addition, Fig.13 In the example of FIG. 1 , shields 1200 are also provided on both sides of the control line 130. As a result, it is possible to suppress interference of the digital signal transmitted to the control line 130 with the wirings 17 in the circuit chip 301.

[0121] (2-4. Effects of Embodiments)

[0122] Next, we will refer to Fig.14A and Fig. 14B The effect of the configuration according to the embodiment is explained. As an example, it is shown how much the delay of the pixel control signal can be suppressed by passing the control line 130 through the transfer circuit 110.

[0123] As a prerequisite, refer to Fig. 14B , the length of the pixel area in the horizontal direction of the pixel array unit 150 is set to 10 [cm], and the length in the vertical direction is set to 500 [μm]. In addition, the vertical length of the time code generator 104 is set to 200 [μm], the vertical length of the transmission circuit 110 is set to 300 [μm], and the delay time per 1 [cm] is set to the delay time ΔT.

[0124] Fig.14A FIG. 2 shows an example of the layout of a solid-state imaging element 10 according to the related art. Fig.14AIn the example, the timing generation circuits 120a and 120b are respectively arranged on the left and right sides of the pixel array unit 150, that is, at both ends in the horizontal direction, and the timing signals are output to the control lines 132a and 132b arranged in parallel in the horizontal direction of the pixel array unit 150.

[0125] As described above, in the prior art, since the control lines 132a and 132b are wired from the left and right timing generation circuits 120a and 120b, respectively, the left timing generation circuit 120a controls the left half of the pixel array unit 150, and the right timing generation circuit 120b controls the right half of the pixel array unit 150. That is, since the delay time per 1 [cm] is the delay time ΔT, the delay time difference between the left and right is "5×ΔT". This delay time difference corresponds to shading. In addition, since the timing signal is sent along the long side of the pixel array unit 150 whose aspect ratio is very large, it is difficult to achieve a high frame rate because the delay time itself is large.

[0126] Fig. 14B An example of the layout of the solid-state imaging element 10 according to the embodiment is shown. In the embodiment, since the length of the control line 130 from the timing generation circuit 120 to the pixel driving circuit 103 is the sum of the lengths in the vertical direction of the transmission circuit 110 and the time code generator 104, 300 [μm] + 200 [μm] = 500 [μm] is obtained. This distance does not change depending on the position within the pixel array unit 150, and no distance difference is generated in the timing signal sent through the control line 130. In addition, the delay time of the timing signal is (500 [μm] / 1 [cm]) × ΔT = 0.05 × ΔT, which is 1 / 100 compared with the example of the prior art. As a result, high-speed response can be performed, and a high frame rate can be achieved.

[0127] In addition, in the prior art, the longer the length in the horizontal direction is, the longer the control lines 132a and 132b are, and the longer the delay time is. On the other hand, in the configuration of the embodiment, the length of the control line 130 is the sum of the lengths in the vertical direction of the above-mentioned transmission circuit 110 and the time code generator 104, and is constant. That is, the longer the length in the horizontal direction is, the greater the improvement effect of the delay time relative to the prior art is.

[0128] (3. First Modification of the Embodiment)

[0129] Next, a first modification of the embodiment will be described. The first modification of the embodiment is an embodiment in which the configuration of the control line 130 provided for the transmission circuit 110 or the timing signal transmitted through the control line 130 is different depending on the function of each control line 130a to 130d included in the control line 130 to provide a supply destination of the timing signal.

[0130] Hereinafter, a case where the configuration of the control line 130 provided for the transfer circuit 110 is made different will be described.

[0131] Fig.15 1 is a schematic diagram showing the configuration of an example of a solid-state image pickup element 10 according to a first modification of the embodiment. For example, a pixel driving circuit 103 is provided for each column. In addition, an ADC 102 is provided for each pixel 11. Therefore, since the pixel driving circuit 103 and the ADC 102 need to operate at high speed, a control line 130a for supplying a timing signal to the pixel driving circuit 103 and a control line 130c for supplying a timing signal to each ADC 102 are provided in all the transmission circuits 110.

[0132] On the other hand, the time code generator 104 is not required to operate at a high speed compared to the pixel driving circuit 103 and each ADC 102. Therefore, the time code generator 104 can be arranged in multiple columns, for example. Fig.15 In the example of , the control line 130 d that supplies the timing signal to the time code generator 104 is provided in the transmission circuit 110 by passing through every other sparse transmission circuit 110 .

[0133] For example, the pixel array unit 150 only needs to be provided with one or two DACs 101. In the case where only one DAC 101 is provided, all pixels 11 of the pixel array unit 150 use one reference signal REF in common. In the case where two DACs 101 are provided, the reference signals REF generated by the two DACs 101 may be combined, or regions may be divided in the pixel array unit 150, and the reference signals REF generated by the two DACs 101 may be provided to the respective regions.

[0134] As mentioned above, the DAC 101 is not required to operate at high speed. Fig.15 An example is shown in which two DACs 101 are provided for the pixel array unit 150 , and a control line 130 b for supplying a timing signal to the DAC 101 is provided in the transfer circuit 110 of every four transfer circuits 110 by thinning out three transfer circuits 110 .

[0135] As described above, by making the configuration of the control line 130 provided for the transmission circuit 110 different, effects such as reduction in power consumption and suppression of generation of noise caused by a timing signal transmitted by the control line 130 can be expected.

[0136] (4. Second Modification of the Embodiment)

[0137] Next, a second variation of the embodiment will be described. The second variation of the embodiment has a unit structure in which the pixel area of ​​the pixel array unit 150 is divided and a timing signal is sent for each divided area. In other words, the unit is a divided pixel array unit obtained by dividing the pixel area of ​​the pixel array unit 150.

[0138] Fig.16A 1 is a schematic diagram showing a configuration of an example of a solid-state image pickup element 10 according to a second modification of the embodiment. Fig.16A In the embodiment, the solid-state imaging element 10 includes a plurality of cells 200. 1 , 200 2 , ... and 200 N , and unit 200 1 , 200 2 , ... and 200 N Respectively including according to unit 200 1 Up to 200 N The pixel array unit 150 is divided into a number of divided pixel array units 152 1 Up to 152 N . Note that in Fig.16A Unit 200 1 , 200 2 , ... and 200 N Also referred to as unit #1, unit #2, ... and unit #N respectively.

[0139] Unit 200 1 Up to 200 N Includes DAC 101 one by one respectively 1 To DAC 101 N , pixel driving circuit 103 1 Up to 103 N , time code generator 104 1 Up to 104 N , timing generation circuit 120 10 Up to 120 1N and the signal processing circuit 105 1 Up to 105 N . Note that for each unit 200 1 Up to 200 N An output interface 106 is commonly provided.

[0140] Fig. 16B The unit 200 according to the second modification example of the embodiment is shown in more detail. 1 Up to 200 N Any unit in 200 X A block diagram of the structure of (unit #X). Fig. 16BAs shown, unit 200 X Includes DAC 101 X , pixel driving circuit 103 X , segmented pixel array unit 152 X , timing generation circuit 120 X and signal processing circuit 105 X In addition, Fig. 16B In the example, in unit 200 X There are four transmission circuits 110 provided in 11 , 110 12 , 110 13 and 110 14 .

[0141] Timing generation circuit 120 X For example, the synchronization signal 121 is received from the left adjacent unit #(X-1) X-1 , based on the synchronization signal 121 X-1 Generates a timing signal and outputs the timing signal, and sends the synchronization signal 121 X-1 As the synchronization signal 121 X Passed to, for example, the right adjacent cell #(X+1).

[0142] By the timing generation circuit 120 X The generated timing signal is sent to the control line 130. The control line 130 is divided into four control lines 130 1 , 130 2 , 130 3 and 130 4 , which are respectively arranged one by one in the transmission circuit 110 11 , 110 12 , 110 13 and 110 14 Control line 130 1 , 130 2 , 130 3 and 130 4 Control lines 130a, 130b, 130c and 130d (not shown) are included respectively.

[0143] Via control line 130 1 , 130 2 , 130 3 and 130 4 Provides timing signal to DAC 101 X , pixel driving circuit 103 X and time code generator 104 X At this time, as described in the first variant of the embodiment, at 110 11 , 110 12, 110 13 and 110 14 In each of the transmission circuits, the timing signals transmitted through the control lines 130a to 130d can be appropriately thinned out.

[0144] Via the corresponding transmission circuit 110 11 , 110 12 , 110 13 and 110 14 The pixel data read from each pixel 11 is supplied to the signal processing circuit 105 X .

[0145] As described above, by performing generation and transmission of timing signals for each unit, for example, even when the number of effective pixels in the pixel array unit 150 increases or decreases, it can be handled by increasing or decreasing the number of units, and derivative development of products becomes easy.

[0146] Note that the effects described in this specification are merely examples and are not limiting, and other effects may be provided.

[0147] Note that the present technology can also have the following configurations. (1)

[0149] A camera device, comprising:

[0150] a pixel array in which pixels are arranged in a matrix array;

[0151] a time code generating unit, which generates a time code;

[0152] a signal processing unit that performs signal processing on the pixel data;

[0153] a timing signal generating unit that generates a timing signal for controlling at least the timing of generating the time code in the time code generating unit; and

[0154] a plurality of transmission units, which transmit the time code to each of the pixels and transmit the pixel data to the signal processing unit, wherein

[0155] The time code generation unit is arranged toward the first side of the pixel array,

[0156] The signal processing unit is disposed toward a second side of the pixel array opposite to the first side,

[0157] The timing signal generating unit is arranged toward the second side of the pixel array, each of the plurality of transmission units is arranged from the first side to the second side through the pixel array, and

[0158] A control line for transmitting the timing signal generated by the timing signal generating unit to the time code generating unit is provided in each of two or more of the plurality of transmitting units,

[0159] Each pixel includes: a light receiving element that generates electric charge by photoelectric conversion according to received light;

[0160] a pixel circuit that reads the charge from the light receiving element and outputs an analog signal corresponding to the charge; and

[0161] A conversion circuit compares the analog signal with a reference signal whose voltage varies with time, and converts the analog signal into the pixel data as a digital signal based on a time code whose value is updated per unit time according to the comparison result. (2)

[0163] The imaging device according to (1), wherein:

[0164] The first side is a side along a row direction of the array, and

[0165] Each of the plurality of transmission units is arranged along a column direction of the array. (3)

[0167] The imaging device according to (1) or (2), wherein:

[0168] A control line for transmitting the timing signal generated by the timing signal generating unit to the pixel circuit is further provided in each of two or more of the plurality of transmitting units. (4)

[0170] The imaging device according to any one of (1) to (3), further comprising:

[0171] A reference signal generating circuit generates the reference signal, wherein

[0172] A control line for transmitting the timing signal generated by the timing signal generating unit to the reference signal generating circuit is further provided in each of two or more of the plurality of transmitting units. (5)

[0174] The imaging device according to any one of (1) to (4), wherein:

[0175] The timing signal generating unit comprises a delay adjusting unit,

[0176] The delay adjustment unit adjusts a delay of the timing signal between the control lines, the timing signal being transmitted through each of the control lines provided in each of two or more transmission units of the plurality of transmission units. (6)

[0178] The imaging device according to any one of (1) to (5), wherein

[0179] The timing signal generating unit

[0180] The common timing signal is transmitted through each of the control lines provided in each of two or more transmission units of the plurality of transmission units. (7)

[0182] The imaging device according to any one of (1) to (6), wherein:

[0183] The timing signal generating unit

[0184] After the predetermined transmission unit is thinned out from the plurality of transmission units, the timing signal is transmitted through each of the control lines provided in each of the remaining transmission units. (8)

[0186] The imaging device according to (7), wherein:

[0187] The timing signal generating unit

[0188] After thinning out the transmission units from the plurality of transmission units according to the accuracy required for the timing signal of the transmission destination, the timing signal is transmitted through each of the control lines provided in each of the remaining transmission units. (9)

[0190] The imaging device according to any one of (1) to (8), wherein:

[0191] A plurality of units are provided, and the plurality of units include:

[0192] a segmented pixel array obtained by segmenting the pixel array in the direction of the first side;

[0193] the time code generating unit, which is disposed toward the first side of the segmented pixel array and generates the time code for the segmented pixel array;

[0194] the signal processing unit, which is disposed toward the second side of the divided pixel array and performs the signal processing on the pixel data output from the divided pixel array;

[0195] a timing signal generating unit, which generates a timing signal for the segmented pixel array, the timing signal being used to at least control the timing of generating the time code in the time code generating unit; and

[0196] One or more transfer units are arranged from the first side to the second side of the segmented pixel array.

[0197] (10) The imaging device according to any one of (1) to (9), comprising:

[0198] a first chip including a first substrate on which the light receiving element, the pixel circuit, and a part of the conversion circuit are disposed, and a first wiring layer disposed on the first substrate; and

[0199] a second chip, comprising a second substrate and a second wiring layer, on which another part of the conversion circuit, the signal processing unit and the timing signal generating unit are arranged, the second wiring layer is arranged on the second substrate and comprises the control line, and a surface of the second substrate away from the second wiring layer is bonded to a surface of the first substrate away from the first wiring layer, wherein:

[0200] A shielding layer is provided between the bonding surface between the first chip and the second chip and the control line.

[0201] (11) An electronic device comprising:

[0202] Camera unit;

[0203] an optical unit that condenses incident light and guides the incident light to a light receiving element; and

[0204] a storage unit for storing pixel data that has undergone signal processing by the signal processing unit,

[0205] The camera unit comprises:

[0206] a pixel array in which pixels are arranged in a matrix array,

[0207] a time code generating unit, which generates a time code;

[0208] a signal processing unit that performs signal processing on the pixel data;

[0209] a timing signal generating unit that generates a timing signal for controlling at least the timing of generating the time code in the time code generating unit; and

[0210] a plurality of transmission units that transmit the time code to each of the pixels and transmit the pixel data to the signal processing unit,

[0211] in,

[0212] In the camera unit,

[0213] The time code generation unit is arranged toward the first side of the pixel array,

[0214] The signal processing unit is disposed toward a second side of the pixel array opposite to the first side,

[0215] The timing signal generating unit is arranged toward the second side of the pixel array,

[0216] Each of the plurality of transmission units is arranged from the first side to the second side through the pixel array, and

[0217] providing a control line in each of two or more transmission units of the plurality of transmission units, the control line being used to transmit the timing signal generated by the timing signal generating unit to the time code generating unit,

[0218] Each pixel consists of:

[0219] a light receiving element that generates electric charge by photoelectric conversion according to received light;

[0220] a pixel circuit that reads the charge from the light receiving element and outputs an analog signal corresponding to the charge; and

[0221] A conversion circuit compares the analog signal with a reference signal whose voltage varies with time, and converts the analog signal into the pixel data as a digital signal based on a time code whose value is updated per unit time according to the comparison result.

[0222] Reference numerals list

[0223] 10 Solid-state imaging element

[0224] 11 pixels

[0225] 13. First substrate

[0226] 14,16 Wiring layer

[0227] 15. Second substrate

[0228] 17 Wiring

[0229] 61 Differential Input Circuit

[0230] 100 pixel circuit

[0231] 101,101 1 ,101 NDAC

[0232] 102 ADC

[0233] 103,103 1 ,103 N Pixel driving circuit

[0234] 104,104 1 ,104 N Timecode Generator

[0235] 105,105 1 ,105 N Signal processing circuit

[0236] 106 Output Interface

[0237] 110,110 1 ,110 2 ,110 n-1 Transmission circuit

[0238] 120,120 1 ,120 2 ,120 N ,120 10 ,120 1N ,120a,120b Timing generation circuit

[0239] 122 1 ,122 2 ,122 N Timing Generation Unit

[0240] 123 1 ,123 2 ,123 N Delay adjustment unit

[0241] 130,130 1 ,130 2 ,130 3 ,130 4 ,130a,130b,130c,130d control line

[0242] 140 Cluster

[0243] 150 pixel array unit

[0244] 152 1 ,152 N ,152 X Segmented pixel array unit

[0245] 200 1 ,200 2,200 N unit

[0246] 300 optical receiver chip

[0247] 301 Circuit Chip

[0248] 1000 Electronic equipment

[0249] 1101 MCK clock transmission unit

[0250] 1102 FF data transmission unit

[0251] 1103 REN signal transmission unit

[0252] 1200 Shield

Claims

1. A camera device, include: A pixel array in which pixels are arranged in a matrix array, each pixel including: a light receiving element that generates electric charge by photoelectric conversion according to received light; a pixel circuit that reads the electric charge from the light receiving element and outputs an analog signal corresponding to the electric charge; and a conversion circuit that compares the analog signal with a reference signal whose voltage changes with time and, based on the comparison result, converts the analog signal into pixel data that is a digital signal based on a time code whose numerical value is updated per unit time; A time code generating unit, which generates the time code; a signal processing unit that performs signal processing on the pixel data; a timing signal generating unit that generates a timing signal for controlling at least the timing of generating the time code in the time code generating unit; and a plurality of transmission units, which transmit the time code to each of the pixels and transmit the pixel data to the signal processing unit, wherein The time code generation unit is arranged on a first side of the pixel array, The signal processing unit is disposed on a second side of the pixel array opposite to the first side, The timing signal generating unit is arranged on the second side of the pixel array, Each of the plurality of transmission units is arranged from the first side to the second side through the pixel array, and A control line for transmitting the timing signal generated by the timing signal generating unit to the time code generating unit is provided in each of two or more of the plurality of transmitting units.

2. The imaging device according to claim 1, in, The first side is a side along a row direction of the array, and Each of the plurality of transmission units is arranged along a column direction of the array.

3. The imaging device according to claim 1, in, A control line for transmitting the timing signal generated by the timing signal generating unit to the pixel circuit is further provided in two or more of the plurality of transmitting units.

4. The camera device according to claim 1, further comprising: include: A reference signal generating circuit generates the reference signal, wherein A control line for transmitting the timing signal generated by the timing signal generating unit to the reference signal generating circuit is further provided in two or more of the plurality of transmitting units.

5. The imaging device according to any one of claims 1 to 4, in, The timing signal generating unit comprises a delay adjusting unit, The delay adjustment unit adjusts the delay of the timing signal between the control lines, the timing signal being transmitted through each of the control lines provided in each of more than two transmission units of the plurality of transmission units.

6. The imaging device according to any one of claims 1 to 4, in, The timing signal generating unit The common timing signal is transmitted through each of the control lines provided in two or more transmission units of the plurality of transmission units.

7. The imaging device according to any one of claims 1 to 4, in, The timing signal generating unit The timing signal is transmitted through each of the control lines provided in the transmission units remaining after the predetermined transmission units are thinned out from the plurality of transmission units.

8. The imaging device according to claim 7, in, The timing signal generating unit After thinning out the transmission units from the plurality of transmission units according to the accuracy required for the timing signal in the transmission destination, the timing signal is transmitted through each of the control lines provided in the remaining transmission units.

9. The imaging device according to any one of claims 1 to 4, in, A plurality of units are provided, and the plurality of units include: a segmented pixel array, wherein the pixel array is segmented in a direction of the first side; The time code generating unit is disposed on the first side of the segmented pixel array and generates the time code for the segmented pixel array; the signal processing unit being disposed on the second side of the segmented pixel array and performing the signal processing on the pixel data output from the segmented pixel array; a timing signal generating unit, which generates a timing signal for the segmented pixel array, wherein the timing signal at least controls the timing of generating the time code in the time code generating unit; and One or more transfer units are arranged from the first side to the second side of the segmented pixel array.

10. The imaging device according to any one of claims 1 to 4, include: A first chip including a first substrate, the light receiving element, the pixel circuit, and a part of the conversion circuit are arranged on the first substrate, and a first wiring layer is arranged on the first substrate; and a second chip, comprising a second substrate and a second wiring layer, on which another part of the conversion circuit, the signal processing unit and the timing signal generating unit are arranged, the second wiring layer is arranged on the second substrate and comprises the control line, and a surface of the second wiring layer opposite to the second substrate is bonded to a surface of the first wiring layer opposite to the first substrate, wherein: A shielding layer is provided between the bonding surface between the first chip and the second chip and the control line.

11. An electronic device, include: Camera unit; an optical unit that condenses incident light and guides the incident light to a light receiving element; and a storage unit for storing pixel data that has undergone signal processing by the signal processing unit, The camera unit comprises: A pixel array in which pixels are arranged in a matrix array, each pixel including: a light receiving element that generates electric charge by photoelectric conversion according to received light; a pixel circuit that reads the electric charge from the light receiving element and outputs an analog signal corresponding to the electric charge; and a conversion circuit that compares the analog signal with a reference signal whose voltage changes with time and, based on the comparison result, converts the analog signal into the pixel data as a digital signal based on a time code whose numerical value is updated per unit time; A time code generating unit, which generates the time code; a signal processing unit that performs the signal processing on the pixel data; a timing signal generating unit that generates a timing signal for controlling at least the timing of generating the time code in the time code generating unit; and a plurality of transmission units that transmit the time code to each of the pixels and transmit the pixel data to the signal processing unit, in, In the camera unit, The time code generation unit is arranged on a first side of the pixel array, The signal processing unit is disposed on a second side of the pixel array opposite to the first side, The timing signal generating unit is arranged on the second side of the pixel array, Each of the plurality of transmission units is arranged from the first side to the second side through the pixel array, and A control line for transmitting the timing signal generated by the timing signal generating unit to the time code generating unit is provided in each of two or more of the plurality of transmitting units.

Images