Changing the nitrogen content in the switching layer of a two-terminal resistance switching device

Abstract

A two-terminal resistance switching device can have a switching layer in which filaments are formed and deformed to different degrees to represent different logic states. The switching layer can be formed to have a varying ratio X of nitrogen to silicon at different layers of the switching layer. This can result in a two-terminal memory device with improved stability and other characteristics. The switching layer can be formed in a vacuum chamber in which the gas mixture has a ratio Y of nitrogen to argon that is varied during fabrication.

Description

[0001] Incorporated by Reference

[0002] U.S. Patent No. 10,608,180, filed on August 14, 2017, and entitled “RESISTIVE MEMORY CELL WITH INTRINSIC CURRENT CONTROL”; U.S. Patent No. 9,735,357, filed on February 1, 2016, and entitled “RESISTIVE MEMORY CELL WITH INTRINSIC CURRENT”; U.S. Patent No. 10,840,442, filed on May 19, 2016, and entitled “NON-STOICHIOMETRIC RESISTIVE SWITCHING MEMORY DEVICE AND FABRICATION METHODS”; and U.S. Provisional Application No. 62 / 165,874, filed on May 22, 2016, are hereby incorporated by reference in their entirety and for all purposes. Technical Field

[0003] The present disclosure generally relates to a two-terminal resistance switching device with a resistance switching layer having a varying nitrogen content. Background Art

[0004] Resistive switching memory represents the latest innovation in the field of integrated circuit technology. Although most of the resistive switching memory technology is in the development stage, various technical concepts of resistive switching memory have been demonstrated by the inventors and are in one or more verification stages for proving or refuting related theories or technologies. The inventors believe that the resistive switching memory technology shows convincing evidence to prove that it has significant advantages over competing technologies in the semiconductor electronics industry.

[0005] The inventors believe that the resistance switching memory cell can be configured to have multiple states with different resistance values. For example, for a single bit cell, the resistance switching memory cell can be configured to exist in a relatively low resistance state, or alternatively, in a relatively high resistance state. Multi-bit cells may have additional states with corresponding resistances that are different from each other and different from the relatively low resistance state and the relatively high resistance state. The different resistance states of the resistance switching memory cell represent different logical information states, thereby facilitating digital memory operations. Accordingly, the inventors believe that an array of many such memory cells can provide digital memory storage of many bits.

[0006] The inventors have successfully induced a resistance-switching memory to enter one resistance state or another in response to an external condition. Thus, in transistor parlance, applying or removing the external condition can be used to program or deprogram (e.g., erase) the memory. Furthermore, depending on the physical makeup and electrical arrangement, the resistance-switching memory cell can generally maintain either a programmed state or a deprogrammed state. Depending on the characteristics of the memory cell device, maintaining the state may require other conditions to be met (e.g., the presence of a minimum operating voltage, the presence of a minimum operating temperature, etc.) or not met.

[0007] Several proposals have been made by inventors for practically utilizing resistance switching technology to include transistor-based memory applications. For example, resistance switching elements are often theorized, at least in part, as viable replacements for metal oxide semiconductor (MOS) type memory transistors for electronic storage of digital information. Models of resistance switching memory devices offer some potential technical advantages over non-volatile FLASH MOS type transistors.

[0008] In view of this, the inventors hope to continue to develop practical applications of resistance switching technology. Summary of the invention

[0009] A simplified summary of the specification is given below to provide a basic understanding of some aspects of the specification. This summary is not an extensive overview of the specification. It is neither intended to specify the key or key elements of the specification, nor to describe the scope of any particular embodiment of the specification or any scope of the claims. Its purpose is to present certain concepts of the specification in a simplified form as a prelude to the more detailed description presented in this disclosure.

[0010] Some embodiments of the subject disclosure relate to a two-terminal memory device having a switching layer having different amounts of nitrogen content at different strata of the switching layer. The two-terminal memory device may include a first electrode located in a first region of the two-terminal memory device, and a second electrode located in a second region of the two-terminal memory device. The two-terminal memory device may also include a resistive switching layer, wherein a first portion is adjacent to the first region or closer to the first region than a second portion. The second portion may be adjacent to the second region or closer to the second region than the first portion. The resistive switching layer may include nitrogen (N) and silicon (Si) and may have a ratio X, characterized as N / Si, which varies between the first portion and the second portion according to a determined difference.

[0011] The subject disclosure may also relate to a method for manufacturing a two-terminal memory device. For example, the manufacturing device may form a bottom electrode of a two-terminal memory device covering a metal layer. The manufacturing device may introduce a gas mixture having a defined ratio Y into a vacuum chamber including BE. The defined ratio Y may be characterized as an amount of nitrogen (N2) to argon (Ar). The manufacturing device may form a resistive switching layer in a vacuum chamber in response to a physical vapor deposition (PVD) sputtering process that varies Y during the formation of the resistive switching layer. The manufacturing device may form a top electrode covering the resistive switching layer of the two-terminal memory device.

[0012] The following description and the accompanying drawings set forth certain illustrative aspects of the specification. However, these aspects are only indicative of a few of the various ways in which the principles of the present specification may be employed. Other advantages and novel features of the specification will become apparent from the following detailed description of the specification when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Many aspects, embodiments, objects and advantages of the present invention will be apparent from the following detailed description considered in conjunction with the accompanying drawings, in which like reference numerals refer to like parts throughout. In this specification, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the subject disclosure may be implemented without these specific details, or with other methods, components, materials, etc. In other cases, well-known structures and devices are shown in block diagram form to facilitate description of the subject disclosure.

[0014] Figure 1 A block diagram of an integrated circuit device providing formation of a barrier layer that mitigates material diffusion of a metal layer is shown in accordance with certain embodiments of the present disclosure.

[0015] Figure 2A An example integrated circuit device providing vias formed in a barrier layer is shown in accordance with certain embodiments of the present disclosure.

[0016] Figure 2B An example integrated circuit device showing formation of a bottom electrode in a via is shown in accordance with certain embodiments of the present disclosure.

[0017] Figure 3 Depicted is a block diagram of an example integrated circuit device providing for formation of a stack of layers overlying a bottom electrode, according to certain embodiments of the present disclosure.

[0018] Figure 4 Depicted is a block diagram representing an exploded view of an example two-terminal resistance switching device with variable nitrogen content, in accordance with certain embodiments of the present disclosure.

[0019] Figure 5A-5DVarious example switching layers are shown that illustrate non-limiting examples of variable nitrogen content throughout the layer of the respective switching layer according to a smooth gradient function, in accordance with certain embodiments of the present disclosure.

[0020] Figure 6A-6D Various example switching layers are shown that illustrate non-limiting examples of nitrogen content that may be varied by discrete amounts per sub-layer of the respective switching layers, in accordance with certain embodiments of the present disclosure.

[0021] Figure 7 Depicted is a block diagram of an example deposition for a resistive switching device having a gradient nitrogen composition in further embodiments.

[0022] 8 illustrates a block diagram of sample nitrogen concentration profiles of an active metal portion of a resistive switching device in accordance with one or more embodiments.

[0023] 9 depicts a block diagram of sample nitrogen concentrations of the active metal portion and the top electrode portion in one or more alternative embodiments.

[0024] Fig.10 An example method that can provide for fabrication of a two-terminal memory device that can vary a gas mixture during fabrication of the two-terminal memory device is shown in accordance with certain embodiments of the present disclosure.

[0025] Fig.11 An example method that may provide for selecting the type of PVD sputtering and the type of difference in Y according to certain embodiments of the present disclosure is shown.

[0026] Fig.12 Example methods for varying a gas mixture during fabrication of a switching layer of a resistive switching device in further embodiments are shown.

[0027] Fig.13 Depicted are example methods for forming a resistive switching device having a gradient nitrogen concentration in additional embodiments disclosed herein.

[0028] Fig.14 A block diagram of an example electronic operating environment is shown in accordance with certain implementations of the present disclosure.

[0029] Fig.15 A block diagram of an example computing environment is shown in accordance with certain implementations of the present disclosure. DETAILED DESCRIPTION

[0030] Introduction to Two-Terminal Memory

[0031] The present disclosure relates to memory devices for digital or multi-level information storage, and processes involved in manufacturing memory devices. In some embodiments, a two-terminal memory cell may be constructed at least in part according to the processes disclosed herein. As an example, the two-terminal memory cell may include a resistance technology, such as a resistance-switched two-terminal cell. A resistance-switched two-terminal cell (also referred to as a two-terminal resistance-switching cell, a two-terminal resistance-switching device, or a resistance-switching memory cell or device, etc.) may include a circuit component having a conductive contact portion (e.g., an electrode or terminal), wherein two conductive contacts have an active region between them.

[0032] In some embodiments, the subject disclosure relates to a two-terminal resistance switching device having a switching layer having different amounts of nitrogen content at different layers of the switching layer. The two-terminal memory device may also include a resistance switching layer. The resistance switching layer may include nitrogen and silicon and may have a ratio of nitrogen to silicon that varies over the thickness of the resistance switching layer according to a determined difference.

[0033] In other embodiments, the subject disclosure is directed to a two-terminal resistance switching device comprising a switching layer, an active layer (also referred to as a particle donor layer) covering the switching layer, and a top electrode covering the active layer. The active layer may include a compound or mixture of a metal and nitrogen, and the relative concentration of the metal and nitrogen may vary in the active layer. In one embodiment, the top electrode may include a second metal and a nitrogen material and the relative concentration of the second metal and the nitrogen material may be non-uniform within the top electrode.

[0034] Herein, the terms "electrode" and "terminal" are used interchangeably; furthermore, a two-terminal resistance switching device includes a non-volatile two-terminal memory device as well as a volatile two-terminal switching device. Typically, the first electrode of the two-terminal resistance switching device is referred to as the "top electrode" (TE), and the second electrode of the two-terminal resistance switching device is referred to as the "bottom electrode" (BE), however it should be understood that the electrodes of the two-terminal resistance switching device can be arranged in any suitable manner, including a horizontal arrangement in which the components of the memory cell are (substantially) side by side rather than stacked on top of each other. Between the TE and BE of a two-terminal resistive switching device is typically an interfacial layer, sometimes also referred to as a switching layer, resistive switching medium (RSM) or resistive switching layer (RSL); such devices are not limited to these layers, however, one or more barrier layers, (one or more) adhesion layers, (one or more) ion conducting layers, (one or more) seed layers, (one or more) particle source layers, etc. - as disclosed herein, disclosed in publications incorporated herein by reference, as generally understood and utilized in the art, or as reasonably conveyed to a person of ordinary skill in the art by the context provided herein and its supplement to the general understanding of the art or the incorporated publications - may be included between or adjacent to one or more of the TE, BE or interfacial layers consistent with proper operation of such devices.

[0035] In the context of a resistive switching memory, the interface layer of a two-terminal resistive switching device exhibits multiple stable or semi-stable resistance states, each resistance state having a different resistance. In addition, each of the multiple states can be formed or activated in response to a suitable electrical signal applied to two conductive contacts. The suitable electrical signal can be a voltage value, a current value, a voltage polarity or a current polarity, etc., or a suitable combination thereof. Although not exhaustive, examples of resistive switching two-terminal memory devices can include: resistive random access memory (RRAM), phase change RAM (PCRAM), and magnetic RAM (MRAM).

[0036] Embodiments of the subject disclosure may provide a filament-based memory cell. In some embodiments, the filament-based memory cell includes a non-volatile memory device, while other embodiments provide a volatile selector device, while other embodiments provide a volatile selector device electrically connected in series with the non-volatile memory device. In other embodiments, both the volatile selector device and the non-volatile memory device may be filament-based devices, but the subject disclosure is not limited to these embodiments.

[0037] In general, the composition of the two-terminal resistance switching unit can be different depending on the device, which has different components, materials or deposition processes selected to achieve the desired characteristics (e.g., stoichiometry / non-stoichiometry, volatility / non-volatility, on / off current ratio, switching time, read time, memory endurance, program / erase cycles, etc.). An example of a filament-based device may include: a conductive layer, such as a metal, a metal alloy, a metal nitride (e.g., including TiN, TaN, TiW or other suitable metal compounds), an optional interface boundary layer (e.g., a doped p-type (or n-type) silicon (Si) carrier layer (e.g., p-type or n-type Si carrier layer, p-type or n-type polysilicon, p-type or n-type polycrystalline SiGe, etc.)), a resistance switching layer (RSL) and an active metal-containing layer that can be ionized. Under appropriate conditions, the active metal-containing layer can provide ions to the RSL to form filaments. In such an embodiment, a conductive filament (e.g., formed by ions) can facilitate conductivity through at least a subset of the RSL, and as an example, the resistance of the filament-based device can be determined by the tunneling resistance between the filament and the conductive layer. A memory cell having such a characteristic can be described as a filament-based device.

[0038] The RSL in the filament device (which may also be referred to in the art as a resistive switching medium (RSM), an interfacial layer, an active region, etc.) may include, for example, an undoped amorphous Si-containing layer, a semiconductor layer having intrinsic properties, a stoichiometric or non-stoichiometric silicon nitride (e.g., SiN, Si3N4, SiN xetc.), Si suboxides (such as SiO x , where the value of x is between 0.1 and 2), Si nitrides, metal oxides, metal nitrides, non-stoichiometric silicon compounds, etc. Other examples of materials suitable for RSL may include Si x Ge y O z (where x, y, and z are respectively suitable positive numbers), silicon oxide (e.g., SiO N , where N is a suitable positive number), silicon oxynitride, undoped amorphous silicon (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a suitable positive number), HfO C (where C is a suitable positive number), TiO D (where D is a suitable number), Al2O E (wherein E is a suitable positive number), etc., nitrides (e.g., AlN, SiN), or suitable combinations thereof.

[0039] In some embodiments, an RSL as part of a nonvolatile memory device (nonvolatile RSL) may include a relatively large number (e.g., compared to a volatile selector device) of material voids or defects to capture neutral metal particles within the RSL (e.g., at low voltages). A large number of voids or defects may facilitate the formation of a thick, stable structure of neutral metal particles. In such a structure, these trapped particles may maintain the nonvolatile memory device in a low resistance state in the absence of an external stimulus (e.g., electricity), thereby achieving nonvolatile operation. In other embodiments, an RSL for a volatile selector device (volatile RSL) may have very few material voids or defects for capturing particles. Since there are few voids / defects for capturing particles, the conductive filaments formed in such an RSL may be very thin (e.g., one to a few particle widths depending on the field strength, the particle material, or the RSL material, or a suitable combination of the foregoing) and are unstable without a suitable high external stimulus (e.g., an electric field, voltage, current, Joule heating, or a suitable combination thereof). In addition, the particles can be selected to have high surface energy and good diffusion within the RSL. This results in the conductive filaments being able to form quickly in response to an appropriate stimulus, but also being easily deformed, such as in response to an external stimulus that is reduced to below the deformation level (which can be below the formation level of the external stimulus associated with the formation of volatile conductive filaments, for example, in response to a current flowing through the selector device; see U.S. Patent No. 9,633,724 B2, the entire contents of which are incorporated herein by reference and for all purposes). Note that the volatile RSL and conductive filaments used in the selector device can have different electrical properties than the conductive filaments and non-volatile RSL used in the non-volatile memory device. For example, the selector device RSL can have a higher material resistance and can have a higher on / off current ratio, etc.

[0040] The active metal-containing layer for the filament-based memory cell may include silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN) or other suitable compounds or non-stoichiometric mixtures of titanium, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf) and palladium (Pd), etc. Other suitable conductive materials, as well as stoichiometric or non-stoichiometric compounds, nitrides, oxides, alloys, mixtures or combinations of the foregoing or similar materials may be used for the active metal-containing layer in some aspects of the subject disclosure. In addition, non-stoichiometric compounds or mixtures, such as non-stoichiometric metal oxide / metal-oxygen or metal nitride / metal nitrogen (e.g., AlO x 、AlN x , CuO x , CuN x, AgO x , AgN x etc., where x is a suitable positive number or range of numbers, such as: 0 < x < 2, 0 < x < 3, 0 < x < 4 or other numbers / ranges of numbers, depending on the metal in question, which may have different values for different ones in the non-stoichiometric compound / mixture) or in at least one embodiment, other suitable metal compounds / mixtures may be used for the active metal layer.

[0041] In one or more embodiments, the disclosed filament resistive switching device may include an active metal layer that includes a metal-nitrogen selected from the group consisting of: TiN x , TaN x , AlN x , CuN x , WN x and AgN x , where x is a positive number (or range of numbers), which may vary according to the metal-nitrogen material. In additional (one or more) embodiments, the active metal layer may include a metal-oxygen selected from the group consisting of: TiO x , TaO x , AlO x , CuO x , WO x and AgO x , where x is a positive number (or range of numbers, which may be different from those ranges using nitrogen above), which may also vary according to the metal-oxygen material. In other additional (one or more) embodiments, the active metal layer may include a metal oxynitride selected from the group consisting of: TiO a N b , AlO a N b , CuO a N b , WO a N b and AgO a N b , where a and b are suitable positive numbers / ranges of numbers. The disclosed filament resistive switching device may also include a switching layer that includes a switching material selected from the group consisting of: SiO y , AlN y , TiO y , TaO y , AlO y , CuO y , TiN x , TiN y , TaN x , TaN y , SiO x、SiN y 、AlN x , CuN x , CuN y 、AgN x 、AgN y 、TiO x 、TaO x 、AlO x , CuO x 、AgO x and AgO y , where x and y are positive numbers (or ranges), and y is greater than x. Various combinations of the above are contemplated and considered within the scope of embodiments of the present invention.

[0042] In one example, the disclosed filament resistive switching device includes a particle donor layer (e.g., an active metal layer) containing a stoichiometric or non-stoichiometric metal compound (or mixture) and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer contains metal-nitrogen: MN x , such as AgN x 、TiN x 、AlN x etc., and the resistance switching layer comprises metal-nitrogen: MN y , such as AgN y 、TiN y 、AlN y etc., where y and x are positive numbers (or ranges), and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises metal-oxygen: MO x , such as AgO x 、TiO x 、AlO x etc., and the resistance switching layer comprises metal-oxygen:MO y , such as AgO y 、TiO y 、AlO y etc., wherein y and x are positive numbers (or ranges), and in some cases y is greater than x. In yet another alternative, the metal compound of the particle donor layer is MN x (e.g. AgN x 、TiN x 、AlN x etc.), and the resistance switching layer is selected from MO y (e.g. AgO y 、TiO y 、AlO y ) etc.) and SiO y , wherein x and y are typically non-stoichiometric values, and in yet another embodiment, vice versa (e.g., the particle donor layer is metal-oxygen:MOx material, and the resistance switching layer is metal-nitrogen: MN y materials, where x and y are typically non-stoichiometric values).

[0043] As used herein, variables x, y, a, b, etc., representing the ratio or value of one element relative to another (or other) element in a compound or mixture may have different values ​​(or ranges) suitable for the corresponding compound / mixture, and are not intended to represent the same or similar values ​​or ratios between compounds. A mixture may refer to non-stoichiometric materials containing free elements therein, such as metal-rich nitrides or oxides (metal oxides / nitrides with free metal atoms), metal-poor nitrides or oxides (metal oxides / nitrides with free oxygen / nitrogen atoms), and other combinations of elements that do not form compounds of conventional stoichiometry as understood in the art. Some details related to embodiments of the subject disclosure may be found in the following U.S. patent applications issued to the assignee of the present patent application: Application Serial No. 11 / 875,541 filed on October 19, 2007 and Application Serial No. 12 / 575,921 filed on October 8, 2009; each of the foregoing patent applications is incorporated herein by reference in its entirety and for all purposes, except for those patent applications incorporated herein by reference elsewhere.

[0044] It should be understood that various embodiments herein may utilize various memory cell technologies having different physical properties. For example, different resistance-switching memory cell technologies may have different discrete programmable resistances, different associated programming / erase voltages, and other differentiated characteristics. For example, various embodiments disclosed herein may employ a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of programming states) to an electrical signal having a first polarity and exhibits a second switching response (e.g., erasing to an erased state) to an electrical signal having a second polarity. For example, a bipolar switching device is contrasted with a unipolar device that exhibits both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals having the same polarity and different amplitudes.

[0045] In various embodiments, the filament-based resistance switching device can operate in a bipolar manner, behaving differently in response to external stimuli of different polarities (or directions, energy flows, energy source orientations, etc.). For a volatile filament-based selector device, as an illustrative example, in response to a first polarity stimulus exceeding a first threshold voltage (or voltage group), the filament selector device can change from a first resistance state to a second resistance state. In addition, in response to a second polarity stimulus exceeding (one or more) a second threshold voltage, the filament selector device can change from a first state to a third state. In some embodiments, the third state can be substantially the same as the first state, having the same or similar measurable different characteristics (e.g., conductivity, etc.), having the same or similar threshold stimulus amplitude (although of opposite polarity or direction), etc. In other embodiments, the third state can be different from the second state, either in terms of measurable characteristics (e.g., different conductivity values ​​in response to reverse polarity compared to forward polarity) or in terms of threshold stimuli associated with switching out of the first state (e.g., the amplitude of the positive voltage required to switch to the second state is different compared to the amplitude of the negative voltage required to switch to the third state).

[0046] For bipolar operation of nonvolatile filament-based memory cells, a conductive path or filament is formed through the nonvolatile RSL in response to a suitable programming voltage applied to the memory cell. In particular, upon application of the programming voltage, metal ions are generated from the active metal-containing layer and migrate into the nonvolatile RSL layer. The metal ions may occupy voids or defects within the nonvolatile RSL layer. In some embodiments, upon removal of the bias voltage, the metal ions become neutral metal particles and remain trapped in the voids or defects of the nonvolatile RSL layer. When enough particles are trapped, a filament is formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide a conductive path or filament through the nonvolatile RSL layer, and the resistance is typically determined by the tunneling resistance through the nonvolatile RSL layer. In some resistance switching devices, an erase process may be implemented to deform the conductive filament, at least partially returning the memory cell from a low resistance state to a high resistance state. More specifically, when an erase bias voltage is applied, metal particles trapped in the voids or defects of the nonvolatile RSL become mobile ions and migrate back to the active metal layer. In the context of memory, this state change can be associated with the corresponding state of a binary bit. For an array of multiple memory cells, (one or more) words, (one or more) bytes, (one or more) pages, (one or more) blocks, etc. of memory cells can be programmed or erased to represent binary zero or one, and by retaining these states over time to actually store binary information. In various embodiments, multi-level information (e.g., multiple bits) can be stored in such a memory cell.

[0047] Where no particular memory cell technology or programming / erase voltages are specified for the various aspects and embodiments herein, such aspects and embodiments are intended to operate in conjunction with any suitable memory cell technology and with programming / erase voltages appropriate for that technology, as known to one of ordinary skill in the art or made known to one of ordinary skill by the context provided herein. It should also be understood that where substitution of a different memory cell technology would require circuit modifications known to one of ordinary skill in the art or changes in operating signal levels known to such a person of ordinary skill, embodiments that include the substituted memory cell technology(s) or signal level changes are considered to be within the scope of the subject disclosure.

[0048] As described above, application of a programming voltage (also referred to as a "programming pulse") to one of the electrodes of a two-terminal memory can result in the formation of a conductive filament in an interface layer (e.g., RSL). By convention and as generally described herein, TE receives the programming pulse and BE is grounded (or maintained at a lower voltage or opposite polarity than the programming pulse), but this is not intended to limit all embodiments. Conversely, application of an "erase pulse" to one of the electrodes (typically a pulse of opposite polarity to the programming pulse or a pulse applied to the opposite electrode as the programming pulse) can disrupt the continuity of the filament, such as by driving metal particles or other materials that form filaments back to the active metal source, by dispersing metal particles within the interface layer such that electrical continuity between particles is appropriately interrupted, etc., or a combination of these mechanisms. The nature of such a conductive filament and its presence or absence affect the electrical characteristics of the two-terminal memory cell, such as, for example, reducing resistance and / or increasing conductance at both ends when the conductive filament is present, as opposed to when the conductive filament is not present.

[0049] After a programming pulse or an erase pulse, a read pulse may be asserted. The amplitude of the read pulse is typically relatively lower than the programming pulse or the erase pulse, and is typically insufficient to affect the conductive filament and / or change the state of the two-terminal memory cell. By applying a read pulse to one of the electrodes of the two-terminal memory, a current (e.g., I 导通 ) can indicate the conduction state of the two-terminal memory cell. The threshold current can be preset based on the expected current values ​​in different states of the two-terminal memory device (e.g., high-resistance state current; corresponding currents of one or more low-resistance states, etc.), suitable for a given two-terminal memory technology. For example, when a conductive filament has been formed (e.g., in response to the application of a programming pulse), the conductance of the cell is greater than otherwise, and the measured current in response to a read pulse (e.g., I 导通 On the other hand, when the conductive filament is removed (e.g., in response to applying an erase pulse), the resistance of the cell is high because the interface layer has a relatively high resistance, so the conductance of the cell is low and the measured current in response to the read pulse (e.g., I关断 ) reading will be lower. By convention, when a conductive filament is formed, the memory cell is said to be in the "on state" and have a high conductance. When the conductive filament is not present, the memory cell is said to be in the "off state". Memory cells in the on state or the off state can be logically mapped to binary values, such as "1" and "0". It should be understood that the conventions used herein associated with the state of the cell or the associated logical binary mapping are not intended to be limiting, as other conventions, including opposite conventions, may be used in conjunction with the disclosed subject matter. The techniques detailed herein are described and illustrated in conjunction with single-level cell (SLC) memory, but it should be understood that the disclosed techniques may also be used in multi-level cell (MLC) memory, where a single memory cell can retain a set of measurable different states representing multiple bits of information.

[0050] Digital information can be stored in such devices by mapping the digital information to the non-volatile resistance states of the two-terminal memory cells. Electronic devices containing many of these two-terminal memory cells can likewise store large amounts of data. High-density arrays are configured to contain as many memory cells as possible for a given chip space area, thereby maximizing the data storage capacity of a memory chip or system-on-chip device.

[0051] For two-terminal memories (e.g., crossbar arrays) formed at the intersection of metal lines within a wafer, two general conventions for arranging memory cells are considered. The first convention is a 1T1R memory array, in which each memory cell is isolated from the electrical effects (e.g., current, including (one or more) leakage path currents) of the surrounding circuits by an associated transistor. The second convention is a 1TnR memory array (n is a positive number greater than 1), in which a group of multiple memory cells are isolated from the electrical effects of the surrounding circuits by one (or more) transistors. In a 1T1R environment, a single memory cell can be configured to have high current suppression between memory cells, thereby significantly reducing the leakage path current of the 1T1R memory array. In a 1TnR environment, many single memory cells with high device density in a given amount of silicon space can be connected to a single transistor with much lower density. Accordingly, the 1TnR environment promotes higher bit density of resistive memory cells on semiconductor chips.

[0052] An example mechanism for connecting a 1T1R memory array includes a first end of a two-terminal resistor memory device connected to the drain of a transistor. A second end of the two-terminal resistor memory device can be connected to a bit line of the 1T1R memory array. Depending on the erase / programming conditions of the memory array, the source of the transistor is grounded or used as a source of an erase signal or a programming signal. Another example mechanism relates to a three-terminal memory including a transistor coupled to a volatile two-terminal resistor switching device. A first end of the volatile RSD is connected to the gate of the transistor, and a second end of the volatile RSD is connected to a voltage source. When activated, the volatile RSD allows charge to accumulate at the gate of the transistor, and when deactivated, the accumulated charge can be captured at the gate of the transistor. Other resistor switching device (RSD) circuits can be used within the scope of the present disclosure.

[0053] General Overview

[0054] A two-terminal resistance switching device such as a two-terminal memory and a two-terminal selector device can have a resistance switching layer (also referred to as an interface layer) in which filaments are formed and deformed in response to electrical stimulation. The formation and deformation of the filaments (e.g., retreating to an active metal layer; destroying electrical continuity, etc.) can change the electrical properties of the device, and various electrical states of the device can be mapped to logical data values. In some embodiments, on the one hand, the properties of the resistance switching layer generally benefit from being strictly controlled, but on the other hand, the resistance switching layer may be somewhat fragile. Stress and extreme conditions that occur during the manufacturing process can negatively affect the various properties of the resistance switching layer, which in turn can affect the properties of the two-terminal resistance switching device. Examples can include properties such as programming voltage, erase voltage, memory endurance, memory retention, leakage characteristics, etc.

[0055] Various embodiments of the present disclosure provide the use of one or more nitrogen compounds or mixtures as a resistive switching layer or an active metal layer (e.g., a particle donor layer) and the associated advantages. In other embodiments, it may be advantageous to use one or more oxygen compounds or mixtures as a resistive switching layer. As some examples, a silicon-nitrogen film (e.g., one or more layers), a metal-nitrogen film, or a metal-oxygen film used as a resistive switching layer may be advantageous. Further, for nitrogen compounds or mixtures, many advantages can be obtained by varying the nitrogen content in these one or more layers of the film. For example, silicon-nitrogen films can have better contact control. In addition, silicon-nitrogen films can be much more stable than other switching layer compositions or manufacturing techniques. This can make the film less likely to change in an undesirable manner during the device manufacturing process, or allow a higher thermal budget during the manufacturing process. Therefore, the properties of the device can be more tightly controlled, can be more uniform, or have smaller differences in performance. In other embodiments, (one or more) metal-nitrogen films can have varying percentages of nitrogen throughout the thickness of the film (or from film to film in multiple film layers). Varying percentages of nitrogen throughout the thickness of the film can be used to achieve a target contact resistance between layers, to achieve a high degree of control over the nitrogen concentration at a boundary with another nitrogen-based layer, to achieve a target minimum resistance for a layer, to achieve a target free metal concentration, to promote thermal stability of the metallic material, to promote adhesion between the film and other layers, etc., or appropriate combinations of the foregoing.

[0056] In order to manufacture the disclosed (one or more) silicon-nitrogen films having some or all of the desired properties mentioned herein or other beneficial properties, the present disclosure also provides various techniques for regulating gas flow in a vacuum chamber to produce the disclosed resistive switching layer. For example, techniques using physical vapor deposition (PVD) are provided, which are not limited to one or the other of direct current (DC) sputtering and radio frequency (RF) sputtering. Instead, either or both of DC sputtering or RF sputtering can be employed. It should be understood that conventional DC sputtering is typically used in connection with the formation of films comprising metals or other conductive materials, while RF sputtering is typically used in connection with the formation of films comprising insulators. Therefore, previous systems select one or the other, but are typically not capable of utilizing either or both of DC sputtering and RF sputtering.

[0057] In some embodiments, the disclosed film(s) may be fabricated by adjusting the gas flow in a manner that changes the ratio of nitrogen to argon, adjusting the power applied to the sputtering target, adjusting the temperature or pressure within the deposition chamber, etc., or a suitable combination thereof. In some embodiments, the film(s) may be deposited in the same vacuum chamber or using the same fabrication tool without breaking the vacuum. This may avoid undesirable contamination and other composition control issues.

[0058] In the following description, Figure 4-6D Various example configurations are directed to a resistive switching layer, which may be a single film or may have multiple films (eg, sub-layers). Figure 7 - Figure 9 relates to various example techniques for fabricating a resistive switching layer. Figure 1-Figure 3 Various two-terminal memory device configurations are compatible with the disclosed resistive switching layer. Accordingly, it should be understood that Figure 1-Figure 3 Non-limiting examples of overall devices are presented, and it should be understood that the resistive switching layer may be employed in other devices having different configurations.

[0059] Example Implementations

[0060] Various aspects or features of the present disclosure are described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In this specification, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the present disclosure may be implemented without these specific details, or implemented using other methods, components, materials, etc. In other cases, known structures and devices are shown in block diagram form to facilitate description of the subject disclosure.

[0061] First reference Figure 1 , depicts an integrated circuit device 100 showing a barrier layer, as an example function, which mitigates diffusion of materials used in the metal layer of the integrated circuit device 100, or in combination with integrated circuit manufacturing technology. For example, a barrier layer 104 can be formed covering the metal layer 102 of a two-terminal memory device. In various embodiments, the metal layer 102 can be a diffused metal, a metal alloy, or a metal compound. As an illustrative case, the metal layer 102 can be, for example, copper (Cu) or other suitable materials. In some embodiments, the metal layer 102 can be a bit line or word line of an integrated circuit memory array, while in other embodiments, the metal layer 102 can be local to the integrated circuit device 100, or local to a subset of the integrated circuit memory array.

[0062] The barrier layer 104 may include a dielectric material 106. The dielectric material 106 may be a material selected to mitigate diffusion of a diffused metal material (e.g., copper) or other diffused material of the metal layer 102. The dielectric material 106 may be referred to herein as the barrier layer 104 and / or may represent a portion of the barrier layer 104. In some embodiments, the dielectric material 106 may include nitrogen-doped carbide (NDC), SiN, silicon carbide compounds, SiCN, SiON, amorphous silicon, etc. In some embodiments, the dielectric material 106 is a single layer, while in other embodiments, the dielectric material 106 includes multiple layers of different materials.

[0063] In some embodiments, the metal layer 102 can be formed on or above the substrate 106. In some embodiments, an interposer (not shown) can be formed between the metal layer 102 and the substrate 106. In some embodiments, the metal layer 102 and the barrier layer 104 can be formed in a front-end processing layer and located above the substrate 106 and / or above one or more optional interposers. In some embodiments, the metal layer 102 and the barrier layer 104 can be formed in a back-end processing layer and located above the substrate 106 and / or one or more interposers. In some embodiments, the metal layer 102 and the barrier layer 104 can be provided as part of another suitable integrated circuit manufacturing process.

[0064] Figure 2A An integrated circuit device 200A according to some embodiments of the present disclosure is depicted, which has a first via 201 formed in the barrier layer 104 of the integrated circuit device 100. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. The first via 201 can be formed in response to a pattern and etching process. The formation of the first via 201 can expose the (top) surface of the metal layer 102 of the integrated circuit device 100. In some embodiments, the sidewalls of the barrier layer 104 adjacent to and exposed by the via 201 can be inclined (not shown, but see Figure 2B and Figure 3 In other embodiments, the sidewalls of the barrier layer 104 may be vertical or substantially vertical to the exposed surface of the metal layer 102, as shown.

[0065] Figure 2B An integrated circuit device 200B according to some embodiments of the present disclosure is depicted, which includes a bottom electrode formed in the first via 201 of the integrated circuit device 200A of FIG. 2 described above. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. For example, the bottom electrode 202 can be deposited or otherwise formed in the first via 201. The bottom electrode (BE) 202 can include a conductive material and can contact (e.g., electrically contact, directly contact, etc.) the metal layer 102 and adjacent portions of the barrier layer 104. Figure 2B An embodiment is shown in which the sidewalls of the barrier layer 104 (and the via 201 ) are sloped.

[0066] Now turn to Figure 3, depicting an integrated device 300. According to certain embodiments of the present disclosure, the integrated device 300 provides for the formation of a stack of layers 302 covering the integrated device 200B (including the BE 202). For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. As shown, the stack of layers 302 and the BE 202 can be formed into a column and collar configuration (e.g., the BE 202 is used as a relatively narrow column located below the stack of layers 302, and the stack of layers 302 is used as a relatively wide ring of the column and collar configuration). In other words, the width 314 of the BE 202 can be less than the width 312 of the top electrode 306 and less than the switching layer 304 and / or the cap layer 306. In other embodiments, the integrated device 300 can be formed as a monolithic stack, or any other suitable configuration. As depicted, the stack of layers 302 can include the switching layer 304. In one or more embodiments, the switching layer 304 can cover the BE 202 and contact the BE 202. In alternative or additional embodiments, one or more intermediary layers (not shown, but see Figure 4 ).

[0067] In one embodiment, the stack of layers 302 may include a top electrode (TE) 306 that may cover and contact the switching layer 304. In alternative or additional embodiments, one or more intervening layers 302 may be provided between the top electrode 306 and the switching layer 304. The stack of layers 302 may include a cap layer 308 that may cover and contact the top electrode 306 (optionally including one or more suitable intervening layers). In some embodiments, the cap layer 308 may include titanium nitride (TiN).

[0068] In some embodiments, TE 306 (or BE 202) may include an active metal layer. As described above, the active metal layer may include a metal nitride such as, for example, TiN x 、TaN x 、AlN x , CuN x , WNx and AgN x , where x is a positive number. In some embodiments, TE 306 (or BE 202) may include a metal nitride in a layer of TE 306 (or BE 202) and a metal in another layer of TE 306 (or BE 202). For example, TE 306 may include AlNx in a lower layer near the switching layer 304 and Al in an upper layer near the cap layer 308.

[0069] In some embodiments, the thickness (eg, height) 310 of the switching layer 304 can be in a range between about 1 angstrom and about 100 angstroms. In some embodiments, the thickness 310 can be in a range between about 10 angstroms and about 50 angstroms.

[0070] Reference now Figure 4 , which shows an exploded view of an example two-terminal resistance switching device 400 with variable nitrogen content according to certain embodiments of the present disclosure. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. The two-terminal resistance switching device 400 is depicted herein as a stack of monolithic layers, but other configurations are possible, such as column and ring configurations, etc. The two-terminal resistance switching device 400 may include a resistance switching layer (e.g., switching layer 304) in which the nitrogen and / or silicon content varies according to a defined or determined differential scheme. In some embodiments, the resistance switching layer 304 is configured to be non-volatile, for example, the state of the filament does not change in the absence of power. In some embodiments, the resistance switching layer 304 is configured to be volatile, for example, the state of the filament reverts to a base state in the absence of power.

[0071] The two-terminal resistance switching device 400 may include a first electrode 402 that may be located in a first region 404 of the device. The two-terminal resistance switching device 400 may include a second electrode 408 that may be located in a second region 410 of the device. The first region 404 and the second region 410 are depicted with dashed lines and, in some embodiments (not shown), may include corresponding portions of the switching layer 304. The first region 404 and the second region 410 are used herein as an orientation means and / or to better explain the disclosed subject matter.

[0072] In some embodiments, the first region 404 and the second region 410 may include one or more intervening layers 406. The intervening layer(s) 406 may include one or more of the following: a resistive switching selector device and / or a volatility-based resistive switching layer, an electrical contact layer, a diffusion barrier layer, an adhesion layer, a silicon-containing layer (e.g., to control the defect density of the switching layer 304), etc., or a suitable combination of the foregoing, or other suitable layers or components. Figure 4 An exploded view is shown, but it should be understood that in embodiments where intervening layer 406 is present, switching layer 304 can be in direct physical contact with intervening layer 406. In embodiments where intervening layer 406 is not present, switching layer 304 can be in direct physical contact with first electrode 402 and / or second electrode 408.

[0073] The switching layer 304 may include a first portion 412 that may be adjacent to the first region 404 or closer to the first region 404 than the second portion 414. In other words, the first portion 412 may be in contact with or adjacent to the first electrode 402, or in contact with or adjacent to the interposer 406, if these are present in the first region 404. The switching layer 304 may include a second portion 414 that may be adjacent to the second region 410. In other words, the second portion 414 may be in contact with or adjacent to the second electrode 408, or in contact with or adjacent to the interposer 406, if these are present in the second region 410. However, while the first portion 412 and the second portion 414 are depicted as being at the edge of the switching layer, this need not be the case in all embodiments. For example, one or both of portions 412, 414 may be more concentrated in position, but in all cases, portions 412, 414 may represent different layers of the switching layer 304 and one of the portions (e.g., 412) may be closer to one of regions 404, 410 than the other portion (e.g., 414), or vice versa.

[0074] In some embodiments, the switching layer 304 may be substantially entirely composed of a certain combination of nitrogen (N) and silicon (Si). In other embodiments, in addition to N and Si, the switching layer 304 may include other suitable materials. Regardless of the presence or absence of other materials, the switching layer 304 may have a ratio referred to herein as X, which represents the ratio of N / Si (e.g., N:Si). Advantageously, the ratio X of the switching layer 304 may vary between the first portion 412 and the second portion 414. As further described below, the nitrogen content or X may vary at a layer or specific location 418 of the switching layer 304 according to a defined or determined difference. For example, in some embodiments, X may vary according to a smooth gradient, while in other embodiments, X may vary according to a discrete step function or the like. It should be understood that the defined difference may represent an actively determined difference and may therefore be distinguished from manufacturing inaccuracies, defects or contaminants or other unintentional differences.

[0075] In some embodiments, X can vary between the first portion 412 and the second portion 414 in a range between about 0 and about 1.33. In other words, 0≤X≤1.33. Therefore, consider the case where the first portion 412 has a value of X1=0 and the second portion 414 has a value of X2=1.33. In this case, the first portion 412 has virtually no nitrogen content and can therefore be composed entirely of silicon or a combination of silicon and other materials. However, the second portion 414 has approximately 1.33 parts nitrogen to one part silicon and can be composed entirely of stoichiometric silicon nitride (Si3N4) or a combination of Si3N4 and other suitable materials. In this example, the switching layer 304 can be composed of substantially pure silicon (e.g., X=0) on one side (e.g., closer to the first electrode 402) and substantially pure stoichiometric silicon nitride (with the same or other X value in between) on the other side (e.g., closer to the second electrode 408). The first electrode 402 may be a bottom electrode (eg, BE 202) and the second electrode 408 may be a top electrode (eg, TE 306), although the reverse convention is also suitable.

[0076] As detailed, X can vary based on the determined difference. In some embodiments, the determined difference can represent a gradient function that increases or decreases the proportion X at a specific location 418 of the switching layer 304 based on a change in the height 416 of the specific location 418. In some embodiments, the height 416 can be bounded by a thickness 310, which can be in a range between about 1 angstrom to about 100 angstroms; or in a range between about 10 angstroms to about 50 angstroms. In some embodiments, the determined difference can be a function of the distance from the first portion 412 or the second portion 414. In some embodiments, the gradient function can increase or decrease the proportion X based on a change in another distance from the first electrode 402 or the second electrode 408. It can be combined Figure 5A-5D Find various non-limiting examples of gradient functions.

[0077] Now turn to Figure 5A-5D, which depicts various example switching layers 500A-500D, which illustrate non-limiting examples of variable nitrogen content throughout the layers of the corresponding switching layers according to a smooth gradient function according to certain embodiments of the present disclosure. In the depicted examples, lighter shades or colors indicate more silicon (e.g., lower X values), while darker colors or shades indicate more nitrogen (e.g., higher X values). For example, the switching layer 500A has a lower X value (e.g., less nitrogen) at the upper portion or layer of the switching layer 500A, while the lower portion or layer has a higher X value (e.g., more nitrogen). In some embodiments, the top surface of the switching layer 500A can be composed of substantially pure silicon (e.g., zero nitrogen) and the bottom surface can be composed of substantially stoichiometric silicon nitride. As depicted, the position between the two surfaces can vary X according to a smooth gradient. However, it should be understood that the gradient that varies X does not have to remain constant, but can be according to any suitable function.

[0078] Switching layer 500B depicts essentially the opposite of switching layer 500A, where the top surface has the most nitrogen content and the bottom surface has the least nitrogen content. Again, this can represent materials ranging from silicon at the bottom to stoichiometric silicon nitride at the top, or other X values ​​within that range.

[0079] Switching layer 500C shows a configuration where the outer edge contains the least nitrogen and the middle region contains the most nitrogen. Switching layer 500D shows a configuration where the middle region contains the least nitrogen and the upper and lower edges contain the most nitrogen. It should be understood that other configurations may be suitable, including multiple instances of the example gradient functions and combinations of the example gradient functions.

[0080] Now turn to Figure 6A-6D , which depicts various example switching layers 600A-600D, which illustrate non-limiting examples of nitrogen content that can be varied by discrete amounts of each sublayer of the respective switching layers according to certain embodiments of the present disclosure. In the depicted examples, lighter shades or colors indicate more silicon (e.g., lower X values), while darker colors or shades indicate more nitrogen (e.g., higher X values). For example, the switching layer 600A has a lower X value (e.g., less nitrogen) at the topmost sublayer, while the bottommost sublayer has a higher X value (e.g., more nitrogen). In some embodiments, the topmost sublayer of the switching layer 600A can be composed of substantially pure silicon (e.g., zero nitrogen) and the bottommost sublayer can be composed of substantially stoichiometric silicon nitride. As depicted, the sublayers in between can have different X values.

[0081] Switching layer 600B depicts essentially the opposite of switching layer 600A, where the top sublayer has the most nitrogen content and the bottom sublayer has the least nitrogen content. Again, this can represent materials ranging from silicon at the bottom to stoichiometric silicon nitride at the top, or other X values ​​within that range.

[0082] Switching layer 600C shows a configuration where the top and bottom sublayers contain the least nitrogen and the middle sublayers contain more nitrogen. Switching layer 600D shows a configuration where the middle sublayers contain less nitrogen and the top and bottom sublayers contain the most nitrogen. It should be understood that other configurations may also be suitable.

[0083] According to the convention herein, the different layers are smoothed or gradient-shaped (e.g. Figure 5A-5D ) causes X changes to be considered to represent a single layer, while at different layers (e.g., Figure 6A-6D ) Varying X by discrete amounts is considered to represent multiple sub-layers. Thus, switching layers 500A-500D are considered herein as a single layer or single film, while switching layers 600A-600D are considered to include multiple layers or multiple films, referred to as sub-layers. The rationale for this convention is that X can be varied by adjusting the gas flow in the vacuum chamber, which in combination with Figure 7 To provide a smooth gradient, it is generally not necessary to stop the airflow. On the other hand, to vary X by discrete amounts, the airflow may be temporarily stopped between each sublayer. Thus, treating a switching layer (e.g., switching layer 304) as having a single layer rather than having multiple sublayers may be based on whether the airflow is stopped or significantly reduced during fabrication of the switching layer.

[0084] Therefore, it should be understood that the switching layer 500A, which is considered to be composed of a single layer, can be similar in thickness to the switching layer 600A, which is considered to be composed of many layers. As an example, both the switching layers 500A and 600A can have a thickness or height in the range between about 1 angstrom and about 100 angstroms. In other embodiments, the range can be between about 10 angstroms and about 50 angstroms. In some embodiments, a separate sublayer (e.g., of the switching layers 600A-600D) can have a thickness or height in the range between about 1 angstrom and about 5 angstroms. In some embodiments, a separate sublayer can have a thickness or height in the range between about 2 angstroms and about 3 angstroms. It is therefore observed that in some embodiments, a given switching layer can have up to about 100 sublayers at most. In other embodiments, a given switching layer can have up to about 20-30 sublayers at most.

[0085] It should also be understood that in some embodiments, the value of X within a given sublayer can be substantially uniform, or in other words, the nitrogen content within the sublayer can be substantially uniform. In other embodiments, as an example, X can be obtained by combining Figure 5A-5DGradient functions such as those discussed vary within the sublayer.

[0086] Figure 7 A block diagram of an example two-terminal resistance switching device 700 having an active layer including a metallic nitrogen material having a discontinuous nitrogen concentration is shown. As shown, the two-terminal resistance switching device 700 includes a conductive layer 714. The conductive layer 714 can be a metallic material, such as tungsten (W), titanium (Ti), a mixture, alloy or compound of W and Ti, or a conductive compound (e.g., nitride) of one or more of the above substances.

[0087] A switching layer 708 is provided overlying the conductive layer 714. The switching layer 708 is a relatively non-conductive material (e.g., compared to the conductive layer 714 or compared to the TiN / TaN electrode material 712, described below). In one embodiment, the switching layer 708 may include a SiN material as described herein. In other embodiments, the switching layer 708 may include a MN y Materials; In other embodiments, the switching layer 708 may include MO y material, wherein y is a suitable value to provide a non-stoichiometric relative concentration of metal to nitrogen or metal to oxygen, and is selected to provide a relative concentration of MN x Layer 710 has a higher resistance of MN y or MO y material. In one embodiment, y can be selected from a value suitable for providing the relatively non-conductive properties of the switching layer 708 described above. For example, the resistance of the switching layer 708 can be in a range from about 50 megohms (Mohm) to about 5 gigaohms (Gohm), or any suitable value or range therebetween (e.g., greater than 500 Mohm). In at least one embodiment, the value of y in terms of relative concentration (of N or O) can be greater than the value of x used for the MNx layer 710. In various embodiments, the metal M can be Al, Cu, Ag, Ni, W, Ti, or Ta. In at least one embodiment, the switching layer 708 can include a metal oxygen-nitrogen compound or a mixture MO a N b , where a and b are suitable values ​​for providing relatively non-conductive properties of the switching layer 708.

[0088] In one or more embodiments, the switching layer 708 may at least partially include AlO y Material: AlO yThe material may be formed by a physical vapor deposition (PVD) process. The PVD process may employ sputtering of an Al metal target (optionally doped with 0%-2% Si, W, or a combination thereof) having a power in the range of 250 watts (W) to 5000 W (e.g., a range of 500 W to 2000 W, a range of 500 W to 1000 W, about 700 W, about 750 W, about 800 W, etc.), or any suitable value or range therebetween. Further, the AlO deposition process may be performed by sputtering of an Al metal target (optionally doped with 0%-2% Si, W, or a combination thereof). y The temperature of the material can be in the range of about 25 degrees Celsius (C) to about 350C (e.g., about 25C to 300C, about 100C to 300C, about 200C, about 250C, about 300C, about 350C, etc.) or any suitable value or range therebetween. In addition to the above, the pressure used for deposition can be from about 1 millitorr (mT) to about 10mT, or any suitable value or range therebetween (e.g., 3mT-5mT, 3mT, 4mT, 5mT, etc.), and the deposition can occur in an argon and oxygen environment, wherein the ratio of O2 to Ar is between about 1 to 4 and about 1 to 30 (e.g., about 10 to 20; about 12 to 18; about 15, about 12, about 20, about 18, etc.) or any suitable value or range therebetween.

[0089] Provide a metal nitrogen MN having a discontinuous nitrogen concentration covering the switching layer 708 x 710. In various embodiments, the metal nitride 710 can have multiple nitrogen concentration regions. In some embodiments, the metal nitride 710 can have a first metal nitride region 702 having a first nitrogen concentration that is rich in nitrogen. The nitrogen-rich region near the switching layer 708 is selected to bind the metal of the metal nitride material, resulting in reduced free metal (e.g., compared to a lower non-stoichiometric concentration), increased thermal stability (e.g., mitigating or avoiding metal thermal diffusion into the switching layer 708, and mitigating or avoiding the metal of the metal nitride material in the metal nitride MN). x The first metal nitride region 702 may have a first nitrogen concentration having a relative atomic percentage of nitrogen to metal in the range of about 20% to about 28% (or up to about 30% nitrogen to metal).

[0090] As used herein, related terms such as "about," "substantially," and the like, when used in conjunction with a quantitative value or range or in conjunction with a qualitative noun or modifier, refer to variations having similar functions or operational effects within manufacturing tolerances generally understood by those of ordinary skill in the art (e.g., a range of values ​​of mathematical values ​​that can be actually achieved with manufacturing equipment), and the like. As an example, a nitrogen concentration of about 20% in a metal nitride material may be a nitrogen concentration range of about 20% that a person of ordinary skill in the art would understand to be achievable using manufacturing equipment available in the art. As another example, about 20% to about 28% may refer to a number that is above or below a definite number that achieves some or all of the described functions or operational effects of an associated component (e.g., an active layer of a two-terminal resistance switching device 700). In the case of the above-mentioned metal nitride MN x In the example provided by layer 710, about 20% to about 28% may include a range of values ​​above or below the figures that achieve at least one disclosed function or disclosed operational effect of the active metal material, or at least one disclosed function or operational effect of first metal nitride region 702. For example: reduced free metal, increased thermal stability (e.g., reduced thermal diffusion; reduced metal agglomeration, ...) or reduced chemical stability (e.g., reduced chemical diffusion), while achieving drift of metal particles into switching layer 708 in response to an external stimulus.

[0091] Overlying the first metal nitride region 702 is a second metal nitride region 704, and a third metal-nitrogen region 706. In one or more embodiments, the second metal nitride region 704 may have a relative concentration of nitrogen in a second range of about 15% to about 20%. The second range may be selected to achieve thermal and chemical stability over the previous metal nitride layer (metal nitride region 702), while providing a greater amount of free metal to provide particles to form filaments to the switching layer 708. In various embodiments, the third metal nitride region 706 may have a relative concentration of nitrogen in a third range of about 10 percent to about 15 percent. The third range may be selected to be high enough to avoid metal agglomeration due to excessive metal concentration, while also avoiding excessive nitrogen in the metal nitride region 706 due to subsequent deposition of the TiN / TaN electrode material 712. Because the TiN / TaN electrode material 712 has a relatively high nitrogen concentration (e.g., about 40% in one or more embodiments), depositing the TiN / TaN electrode material 712 can effectively increase the nitrogen concentration of the third metallic nitride region 706 to be higher than the nitrogen concentration of the second nitride region 704. Accordingly, the third metallic nitride region 706 can be intentionally nitrogen-poor when deposited, and acquire additional nitrogen when the TiN / TaN electrode material 712 is deposited, resulting in an increased nitrogen concentration of at least some (or all) portions of the third metallic nitride region 706. In one embodiment, the increased nitrogen concentration of the third metallic nitride region 706 can approach or reach about 15 percent to about 20 percent of the second metallic nitride region 704.

[0092] In some embodiments, the first metal nitride region 702 can be formed using a PVD process that sputters a metal of metal nitride in a nitrogen and argon environment. In such (one or more) embodiments, the first metal nitride region 702 can be formed by sputtering a metal material at a power of about 500W (or a range within + / -10% of 500W) and a ratio of about 1 to 10 of N2 gas to argon gas in a nitrogen and argon environment. As an example, the metal material can be aluminum metal (optionally including up to about 2% Si, W, or both) as a sputtering target. Other metals for the disclosed metal nitride materials (optionally including up to about 2% Si, W, or both) can be used instead. The second metal nitride region 704 can be formed by changing the nitrogen and argon environment to a ratio of about 1 to 12 of N2 gas to Ar gas and a sputtering power of 500W (+ / -10%). In one or more embodiments, the first metal nitride region 702 may be about 50 angstroms (Å) thick, while the second metal nitride region 704 may be about 300 Å thick. In at least one such embodiment, the third metal nitride region 706 is not formed, and instead, the TiN / TaN electrode material 712 is formed to initially have a lower nitrogen percentage for a first region of the TiN / TaN electrode material 712, and subsequently to have a higher nitrogen percentage for a second region of the TiN / TaN electrode material 712 (see FIG. 9-10 below). Fig.9F ;For example, Fig.9E 912 and 914).

[0093] In an alternative embodiment, the first metal nitride region 702 can be formed using a PVD process by sputtering a metal target at a power of 500 W (+ / - 10%) and a nitrogen and argon environment having a ratio of about 1 to 8 of N2 gas to argon. The second metal nitride region 704 can then be formed by changing the nitrogen and argon environment to a ratio of about 1 to 12 of nitrogen to argon. In such an embodiment, the third metal nitride region 706 can then be formed by increasing the sputtering power to about 750 W (+ / - 10%) while maintaining an environment with a ratio of (about) 1 to 12 of nitrogen to argon. In at least one such embodiment, the first metal nitride region 702 can be about 50 angstroms, the second metal nitride region 704 can be about 300 angstroms, and the third metal nitride region 706 can be about 50 angstroms.

[0094] In a further embodiment, the first metal nitride region 702 may be formed by a PVD process that includes sputtering a metal target at a power of 500 W (+ / - 10%) in a nitrogen and argon environment with a ratio of about 1 to 10 of N2 gas to Ar gas. The second metal nitride region 704 may then be formed by changing the nitrogen and argon environment to a ratio of about 1 to 12 of N2 gas to Ar gas with a sputtering power within the same range (500 W + / - 10%), and the third metal nitride region 706 may then be formed by changing the nitrogen and argon environment to a ratio of about 1 to 15 of N2 gas to Ar gas with a sputtering power within the same range (500 W + / - 10%). Similar to the above embodiment, the first metal nitride region 702 may be about 50 angstroms, the second metal nitride region 704 may be about 300 angstroms, and the third metal nitride region 706 may be about 50 angstroms.

[0095] In various embodiments, the MNx layer 710, including the first metal nitride region 702, the second metal nitride region 704, and the optional third metal nitride region 706, can be formed by continuous deposition involving process parameters that are varied in real time during deposition to form a smooth nitrogen concentration gradient according to the concentrations listed above. x One or more of the corresponding metal nitride regions 702, 704, 706 of layer 710 can be formed as (one or more) discrete sub-layers, where deposition is stopped before or after (one or more) sub-layers, process parameters are reset to form (one or more) sub-layers or (one or more) subsequent regions, and then deposition is restarted based on the reset process parameters.

[0096] In an alternative embodiment, the desired MN may be achieved using a suitable combination of the following process parameters: x The nitrogen concentration of layer 710. The temperature is in the range of 25C to 150C; the sputtering power ranges from 200W to 5000W; the pressure is in the range of 1 millitorr (mT) to 10mT (e.g., about 4mT-6mT, about 5mT, etc.); the flow ratio of N2 gas to Ar gas is about 1 to 8 to about 1 to 20 (e.g., a ratio of about 10-15; a ratio of about 11-13; a ratio of about 12, etc.). Any suitable value or range between the above ranges of one or more parameters (e.g., temperature and pressure), alone and in combination with any suitable value or range between the above ranges of one or more other parameters (e.g., sputtering power and gas ratio), is within the scope of the present disclosure.

[0097] In one or more embodiments, the TiN / TaN electrode material 712 may be deposited by a PVD process. The TiN / TaN electrode material 712 may be a non-stoichiometric (e.g., amorphous, amorphous, etc.) material having about 40% nitrogen at an atomic concentration and the remainder being Ti or Ta metal. In at least one embodiment, the TiN / TaN electrode material 712 may be initially deposited (or deposited with an initial sub-layer) having a nitrogen concentration of about 15%-20% and the remainder being Ti or Ta metal (e.g., see below). Fig.9E As an example, the initial deposition may be 50 angstroms to 100 angstroms thick. Subsequently, the remaining TiN / TaN electrode material 712 may have a nitrogen concentration of 40%. An initial deposition of 15%-20% nitrogen concentration may be used to deposit the MN x After layer 710 is deposited to its desired nitrogen concentration (eg, as provided above), it is possible to mitigate or avoid increasing the MN below the TiN / TaN electrode material 712. x The nitrogen concentration of layer 710 (eg, third metal nitride region 706 , but may include second metal nitride region 704 and first metal nitride region 702 ).

[0098] Figure 8A-8E An example deposition 800 for fabricating a two-terminal resistance switching device according to one or more disclosed embodiments is shown. Although some layers are shown as having discrete sub-layers, it should be understood that the layers or sub-layers shown may be formed with discrete deposition processes, with established parameters for a given layer or sub-layer, or may be formed with a continuous deposition process that changes from one layer or sub-layer to another as appropriate.

[0099] Fig. 8A A diagram of a switching layer 802 is depicted. The switching layer 802 may be formed overlying one or more other layers of the semiconductor device (e.g., including but not limited to the conductive layer 714). The switching layer 802 may be formed of any suitable material disclosed herein or by any process disclosed herein. In at least one example, the switching layer 802 may be formed of AlO y Material formation. Figure 8B Deposition of a first metal nitride region 804 of a metal nitride active layer (or particle donor layer) is shown. The metal nitride region 804 can have the highest (relative) nitrogen concentration for the active layer. In some embodiments, the metal nitride region 804 can have a substantially constant nitrogen concentration in the range of about 20 percent to about 30 percent, or can have a decreasing nitrogen concentration starting from a higher value in the range of about 20 percent to about 30 percent (e.g., about 28 percent) to a lower value in the range of about 20 percent to about 30 percent (e.g., about 20 percent to 22 percent). In one or more embodiments, the metal nitride region 804 can be about 50 angstroms thick.

[0100] Figure 8C Deposition of a metallic nitride region 806 having a moderate nitrogen concentration (eg, a nitrogen concentration of about 15% to about 20%) is shown. In at least one embodiment, the metallic nitride region 806 may be about 300 angstroms thick. Fig.8D A metal nitride region 808 is shown having a low nitrogen concentration (e.g., a nitrogen concentration of about 10% to about 15%). In various embodiments, the metal nitride region 808 may have a thickness of about 50 angstroms in various embodiments. Combined, the metal nitride regions 804, 806, and 808 form a MN. x Layer 810, having Fig. 8E The relative nitrogen concentration along the X-axis is shown as a function of the deposition thickness along the Y-axis. x Layer 810 is a TiN / TaN conductive layer 812 .

[0101] Figure 9A-9F An example deposition 900 for fabricating a two-terminal resistance switching device according to one or more disclosed embodiments is shown. Although some layers are shown as having discrete sub-layers, it should be understood that the layers or sub-layers shown may be formed with discrete deposition processes, with established parameters for a given layer or sub-layer, or may be formed with a continuous deposition process that changes from one layer or sub-layer to another as appropriate.

[0102] Fig. 9A A switching layer 902 is depicted that may be formed overlying one or more other layers of a semiconductor device. Fig. 9B Deposition of a metallic nitride region 904 having the highest nitrogen concentration (eg, a nitrogen concentration of about 20 percent to about 30 percent) is depicted. In one embodiment, the metallic nitride region 904 may be about 50 Å thick. Fig. 9C A metallic nitrogen region 906 is depicted having a moderate nitrogen concentration (eg, a nitrogen concentration of about 15 percent to about 20 percent). Fig.9D A TiN / TaN deposition 912 concentration having a low non-stoichiometric nitrogen concentration (eg, a nitrogen concentration of about 15 percent to about 20 percent) is depicted. In various embodiments, the TiN / TaN deposition 912 may be about 50 Å to about 100 Å. Fig.9E A second TiN / TaN deposition 914 concentration is depicted having a higher non-stoichiometric nitrogen concentration (eg, a nitrogen concentration of approximately 40 percent). Fig.9F MN x Nitrogen concentration profile (along the X-axis) of layer 908 and the deposited thickness (along the Y-axis) of TiN / TaN deposit 912.

[0103] The figures included herein are described with respect to the interaction between several components of a memory device or an integrated circuit device, or a storage architecture including one or more memory devices or integrated circuit devices. It should be understood that such a figure may include those components, devices and architectures specified therein, some of the specified components / devices, or additional components / devices. Subcomponents may also be implemented as being electrically connected to other subcomponents rather than being included in a parent device. In addition, it should be noted that one or more disclosed processes may be combined into a single process that provides a polymeric function. For example, a deposition process may include an etching process, or vice versa, to facilitate deposition and etching of components of an integrated circuit device by a single process. The components of the disclosed architecture may also interact with one or more other components not specifically described herein but known to those skilled in the art.

[0104] In view of the above exemplary figures, referring to Figure 10-13 The flowchart of the present invention will better understand the process method that can be implemented according to the disclosed subject matter. Although for the sake of simplicity of explanation, Figure 10-13 The methods are shown and described as a series of blocks, but it should be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in different orders and / or simultaneously with other blocks depicted and described herein. In addition, all of the blocks shown may not be required to implement the methods described herein. In addition, it should also be understood that the methods disclosed throughout this specification can be stored on an article of manufacture to facilitate the transmission and transfer of these methods to an electronic device. The term article of manufacture used is intended to cover a computer program accessible from any computer-readable device, device in combination with a carrier, or storage medium.

[0105] Reference now Fig.10 , an exemplary method 1000 is shown. According to certain embodiments of the present disclosure, method 1000 can provide for the manufacture of a two-terminal memory device that changes a gas mixture during the manufacture of a switching layer. For example, at reference numeral 1002, a two-terminal memory manufacturing device can form a bottom electrode (BE) covering a metal layer. In some embodiments, the metal layer can represent a bit line, a word line, etc., and can include copper or another suitable material in some embodiments. In some embodiments, the metal layer can be formed to cover the substrate. In some embodiments, the BE can be formed in a vacuum chamber or placed in a vacuum chamber during the manufacture of the two-terminal memory device.

[0106] At reference numeral 1004, the manufacturing apparatus may introduce a gas mixture having a defined ratio Y of nitrogen (N2) to argon (Ar) into a vacuum chamber including the BE. In some embodiments, the gas mixture may consist essentially entirely of some combination of N2 and Ar. In other embodiments, the gas mixture may include other suitable gases in addition to N2 and Ar. Regardless of the presence or absence of other gases, the gas mixture may have a ratio referred to herein as Y, which represents the ratio of N2:Ar.

[0107] At reference numeral 1006, a manufacturing apparatus can form a resistance-switching layer in a vacuum chamber in response to a physical vapor deposition (PVD) sputtering process. The PVD sputtering process can cause a defined ratio Y to vary during formation of the resistance-switching layer. The manner in which Y is varied during formation of the resistance-switching layer can be according to a defined scheme determined to vary Y in an advantageous or desired manner. For example, a difference in Y can be defined to distinguish from manufacturing inaccuracies, defects or contaminants, or other unintentional differences.

[0108] At reference numeral 1008, the fabricated device may form a top electrode (TE) of a two-terminal memory device. The TE may be formed to cover the resistive switching layer. The method 1000 may end and proceed to combining Fig.11 Tab A for further discussion, or proceed to Combine Fig.12 Tab B for further discussion.

[0109] Now turn to Fig.11 , an exemplary method 1100 is shown. According to certain embodiments of the present disclosure, method 1100 may provide for selecting a type of PVD sputtering and selecting a type of difference in a defined ratio Y. At reference numeral 1102, a manufacturing apparatus may perform a selection process for selecting a type of PVD sputtering for forming a resistive switching layer.

[0110] At reference numeral 1104, the manufacturing apparatus may select between direct current (DC) sputtering techniques and radio frequency (RF) sputtering techniques. For example, the manufacture of the switching layer is not limited to one or the other of DC sputtering and RF sputtering. Instead, either or both of DC sputtering or RF sputtering may be employed. It should be understood that DC sputtering is typically used in connection with forming films comprising metals or other conductive materials, while RF sputtering is typically used in connection with forming films comprising insulators. Therefore, previous techniques select one or the other, but typically do not have the ability to utilize either or both of DC sputtering and RF sputtering.

[0111] At reference numeral 1106, as Fig.10As detailed at reference numeral 1006 of the present invention, the manufacturing apparatus that varies the defined ratio Y during formation of the resistance switching layer may vary Y according to a smooth function that varies Y continuously or substantially continuously over time. Additionally or alternatively, at reference numeral 1108, the manufacturing apparatus may vary Y according to a step function that varies Y at discrete intervals.

[0112] Now turn to Fig.12 , which illustrates an exemplary method 1200. According to certain embodiments of the present disclosure, the method 1200 may provide additional elements or aspects related to the fabrication of a two-terminal memory device that varies a gas mixture during fabrication of a switching layer.

[0113] As previously described, the defined ratio Y, which can be varied at reference numerals 1006, 1106, and 1108 by manufacturing the apparatus, can be characterized as N2:Ar. At reference numeral 1202, the manufacturing apparatus can vary Y within a range between about 0:1 to about 2:1. In other words, the ratio Y in the gas mixture can range from having little or no N2 (e.g., essentially all argon) to having twice the amount of N2 as Ar.

[0114] At reference numeral 1204, the manufacturing apparatus can change Y and complete the formation of the resistance switching layer without breaking the vacuum seal of the vacuum chamber. In some embodiments, this can avoid or mitigate contamination and composition control issues that may occur during the manufacturing process.

[0115] At reference numeral 1206, the manufacturing apparatus can form a resistive switching layer having a varying ratio X of N to Si, where X can vary as a function of a defined ratio Y. For example, the amount of nitrogen content within a given layer of the resistive switching layer (e.g., see Figures 5A-6D ) may vary with the amount of nitrogen included in the gas mixture used during formation of the resistance switching layer (see, for example, Fig.10 ).

[0116] At reference numeral 1208, the manufacturing apparatus can vary X by adjusting the gas flow and changing Y. This can be accomplished such that X varies within a range between about 0:1 (corresponding to substantially pure Si with little or no N content) to about 1.33:1 (corresponding to substantially stoichiometric silicon nitride (Si3N4)).

[0117] Fig.13A flow chart of an example method 1300 for fabricating a two-terminal resistance switching device according to an alternative or additional embodiment of the present disclosure is shown. At 1302, method 1300 may include forming a switching layer of a two-terminal resistance switching device overlying a conductive metal layer. At 1304, method 1300 may include forming a first portion of a particle donor layer overlying the switching layer of a metal and nitrogen material and including a relatively high relative concentration of nitrogen. At 1306, method 1300 may include forming a second portion of the particle donor layer, the second portion including a medium relative concentration of nitrogen for the metal and nitrogen materials. At 1308, method 1300 may include optionally forming a third portion of the particle donor layer, the third portion including a low relative concentration of nitrogen for the metal and nitrogen materials. At 1310, it is determined whether the optional third portion of the particle donor layer is deposited. If so, method 1300 may proceed to reference numeral 1314; otherwise, method 1300 may proceed to reference numeral 1312 and may include forming a low relative concentration of nitrogen for the conductive metal and nitrogen material overlying the particle donor layer. At 1314 , method 1300 can include forming a constant nitrogen concentration portion of the metal and nitrogen material for the conductive layer overlying the particle donor layer.

[0118] Example operating environment

[0119] Fig.14 A block diagram of an example operating and control environment 1400 for a memory array 1402 for a memory cell array according to aspects of the subject disclosure is shown. In at least one aspect of the subject disclosure, the memory array 1402 can include memory selected from a plurality of memory cell technologies. In at least one embodiment, the memory array 1402 can include a two-terminal memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal memory technologies can include resistive switching memory, conductive bridge memory, phase change memory, organic memory, magnetoresistive memory, etc., or a suitable combination of the foregoing.

[0120] The column controller 1406 and the sense amplifier 1408 may be formed adjacent to the memory array 1402. In addition, the column controller 1406 may be configured to activate (or identify activation of) a subset of the bit lines of the memory array 1402. The column controller 1406 may activate and operate corresponding bit lines in the subset of bit lines using control signals provided by (one or more) reference and control signal generators 1418, thereby applying appropriate programming, erasing, or reading voltages to these bit lines. Inactivated bit lines may be maintained at an inhibit voltage (also applied by (one or more) reference and control signal generators 1418) to mitigate or avoid bit disturbance effects on these inactivated bit lines.

[0121] Additionally, the operating and control environment 1400 may include a row controller 1404. The row controller 1404 may be formed adjacent to and electrically connected to the word lines of the memory array 1402. Moreover, the row controller 1404 may select a particular row of memory cells with an appropriate select voltage using control signals from the reference and control signal generator(s) 1418. Furthermore, the row controller 1404 may facilitate programming, erasing, or reading operations by applying an appropriate voltage at the selected word line.

[0122] The sense amplifier 1408 may read data from or write data to an activated memory cell of the memory array 1402, which is selected by the column control 1406 and the row control 1404. The data read out from the memory array 1402 may be provided to the input / output buffer 1412. Likewise, the data to be written to the memory array 1402 may be received from the input / output buffer 1412 and written to the activated memory cell of the memory array 1402.

[0123] The clock source(s) 1408 may provide corresponding clock pulses to facilitate the timing of the row controller 1404 and the column controller 1406 for read, write, and program operations. The clock source(s) 1408 may also facilitate the selection of word lines or bit lines in response to external and internal commands received by the operating and control environment 1400. The input / output buffer 1412 may include command and address inputs and bidirectional data inputs and outputs. Instructions are provided via the command and address inputs, and data to be written to the memory array 1402 and data to be read from the memory array 1402 are transmitted on the bidirectional data inputs and outputs to facilitate connection to an external host device, such as a computer or other processing device (not described, but see, e.g., below). Fig.15 computer 1502).

[0124] The input / output buffer 1412 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, and receive address data and command data, as well as address data for corresponding instructions. The address data may be transmitted to the row controller 1404 and the column controller 1406 via the address register 1410. In addition, input data is transmitted to the memory array 1402 via a signal input line between the sense amplifier 1408 and the input / output buffer 1412, and output data is received from the memory array 1402 via a signal output line from the sense amplifier 1408 to the input / output buffer 1412. The input data may be received from a host device, and the output data may be transmitted to the host device via an I / O bus.

[0125] The command received from the host device may be provided to the command interface 1416. The command interface 1416 may be configured to receive an external control signal from the host device and determine whether the data input to the input / output buffer 1412 is write data, a command, or an address. The input command may be transmitted to the state machine 1420.

[0126] The state machine 1420 can be configured to manage the programming and reprogramming of the memory array 1402 (and other memory banks of the multi-bank memory array). The instructions provided to the state machine 1420 are implemented according to the control logic configuration, enabling the state machine to manage reading, writing, erasing, data input, data output, and other functions associated with the memory cell array 1402. In some aspects, the state machine 1420 can send and receive confirmations and negative confirmations related to the successful receipt or execution of various commands. In other embodiments, the state machine 1420 can decode and implement state-related commands, decode and implement configuration commands, etc.

[0127] To implement functions such as read, write, erase, input, output, etc., the state machine 1420 can control (one or more) clock sources 1408 or (one or more) reference and control signal generators 1418. Control of the (one or more) clock sources 1408 can result in output pulses configured to facilitate the row controller 1404 and the column controller 1406 to implement specific functions. The output pulses can be transmitted to a selected bit line through, for example, the column controller 1406, or to a selected word line through, for example, the row controller 1404.

[0128] Combination Fig.15 , the systems, devices and / or processes described below may be embodied in hardware, such as a single integrated circuit (IC) chip, multiple ICs, an application specific integrated circuit (ASIC), etc. In addition, the order in which some or all of the process blocks in each process appear should not be considered limiting. Instead, it should be understood that some of the process blocks may be performed in a variety of orders, and all orders may not be explicitly stated herein.

[0129] refer to Fig.15 , a suitable environment 1500 for implementing various aspects of the claimed subject matter includes a computer 1502. The computer 1502 includes a processing unit 1504, a system memory 1510, a codec 1514, and a system bus 1508. The system bus 1508 couples system components including, but not limited to, the system memory 1510 to the processing unit 1504. The processing unit 1504 can be any of a variety of available processors. Dual microprocessors and other multi-processor architectures can also be used as the processing unit 1504.

[0130] The system bus 1508 can be any of several types (one or more) of bus structures including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), card bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0131] The system memory 1510 includes a volatile memory 1510A and a non-volatile memory 1510B. A basic input / output system (BIOS), which contains basic routines such as for transferring information between elements within the computer 1502 during startup, is stored in the non-volatile memory 1510B. In addition, according to the present innovation, the codec 1514 may include at least one of an encoder or a decoder, wherein at least one of the encoder or the decoder may include hardware, software, or a combination of hardware and software. Although the codec 1514 is described as a separate component, the codec 1514 may be included in the non-volatile memory 1510B. As an illustration and not limitation, the non-volatile memory 1510B may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM) or a flash memory, a two-terminal memory, etc. The volatile memory 1510A includes a random access memory (RAM), and in some embodiments may include a cache memory. By way of illustration and not limitation, RAM may take many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM).

[0132] The computer 1502 may also include removable / non-removable, volatile / nonvolatile computer storage media. Fig.15Disk storage 1506 is illustrated. Disk storage 1506 includes, but is not limited to, devices such as disk drives, solid state disks (SSDs), floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. In addition, disk storage 1506 may include storage media alone or in combination with other storage media, including but not limited to optical disk drives, such as compact disk ROM devices (CD-ROMs), CD recordable drives (CD-R Drives), CD rewritable drives (CD-RW drives), or digital versatile disk ROM drives (DVD-ROMs). In order to facilitate connecting disk storage 1506 to system bus 1508, removable or non-removable interfaces, such as storage interface 1512, are typically used. It is understood that storage 1506 may store information related to a user. Such information may be stored at a server or provided to a server or provided to an application running on a user device. In one embodiment, a user may be notified (e.g., via (one or more) output devices 1532) of the type of information stored in disk storage 1506 or transmitted to a server or application. The user may be provided an opportunity to opt-in or opt-out of having such information collected and / or shared with a server or application (eg, via input from input device(s) 1542 ).

[0133] It should be understood that Fig.15 Software is described that acts as an intermediary between a user and the basic computer resources described in a suitable operating environment 1500. Such software includes an operating system 1506A. The operating system 1506A, which may be stored on disk storage 1506, is used to control and allocate the resources of the computer system 1502. Application programs 1506C utilize the management of resources by the operating system 1506A through program modules 1506D and program data 1506D, such as startup / shutdown transaction tables stored in system memory 1510 or on disk storage 1506. It should be understood that the claimed subject matter can be implemented with various operating systems or combinations of operating systems.

[0134] A user enters commands or information into the computer 1502 through input device(s) 1542. Input devices 1542 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, game controller, satellite dish, scanner, TV tuner card, digital camera, digital video camera, webcam, etc. These and other input devices are connected to the processing unit 1504 through the system bus 1508 via input port(s) 1540. Input port(s) 1540 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output device(s) 1532 use some of the same types of ports as input device(s) 1542. Thus, for example, a USB port can be used to provide input to the computer 1502 and output information from the computer 1502 to an output device 1532. Output adapters 1530 are provided to illustrate that there are some output devices 1532, such as monitors, speakers, and printers, and other output devices 1532 that require special adapters. By way of illustration and not limitation, output adapters 1530 include video and sound cards that provide a means of connection between output devices 1532 and system bus 1508. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer(s) 1538.

[0135] The computer 1502 can operate in a networked environment using a logical connection to one or more remote computers such as (one or more) remote computers 1524. (One or more) remote computers 1524 can be personal computers, servers, routers, network PCs, workstations, microprocessor-based devices, peer devices, smart phones, tablet computers, or other network nodes, and typically include many of the elements described in relation to the computer 1502. For simplicity, only the memory storage device 1526 is shown with (one or more) remote computers 1524. (One or more) remote computers 1524 are logically connected to the computer 1502 through a network 1522, and then connected via (one or more) communication interfaces 1520. The network 1522 includes wired or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs) and cellular networks. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet, token ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL).

[0136] The communication interface(s) 1520 refers to the hardware / software used to connect the network 1522 to the bus 1508. Although the communication interface(s) 1520 are shown to be internal to the computer 1502 for clarity of illustration, they may also be external to the computer 1502. The hardware / software required to connect to the network 1522 includes (for exemplary purposes only) internal technology and external technology, such as modems, including conventional telephone grade modems, cable modems and DSL modems, ISDN adapters, and wired and wireless Ethernet cards, hubs, and routers.

[0137] As used herein, the terms "component," "system," "architecture," and the like are intended to refer to a computer or electronic related entity, hardware, a combination of hardware and software, software (e.g., in execution), or firmware. For example, a component may be one or more transistors, memory cells, an arrangement of transistors or memory cells, a gate array, a programmable gate array, an application specific integrated circuit, a controller, a processor, a process running on a processor, an object, an executable program or application that accesses or interfaces with semiconductor memory, a computer, etc., or a suitable combination thereof. The component may include erasable programming (e.g., process instructions stored at least in part in an erasable memory) or hard programming (e.g., process instructions burned into a non-erasable memory at the time of manufacture).

[0138] As an illustration, the processes executed from the memory and the processor can be components. As another example, the architecture can include the arrangement of electronic hardware (e.g., parallel or serial transistors), processing instructions and processors, which implement the processing instructions in a manner suitable for the arrangement of electronic hardware. In addition, the architecture can include a single component (e.g., a transistor, a gate array, etc.) or an arrangement of components (e.g., a series or parallel arrangement of transistors, a gate array connected to a program circuit, a power line, an electrical ground, an input signal line, and an output signal line, etc.). A system can include one or more components and one or more architectures. An example system can include a switch block architecture, which includes crossed input / output lines and transmission gate transistors, as well as (one or more) power supplies, (one or more) signal generators, (one or more) communication buses, controllers, I / O interfaces, address registers, etc. It should be understood that some overlaps in the definitions are expected, and the architecture or system can be an independent component, or a component of another architecture, system, etc.

[0139] In addition to the foregoing, the disclosed subject matter can be implemented as a method, device or product that uses typical manufacturing, programming or engineering techniques to produce hardware, firmware, software or any suitable combination thereof to control an electronic device to implement the disclosed subject matter. The terms "device" and "product" used herein are intended to cover electronic devices, semiconductor devices, computers or computer programs that can be accessed from any computer-readable device, carrier or medium. Computer-readable media may include hardware media or software media. In addition, the medium may include non-transitory media or transmission media. In one example, non-transitory media may include computer-readable hardware media. Specific examples of computer-readable hardware media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips...), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs)...), smart cards and flash memory devices (e.g., cards, sticks, key drives...). Computer-readable transmission media may include carrier waves, etc. Of course, those skilled in the art will recognize that many modifications may be made to the configuration without departing from the scope or spirit of the disclosed subject matter.

[0140] The content described above includes examples of the subject innovation. Of course, it is impossible to describe every possible combination of components or methods for describing the subject innovation, but those of ordinary skill in the art can recognize that many other combinations and arrangements of the subject innovation are possible. Accordingly, the disclosed subject matter is intended to include all such changes, modifications and variations that fall within the spirit and scope of the present disclosure. In addition, if the terms "comprise", "include", "have" or "have" and their variants are used in the detailed specification or claims, such terms are intended to be inclusive in a manner similar to that in which the term "comprise" is interpreted as "including" when used as a transition word in the claims.

[0141] In addition, the word "exemplary" is used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as better or superior to other aspects or designs. On the contrary, the use of the word exemplary is intended to present concepts in a concrete way. The term "or" used in this application is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any natural inclusive arrangement. That is, if X uses A; X uses B; or X uses A and B, then in any of the foregoing cases "X uses A or B" is satisfied. In addition, unless otherwise specified or clearly pointed to a singular form from the context, the articles "one" and "a" used in this application and the appended claims should generally be interpreted as meaning "one or more".

[0142] In addition, some portions of the detailed description have been presented in terms of algorithms or processing operations on data bits within an electronic memory. These process descriptions or representations are mechanisms used by those skilled in the art to effectively convey the substance of their work to other equally skilled persons. A process herein is generally considered to be a self-consistent sequence of actions leading to a desired result. These actions are those that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transmitted, combined, compared, and / or otherwise manipulated.

[0143] It has proven convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated or apparent from the foregoing discussion, it should be understood that throughout the disclosed subject matter, discussions using terms such as process, compute, replicate, emulate, determine, or transmit refer to the act and process of a processing system, and / or similar consumer or industrial electronic device or machine, of processing or converting data or signals represented as physical (electrical or electronic) quantities in the circuits, registers, or memories of (one or more) electronic devices to other data or signals similarly represented as physical quantities in the machine or computer system memory or registers or other such information storage, transmission, and / or display devices.

[0144] With respect to the various functions performed by the above-described components, architectures, circuits, processes, etc., unless otherwise noted, the terms used to describe these components (including references to "means") are intended to correspond to any component (e.g., functional equivalent) that performs the specified functions of the described components, even if not structurally equivalent to the disclosed structures, which performs the functions in the exemplary aspects of the embodiments shown herein. In addition, while a particular feature may be disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations, as may be desirable and advantageous for any given or particular application. It will also be recognized that the embodiments include systems as well as computer-readable media having computer-executable instructions for performing the actions and / or events of the various processes.

Claims

1. A two-terminal memory device, the device comprising: a first electrode located in a first region of the two-terminal memory device; a second electrode located in a second region of the two-terminal memory device; The first electrode is a bottom electrode and the second electrode is a top electrode, and a resistance-switching layer having a first portion adjacent to the first region and a second portion adjacent to the second region, wherein the resistance-switching layer comprises nitrogen and silicon and has a ratio X characterized as N / Si, the ratio X varying between the first portion and the second portion according to the determined difference; wherein the determined difference is represented by a gradient function or a discrete sublayer function, and when the determined difference is represented by a gradient function, the gradient function causes the ratio X at a position of the resistance switching layer to increase or decrease according to a height change of the position; When the determined difference is represented by a discrete sublayer function, the resistance-switching layer includes a plurality of sublayers, and the discrete sublayer function increases or decreases the ratio X by a discrete amount for each of the plurality of sublayers; wherein X varies between the first portion and the second portion in the range of 0 to 1.33; The first portion has a first ratio X1, which is equal to 0, and the first portion is entirely composed of Si; and the second portion has a second ratio X2, which is equal to 1.33, and the second portion is entirely composed of stoichiometric silicon nitride.

2. The two-terminal memory device according to claim 1, wherein: A thickness of a sub-layer in the plurality of sub-layers is between 1 angstrom and 5 angstroms.

3. The two-terminal memory device according to claim 1, wherein: The resistance switching layer has a thickness between 1 angstrom and 100 angstroms.

4. The two-terminal memory device according to claim 1, wherein: The resistance switching layer has a thickness between 10 angstroms and 50 angstroms.

5. The two-terminal memory device according to claim 1, wherein: The two-terminal memory device is configured according to a post and ring configuration characterized by a first width of the bottom electrode being less than a second width of the top electrode.

6. The two-terminal memory device according to claim 1, wherein: The resistance switching layer is a non-volatile resistance switching layer.

7. A method of manufacturing a two-terminal memory device as claimed in any one of claims 1 to 6, the method comprising: forming a bottom electrode of a capping metal layer of the two-terminal memory device; introducing a gas mixture of nitrogen and argon having a defined ratio Y into a vacuum chamber including the bottom electrode, Y being characterized as N2:Ar; forming a resistance switching layer in the vacuum chamber in response to a physical vapor deposition sputtering process, wherein the physical vapor deposition sputtering process causes Y to change during formation of the resistance switching layer, and X changes according to the change in Y; A top electrode of the two-terminal memory device is formed overlying the resistance-switching layer.

8. The method of claim 7, further comprising performing a selection process that selects a type of physical vapor deposition sputtering to be employed to form the resistance switching layer.

9. The method according to claim 8, wherein: The selection process for selecting the type of physical vapor deposition sputtering to be employed includes choosing between direct current sputtering techniques and radio frequency sputtering techniques.

10. The method according to claim 7, wherein: The physical vapor deposition sputtering process varies Y according to a smooth function that varies Y continuously over time.

11. The method according to claim 7, wherein: The physical vapor deposition sputtering process varies Y according to a step function that varies Y at discrete intervals.

12. The method according to claim 7, wherein: The Y has a range of 0:1 to 2:

1.

13. The method according to claim 7, wherein: The physical vapor deposition sputtering process changes Y and completes the formation of the resistance switching layer without breaking the vacuum seal of the vacuum chamber.

14. The method according to claim 7, wherein: Forming the resistance-switching layer includes forming the resistance-switching layer having a varying ratio X of nitrogen to silicon.

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