Partition Block Caching Component of a Memory Subsystem with a Partitioned Namespace

Abstract

Embodiments of the present application relate to a block staging component for a memory subsystem having a partitioned namespace. A memory subsystem may determine a block granularity for an input / output (I / O) data stream received from a host system. The memory subsystem may determine that the block granularity is different from a memory block granularity of a first memory region in a first namespace of one or more memory devices, where the first memory region will store the I / O data stream. The memory subsystem may accumulate blocks from the I / O data stream in a second memory region in a second namespace of the one or more memory devices. Responsive to a capacity of the accumulated blocks in the second memory region meeting a threshold criterion, the memory subsystem may migrate the accumulated plurality of blocks from the second memory region to the first memory region.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to a block staging component for a memory subsystem having a partitioned namespace. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a system is provided, and the system includes: one or more memory devices; a processing device operatively coupled to the one or more memory devices to perform the following operations: determining a block granularity for an input / output (I / O) data stream received from a host system; determining that the block granularity is different from a memory block granularity of a first memory region in a first namespace of the one or more memory devices, wherein the first memory region is to store the I / O data stream; accumulating a plurality of blocks from the I / O data stream in a second memory region in a second namespace of the one or more memory devices; and in response to a capacity of the accumulated blocks in the second memory region satisfying a threshold criterion, migrating the accumulated plurality of blocks from the second memory region to the first memory region.

[0004] According to an embodiment of the present disclosure, a method is provided, and the method includes the steps of: determining a block granularity for an input / output (I / O) data stream received from a host system; determining that the block granularity is different from a memory block granularity of a first memory region in one or more memory devices, wherein the first memory region is to store the I / O data stream; mapping the first memory region to a second memory region using one or more mapping entries from a mapping table; storing a plurality of blocks from the I / O data stream in the second memory region of the one or more memory devices; and in response to a capacity of the stored blocks in the second memory region satisfying a threshold criterion, migrating the stored blocks from the second memory region to the first memory region.

[0005] According to an embodiment of the present disclosure, there is provided a non - transitory computer - readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform the following operations: determining a block granularity for an input / output (I / O) data stream received from a host system; determining that the block granularity is different from a memory block granularity of a first memory region in a first namespace of the one or more memory devices, where the first memory region is to store the I / O data stream; accumulating a plurality of blocks from the I / O data stream in a second memory region in a second namespace of the one or more memory devices; and in response to a capacity of the accumulated blocks in the second memory region meeting a threshold criterion, migrating the accumulated plurality of blocks from the second memory region to the first memory region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure. However, the figures should not be regarded as limiting the present disclosure to specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 Illustrates an example computing system including a memory subsystem in accordance with some embodiments of the present disclosure.

[0008] Figure 2 Is a flowchart of an example method for performing block - staging for a memory subsystem with a partitioned namespace in accordance with some embodiments of the present disclosure.

[0009] Figure 3 Is a block diagram of a memory subsystem having a memory device with a partitioned namespace and a memory device with a conventional namespace in accordance with some embodiments of the present disclosure.

[0010] Figure 4 Is a block diagram of a memory subsystem having a memory device with both a partitioned namespace and a conventional namespace in accordance with some embodiments of the present disclosure.

[0011] Figure 5 Is a flowchart of block - staging in accordance with some embodiments of the present disclosure.

[0012] Figure 6 Illustrates block accumulation and migration in accordance with some embodiments of the present disclosure.

[0013] Figure 7 Illustrates an example mapping table for mapping data chunks to partitioned blocks in accordance with some embodiments of the present disclosure.

[0014] Figure 8 Is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to block staging for a memory subsystem having a partitioned namespace. The memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in conjunction with Figure 1 Typically, a host system can utilize a memory subsystem that includes one or more components such as memory devices that store data. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0016] The memory subsystem can include high-density non-volatile memory devices where data is desired to be retained when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described below in conjunction with Figure 1 A non-volatile memory device is an encapsulation of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits stored. The logical states can be represented as binary values such as “0” and “1”, or combinations of such values.

[0017] The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data, for example, on a memory device at the memory subsystem and to read data from a memory device on the memory subsystem. As specified by the host request, the data to be read or written can typically be performed via memory paging. Memory paging can be a memory management scheme used by a host system to store and retrieve data from a storage device (e.g., non-volatile memory) for use by a main memory (or volatile memory). A page or memory page is a fixed-length contiguous block of memory (or “block”) and is the smallest data unit managed by the memory subsystem. For example, some systems have a page size of 4 KB. Other systems can have a page size of 8 KB or other multiples of 4 KB.

[0018] Some memory devices are also configured with a zoned namespace (ZNS). In a zoned namespace, the address space of the memory device is divided into zones, which allows for more efficient management of data as the capacity of the memory device increases. However, host systems designed to work with conventional file systems may face certain challenges when interacting with memory devices having a zoned namespace. For example, a conventional file system may write data in blocks as small as 4 kilobytes (KB), while a zoned namespace memory device may have an optimal write size in the range of approximately 100 KB (e.g., 64 KB, 128 KB, 196 KB).

[0019] Accordingly, to enable use of a zoned namespace memory device with a conventional file system that does not support the zoned block size, some costly modifications may be required. For example, when writing 4 KB blocks to a memory device having a zoned namespace, the memory subsystem of the memory device may utilize a staging area to accumulate the blocks until the total size of the accumulated blocks equals or exceeds the zoned block size.

[0020] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that provides a zoned block staging area for a memory subsystem having a zoned namespace. In one embodiment, the memory subsystem determines a block granularity for an input / output (I / O) data stream received from a host system. The memory subsystem may determine that the granularity of the blocks is different from the granularity of the zoned blocks of a zoned memory region in the memory device of the memory subsystem, where the zoned memory region will store the I / O data stream. The memory subsystem may accumulate blocks from the I / O data stream in a conventional memory region in a memory device having a conventional namespace. In response to the capacity of the accumulated blocks in the conventional memory region reaching the size of a zoned block, the memory subsystem migrates the accumulated blocks from the conventional memory region to the zoned memory region. Advantages of the present disclosure include, but are not limited to, compatibility of a conventional file system with a memory device having a zoned namespace.

[0021] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated in accordance with some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0022] The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0024] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to a single memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0025] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0026] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory buses, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces that support Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. In general, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. A volatile memory device (e.g., the memory device 140) can be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., the memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells in the memory devices 130 may be grouped into pages, which may refer to logical units of the memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0030] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, the memory devices 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), nor flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (or simply the controller 115 for simplicity) may communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-wired) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 can include processing circuitry that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include a read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 Figure 1 is illustrated as including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 can be responsible for other operations such as wear-leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 can also include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 can also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0036] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device that is an original memory device 130 with control logic (e.g., the local controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a chunk staging component 113 that can perform operations for converting blocks of a first granularity into a chunk granularity staging area. For example, the chunk staging component 113 can accumulate blocks received from the host system in a staging area (conventional memory area) in the memory subsystem. When the blocks reach the chunk granularity, the chunk staging component 113 migrates the blocks to the partitioned memory area. In some embodiments, the memory subsystem controller 115 includes at least a portion of the chunk staging component 113. In some embodiments, the chunk staging component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the chunk staging component 113 and is configured to perform the functions described herein.

[0038] The chunk staging component 113 can accumulate blocks incoming from the host system in a staging area (conventional memory area) in the memory subsystem. When the accumulated blocks reach the chunk granularity, the chunk staging component 113 can migrate the blocks to the partitioned memory area. Other details regarding the operation of the chunk staging component 113 are described below.

[0039] Figure 2 is a flowchart of an example method 200 for performing chunk staging for a memory subsystem having a partitioned namespace in accordance with some embodiments of the present disclosure. The method 200 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1The block staging component 113 performs. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0040] At operation 210, the processing logic determines a block granularity for an input / output (I / O) data stream received from the host system 120.

[0041] In one embodiment, the host system may program data into the memory subsystem 110 at a granularity specified by an operating system running on the host system 120. In one embodiment, the processing logic may send a request to discover the page size to the operating system of the host system 120 at runtime. Based on the page size information, the processing logic may determine that the block granularity of the I / O stream from the host system is the same granularity as the page size of a particular I / O stream or subsequent I / O streams. In another embodiment, if the processing logic receives some blocks from the I / O stream and the blocks contain size information, the processing logic may parse the blocks for block size. For example, in some embodiments, a block may have a header segment and a data segment. The processing logic may obtain the size information of the block from the header segment as the block granularity.

[0042] At operation 220, the processing logic determines that the block granularity is different from a memory (partitioned) block granularity of a first (partitioned) memory region in a first (partitioned) namespace of one or more memory devices, where the first (partitioned) memory region is for storing the I / O data stream.

[0043] For example, under the condition that a block is to be programmed into a particular partition of a partitioned namespace (zns) memory device, the processing logic may access the configuration settings of the memory device configured with the partitioned namespace. The configuration settings may include a block size configuration for the partition. The processing logic may compare the partition block size with the I / O stream block granularity to determine that the block granularity is different from the partition block granularity.

[0044] At operation 230, the processing logic accumulates (or stores) multiple blocks of the I / O data stream from a second memory region in a second namespace of the one or more memory devices.

[0045] The processing logic can identify a memory address range (data chunk) in a regular namespace that is not in use, where the memory range has the same size as the partition block. In one embodiment, the memory address range can include a logical block address (LBA). The processing logic can map the data chunk to a partition by adding an entry to a mapping table that maps the data chunk to the partition via a partition identifier, where the I / O block is to be programmed to the partition. The processing logic can then receive blocks from the I / O stream and accumulate the blocks in the data chunk.

[0046] At operation 240, in response to the capacity of the accumulated blocks in the second memory region (data chunk) satisfying a threshold criterion (the capacity of the accumulated blocks is greater than or equal to the capacity of the partition block), the processing logic migrates the accumulated blocks from the second memory region (data chunk) to the first memory region (partition block).

[0047] Once the data in the data chunk is full, the processing logic migrates (copies) the data from the data chunk to the partition using the write pointer of the partition. Next, the processing logic reclaims the data chunk and makes the data chunk available for subsequent use. In one embodiment, the data written to the data chunk can be random writes, while the data written to the partition block in the partition has sequential writes.

[0048] Using the data chunk in the regular namespace as a staging area, the memory subsystem 110 including a zns memory device having a partition block granularity is compatible with a regular file system having a block granularity different from the partition block granularity.

[0049] Figure 3 is a block diagram illustrating a memory subsystem having a memory device with a partitioned namespace and a memory device with a regular namespace according to some embodiments of the present disclosure. In Figure 3 , the host system 120 can include one or more I / O streams 0 to 1. The I / O streams 0 to 1 can represent I / O accesses from a file system or a stand-alone application running on the host system 120. Based on the page size of the operating system running on the host system 120, the I / O streams 0 to 1 can have a specific block granularity.

[0050] In one embodiment, the chunk staging component 113 is configured to map I / O streams 0 to 1 from the host system 120 to partitions in one or more memory devices 130 having a partitioned namespace. For example, I / O stream 0 may be mapped to partition 0 in memory device 130-1, where memory device 130-1 is configured with a partitioned namespace. Since partition 0 has a data granularity of chunk size, and I / O stream 0 has a different data granularity, such as a granularity of 4KB page size (or other multiple of 4KB), a conventional memory region in memory device 130-2 having a conventional namespace may be used by the memory subsystem 110 as a staging area. The staging area supports a first (e.g., 4KB) block granularity for reading and / or writing from the host system 120 and a different chunk granularity (e.g., 64KB) for reading and / or writing from the memory device 130-1 having a partitioned namespace. In one embodiment, memory device 130-2 is configured with a conventional namespace, and a memory region (or data chunk 0) in memory device 130-2 is allocated as the staging area. When allocating a data chunk, the chunk staging component 113 adds an entry to a mapping table, such as Figure 7 table 700, to map the data chunk to a partition by memory address. Here, the partition is a memory region in the zns memory device of the memory subsystem 110, where the I / O stream blocks will be stored.

[0051] Figure 4 is a block diagram illustrating a memory subsystem having memory devices with both a partitioned namespace and a conventional namespace according to some embodiments of the present disclosure. In Figure 4 , the host system 120 may include one or more I / O streams 0 to 1. The I / O streams 0 to 1 may represent I / O accesses from a file system or a stand-alone application running on the host system 120. Based on the page size of the operating system running on the host system 120, the I / O streams 0 to 1 may have a specific block granularity.

[0052] In one embodiment, the block partitioned staging component 113 is configured to map I / O streams 0 to 1 from the host system 120 to partitions of a partitioned memory region in one or more memory devices 130. For example, the component 113 may map I / O stream 0 to partition 0 of the memory device 130-1. Since partition 0 has a data granularity of a block partition size (e.g., 64 KB), and I / O stream 0 has a different data granularity, e.g., a granularity of a 4 KB page size (or other multiple of 4 KB), a conventional memory region may be used by the memory subsystem 110 as a staging area. The staging area may support a first (e.g., 4 KB) block granularity from the host system 120 and a different block partition granularity (e.g., 64 KB) from the memory device 130-1. In one embodiment, a separate partition of the memory device 130-1 may be configured with a conventional namespace, and a memory region (or data chunk 0) in the memory device 130-1 is allocated as the staging area. When allocating a data chunk, the block partitioned staging component 113 may add an entry to a mapping table, such as Figure 7 Table 700, to map the data chunk to the partition that will store the I / O stream block by memory address. Here,[ Figure 4 the memory device 130-1 in may be divided into at least two partitions, where one partition is configured with a conventional namespace and the other partition is configured with a partitioned namespace, while in Figure 3 different memory devices (e.g., memory device 130-2) are configured with a conventional namespace.[

[0053] Figure 5 FIG. 500 is a flow chart illustrating block partitioned staging according to some embodiments of the present disclosure. Operations 501 to 511 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, operations 501 to 511 are performed by the Figure 1 block partitioned staging component 113. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Thus, the illustrated embodiments should only be understood as examples, and the illustrated process may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.[

[0054] At block 501, the processing logic detects an I / O access from the host system. The I / O access may be an I / O stream write to a storage region (e.g., memory device 130-1) having a partitioned namespace. The processing logic may allocate a partition to the I / O stream by a partition identifier.[

[0055] At block 503, the processing logic determines whether the sub-block size (data granularity for the partition) is equal to the I / O block size (data granularity for the input / output data transferred to the memory device 130-1). In one embodiment, the processing logic may query the memory controller for the configuration settings of the allocated partition to determine the data granularity (sub-block size) of the allocated partition. In one embodiment, the processing logic may query the operating system running on the host system 120 to determine the data granularity (block size) of the I / O stream. In one embodiment, the block size is the page size of the operating system running on the host system 120.

[0056] At block 505, if it is determined that the sub-block size is equal to the I / O block size, the processing logic programs the I / O block directly into the allocated partition using the write pointer of the allocated partition. Here, the partition is written sequentially.

[0057] At block 507, if it is determined that the sub-block size is different from the I / O block size, the processing logic prepares a staging area in which blocks from the I / O stream can be accumulated. For example, the processing logic may allocate one or more available conventional memory address ranges from the non-volatile memory with a conventional namespace. The processing logic may map the data chunk identifier to the one or more memory address ranges (by logical address numbering), and map the data chunk identifier to the allocated partition by the partition identifier, as Figure 7 shown in Table 700.

[0058] Once the mapping entry is added, the blocks for the incoming I / O stream can be programmed into the memory address range corresponding to the data chunk. Here, the processing logic programs the blocks for the I / O stream with the granularity of the conventional file system. In one embodiment, the blocks can be programmed into the data chunk with a granularity of 4KB. In one embodiment, the blocks can be programmed into the data chunk in random access.

[0059] At block 509, the processing logic determines whether the data chunk is full. In one embodiment, if the processing logic accesses a memory address outside the memory address range mapped to the data chunk, the data chunk is full.

[0060] At block 511, if the data chunk is full, the processing logic migrates (copies) the data from the data chunk to the partition at the write pointer of the partition. Here, the processing logic writes to the partition sequentially with the granularity of the sub-block size. In one embodiment, the sub-block has a granularity of 64KB, 128KB, or any other multiple of 4KB.

[0061] Once migrated, the processing logic reclaims the memory range associated with the data chunk and makes the memory range available for other uses. In one embodiment, reclaiming the memory range includes releasing the memory range for other uses. In one embodiment, reclaiming the memory range includes erasing the data in the memory range.

[0062] Figure 6 Illustrates block accumulation and migration according to some embodiments of the present disclosure. In Figure 6 this example, the block partition mapping table 700 may reside in a conventional memory area in the memory device 130-2, where the memory device 130-2 is configured with a conventional namespace.

[0063] In Figure 6 this example, the memory device 130-2 may include one or more data chunks 0 to 3 as a staging area for one or more I / O streams. In one embodiment, one or more incoming I / O streams may simultaneously accumulate blocks into one or more of the chunks 0 to 3. Once a chunk is full, the component 133 migrates the chunk to a partition in the memory device 130-1, where the partition is mapped to the chunk via a mapping table (e.g., the block partition mapping table 700). Although a conventional namespace is shown in the memory device 130-2, individual partitions of the memory device 130-1 may be configured with a conventional namespace and a partitioned namespace.

[0064] Figure 7 Illustrates an example of a mapping table for mapping data chunks to block partitions according to some embodiments of the present disclosure.

[0065] In one embodiment, the table 700 may include a mapping for logical block numbers, chunk identifiers, and partitions. The logical block numbers may indicate, via the chunk identifier, one or more logical blocks assigned to a particular chunk, where the chunk is mapped to a particular partition via the partition identifier. In one embodiment, the logical block numbers may be mapped to one or more memory address ranges via a logical block addressing scheme (LBA). The chunk identifier and the partition identifier may be identifiers used by the memory controller to access data chunks and / or partitions in one or more memory devices.

[0066] Figure 8 Illustrates an example machine of a computer system 600 within which a set of instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 the host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 the memory subsystem 110) or may be used to perform the operations of a controller (e.g., executing an operating system to perform operations corresponding to Figure 1(operation of the block-based caching component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0067] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of (or multiple sets of) instructions that specify actions to be taken by the machine, either sequentially or otherwise. Further, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0068] Example computer system 600 includes a processing device 602, a main memory 604 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0069] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, etc. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may also include a network interface device 608 to communicate over a network 620.

[0070] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution by the computer system 600, which main memory 604 and processing device 602 also constitute machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 the memory subsystem 110.

[0071] In one embodiment, the instructions 626 include instructions for implementing the functionality corresponding to a block staging component (such as Figure 1 the block staging component 113). Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0072] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0073] However, it should be borne in mind that all such and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers of the computer system or other such information storage systems.

[0074] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to the computer system bus.

[0075] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure of various of these systems will be presented as will be set forth in the description below. In addition, the present disclosure has not been described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0076] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that may be used to program a computer system (or other electronic devices) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0077] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory system, comprising: One or more memory devices; A processing device operatively coupled to the one or more memory devices to perform operations including: Determining a block granularity for an input / output (I / O) data stream received from a host system; Determining that the block granularity is different from a memory block granularity of a partitioned memory region in a partitioned namespace of the one or more memory devices, wherein the partitioned memory region will store the I / O data stream; Accumulating a plurality of blocks from the I / O data stream in a separate memory region in a separate namespace of the one or more memory devices, wherein the separate memory region is configured to write data at the block granularity of the I / O data stream, and wherein the block granularity of the I / O data stream is less than the memory block granularity of the partitioned memory region; Determining that a capacity of the accumulated blocks in the separate memory region is equal to or greater than the memory block granularity of the partitioned memory region; And In response to determining that the capacity of the accumulated blocks in the separate memory region is equal to or greater than the memory block granularity of the partitioned memory region, migrating the accumulated plurality of blocks from the separate memory region to the partitioned memory region.

2. The memory system according to claim 1, wherein the partitioned memory region is configured to accept sequential write operations, and the separate memory region is configured to accept random write operations.

3. The memory system according to claim 1, wherein the one or more memory devices include non-volatile memory devices, and wherein the partitioned memory region and the separate memory region are located in the non-volatile memory devices.

4. The memory system according to claim 1, wherein the processing device will perform operations further including: Recycling the separate memory region in response to migrating the accumulated blocks from the separate memory region to the partitioned memory region.

5. The memory system according to claim 1, wherein the processing device will perform operations further including: Mapping the partitioned memory region to the separate memory region using one or more mapping entries from a mapping table.

6. The memory system according to claim 5, wherein the mapping table is stored in the separate namespace in the one or more memory devices.

7. A method for a memory, comprising: Determining a block granularity for an input / output (I / O) data stream received from a host system; Determining that the block granularity is different from a memory block granularity of a partitioned memory region in a partitioned namespace of one or more memory devices, wherein the partitioned memory region will store the I / O data stream; Mapping the partitioned memory region to a separate memory region using one or more mapping entries from a mapping table; Store multiple blocks from the I / O data stream into the separate memory regions of the one or more memory devices, where the separate memory regions are configured to write data at the block granularity of the I / O data stream, and where the block granularity of the I / O data stream is less than the memory block granularity of the partitioned memory region; Determine that the capacity of the stored blocks in the separate memory region is equal to or greater than the memory block granularity of the partitioned memory region; And In response to determining that the capacity of the stored blocks in the separate memory region is equal to or greater than the memory block granularity of the partitioned memory region, migrate the stored blocks from the separate memory region to the partitioned memory region.

8. The method according to claim 7, wherein the partitioned memory region is configured to accept sequential write operations, and the separate memory region is configured to accept random write operations.

9. The method according to claim 7, wherein the one or more memory devices include non-volatile memory devices, and wherein the partitioned memory region and the separate memory region are located in the non-volatile memory devices.

10. The method according to claim 7, further comprising: In response to migrating the stored blocks from the separate memory region to the partitioned memory region, reclaim the separate memory region.

11. The method according to claim 7, wherein the separate memory region is in a separate namespace.

12. The method according to claim 11, wherein the mapping table is stored in the separate namespace in the one or more memory devices.

13. A non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: Determine the block granularity for an input / output (I / O) data stream received from a host system; Determine that the block granularity is different from the memory block granularity of a partitioned memory region in a partitioned namespace of one or more memory devices, where the partitioned memory region will store the I / O data stream; Accumulate multiple blocks from the I / O data stream in a separate memory region in a separate namespace of the one or more memory devices, where the separate memory region is configured to write data at the block granularity of the I / O data stream, and where the block granularity of the I / O data stream is less than the memory block granularity of the partitioned memory region; Determine that the capacity of the accumulated blocks in the separate memory region is equal to or greater than the memory block granularity of the partitioned memory region; And In response to determining that the capacity of the accumulated blocks in the separate memory region is equal to or greater than the memory block granularity of the partitioned memory region, migrate the accumulated multiple blocks from the separate memory region to the partitioned memory region.

14. The non-transitory computer-readable storage medium according to claim 13, wherein the partitioned memory region is configured to accept sequential write operations, and the separate memory region is configured to accept random write operations.

15. The non-transitory computer-readable storage medium according to claim 13, wherein the one or more memory devices include non-volatile memory devices, and wherein the partitioned memory area and the separate memory area are located in the non-volatile memory devices.

16. The non-transitory computer-readable storage medium according to claim 13, wherein the processing device will perform operations further including the following: Upon migrating the accumulated blocks from the separate memory area to the partitioned memory area, reclaim the separate memory area.

17. The non-transitory computer-readable storage medium according to claim 13, wherein the processing device will perform operations further including the following: Map the partitioned memory area to the separate memory area using one or more mapping entries from a mapping table.

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