System and method for remapping bad blocks in a memory subsystem

Abstract

The present disclosure relates to systems and methods for remapping bad blocks in a memory subsystem. A system is disclosed comprising: a memory device comprising a plurality of memory planes; and a processing device operatively coupled to the memory device to perform operations comprising: generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and in response to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a memory subsystem, and more particularly, to remapping bad blocks in a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of the present disclosure relates to a system comprising: a memory device comprising a plurality of memory planes; and a processing device operatively coupled with the plurality of memory devices to perform operations comprising: generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and in response to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

[0004] Another aspect of the present disclosure relates to a method that includes generating a block stripe of a memory device including a plurality of memory planes, wherein the block stripe includes a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and in response to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

[0005] Yet another aspect of the present disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: generating a block stripe for a memory device comprising a plurality of memory planes, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes, and wherein the memory device comprises a first portion configured as SLC memory and a second portion configured as QLC memory; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; in response to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe; and in response to performing the error recovery operation to replace the first block with the replacement block in the block stripe, performing a write operation to write first data from the block stripe in the first portion configured as SLC memory to the second portion configured as QLC memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2A A block diagram illustrating a memory subsystem that implements remapping of bad blocks in a memory device according to some embodiments of the present disclosure.

[0009] Figure 2B An example bad block replacement table according to some embodiments of the present disclosure is schematically illustrated.

[0010] Figure 3 A block diagram illustrating a set of blocks in a block stripe spanning a multi-plane memory device according to some embodiments of the present disclosure.

[0011] Figure 4 is a flow chart of an example method 400 for remapping bad blocks in a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 5 is a flow chart of an example method 500 for remapping bad blocks in a memory subsystem according to some embodiments of the present disclosure.

[0013] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure are directed to remapping bad blocks in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may include a high-density non-volatile memory device, where data retention is required when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a collection of physical blocks. Each block is composed of a collection of pages. Each page is composed of a collection of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits being stored. The logical state can be represented by a binary value (e.g., "0" and "1") or a combination of such values.

[0016] A die is also referred to below as a logical unit (LUN). A LUN may contain one or more planes. The memory subsystem may use a striping scheme to treat individual sets of data as units when performing data operations (e.g., write, read, erase). A LUN stripe is a collection of planes that are treated as a single unit when writing, reading, or erasing data. Each plane in a LUN stripe can perform the same operations as all other planes in the LUN stripe in parallel. A block stripe is a collection of blocks (one for each plane in the LUN stripe) that are treated as a unit. Blocks in a block stripe have the same block identifier (e.g., block number) in their respective planes.

[0017] The memory subsystem may include multiple memory devices that can store data from a host system. Each memory device may include a different type of media. Examples of media include, but are not limited to, cross-point arrays of non-volatile memory and flash-based memory, such as single-level cell (SLC) memory, triple-level cell (TLC) memory, and quad-level cell (QLC) memory. Different types of media may have different data densities. The data density corresponds to the amount of data (e.g., data bits) that can be stored per memory cell of the memory device. Using the example of flash-based memory, a quad-level cell (QLC) can store four data bits, while a single-level cell (SLC) can store one data bit. Therefore, a memory device including QLC memory cells will have a higher data density than a memory device including SLC memory cells.

[0018] Conventional memory subsystems include memory devices with bad blocks. A bad block is a block (i.e., a group of one or more memory cells in a memory device) that cannot reliably store data. For example, a bad block may refer to a block that meets an error condition described in further detail below. Due to non-uniformity and variations in the manufacturing process, conventional memory subsystems initially include a small percentage of bad blocks (hereinafter referred to as "factory error bad blocks"). In addition, as blocks wear out over the life of the memory subsystem and / or due to damage or defects in memory cells, good blocks (i.e., blocks that were not classified as bad blocks and initially reliably stored data) may become bad blocks (hereinafter referred to as "grown bad blocks"). For example, during an erase operation, data stored in one or more memory cells in a bad block may not be properly erased. Therefore, in conventional memory subsystems, bad blocks are not used to store data. Instead, conventional memory subsystems track bad blocks to avoid storing any data in the bad blocks. Therefore, as more blocks become unreliable and therefore unused for data storage, the memory capacity of a conventional memory subsystem may decrease.

[0019] Some memory subsystems implementing QLC memory use a standard 16-16 coarse-fine two-pass programming algorithm. Since a QLC memory cell stores four bits of data, there are 16 possible programming levels (i.e., 2 4), representing the possible values ​​for those four data bits. Programming the word lines begins by coarsely programming all 16 levels in a first pass. The goal of this "coarse" first pass is to quickly program all cells to just below their final target programming level. During a slower, "fine" second pass, the memory cells are programmed to a slightly higher final target programming voltage. This type of two-pass programming minimizes cell-to-cell (C2C) interference because each cell and its neighbors are almost at their final target programming voltage when the fine programming pass is performed and only require "slight modifications." The combination of not requiring precision programming in the first pass and minimized C2C coupling enables fast programming with a high read window budget (RWB). However, this type of standard 16-16 coarse-fine programming requires that all data be written to single-level cell (SLC) memory (i.e., memory cells storing one bit of data per cell) before the first pass to prevent asynchronous power loss (APL) from occurring and to limit buffer utilization and keep the data available for host reads.

[0020] The data can then be moved from the SLC memory to other memories, such as MLC memory, TLC memory, QLC memory, etc., via an on-chip copy-back operation (hereinafter referred to as a "copy-back operation"). The copy-back operation may involve, for example, moving data from the SLC memory to the QLC memory using a cache register. Thus, the data does not have to be written from the memory device first. However, the copy-back operation has the limitation that only data within the same plane can be moved between the SLC memory and the QLC memory. Therefore, if there are any bad blocks within the stripe that spread across different planes, the memory subsystem will not be able to use the copy-back operation to move data between the SLC memory and the QLC memory. Alternatively, the memory subsystem may employ an off-chip copy-back operation, a combination of an on-chip copy-back operation and an off-chip copy-back operation, or an on-chip copy-back operation, wherein if there are any bad blocks within those planes, the planes are filled with dummy data. However, in all of these options, performance and quality of service (QoS) are reduced due to higher latency.

[0021] For example, aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that remaps bad blocks in a block stripe of the memory subsystem in order to perform a copyback operation to move data between SLC memory and QLC memory. Specifically, aspects of the present disclosure can avoid having to use an off-chip copyback operation, a combination of an on-chip copyback operation and an off-chip copyback operation, or an on-chip copyback operation with padded dummy data to move data from SLC memory to QLC memory, as described above herein. This can be achieved by creating a block stripe that does not contain bad blocks, whose data can be moved from SLC memory to QLC memory. In some embodiments of the present disclosure, a bad block (factory error bad block or growth bad block) can be identified on a particular block stripe of a plane of a memory device. The address of the bad block can be stored in a data structure (e.g., a table). The bad block can then be replaced with a replacement block (e.g., a good block) residing on the same plane as the bad block. The replacement block is a block that is neither a factory error bad block nor a growth bad block. The address of the replacement block can be stored in a data structure (e.g., a table storing the addresses of the bad blocks). Thus, bad blocks can be identified and then replaced with replacement blocks, thus creating a block stripe that does not contain bad blocks.A copyback operation can then be performed so that data can be moved from the SLC memory to the QLC memory.

[0022] Advantages of the present disclosure include, but are not limited to, improved performance and QoS in copyback operations to move data from SLC memory to QLC memory. Because data no longer needs to be moved from SLC memory to QLC memory using an off-chip copyback operation, a combination of an on-chip copyback operation and an off-chip copyback operation, or an on-chip copyback operation with padded data, performance and QoS are improved due to reduced latency.

[0023] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0026] Computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0027] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0028] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket supporting Double Data Rate (DDR)), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to store bits based on changes in bulk resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages, which may refer to logical units of a memory device for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or, for simplicity, the controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processing device comprising one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Generally speaking, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is a raw memory device 130 with on-die control logic (e.g., local media controller 135) and a controller for media management (e.g., memory subsystem controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The memory subsystem 110 includes a memory interface component 113 that can handle the interaction between the memory subsystem controller 115 and the memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface component 113 can receive data from the memory device 130, such as data retrieved in response to a copyback operation or confirmation of a successfully performed copyback operation. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein.

[0040] In some embodiments, memory device 130 includes a programming manager 134 configured to perform a copyback operation. In some embodiments, local media controller 135 includes at least a portion of programming manager 134 and is configured to perform the functionality described herein. In some embodiments, programming manager 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, programming manager 134 receives a request from a requestor, such as memory interface component 113, to perform a copyback operation on a memory array of memory device 130. In one embodiment, the memory array may include a first portion configured as SLC memory and a second portion configured as QLC memory. In one embodiment, to enable the copyback operation, programming manager 134 may identify and replace bad blocks in the memory array using replacement blocks. Programming manager 134 may further map a bad block replacement table (e.g., Figure 2A and Figure 2B 134). The memory subsystem controller 115 includes at least a portion of the program manager 134. In some embodiments, the program manager 134 is part of the host system 120, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the program manager 134 and is configured to perform the functionality described herein. Additional details regarding the operation of the program manager 134 are described below.

[0041] Figure 2A A block diagram illustrating a memory subsystem for remapping bad blocks in a memory device according to some embodiments of the present disclosure. In one embodiment, the memory device 130 is operatively coupled to the memory device 130. In one embodiment, the memory device 130 includes a program manager 134, a bad block replacement table 256, and a memory array 250. The memory array 250 is Figure 3 372(0) through 372(3) are one example of a memory cell array of planes 372(0) through 372(3) illustrated in FIG. Memory array 250 may include an array of memory cells formed at the intersections of word lines and bit lines. In one embodiment, memory cells are grouped into blocks, and the blocks are further grouped into block stripes that span the planes, such as across Figure 3 3. In one embodiment, there may be a first portion 252 of the memory array 250 where the blocks are configured as SLC memory, and a second portion 254 of the memory array 250 where the blocks are configured as QLC memory. In other embodiments, the second portion 254 may include blocks configured differently, such as MLC memory, TLC memory, or some other type of memory.

[0042] In one embodiment, program manager 134 may identify one or more bad blocks in a block stripe by determining that one or more blocks in the block stripe are associated with an error condition, as described in more detail below. Program manager 134 may perform error recovery operations on the one or more bad blocks in the block stripe. The error recovery operations may include replacing the one or more bad blocks with replacement blocks in the block stripe, as described in more detail below.

[0043] In one embodiment, program manager 134 may move data from blocks in a block stripe configured as SLC memory to a block stripe configured as QLC memory. Program manager 134 may move data by performing a write operation to write data from the SLC block stripe to the QLC block stripe, as described in more detail below. Program manager 134 may move data in response to performing an error recovery operation to replace a bad block in the SLC block stripe with a replacement block, as described in more detail below.

[0044] Figure 2B Schematically illustrates an example bad block replacement table 256 according to some embodiments of the present disclosure. In one embodiment, when the program manager 134 performs an error recovery operation, as described above Figure 2A As described in greater detail in and below, programming manager 134 may identify a block offset address associated with a bad block. Programming manager 134 may store the block offset in an entry in a data structure (e.g., bad block replacement table 256). The block offset may be associated with the block stripe in which the bad block is located. In one embodiment, when programming manager 134 replaces a bad block with a replacement block, programming manager 134 may identify a replacement block offset address associated with the bad block. Programming manager 134 may store the replacement block offset as an entry in bad block replacement table 256. Programming manager 134 may associate the replacement block offset with the block stripe in which the replacement block is located. In one embodiment, the bad block and the replacement block may be located on block stripes in the same plane. In one embodiment, bad block replacement table 256 may be included in a memory device (e.g., Figure 1 On the memory device 130).

[0045] Figure 3A block diagram illustrating a set of blocks in a block stripe across a multi-plane memory device according to some embodiments of the present disclosure. Each plane in the multi-plane memory device may include one or more block stripes. A block stripe is a collection of blocks (one for each plane) that are processed as a single unit. The blocks in a block stripe have the same block identifier (e.g., block number) in their respective planes. A first portion of the plane may be configured as SLC memory, and a second portion of the plane may be configured as QLC memory. For example, block stripes 360 and 361 may be configured as SLC memory, and block stripes 362 and 363 may be configured as QLC memory. During a copyback operation, data may be moved from block stripe 360 ​​in SLC memory to block stripe 362 in QLC memory. Due to copyback operation limitations, only blocks within the same plane may be moved from SLC memory to QLC memory, for example, block 382A residing on plane 372(0) must be moved to block 382C residing on plane 372(0). Various aspects of the present disclosure create a perfect SLC block stripe (e.g., a block stripe that contains no bad blocks) so that a copyback operation can be performed without performing an off-chip copyback operation, a combination of an off-chip copyback and an on-chip copyback operation, or an on-chip copyback operation that uses dummy data to fill in the block stripe that contains bad blocks, as described in more detail above.

[0046] In one embodiment of the present disclosure, program manager 134 may identify a bad block located on a block stripe within a plane, for example, block 382A of block stripe 360 ​​within plane 372(0). Program manager 134 may also identify a replacement block located on a block stripe within the same plane as the identified bad block, for example, replacement block 382E of block stripe 364 within plane 372(0). The replacement block may be a block that is not associated with an error condition, i.e., a good block. In one embodiment of the present disclosure, program manager 134 may replace the identified bad block with the replacement block.

[0047] Figure 4 4 is a flow chart of an example method 400 for remapping bad blocks in a memory subsystem according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The processes are executed by the programming manager 134. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0048] At operation 405, processing logic generates a block stripe for a memory device (e.g., memory device 130) comprising multiple memory planes. The block stripe may be generated by identifying multiple blocks that span the memory planes and processing the blocks as a single unit. Each block may reside on a plane of the multiple memory planes. Generating the block stripe may further include scanning the block stripe of the memory device and determining whether each block of the block stripe is associated with a factory error. A factory error may be an error associated with a factory-level bad block, which is a block that has defects due to non-uniformity and variations in the manufacturing process. In one embodiment, if processing logic determines that a block of the block stripe is associated with a factory error, processing logic reclaims the block stripe containing the block associated with the factory error to a data structure, such as a table (hereinafter referred to as a "reclaimed block table"). In an illustrative example, reclaiming the block stripe may include determining a block offset corresponding to each block of the block stripe. The block offset may be a block address corresponding to each block of the block stripe. Processing logic may store the block offset for each block of the block stripe as an entry in the reclaimed block table. In one embodiment, processing logic generates another block stripe of the memory device by identifying additional blocks that span the memory plane and processing the blocks as a single unit. Processing logic then repeats the process of scanning the block stripe and determining whether each block of the block stripe is associated with a factory-level bad block. If none of the blocks in the block stripe are associated with a factory error, processing logic then assigns the block stripe to a pool of block stripes of the memory device. In one embodiment, operation 405 may occur during a low-level format of memory device 130. In one embodiment, the memory device includes a first portion configured as SLC memory and a second portion configured as QLC memory. In one embodiment, the block stripe is configured as SLC memory.

[0049] At operation 410, processing logic determines that a block of the block stripe is associated with an error condition. In one embodiment, determining that a block of the block stripe is associated with an error condition may include determining a failure of a memory access operation associated with the block. The memory access operation may be one of an erase operation, a program operation, or a read operation performed on the block. In one embodiment, the error condition may be an error associated with a poorly grown block, as described above.

[0050] At operation 415, processing logic performs an error recovery operation on the block stripe to replace the block of the block stripe with a replacement block in the block stripe in response to determining that the block is associated with an error condition. In one embodiment, performing the error recovery operation on the block stripe includes determining a block offset corresponding to the block associated with the error condition. The block offset may be a block address corresponding to the block. Processing logic may store the block offset as an entry in a data structure associated with the block stripe. The data structure may be, for example, Figure 2B. In one embodiment, performing an error recovery operation on a block stripe may further include identifying a replacement block from a pool of replacement blocks on a memory device. The replacement block may be a block that is not associated with an error condition, i.e., a good block. The replacement block may be associated with a plane in which the block associated with the error condition resides, e.g., the replacement block may be in the same plane as the first block associated with the error condition. Processing logic may replace a block of the block stripe associated with the error condition with a replacement block. For example, processing logic may replace block 382A associated with plane 372(0) with replacement block 382F associated with plane 372(0), e.g., Figure 3 The processing logic may store the second block offset corresponding to the replacement block in a data structure associated with the block stripe. The second block offset may be a block address corresponding to the replacement block. In one embodiment, the second block offset may be stored in Figure 2B In one embodiment, in response to performing an error recovery operation to replace a block with a replacement block in the block stripe, processing logic performs a write operation to write data from the block stripe in the first portion configured as SLC memory to the second portion configured as QLC memory. The write operation may be associated with a copyback operation. Because the bad block is replaced by a replacement block (e.g., a good block), the copyback operation may be used to successfully move data from the perfect SLC block stripe to the QLC block stripe.

[0051] Figure 5 Flowchart of an example method 500 for remapping bad blocks in a memory subsystem according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The processes are executed by the programming manager 134. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0052] At operation 505, processing logic generates a block stripe for a memory device (e.g., memory device 130) comprising multiple memory planes. The block stripe may be generated by identifying multiple blocks that span the memory planes and processing the blocks as a single unit. Each block may reside on a plane of the multiple memory planes. Generating the block stripe may further include scanning the block stripe of the memory device and determining whether each block of the block stripe is associated with a factory error. A factory error may be an error associated with a factory-level bad block, which is a block that has defects due to non-uniformity and variations in the manufacturing process. In one embodiment, if processing logic determines that a block of the block stripe is associated with a factory error, processing logic reclaims the block stripe containing the blocks associated with the factory error to a data structure, such as a table (hereinafter referred to as a "reclaimed block table"). In an illustrative example, reclaiming the block stripe may include determining a block offset corresponding to each block of the block stripe. The block offset may be a block address corresponding to each block of the block stripe. Processing logic may store the block offset for each block of the block stripe as an entry in the reclaimed block table. In one embodiment, processing logic generates another block stripe of the memory device by identifying additional blocks that span the memory plane and processing the blocks as a single unit. Processing logic then repeats the process of scanning the block stripe and determining whether each block of the block stripe is associated with a factory-level bad block. If none of the blocks in the block stripe are associated with a factory error, processing logic then assigns the block stripe to a pool of block stripes of the memory device. In one embodiment, operation 505 may occur during a low-level format of memory device 130. In one embodiment, the memory device includes a first portion configured as SLC memory and a second portion configured as QLC memory. In one embodiment, the block stripe is configured as SLC memory.

[0053] At operation 510, processing logic determines a failure of a memory access operation associated with a block of a block stripe. The memory access operation may be one of an erase operation, a program operation, or a read operation performed on the block.

[0054] At operation 515, processing logic determines a block offset corresponding to the block. The block offset may be a block address corresponding to the block.

[0055] At operation 520, processing logic stores the block offset corresponding to the block in a data structure associated with the block stripe. The data structure may be, for example, Figure 2B Bad block replacement table 256.

[0056] At operation 525, processing logic identifies a replacement block from the pool of replacement blocks. The replacement block may be a block that is not associated with an error condition, i.e., a good block. The replacement block may be associated with a plane in which the block associated with the error condition resides, for example, the replacement block may be in the same plane as the block associated with the error condition.

[0057] At operation 530, processing logic replaces the blocks of the block stripe with the identified replacement blocks in the block stripe by remapping the bad blocks with the identified replacement blocks. For example, processing logic may replace block 382A associated with plane 372(0) with replacement block 382F associated with plane 372(0), as shown in FIG. Figure 3 As described in .

[0058] At operation 535, processing logic stores the second block offset corresponding to the replacement block in a data structure associated with the block stripe. The second block offset may be a block address corresponding to the replacement block. In one embodiment, the second block offset may be stored in Figure 2B In one embodiment, in response to performing an error recovery operation to replace a block with a replacement block in the block stripe, processing logic performs a write operation to write data from the block stripe in the first portion configured as SLC memory to the second portion configured as QLC memory. The write operation may be associated with a copyback operation. Because the bad block is replaced by a replacement block (e.g., a good block), the copyback operation may be used to successfully move data from the perfect SLC block stripe to the QLC block stripe.

[0059] Figure 6 An example machine illustrating a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 corresponds to a host system (e.g., Figure 1 host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform operations of the controller (for example, execute an operating system to execute corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0060] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be performed by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform one or more of the methodologies discussed herein.

[0061] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0062] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating via a network 620.

[0063] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, with the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0064] In one embodiment, instructions 626 include implementing instructions corresponding to a programming manager component (e.g., Figure 1 The program manager 134 of the present invention may be a program manager that provides functional instructions for the program manager 134. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0065] Some portions of the previously described details have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are a means for those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations that leads to a desired result. The operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, primarily for general reasons, to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0066] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0067] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card, or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0068] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure described herein may be implemented using a variety of programming languages.

[0069] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0070] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a memory device comprising a plurality of memory planes; and a processing device operatively coupled to the plurality of memory planes, wherein the processing device is configured to: generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and In response to determining that the first block of the plurality of blocks of the stripe of blocks is associated with the error condition, an error recovery operation is performed on the plurality of blocks to replace the first block with a replacement block in the stripe of blocks.

2. The system of claim 1 , wherein to generate the block stripes of the memory device, the processing device is further configured to: scanning the block stripe of the memory device; In response to determining that the first block of the plurality of blocks of the block stripe is associated with a factory error, skipping the block stripe; and The block stripe is allocated to a pool of block stripes of the memory device.

3. The system of claim 1 , wherein to determine that the first block of the plurality of blocks of the block stripe is associated with the error condition, the processing device is further configured to: A failure of a memory access operation associated with the first block is determined, wherein the memory access operation includes one of an erase operation, a program operation, or a read operation.

4. The system of claim 1 , wherein to perform the error recovery operation on the plurality of blocks of the block stripe, the processing device is further configured to: determining a first block offset corresponding to the first block associated with the error condition; and The first block offset is stored in a data structure associated with the block stripe.

5. The system of claim 1 , wherein to perform the error recovery operation on the plurality of blocks of the block stripe, the processing device is further configured to: identifying the replacement block from a pool of replacement blocks on the memory device, wherein the replacement block is associated with the first plane of the plurality of planes; replacing the first block of the plurality of blocks of the block stripe that is associated with the error condition with the replacement block in the block stripe, wherein the replacement block is not associated with an error condition; and A second block offset corresponding to the replacement block is stored in a data structure associated with the block stripe.

6. The system of claim 1 , wherein the memory device comprises a first portion configured as SLC memory and a second portion configured as QLC memory, and wherein the processing device is further configured to: In response to performing the error recovery operation to replace the first block with the replacement block in the stripe of blocks, performing a write operation to write first data from the stripe of blocks in the first portion configured as SLC memory to the second portion configured as QLC memory. 7 . The system of claim 1 , wherein the block stripe is configured as a single-level cell (SLC) memory.

8. A method comprising: generating a block stripe of a memory device comprising a plurality of memory planes, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and In response to determining that the first block of the plurality of blocks of the stripe of blocks is associated with the error condition, an error recovery operation is performed on the plurality of blocks to replace the first block with a replacement block in the stripe of blocks.

9. The method of claim 8, wherein generating the block stripe of the memory device comprises: scanning the block stripe of the memory device; In response to determining that the block stripe of the plurality of blocks of the block stripe is associated with a factory error, skipping the block stripe; and The block stripe is allocated to a pool of block stripes of the memory device.

10. The method of claim 8, wherein determining that the first block of the plurality of blocks of the block stripe is associated with the error condition comprises: A failure of a memory access operation associated with the first block is determined, wherein the memory access operation includes one of an erase operation, a program operation, or a read operation.

11. The method of claim 8, wherein performing the error recovery operation on the plurality of blocks of the block stripe comprises: determining a first block offset corresponding to the first block associated with the error condition; and The first block offset is stored in a data structure associated with the block stripe.

12. The method of claim 8, wherein performing the error recovery operation on the plurality of blocks of the block stripe further comprises: identifying the replacement block from a pool of replacement blocks on the memory device, wherein the replacement block is associated with the first plane of the plurality of planes; replacing the first block of the plurality of blocks of the block stripe that is associated with the error condition with the replacement block in the block stripe, wherein the replacement block is not associated with an error condition; and A second block offset corresponding to the replacement block is stored in a data structure associated with the block stripe.

13. The method of claim 8, wherein the memory device comprises a first portion configured as SLC memory and a second portion configured as QLC memory, and wherein a processing device is to perform operations further comprising: In response to performing the error recovery operation to replace the first block with the replacement block in the stripe of blocks, performing a write operation to write first data from the stripe of blocks in the first portion configured as SLC memory to the second portion configured as QLC memory. The method of claim 8 , wherein the block stripe is configured as a single-level cell (SLC) memory.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: generating a block stripe of a memory device comprising a plurality of memory planes, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes, and wherein the memory device comprises a first portion configured as SLC memory and a second portion configured as QLC memory; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; in response to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe; as well as In response to performing the error recovery operation to replace the first block with the replacement block in the stripe of blocks, performing a write operation to write first data from the stripe of blocks in the first portion configured as SLC memory to the second portion configured as QLC memory.

16. The non-transitory computer-readable storage medium of claim 15, wherein generating the block stripe of the memory device comprises: scanning the block stripe of the memory device; In response to determining that the block stripe of the plurality of blocks of the block stripe is associated with a factory error, skipping the block stripe; and The block stripe is allocated to a pool of block stripes of the memory device.

17. The non-transitory computer-readable storage medium of claim 15, wherein determining that the first block of the plurality of blocks of the block stripe is associated with the error condition comprises: A failure of a memory access operation associated with the first block is determined, wherein the memory access operation includes one of an erase operation, a program operation, or a read operation.

18. The non-transitory computer-readable storage medium of claim 15, wherein performing the error recovery operation on the plurality of blocks of the block stripe comprises: determining a first block offset corresponding to the first block associated with the error condition; and The first block offset is stored in a data structure associated with the block stripe.

19. The non-transitory computer-readable storage medium of claim 15, wherein performing the error recovery operation on the plurality of blocks of the block stripe further comprises: identifying the replacement block from a pool of replacement blocks on the memory device, wherein the replacement block is associated with the first plane of the plurality of planes; replacing the first block of the plurality of blocks of the block stripe that is associated with the error condition with the replacement block in the block stripe, wherein the replacement block is not associated with an error condition; and A second block offset corresponding to the replacement block is stored in a data structure associated with the block stripe.

20. The non-transitory computer-readable storage medium of claim 15, wherein the block stripe is configured as a single-level cell (SLC) memory.

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