A data acquisition method, device, and computer-readable storage medium

Abstract

The application discloses a data collection method, device and computer readable storage medium, wherein the method comprises: when a data collection condition is met, a processor calls a first core of the processor to send a data collection instruction to a second core of the processor, the data collection instruction sent by the first core comprises breakpoint information obtained by the first core, the breakpoint information can be understood as breakpoint information corresponding to a page fault interrupt, the second core is further called to respond to the data collection instruction, to obtain the breakpoint information and a counting value of a processor event counter, and the second core is called to take the breakpoint information and the counting value obtained by the second core as performance index data of a target application program. Through the method, the accuracy and the universality of data collection in a big data scene can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data acquisition method, apparatus, and computer-readable storage medium. Background Technology

[0002] When technicians want to analyze the performance of an application, they need to collect runtime data during the application's operation. This runtime data can accurately reflect the performance of an application, and developers can adjust the application's performance metrics based on the runtime data to achieve a better application performance.

[0003] Currently, methods for collecting application runtime data can be broadly categorized into two types. One type obtains runtime data by translating intermediate variable information from various registers during application execution. For example, the Pin tool on the Intel x86 platform can perform binary translation of applications, obtaining information on various intermediate register variables during program execution, including memory access addresses. This method supports x86-related instruction sets such as IA-32, i386, and x86-64. The other type obtains runtime data directly by dynamically translating application execution procedure information. For example, DynamoRIO collects and analyzes execution process information by dynamically translating the current program. This method supports three instruction sets: AArch32, IA-32, and x86-64. Both of these methods have two drawbacks. First, they are strongly bound to instruction sets, resulting in poor versatility; for example, neither of these methods supports the RISC-V architecture. Second, obtaining runtime data through dynamic translation introduces other instructions during execution, leading to inaccurate runtime data.

[0004] Therefore, improving the universality and accuracy of data collection has become an urgent technical issue. Summary of the Invention

[0005] This application provides a data acquisition method, apparatus, and computer-readable storage medium, which can improve the accuracy and versatility of data acquisition.

[0006] One embodiment of this application discloses a data acquisition method, the method comprising:

[0007] When the data acquisition conditions are met, the first core of the processor sends a data acquisition instruction to the second core of the processor. The data acquisition conditions include a page fault interrupt occurring in the memory access of the target application running on the first core, and the first core is in intercept mode. The data acquisition instruction includes the breakpoint information of the page fault interrupt.

[0008] The second core is invoked to respond to the data acquisition instruction and obtain the breakpoint information and the count value of the processor event counter;

[0009] The second core is invoked to use the breakpoint information and the count value as performance metric data for the target application.

[0010] One embodiment of this application discloses a data acquisition device, which includes:

[0011] The sending unit is used to call the first core of the processor to send a data acquisition instruction to the second core of the processor when the data acquisition conditions are met. The data acquisition conditions include a page fault interrupt occurring in the memory access of the target application running on the first core, and the first core is in intercept mode. The data acquisition instruction includes the breakpoint information of the page fault interrupt.

[0012] The acquisition unit is used to call the second core to respond to the data acquisition instruction and acquire the breakpoint information and the count value of the processor event counter;

[0013] The acquisition unit is also used to call the second core to use the breakpoint information and the count value as performance indicator data of the target application.

[0014] One embodiment of this application discloses a computer device, which includes:

[0015] A processor adapted to implement one or more computer programs; and a computer storage medium storing one or more computer programs adapted to be loaded and executed by the processor for the data acquisition method described above.

[0016] One aspect of this application discloses a computer-readable storage medium storing one or more computer programs adapted to be loaded by a processor and executed by the data acquisition method described above.

[0017] One embodiment of this application discloses a computer program product, which includes a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the aforementioned data acquisition method.

[0018] In this embodiment, when the data acquisition conditions are met, the first core of the processor sends a data acquisition instruction to the second core of the processor. The sent data acquisition instruction includes the first core acquiring breakpoint information, which can be understood as the breakpoint information corresponding to a page fault. Then, the second core responds to the data acquisition instruction, acquires the breakpoint information and the count value of the processor event counter, and uses the acquired breakpoint information and count value as performance indicator data for the target application. This method uses the second core to acquire the count value of the processor event counter of the target application running on the first core. Since no extra instructions are introduced into the target application, the accuracy of data acquisition can be improved, ensuring more accurate performance indicator data for the target application, which is more conducive to developers optimizing the target application. Simultaneously, since this application acquires data through other cores in the processor that are not running the target application, there is no strong binding between the program and the instruction set, thus improving the versatility of data acquisition. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the processor architecture of the computer device disclosed in the embodiments of this application;

[0021] Figure 2 This is a flowchart illustrating a data acquisition method disclosed in an embodiment of this application;

[0022] Figure 3 This is a flowchart illustrating another data acquisition method disclosed in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of a memory access method disclosed in an embodiment of this application;

[0024] Figure 5 This is a flowchart illustrating another data acquisition method disclosed in the embodiments of this application;

[0025] Figure 6 This is a schematic diagram of another memory access method disclosed in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the structure of a data acquisition device disclosed in an embodiment of this application;

[0027] Figure 8This is a schematic diagram of the structure of a computer device disclosed in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The data acquisition method provided in this application also involves cloud technology and big data technology within cloud technology. Specifically, cloud technology refers to a hosting technology that unifies hardware, software, network, and other resources within a wide area network (WAN) or local area network (LAN) to achieve data computation, storage, processing, and sharing. Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, and application technology applied based on the cloud computing business model. It can form resource pools, be used on demand, and is flexible and convenient. Cloud computing technology will become an important support. The backend services of technical network systems require a large amount of computing and storage resources, such as video websites, image websites, and many portal websites. With the rapid development and application of the internet industry, every item may have its own identification mark in the future, all of which need to be transmitted to the backend system for logical processing. Data of different levels will be processed separately, and various industry data will all require strong system support, which can only be achieved through cloud computing.

[0030] Big data refers to data sets that cannot be captured, managed, and processed within a certain timeframe using conventional software tools. It represents massive, rapidly growing, and diverse information assets that require new processing models to achieve stronger decision-making, insightful discovery, and process optimization capabilities. With the advent of the cloud era, big data has attracted increasing attention. Big data requires specialized technologies to effectively process large amounts of data within a tolerable timeframe. Technologies suitable for big data include massively parallel processing databases, data mining, distributed file systems, distributed databases, cloud computing platforms, the internet, and scalable storage systems.

[0031] Please see Figure 1 , Figure 1 This is a schematic diagram of the processor architecture of a computer device according to an embodiment of this application, such as... Figure 1As shown, the processor 100 of the computer device is a multi-core processor, which may include at least two cores: a first core 110 and a second core 120. The first core 110 runs a target application 111 and a kernel-mode state thread 112, while the second core 120 runs a data acquisition program 121 and an internal processing thread 122.

[0032] In one possible implementation, the computer device may be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, smart vehicle, etc., but is not limited to these; the computer device may also be a server, which may be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms.

[0033] Based on the processor architecture, the data acquisition method of this application embodiment is briefly summarized, mainly including: when the data acquisition conditions are met, the processor 100 calls the kernel-mode state thread 112 running on the first core 110 of the processor to send a data acquisition instruction to the kernel-mode processing thread 122 running on the second core 120 of the processor. The sent data acquisition instruction includes breakpoint information obtained by the kernel-mode state thread 112 running on the first core 110. The breakpoint information can be understood as the breakpoint information corresponding to the page fault. Then, the data acquisition program 121 running on the second core 120 responds to the data acquisition instruction, obtains the breakpoint information and the count value of the processor event counter, and uses the obtained breakpoint information and count value as the performance index data of the target application 111. In this application embodiment, by using the second core 120 to collect the count value of the processor event counter of the target application 111 running on the first core 110, since no extra instructions are introduced into the target application, the accuracy of data acquisition can be improved, ensuring that the obtained performance index data of the target application is more accurate, which is more conducive to the developers to optimize the target application. Meanwhile, since this application collects data through other cores in the processor that are not running the target application, there is no strong binding between the program and the instructions, thus improving the versatility of data collection.

[0034] In some feasible embodiments, the aforementioned computer equipment can be deployed in a blockchain network as a node. Simultaneously, relevant data from these embodiments, such as page fault breakpoint information, processor event counter values, and other performance metrics, as well as data acquisition time and core identifiers of the acquired data, can all be stored on the blockchain.

[0035] Based on the above description of the processor architecture of computer devices, this application discloses a data acquisition method. Please refer to [link to relevant documentation]. Figure 2 This is a flowchart illustrating a data acquisition method disclosed in an embodiment of this application. This data acquisition method can be executed by a computer device, specifically by a processor within the computer device, which has a first core and a second core deployed on it. The data acquisition method may specifically include steps S201 to S203:

[0036] S201. When the data acquisition conditions are met, the first core of the processor sends a data acquisition instruction to the second core of the processor. The data acquisition instruction includes breakpoint information.

[0037] The data collection conditions include a page fault occurring during memory access by the target application running on the first core, and the first core operating in intercept mode. Intercept mode indicates that data collection is necessary; in intercept mode, the target application's access to virtual memory addresses is unsuccessful. The first core runs both the target application and kernel-mode state threads. The collected performance metrics data corresponds to the runtime data of the target application, primarily to allow developers to analyze the performance of the target application running on the first core and optimize its performance. When the target application cannot access memory successfully, the kernel-mode state threads act as internal workers, performing tasks related to the failed access, such as sending and receiving data, establishing the mapping between virtual memory addresses and physical memory pages, etc. In essence, the results of the target application's execution are visible to the user, while the results of the kernel-mode state threads' execution are invisible, acting as a black box.

[0038] In one possible implementation, if the processor determines that the current acquisition conditions are met, it invokes a kernel-mode state thread running on the first core to obtain the breakpoint information of the page fault. This breakpoint information can be stored in the processor's memory space, or in some feasible implementations, it can be stored in a blockchain node, or it can be stored in a cloud server. The breakpoint information may include the target application's current memory access instructions, the target virtual memory address, and the call stack. For example, the target application's current memory access instruction may be "access A1", the target virtual address may be "A1", and the call stack may include the called functions, etc. Further, the processor invokes the kernel-mode state thread to generate a data acquisition instruction based on the breakpoint information and then invokes the kernel-mode state thread to send the data acquisition instruction to the second core.

[0039] It is important to note that the page fault in this embodiment refers to a soft interrupt, meaning that the data is already in the physical memory page, but the mapping between the virtual memory address and the physical memory page has not been established. Typically, a page fault is an interrupt issued by the CPU's memory management unit when software (an application, such as an app) attempts to access data that is mapped in the virtual address space, but the logical mapping does not exist. Page faults are generally categorized as soft or hard interrupts based on whether the data is in physical memory.

[0040] S202, Invoke the second core response data acquisition instruction to obtain breakpoint information and the count value of the processor event counter.

[0041] The second core runs a kernel-mode processing thread and a data acquisition program. This second core is a new core introduced to implement data acquisition during the application request. The data acquisition program is mainly used to collect performance metrics data, while the kernel-mode processing thread is mainly used for sending and receiving data, and establishing the mapping relationship between the target virtual memory address and the target physical memory page. By using the second core to collect performance metrics data of the target application running on the first core, and because no other instructions are introduced on the first core, the collected performance metrics data can be guaranteed to be more accurate.

[0042] In one possible implementation, after the second core receives the data acquisition instruction sent by the first core, the processor calls a kernel-mode processing thread to obtain the breakpoint information included in the data acquisition instruction. This can be done by directly reading the information or by parsing the data acquisition instruction to obtain the breakpoint information. The kernel-mode processing thread then sends the obtained breakpoint information and the data acquisition instruction to the data acquisition program, which stores the breakpoint information. Simultaneously, the data acquisition program retrieves the count value of the processor event counter based on the data acquisition instruction and stores this count value as well. The processor event counter is the same as the processor event counter corresponding to the first core, thus ensuring the accuracy of the count value obtained for the target application.

[0043] In this application embodiment, the processor event counter can be understood as a CPU event counter (Performance Monitoring Unit, PMU counter), which is generally used for performance analysis. Typical performance data collection observes the cumulative value of the PMU counter over a certain time period (seconds). However, this application does not collect data in units of time, but rather in decomposed collection. Specifically, it observes the difference in PMU counter values ​​before and after the execution of a certain number of instructions, statistically analyzes subtle processes, and then analyzes the performance of the application.

[0044] S203, Call the second core to use the breakpoint information and count value as performance indicator data of the target application.

[0045] In one possible implementation, after the processor calls the second core to obtain breakpoint information and count values, it then calls the second core to save the breakpoint information and count values, using them as performance metrics data for the target application. The location where the second core stores the breakpoint information and count values ​​can be the processor's memory, a blockchain, or a cloud server. This stored performance metrics data is then made available to developers for review and optimization of the target application when needed.

[0046] In this embodiment, when the data acquisition conditions are met, the processor calls the first core to send a data acquisition instruction to the second core. The sent instruction includes the first core acquiring breakpoint information, which can be understood as the breakpoint information corresponding to a page fault. The second core then responds to the data acquisition instruction, acquiring the breakpoint information and the processor event counter value. The second core then uses the acquired breakpoint information and the count value as performance metrics data for the target application. This method uses the second core to acquire the processor event counter value of the target application running on the first core. Since no extra instructions are introduced into the target application, the accuracy of data acquisition is improved, ensuring more precise performance metrics data for the target application, which is more conducive to developers optimizing the target application. Furthermore, since this application acquires data through other cores that are not running the target application, there is no strong binding between the program and instructions. Therefore, the versatility of data acquisition is improved, making it a general data acquisition method that can be used in general-purpose processor environments.

[0047] Based on the above description of the processor architecture and data acquisition method of the computer device, this application discloses another data acquisition method. Please refer to [link to relevant documentation]. Figure 3 This is a flowchart illustrating another data acquisition method disclosed in an embodiment of this application. This data acquisition method can be executed by a computer device, specifically by the processor of the computer device. Specifically, it describes the steps of the processor acquiring data when the data acquisition conditions are met, and the related steps of re-establishing the target virtual address and target physical memory page after data acquisition, which may include steps S301 to S310:

[0048] S301. Obtain the memory access instructions of the target application, including the target virtual memory address.

[0049] Here, the memory access instruction is equivalent to the current memory access instruction of the target application. The memory access instruction can be understood as the "access A1" described above. The memory access instruction includes the target virtual memory address, namely "A1".

[0050] In one possible implementation, since the target application is only responsible for accessing the memory, it cannot technically perceive whether the access was successful. It only judges success or failure based on the final result. For example, if the access fails, the corresponding page is not displayed on the terminal interface; if the access is successful, the corresponding page is displayed on the terminal interface. Whether the access was successful is determined by the processor itself. When the processor determines that the target application's access was unsuccessful, it obtains the memory access instruction corresponding to the target application. This memory access instruction includes the target virtual memory address, which is actively sent by the processor to the kernel-mode thread running on the first core when it detects that it cannot access the physical memory page. For details on how the processor perceives whether the access was successful, please refer to step S302.

[0051] S302. Query the mapping relationship corresponding to the target virtual memory address from the memory page table. If there is no mapping relationship corresponding to the target virtual memory address in the memory page table, it is determined that a page fault has occurred during memory access.

[0052] In one possible implementation, at a certain moment, after the processor obtains the memory access address of the target application, it simultaneously queries the memory page table to check the mapping relationship between the target virtual memory address included in the memory access address; that is, it checks whether a mapping relationship exists between the target virtual memory address and the target physical memory page in the memory page table. Since this application addresses soft page faults, data already exists in the physical memory page. Therefore, it only needs to check whether a mapping relationship exists in the memory page table. If no mapping relationship exists for the target virtual memory address in the memory page table, the processor can determine that a page fault has occurred in the target application's memory access. Correspondingly, the corresponding page will not appear on the terminal interface.

[0053] S303. Call the first core to obtain the indicator of the working mode of the first core. If the indicator is a preset first value, then determine that the working mode of the first core is the interception mode.

[0054] In this embodiment, there are two acquisition conditions: one is a page fault, as described in step S302, and the other is that the first core working mode is the interception mode. Therefore, a detailed explanation is provided in step S303. If only the page fault condition is met, but the interception mode is not, the corresponding processing flow can be found in [reference needed]. Figure 5 as well as Figure 6 This will not be elaborated on here.

[0055] In one possible implementation, the processor determines the operating mode based on an indicator of the first core's operating mode. Specifically, when a page fault is detected in the target application, the processor further calls the kernel-mode state thread running on the first core to obtain the indicator of the first core's operating mode. Typically, this indicator is stored in memory and includes both the kernel-mode state thread identifier and the indicator itself. If the indicator reads a preset first value, the processor can determine that the first core's operating mode is interception mode. In this embodiment, the preset first value can be 1, meaning 1 indicates interception mode.

[0056] In another possible implementation, the specific steps for determining that the first core is in intercept mode are as follows: The processor calls the kernel-mode state thread running on the first core to obtain the count value of the processor event counter. When the increase in the count value reaches a preset first threshold, it is equivalent to meeting the condition for mode switching. At this time, the processor can call the kernel-mode state thread running on the first core to adjust the indicator of the first core's working mode to a preset first value, which, as mentioned above, means adjusting the indicator to 1, thereby switching the first core's working mode to intercept mode. The count value records the number of memory access instructions. For example, assuming the preset first threshold is 100,000, and at a certain moment the obtained processor event counter count value is 300,000, then as the number of instructions increases, when it increases by 100,000, the mode switching condition is met, and the indicator is adjusted accordingly.

[0057] When both the page fault in step S302 and the interception mode in step S303 are satisfied, it can be determined that the acquisition conditions are met.

[0058] S304. Call the first core to delete the mapping relationship between virtual memory addresses and physical memory pages included in the memory page table.

[0059] In one possible implementation, to ensure that the acquisition conditions are not disturbed, the processor calls the kernel-mode state thread running on the first core to delete the mapping relationship between virtual memory addresses and physical memory pages in the memory page table. This ensures that page faults are always present; once all mapping relationships in the memory page table are deleted, even if the user switches to other memory access instructions, successful access will not be possible. Although the mapping relationship in the memory page table is deleted, it still exists in the data structure or in the processor's memory space, allowing for subsequent restoration of the mapping relationship in the memory page table.

[0060] S305: Invoke the first core of the processor to send a data acquisition instruction to the second core of the processor.

[0061] Optionally, step S304 can also be executed after step S305. If it is executed after step S305, the processor can call the kernel-mode processing thread running on the second core to delete the mapping relationship between virtual memory addresses and physical memory pages included in the memory page table. The execution order of the steps is not limited here.

[0062] S306. Call the second core response data acquisition instruction to obtain breakpoint information and the count value of the processor event counter.

[0063] Among them, steps S305 to S306 have already been completed. Figure 2 The relevant embodiments shown have been described in detail, and will not be repeated here.

[0064] In one possible implementation, when the processor calls the second core to respond to the data acquisition instruction and obtains the count value of the processor event counter, it also needs to determine when to end the acquisition. In this embodiment, this can also be determined by statistically analyzing the count value of the processor event counter. Specifically, when switching to intercept mode, when the processor calls the data acquisition program running on the second core to obtain the count value of the processor event counter, the processor calls the kernel-mode state thread running on the first core to obtain the count value of the processor event counter. When the increase in the count value reaches a preset second threshold, the acquisition is determined to end. At the same time, the kernel-mode state thread running on the first core is called to adjust the indicator of the first core's working mode to a preset second value to switch the first core's working mode to non-intercept mode. In this embodiment, the preset first value can be 1, and the preset second value can be set to 0 or other values, as long as they do not conflict with 1.

[0065] Furthermore, when the first core switches to non-intercept mode, which essentially exits the data acquisition process, the processor calls the kernel-mode state thread running on the first core to retrieve all mappings between virtual memory addresses and physical memory pages from the processor's memory space and adds these mappings to the memory page table for subsequent access by the target application. Optionally, the processor can also call the kernel-mode processing thread running on the second core to retrieve all mappings between virtual memory addresses and physical memory pages from the processor's memory space and add these mappings to the memory page table.

[0066] S307: Call the second core to use breakpoint information and count values ​​as performance metrics data for the target application.

[0067] Among them, step S307 has already been completed. Figure 2 The relevant embodiments shown have been described in detail, and will not be repeated here.

[0068] S308: Call the second core to establish the mapping relationship between the target virtual address and the target physical memory page.

[0069] In one possible implementation, after the processor obtains the target application's performance metrics data by calling the second core, it can also call the kernel-mode processing thread running on the second core to establish a mapping relationship between the target virtual address and the target physical memory page. In other words, it establishes a logical mapping relationship between the target virtual address and the target physical memory page.

[0070] For example, if the target virtual memory address is "Aj" and the target physical memory page is "Pj", then the processor calls the kernel-mode processing thread running on the second core to establish the mapping relationship "Lj" between "Aj" and "Pj".

[0071] S309, Invoke the second core to send the mapping relationship to the first core.

[0072] In one possible implementation, after the second core establishes the mapping between the target virtual address and the target physical memory page, the processor then calls the second core to send the mapping to the first core, so that the first core is aware that the mapping has been established. Optionally, the processor can also call a kernel-mode status thread running on the first core to add the mapping to the memory page.

[0073] S310: Call the first core to obtain the data of the target physical memory page according to the mapping relationship and memory page table, and send the data of the target physical memory page to the target application.

[0074] In one possible implementation, after the mapping relationship corresponding to the target virtual memory address is established, in response to the memory access instruction of the target application obtained in step S301, the processor can call the kernel-mode state thread running on the first core to obtain the data of the target physical memory page according to the mapping relationship and the memory page table, and send the data of the target physical memory page to the target application. Correspondingly, the target physical page and the received data of the target physical memory page are displayed on the terminal interface.

[0075] Among them, steps S301 to S310 can be used Figure 4 The examples are explained in detail, such as Figure 4 As shown, Figure 4The premise is that, in the previous moment, the target application accessed the target virtual address Ai, and there was a mapping relationship Li between Ai and the corresponding physical memory page Pi in the memory page table. In the current moment, the application begins to access virtual memory address Aj, but there is no mapping relationship Lj between Aj and the corresponding physical memory page Pj in the memory page table. Therefore, the specific steps may include:

[0076] S1: The target application instruction accesses virtual address Aj;

[0077] S2: The mapping relationship between Aj and the physical memory page does not exist. The processor determines that a page fault has occurred and then switches to kernel-mode thread processing.

[0078] S3: The kernel-mode thread obtains the indicator flag of the first core's working mode. The indicator flag is used to indicate the working mode of the first core. If the indicator flag is 1 at this time, it is determined that the first core's working mode is interception mode, the interrupt point information is obtained, and a data acquisition instruction carrying the interrupt point information is sent to the kernel-mode processing thread of the second core.

[0079] S4: The kernel-mode processing thread sends the breakpoint information (including the target application's current memory access instruction address, target virtual memory address, and call stack) included in the data acquisition instruction to the data acquisition program;

[0080] S5: The data acquisition program performs data acquisition operations, stores the received breakpoint information, obtains the count value of the processor event counter of the target application, uses the breakpoint information and the count value as the performance index data of the target application, and sends a notification message of acquisition completion to the kernel-mode processing thread after the acquisition is completed.

[0081] S6: The kernel-mode processing thread removes the mapping relationship Li between Ai and Pi from the memory page table (but the relationship Li is still stored in the data structure or in the processor's memory space). This step can be executed after S3.

[0082] S7: The kernel-mode processing thread establishes the mapping relationship Lj between Aj and Pj;

[0083] S8: The kernel-mode processing thread notifies the kernel-mode state thread of the mapping relationship Lj. The kernel-mode state thread can then return the access result to the target application, at which point the target application can perform normal access. Furthermore, the kernel-mode state thread can also switch from interception mode to non-interception mode based on the indicator of the first core's working mode.

[0084] In this embodiment, the main description is that when the data acquisition conditions are met, the processor introduces a new processor core to collect performance index data of the target application. Since no other instruction set is introduced during the data acquisition process, the obtained performance index data can be more accurate and is more conducive to developers optimizing the performance of the target application.

[0085] Based on the above description of the processor architecture and data acquisition method of the computer device, this application discloses another data acquisition method. Please refer to [link to relevant documentation]. Figure 5 This is a flowchart illustrating another data acquisition method disclosed in an embodiment of this application. This data acquisition method can be executed by a computer device, specifically by the processor of the computer device. Specifically, it describes how the processor calls the first core for memory access when a page fault occurs but the first core's operating mode is non-intercept mode. This can include steps S501 to S505:

[0086] S501. Obtain the memory access instructions of the target application, including the target virtual memory address.

[0087] S502. Query the mapping relationship corresponding to the target virtual memory address from the memory page table. If there is no mapping relationship corresponding to the target virtual memory address in the memory page table, it is determined that a page fault has occurred during memory access.

[0088] Among them, steps S501 and S502 have already been performed. Figure 3 The relevant embodiments shown have been described in detail, and will not be repeated here.

[0089] S503. Call the first core to obtain the indicator of the working mode of the first core. If the indicator is a preset second value, then determine that the working mode of the first core is non-interception mode.

[0090] In one possible implementation, the processor determines the operating mode based on the indicator of the first core's operating mode. Specifically, when a page fault is detected in the target application, the processor further calls the kernel-mode state thread running on the first core to obtain the indicator of the first core's operating mode. This indicator is stored in memory. Optionally, the indicator of the operating mode may include a kernel-mode state thread identifier and a state identifier. The kernel-mode state thread identifier indicates which kernel-mode state thread is involved, and the state identifier indicates the operating mode. If the indicator reads a preset second value, the processor can determine that the first core's operating mode is non-intercept mode. In this embodiment, the preset second value can be 0, meaning 0 represents non-intercept mode. Non-intercept mode can be understood as a normal mode, where the target application is currently in a stable state, and the corresponding kernel can handle the page fault. In this case, it is not necessary to collect performance metrics data of the target application; only an access mapping relationship needs to be established, as detailed in step S504.

[0091] S504: Call the first core to establish the mapping relationship between the target virtual address and the memory address.

[0092] In one possible implementation, the processor invokes a kernel-mode thread running on the first core to establish a mapping between the target virtual address and the target physical memory page. The target physical memory page is obtained by the kernel-mode thread from the processor's memory space. In other words, this establishes a logical mapping between the target virtual address and the target physical memory page.

[0093] For example, if the target virtual memory address is "A2" and the target physical memory page is "P2", then the processor calls the kernel-mode processing thread running on the first core to establish the mapping relationship "Lj2" between "A2" and "P2".

[0094] S505: The first core is invoked to obtain the data of the target physical memory page according to the mapping relationship and the memory page table, and then sends the data of the target physical memory page to the target application.

[0095] In one possible implementation, after the mapping relationship corresponding to the target virtual memory address is established, in response to the memory access instruction of the target application obtained in step S501, the processor can call the kernel-mode state thread running on the first core to obtain the data of the target physical memory page according to the mapping relationship and the memory page table, and send the data of the target physical memory page to the target application. Correspondingly, the target physical page and the received data of the target physical memory page are displayed on the terminal interface.

[0096] Among them, steps S501 to S505 can be used Figure 6 The examples are explained in detail, such as Figure 6 As shown, Figure 6 The premise shown is that: virtual memory addresses A1 and A3 already have mapping relationships L1 and L3 pointing to physical memory pages P1 and P3 before access, and the target application can directly access the corresponding physical memory pages without interruption when accessing A1 and A3. The mapping relationship from virtual memory address A2 to the physical memory page does not exist at the time of access, and the processor will trigger a page fault mechanism. Specifically, this may include the following steps:

[0097] S11: The target application accesses virtual memory address A2;

[0098] S12: Since the mapping relationship between virtual memory address A2 and physical memory page P2 does not exist, the processor triggers a page fault, and then switches to kernel-mode thread processing;

[0099] S13: The kernel-mode thread finds the physical memory page P2 corresponding to the virtual memory address A2 in the memory space and establishes a mapping relationship L2 between A2 and P2 so that the target application can continue to access the virtual memory address A2.

[0100] in, Figure 6 S14 and S15 shown are the steps by which the target application accesses A1 and A3. Because the mapping relationship exists, physical memory pages P1 and P3 can be successfully accessed.

[0101] In this embodiment, the processor can invoke a first core to obtain the memory access instructions of the target application. These instructions include the target virtual memory address. Then, the processor invokes the first core to determine if a page fault has occurred in the target application. If the first core is operating in non-intercept mode, a kernel-mode thread running on the first core is invoked to establish a mapping relationship, thereby determining the data of the physical memory page for the memory access instructions. Establishing the relationship between the virtual memory address and the physical memory page during a page fault using this method is logically simple and has strong versatility.

[0102] Based on the above method embodiments, this application also provides a schematic diagram of the structure of a data acquisition device. See also... Figure 7 This is a schematic diagram of the structure of an image processing device provided in an embodiment of this application. Figure 7 The data acquisition device 700 shown can operate the following units:

[0103] The sending unit 701 is used to call the first core of the processor to send a data acquisition instruction to the second core of the processor when the data acquisition conditions are met. The data acquisition conditions include a page fault interrupt occurring in the memory access of the target application running on the first core, and the first core is in intercept mode. The data acquisition instruction includes the breakpoint information of the page fault interrupt.

[0104] The acquisition unit 702 is used to call the second core to respond to the data acquisition instruction and acquire the breakpoint information and the count value of the processor event counter;

[0105] The acquisition unit 702 is also used to call the second core to use the breakpoint information and the count value as performance indicator data of the target application.

[0106] In one possible implementation, a kernel-mode state thread runs on the first core, and the sending unit 701 invokes the processor's first core to send a data acquisition instruction to the processor's second core, including:

[0107] The kernel-mode state thread is invoked to obtain the breakpoint information of the page fault.

[0108] The kernel-mode state thread is invoked to generate a data acquisition instruction based on the breakpoint information;

[0109] The kernel state thread is invoked to send the data acquisition instruction to the second core.

[0110] In one possible implementation, the acquisition unit 702 is further configured to call the first core to acquire the memory access instruction of the target application, the memory access instruction including the target virtual memory address;

[0111] Processing unit 703 is used to call the first core to query the mapping relationship corresponding to the target virtual memory address from the memory page table;

[0112] The determining unit 704 is used to determine that a page fault has occurred in memory access if there is no mapping relationship corresponding to the target virtual memory address in the memory page table;

[0113] The acquisition unit 702 is also used to call the first core to acquire the indicator of the working mode of the first core;

[0114] The determining unit 704 is further configured to determine that the working mode of the first core is the interception mode if the indication identifier is a preset first value.

[0115] In one possible implementation, the acquisition unit 702 is further configured to call the first core to acquire the count value of the processor event counter;

[0116] The processing unit 703 is further configured to, when the increase in the count value reaches a preset first threshold, call the first core to adjust the indicator of the working mode of the first core to a preset first value, so as to switch the working mode of the first core to interception mode.

[0117] In one possible implementation, the processing unit 703 is further configured to call the first core to delete the mapping relationship between virtual memory addresses and physical memory pages included in the memory page table.

[0118] In one possible implementation, the acquisition unit 702 is further configured to call the first core to acquire the count value of the processor event counter;

[0119] The processing unit 703 is further configured to, when the increase in the count value reaches a preset second threshold, call the first core to adjust the indicator of the working mode of the first core to a preset second value, so as to switch the working mode of the first core to a non-interception mode.

[0120] The acquisition unit 702 is further configured to call the first core to obtain the mapping relationship between virtual memory addresses and physical memory pages from the processor's memory space, and add the mapping relationship to the memory page table.

[0121] In one possible implementation, the acquisition unit 703 is further configured to call the second core to establish a mapping relationship between the target virtual address and the target physical memory page;

[0122] The sending unit 701 is also used to call the second core to send the mapping relationship to the first core;

[0123] The acquisition unit 702 is further configured to call the first core to acquire the data of the target physical memory page according to the mapping relationship and the memory page table, and send the data of the target physical memory page to the target application.

[0124] In one possible implementation, the second core runs a kernel-mode processing thread and a data acquisition program. The acquisition unit 702 calls the second core in response to the data acquisition instruction to acquire the breakpoint information and the count value of the processor event counter, which can be specifically used for:

[0125] The kernel-mode processing thread is invoked to obtain the breakpoint information included in the data acquisition instruction;

[0126] The data acquisition program is invoked to obtain the count value of the processor event counter;

[0127] The kernel-mode processing thread is invoked to send the breakpoint information to the data acquisition program.

[0128] The data acquisition program is invoked to store the breakpoint information and the count value.

[0129] According to one embodiment of this application, Figure 2 , Figure 3 as well as Figure 5 The data acquisition method shown can involve various steps that are: Figure 7 This is performed by each unit in the data acquisition device 700 shown. For example, Figure 2 In the data acquisition method shown, step S201 can be performed by... Figure 7 The data acquisition device 700 shown is executed by the transmitting unit 701. Steps S202 and S203 can be performed by... Figure 7 The acquisition unit 702 in the data acquisition device 700 shown is used to perform this action; for example, Figure 3 In the data acquisition method shown, steps S305 and S309-S310 can be obtained by... Figure 7 The data acquisition device 700 shown is executed by the transmitting unit 701. Steps S301 and S306-S307 can be performed by... Figure 7 The data acquisition unit 702 in the data acquisition device 700 shown is responsible for executing steps S304 and S308. Figure 7 The processing unit 703 in the data acquisition device 700 shown executes the steps S302-S303, which can be performed by... Figure 7 The determination unit 704 in the data acquisition device 700 shown is used to perform this action; for example... Figure 5 In the data acquisition method shown, step S505 can be performed by... Figure 7 The data acquisition device 700 shown is executed by the transmitting unit 701. Step S501 can be performed by... Figure 7 The data acquisition unit 702 in the data acquisition device 700 shown is responsible for executing step S504, which can be performed by... Figure 7 The processing unit 703 in the data acquisition device 700 shown executes the steps S502-S503, which can be performed by... Figure 7 The determination unit 704 in the data acquisition device 700 shown performs the operation.

[0130] According to another embodiment of this application, Figure 7The data acquisition device 700 shown can be composed of one or more additional units, either individually or entirely. Alternatively, some of the units can be further divided into smaller functional units. This achieves the same operation without affecting the technical effects of the embodiments of this application. The units described above are based on logical function. In practical applications, the function of one unit can be implemented by multiple units, or the function of multiple units can be implemented by one unit. In other embodiments of this application, the data acquisition device 700 may also include other units. In practical applications, these functions can be implemented with the assistance of other units, and multiple units can collaborate to achieve them.

[0131] According to another embodiment of this application, the following can be achieved by running on a general-purpose computing device, such as a computer, which includes processing elements and storage elements such as a central processing unit (CPU), random access memory (RAM), and read-only memory (ROM), a device capable of performing operations such as... Figure 2 , Figure 3 as well as Figure 5 The computer program (including program code) for each step involved in the corresponding method shown, to construct such... Figure 7 The data acquisition device 700 shown herein, and the data acquisition method implemented according to the embodiments of this application, are described. The computer program may be recorded on, for example, a computer-readable storage medium, loaded onto the aforementioned computing device via the computer-readable storage medium, and run therein.

[0132] In this embodiment, the first core of the processor sends a data acquisition instruction to the second core of the processor. The sent data acquisition instruction includes the first core acquiring breakpoint information, which can be understood as the breakpoint information corresponding to a page fault. The second core then responds to the data acquisition instruction, acquiring the breakpoint information and the count value of the processor event counter. The second core then uses the acquired breakpoint information and the count value as performance indicator data for the target application. This method uses the second core to acquire the count value of the processor event counter of the target application running on the first core. Since no extra instructions are introduced into the target application, the accuracy of data acquisition can be improved, ensuring more accurate performance indicator data for the target application, which is more conducive to developers optimizing the target application. Furthermore, since this application acquires data through other cores in the processor that are not running the target application, there is no strong binding between the program and the instruction set, thus improving the versatility of data acquisition.

[0133] Based on the above methods and apparatus embodiments, this application provides a computer device. See also... Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Figure 8The computer device 800 shown includes at least a processor 801, an input interface 802, an output interface 803, a computer storage medium 804, and a memory 805. The processor 801, input interface 802, output interface 803, computer storage medium 804, and memory 805 can be connected via a bus or other means.

[0134] The computer storage medium 804 can be stored in the memory 805 of the computer device 800. The computer storage medium 804 is used to store computer programs, which include program instructions. The processor 801 is used to execute the program instructions stored in the computer storage medium 804. The processor 801 (or CPU (Central Processing Unit)) is the computing and control core of the computer device 800. It is adapted to implement one or more instructions, specifically to load and execute one or more computer instructions to achieve corresponding method flows or corresponding functions.

[0135] This application embodiment also provides a computer storage medium (memory), which is a memory device in a computer device 800. It is understood that the computer storage medium here may include the built-in storage medium in the computer device 800, or it may include an extended storage medium supported by the computer device 800. The computer storage medium provides storage space, which stores the operating system of the computer device 800. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by the processor 801. These instructions may be one or more computer programs (including program code). It should be noted that the computer storage medium here may be a high-speed RAM memory, or a non-volatile memory, such as at least one disk storage device; optionally, it may also be at least one computer storage medium located remotely from the aforementioned processor.

[0136] In one embodiment, the computer storage medium may be loaded by a processor 801 and one or more instructions stored in the computer storage medium may be executed to achieve the aforementioned related... Figure 2 , Figure 3 as well as Figure 5 The corresponding steps of the data acquisition method shown are as follows. In specific implementation, one or more instructions in the computer storage medium are loaded and executed by the processor 801, and the following steps are performed:

[0137] When the data acquisition conditions are met, the first core of the processor sends a data acquisition instruction to the second core of the processor. The data acquisition conditions include a page fault interrupt occurring in the memory access of the target application running on the first core, and the first core is in intercept mode. The data acquisition instruction includes the breakpoint information of the page fault interrupt.

[0138] The second core is invoked to respond to the data acquisition instruction and obtain the breakpoint information and the count value of the processor event counter;

[0139] The second core is invoked to use the breakpoint information and the count value as performance metric data for the target application.

[0140] In one possible implementation, a kernel-mode state thread runs on the first core, and the processor 801 invokes the first core of the processor to send a data acquisition instruction to the second core of the processor, including:

[0141] The kernel-mode state thread is invoked to obtain the breakpoint information of the page fault.

[0142] The kernel-mode state thread is invoked to generate a data acquisition instruction based on the breakpoint information;

[0143] The kernel state thread is invoked to send the data acquisition instruction to the second core.

[0144] In one possible implementation, the processor 801 is further configured to:

[0145] The first core is invoked to obtain the memory access instructions of the target application, the memory access instructions including the target virtual memory address;

[0146] The first core is invoked to query the mapping relationship corresponding to the target virtual memory address from the memory page table;

[0147] If the target virtual memory address is not mapped in the memory page table, a page fault is determined to have occurred during memory access.

[0148] Call the first core to obtain the indicator of the first core's working mode;

[0149] If the indicator is a preset first value, then the working mode of the first core is determined to be the interception mode.

[0150] In one possible implementation, the processor 801 is further configured to:

[0151] Call the first core to obtain the count value of the processor event counter;

[0152] When the increase in the count value reaches a preset first threshold, the first core is invoked to adjust the indicator of the first core's working mode to a preset first value, so as to switch the working mode of the first core to interception mode.

[0153] In one possible implementation, the processor 801 is further configured to:

[0154] The first core is invoked to delete the mapping relationship between virtual memory addresses and physical memory pages included in the memory page table.

[0155] In one possible implementation, the processor 801 is further configured to:

[0156] Call the first core to obtain the count value of the processor event counter;

[0157] When the increase in the count value reaches a preset second threshold, the first core is invoked to adjust the indicator of the first core's working mode to a preset second value, so as to switch the working mode of the first core to non-interception mode.

[0158] The first core is invoked to obtain the mapping relationship between virtual memory addresses and physical memory pages from the processor's memory space, and the mapping relationship is added to the memory page table.

[0159] In one possible implementation, the processor 801 is further configured to:

[0160] The second core is invoked to establish the mapping relationship between the target virtual address and the target physical memory page;

[0161] The second core is invoked to send the mapping relationship to the first core;

[0162] The first core is invoked to obtain the data of the target physical memory page based on the mapping relationship and the memory page table, and then sends the data of the target physical memory page to the target application.

[0163] In one possible implementation, the second core runs a kernel-mode processing thread and a data acquisition program. The processor 801 calls the second core in response to the data acquisition instruction to obtain the breakpoint information and the count value of the processor event counter, which can be specifically used for:

[0164] The kernel-mode processing thread is invoked to obtain the breakpoint information included in the data acquisition instruction;

[0165] The data acquisition program is invoked to obtain the count value of the processor event counter;

[0166] The kernel-mode processing thread is invoked to send the breakpoint information to the data acquisition program.

[0167] The data acquisition program is invoked to store the breakpoint information and the count value.

[0168] According to one aspect of the embodiments of this application, the present application also provides a computer product or computer program including a computer program stored in a computer-readable storage medium. A processor 801 reads the computer program from the computer-readable storage medium and executes the computer program, causing a computer device 800 to perform... Figure 2 , Figure 3 as well as Figure 5 The data acquisition method shown.

[0169] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0170] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, and the division of modules described above is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0171] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data acquisition method, characterized in that, The method includes: Call the processor's first core to obtain the processor event counter value; When the increase in the count value reaches a preset first threshold, the first core is invoked to adjust the indicator of the working mode of the first core to a preset first value, so as to switch the working mode of the first core to interception mode. When the data acquisition conditions are met, the first core sends a data acquisition instruction to the second core of the processor. The data acquisition conditions include a page fault interrupt occurring during memory access of the target application running on the first core, and the first core is in intercept mode. The data acquisition instruction includes the breakpoint information of the page fault interrupt. The second core is invoked to respond to the data acquisition instruction and obtain the breakpoint information and the count value of the processor event counter; The second core is invoked to use the breakpoint information and the count value as performance metric data for the target application.

2. The method according to claim 1, characterized in that, The first core runs a kernel-mode state thread, and the step of calling the first core to send a data acquisition instruction to the second core of the processor includes: The kernel-mode state thread is invoked to obtain the breakpoint information of the page fault. The kernel-mode state thread is invoked to generate a data acquisition instruction based on the breakpoint information; The kernel state thread is invoked to send the data acquisition instruction to the second core.

3. The method according to claim 1, characterized in that, Before invoking the first core to send a data acquisition instruction to the second core of the processor when the data acquisition conditions are met, the method further includes: Obtain the memory access instructions of the target application, wherein the memory access instructions include the target virtual memory address; Query the mapping relationship corresponding to the target virtual memory address from the memory page table; If the target virtual memory address is not mapped in the memory page table, a page fault is determined to have occurred during memory access. Call the first core to obtain the indicator of the first core's working mode; If the indicator is a preset first value, then the working mode of the first core is determined to be the interception mode.

4. The method according to claim 1, characterized in that, After the method involves invoking the first core to adjust the indicator of the first core's working mode to a preset first value, thereby switching the first core's working mode to interception mode, the method further includes: The first core is invoked to delete the mapping relationship between virtual memory addresses and physical memory pages included in the memory page table.

5. The method according to claim 4, characterized in that, After the method involves invoking the first core to adjust the indicator of the first core's working mode to a preset first value, thereby switching the first core's working mode to interception mode, the method further includes: Call the first core to obtain the count value of the processor event counter; When the increase in the count value reaches a preset second threshold, the first core is invoked to adjust the indicator of the first core's working mode to a preset second value, so as to switch the working mode of the first core to non-interception mode. The first core is invoked to obtain the mapping relationship between virtual memory addresses and physical memory pages from the processor's memory space, and the mapping relationship is added to the memory page table.

6. The method according to any one of claims 1 to 3, characterized in that, The breakpoint information includes the target virtual memory address. After invoking the second core response to the data acquisition instruction and obtaining the breakpoint information and the processor event counter value, the method further includes: The second core is invoked to establish the mapping relationship between the target virtual memory address and the target physical memory page; The second core is invoked to send the mapping relationship to the first core; The first core is invoked to obtain the data of the target physical memory page based on the mapping relationship and the memory page table, and then sends the data of the target physical memory page to the target application.

7. The method according to claim 1, characterized in that, The second core runs a kernel-mode processing thread and a data acquisition program. The step of calling the second core in response to the data acquisition instruction to obtain the breakpoint information and the processor event counter value includes: The kernel-mode processing thread is invoked to obtain the breakpoint information included in the data acquisition instruction; The data acquisition program is invoked to obtain the count value of the processor event counter; The kernel-mode processing thread is invoked to send the breakpoint information to the data acquisition program. The data acquisition program is invoked to store the breakpoint information and the count value.

8. A data acquisition device, characterized in that, The device includes: The acquisition unit is used to call the processor's first core to obtain the count value of the processor event counter; The processing unit is configured to, when the increase in the count value reaches a preset first threshold, call the first core to adjust the indicator of the working mode of the first core to a preset first value, so as to switch the working mode of the first core to interception mode. The sending unit is used to call the first core to send a data acquisition instruction to the second core of the processor when the data acquisition conditions are met. The data acquisition conditions include a page fault interrupt occurring in the memory access of the target application running on the first core, and the first core is in intercept mode. The data acquisition instruction includes the breakpoint information of the page fault interrupt. The acquisition unit is also used to call the second core to respond to the data acquisition instruction and acquire the breakpoint information and the count value of the processor event counter; The acquisition unit is also used to call the second core to use the breakpoint information and the count value as performance indicator data of the target application.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more computer programs, which are adapted to be loaded by a processor and executed as described in any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a computer processor, it implements the data acquisition method according to any one of claims 1-7.

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