Resistance change memory cell and memory array

Abstract

The application provides a resistance change memory cell and a memory array, comprising: a first resistance change element, a second resistance change element and a MOS transistor; wherein the MOS transistor is a bidirectional transistor, the gate of the MOS transistor is connected with a word line, the first end of the MOS transistor is connected with a first source line and the second end of the first resistance change element, and the second end of the MOS transistor is connected with a second source line and the second end of the second resistance change element; the first end of the first resistance change element is connected with a first bit line, and the first end of the second resistance change element is connected with a second bit line; the resistance change memory cell is configured so that at most one of the first resistance change element and the second resistance change element is selected at the same time. In the application, a 1T2R resistance change memory cell is provided, compared with 1T1R, not only the storage density can be improved, but also the application has the advantages of simple structure and easy realization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, and particularly relates to a resistive random access memory (RRAM) cell and a memory array. BACKGROUND

[0002] In recent years, as Moore's law is gradually approaching the limit, traditional memory cells such as dynamic random access memory (DRAM) and flash memory are gradually facing the physical limit of size reduction, and it is difficult to improve the storage capacity while reducing the production cost. In view of this problem, a series of new memories have emerged, such as resistive random access memory (RRAM), ferroelectric memory, magnetic memory and phase change memory. Among them, resistive random access memory (RRAM) has been widely valued and researched by the academic and industrial circles because of its high integration density, high layer potential and low production cost.

[0003] When resistive random access memory (RRAM) is integrated in an array, problems such as leakage current between adjacent resistive random access memory (RRAM) and resistive random access memory (RRAM) overwriting will be encountered. The current commercial production solution of resistive random access memory (RRAM) adopts a 1T1R structure (a resistive element is connected in series at the drain end of a MOS transistor), which can effectively solve the two problems mentioned above, but the effective storage cell area will be increased from the original 4F 2 to 12F 2 (F is the lithography size of the storage cell), which reduces the storage density. SUMMARY

[0004] The present application aims to provide a resistive random access memory (RRAM) cell and a memory array for improving the storage density of the resistive random access memory (RRAM) array.

[0005] To solve the above technical problems, the resistive random access memory (RRAM) cell provided by the present application is characterized in that the resistive random access memory (RRAM) cell is connected with a word line, a first bit line, a second bit line, a first source line and a second source line, and the resistive random access memory (RRAM) cell comprises:

[0006] a first resistive element having a first end and a second end;

[0007] a second resistive element having a first end and a second end; and

[0008] a MOS transistor having a gate, a first end and a second end;

[0009] The MOS transistor is a bidirectional transistor, the first and second resistance change elements are located above the MOS transistor, the gate of the MOS transistor is connected to the word line, the first end of the MOS transistor is connected to the first source line, and the second end of the MOS transistor is connected to the second source line; the first end of the first resistance change element is connected to the first bit line, and the second end of the first resistance change element is connected to the second source line; the first end of the second resistance change element is connected to the second bit line, and the second end of the second resistance change element is connected to the first source line.

[0010] The resistance change memory unit is configured to have at most one of the first and second resistance change elements selected at the same time.

[0011] Optionally, the second source line is in a suspended state, the second bit line has the same potential as the first source line, and the word line is in an open state to select the first resistance change element.

[0012] Optionally, the first resistance change element is selected, and the resistance change memory unit is configured to read or control the storage state of the first resistance change element by using the first bit line and the first source line.

[0013] Optionally, the first source line is in a suspended state, the first bit line has the same potential as the second source line, and the word line is in an open state to select the second resistance change element.

[0014] Optionally, the second resistance change element is selected, and the resistance change memory unit is configured to read or control the storage state of the second resistance change element by using the second bit line and the second source line.

[0015] Optionally, the MOS transistor has a symmetric source-drain structure.

[0016] Optionally, the first and second resistance change elements are MIM structures formed in an interconnection structure on the MOS transistor, the MIM structure includes an upper plate, a resistance change layer, and a lower plate, the upper plate of the MIM structure serves as the first end of the first and second resistance change elements, and the lower plate of the MIM structure serves as the second end of the first and second resistance change elements.

[0017] Optionally, the first and second resistance change elements have the same electrical parameters, and two-value storage is realized by using the resistance state information of the first and second resistance change elements.

[0018] Optionally, the electrical parameters of the first resistive change element and the second resistive change element are different, and the four-value storage is realized by combining the resistance state information of the first resistive change element and the second resistive change element.

[0019] Based on another aspect of the present application, a storage array is also provided, which comprises the resistive change storage unit as described above, and a plurality of the resistive change storage units are arranged in rows and columns to form the storage array, wherein the plurality of the resistive change storage units in the ith row are connected to a word line WL extending in the row direction i , the first bit line of the plurality of the resistive change storage units in the jth column is connected to a BL extending in the column direction j , the second bit line of the plurality of the resistive change storage units in the jth column is connected to a BL extending in the column direction j+1 , the first source line of the plurality of the resistive change storage units in the jth column is connected to a SL extending in the column direction j , the second source line of the plurality of the resistive change storage units in the jth column is connected to a SL extending in the column direction j+1 , and i and j are positive integers.

[0020] In summary, the resistive change storage unit and the storage array provided by the present application are characterized in that: a first resistive change element and a second resistive change element are arranged at the first end and the second end of the bidirectional conductive MOS transistor respectively, and the first resistive change element and the second resistive change element are both located above the MOS transistor; and five ports are led out from the MOS transistor, the first resistive change element and the second resistive change element, and the first resistive change element or the second resistive change element is selected by using the five ports, so that the 1T2R structure resistive change storage unit of the present embodiment can realize at least two-value (at least two information) storage only by occupying one MOS transistor area, and has the advantages of simple structure and easy implementation. BRIEF DESCRIPTION OF DRAWINGS

[0021] Those skilled in the art should understand that the provided drawings are used to better understand the present application, and do not constitute any limitation on the scope of the present application.

[0022] Figure 1 is the device principle diagram of the resistive change storage unit provided in embodiment one;

[0023] Figure 2 is the timing control schematic diagram of the resistive change storage unit provided in embodiment one;

[0024] Figure 3 is the structural schematic diagram of the resistive change storage unit provided in embodiment one;

[0025] Figure 4 is the timing control schematic diagram of the resistive change storage unit provided in embodiment two;

[0026] Figure 5A schematic diagram of a memory array is provided for Example Three.

[0027] In the drawings:

[0028] 10 - substrate; 20 - MOS transistor; 21 - gate; 22 - first terminal of MOS transistor; 23 - second terminal of MOS transistor; 30 - first resistive switching element; 31 - upper plate of first resistive switching element; 32 - lower plate of first resistive switching element; 33 - resistive switching layer of first resistive switching element; 40 - second resistive switching element; 41 - upper plate of second resistive switching element; 42 - lower plate of second resistive switching element; 43 - resistive switching layer of second resistive switching element; WL - word line; BL1 - first bit line; BL2 - second bit line; SL1 - first source line; SL2 - second source line. DETAILED DESCRIPTION

[0029] In order to make the objects, advantages and features of the present application clearer, the following further describes the present application in detail with reference to the accompanying drawings and specific examples. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of describing the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0030] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. The term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used only to describe the objects and are not to be construed as indicating or implying relative importance or a specific number of the indicated technical features. Thus, the features defined with "first," "second," "third" can explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0031] Example One

[0032] Figure 1 is a device schematic diagram of a resistive switching memory cell provided by the present embodiment.

[0033] As Figure 1As shown, the resistive switching memory cell provided by the embodiment is connected with a word line WL, a first bit line BL1, a second bit line BL2, a first source line SL1 and a second source line SL2. The resistive switching memory cell comprises: a first resistive switching element 30 having a first end and a second end; a second resistive switching element 40 having a first end and a second end; and a MOS transistor 20 having a gate, a first end and a second end. The MOS transistor 20 is a bidirectional conductive transistor, the first resistive switching element 30 and the second resistive switching element 40 are located above the MOS transistor 20, the gate of the MOS transistor 20 is connected with the word line WL, the first end of the MOS transistor 20 is connected with the second source line SL2, and the second end of the MOS transistor 20 is connected with the first source line SL1; the first end of the first resistive switching element 30 is connected with the first bit line BL1, and the second end of the first resistive switching element 30 is connected with the second source line SL2; the first end of the second resistive switching element 40 is connected with the second bit line BL2, and the second end of the second resistive switching element 40 is connected with the first source line SL1; the resistive switching memory cell is configured such that at most one of the first resistive switching element 30 and the second resistive switching element 40 is selected at the same time.

[0034] The MOS transistor 20 can be any suitable bidirectional conductive MOS transistor 20 (field effect transistor), such as a planar transistor, a FinFET or a GAA (gate-all-around) transistor. The MOS transistor 20 has a gate, a first end and a second end. Preferably, the MOS transistor 20 is a source-drain symmetric transistor, so that the electrical parameters of the conduction from the first end of the MOS transistor 20 and the conduction from the second end of the MOS transistor 20 are the same or as close as possible, facilitating subsequent timing control. Compared with a vertical channel structure, the MOS transistor can be a horizontal channel structure, facilitating manufacturing.

[0035] Compared with a 1T1R structure, the embodiment adopts one MOS transistor 20 and two resistive switching elements located above the MOS transistor 20 to form a 1T2R structure, so as to multiply the storage density of the resistive switching memory array while occupying the same substrate area (layout area). The first resistive switching element 30 and the second resistive switching element 40 each have a first end and a second end, and can be unipolar resistive switching elements or bipolar resistive switching elements based on any suitable principle. In a preferred embodiment, the first resistive switching element 30 and the second resistive switching element 40 can have the same structure and as close as possible electrical parameters to form a symmetric structure, facilitating subsequent timing control.

[0036] Please continue to refer to Figure 1The resistance change memory cell in the embodiment has five connection terminals, i.e. a word line WL, a first bit line BL1, a second bit line BL2, a first source line SL1 and a second source line SL2. The connection relationship of the five connection terminals with the 1T2R structure can be as follows: the gate of the MOS transistor 20 is connected with the word line WL, the first end of the MOS transistor 20 is connected with the second source line SL2, and the second end of the MOS transistor 20 is connected with the first source line SL1; the first end of the first resistance change element 30 is connected with the first bit line BL1, and the second end of the first resistance change element 30 is connected with the second source line SL2; the first end of the second resistance change element 40 is connected with the second bit line BL2, and the second end of the second resistance change element 40 is connected with the first source line SL1.

[0037] The two ends of the MOS transistor 20 are connected with one resistance change element in series respectively, but at most one of the first resistance change element 30 and the second resistance change element 40 is selected at the same time. When the first resistance change element 30 is selected, the resistance change memory cell is configured with the storage state of the first resistance change element 30, and the second resistance change element 40 is in a non-selected state (idle state). When the second resistance change element 40 is selected, the resistance change memory cell is configured with the storage state of the second resistance change element 40, and the first resistance change element 30 is in a non-selected state. Specifically, the second resistance change element 40 can be in the idle state by keeping the second bit line BL2 and the first source line SL1 at the same (or close to the same) potential, i.e. keeping the two ends (the second bit line BL2 and the first source line SL1) of the second resistance change element 40 at the same potential, and the second source line SL2 is in a suspended state to reduce the influence on the first resistance change element 30. Thus, the first resistance change element 30 can be operated (the storage state of the first resistance change element 30 is controlled or read) in the manner of 1T1R through the first bit line BL1 and the first source line SL1. Similarly, the first resistance change element 30 can be in the idle state by keeping the first bit line BL1 and the second source line SL2 at the same potential, i.e. keeping the two ends (the first bit line BL1 and the second source line SL2) of the first resistance change element 30 at the same potential, and the first source line SL1 is in a suspended state to reduce the influence on the second resistance change element 40. Thus, the second resistance change element 40 can be operated in the manner of 1T1R through the second bit line BL2 and the second source line SL2. Thus, the two-value storage can be realized more simply by operating the first resistance change element 30 and the second resistance change element 40 through the MOS transistor 20 respectively.

[0038] Preferably, the first resistance change element 30 and the second resistance change element 40 can both be bipolar resistance change elements. The bipolar resistance change element is initialized or set by applying a high level to the first end (anode end), and is reset by applying a high level to the second end (cathode end).

[0039] On this basis, taking the MOS transistor 20 as an NMOS transistor for example, the first resistance change element 30 and the second resistance change element 40 can be initialized or set by applying a high level to the first end (anode end) of the bipolar resistance change element, and the bipolar resistance change element is reset by applying a high level to the second end (cathode end). Figure 2As shown, the AA region is a timing control diagram for selecting the first resistive change element 30, A1 is a forming stage, the word line WL is at a high level, the second source line SL2 is in a suspended state (a level state is not shown), the second bit line BL2 and the first source line SL1 are at a low level (for example, ground), and the first bit line BL1 is at a high level (for example, Vdd); A2 and A4 are read stages, the word line WL is at a high level, the second source line SL2 is in a suspended state, the second bit line BL2 and the first source line SL1 are at a low level, and the first bit line BL1 is at a sub-high level (for example, Vdlin, slightly lower than Vdd); A3 is a reset stage, the word line WL is at a high level, the second source line SL2 is in a suspended state, the second bit line BL2 and the first source line SL1 are at a high level, and the first bit line BL1 is at a low-high level; and A5 is a set stage, the word line WL is at a high level, the second source line SL2 is in a suspended state, the second bit line BL2 and the first source line SL1 are at a low level, and the first bit line BL1 is at a high level.

[0040] Please continue to refer to Figure 2 , the BB region is a timing control diagram for selecting the second resistive change element 40, B1 is a forming stage, the word line WL is at a high level, the first source line SL1 is in a suspended state, the first bit line BL1 and the second source line SL2 are both at a low level, and the second bit line BL2 is at a high level; B2 and B4 are read stages, the word line WL is at a high level, the first source line SL1 is in a suspended state, the first bit line BL1 and the second source line SL2 are both at a low level, and the second bit line BL2 is at a sub-high level (for example, Vdlin, a read level); B3 is a reset stage, the word line WL is at a high level, the first source line SL1 is in a suspended state, the first bit line BL1 and the second source line SL2 are both at a high level, and the second bit line BL2 is at a low level; and B5 is a set stage, the word line WL is at a high level, the first source line SL1 is in a suspended state, the first bit line BL1 and the second source line SL2 are both at a low level, and the second bit line BL2 is at a high level.

[0041] Please refer to Figure 3The first resistive element 30 and the second resistive element 40 are formed in an interconnection structure on the MOS transistor 20, and can both be MIM structures, i.e. including an upper plate, a lower plate and a resistive layer between the upper plate and the lower plate, wherein the upper plate 31 of the first resistive element is used to connect the first bit line BL1, the lower plate 32 of the first resistive element is used to connect the second source line SL2, the upper plate 41 of the second resistive element is used to connect the second bit line BL2, and the lower plate 42 of the second resistive element is used to connect the first source line SL1. It is not difficult to understand that the MOS transistor 20 and the first resistive element 30 and the second resistive element 40 in the embodiment are all based on CMOS process, i.e. the resistive memory cell provided in the embodiment can not only realize 1T2R in the same layout area as 1T1R, improve the storage capacity and have the advantage of high storage density, but also can be mass-produced by using mature process (CMOS process).

[0042] Embodiment Two

[0043] Figure 4 Timing control schematic diagram of the resistive memory cell provided in Embodiment Two.

[0044] The resistive memory cell provided in the embodiment has similar structure and connection mode as Embodiment One, but the first resistive element and the second resistive element in the embodiment have differentiated electrical parameters (including at least one of high resistance state resistance or low resistance state resistance and resistive voltage). In a specific embodiment, the first resistive element has a first resistive voltage and a first high resistance state resistance, the second resistive element has a second resistive voltage and a second high resistance state resistance, and the low resistance state resistance of the first resistive element can be the same as or close to (e.g. close to 0) the low resistance state resistance of the second resistive element.

[0045] Please refer to Figure 4For example, taking NMOS as the MOS transistor and the first resistance change voltage being greater than the second resistance change voltage as an example, the AA region is a timing control diagram for selecting the first resistance change element, in which the second source line SL2 is always in a suspended state, and the second bit line BL2 and the first source line SL1 always maintain the same potential to make the second resistance change unit in a non-selected state, so that the first resistance change voltage is used as Vdd1 to initialize, reset, set and read the storage information of the first resistance change element through the first bit line BL1 and the first source line SL1. The BB region is a timing control diagram for selecting the second resistance change element, in which the first source line SL1 is always in a suspended state, and the first bit line BL1 and the second source line SL2 always maintain the same potential to make the first resistance change unit in a non-selected state, so that the second resistance change voltage is used as Vdd2 to initialize, reset, set and read the storage information of the first resistance change element through the second bit line BL2 and the second source line SL2. For the sake of comparison, Figure 4 Neither the AA region nor the BB region is marked with a corresponding second high voltage for reading.

[0046] It should be particularly noted that, when the first resistance change element is selected and read (A2 and A4), a corresponding first voltage of V11 or V12 can be obtained from the first source line SL1 under a corresponding reading voltage according to the storage state (first high resistance state or first low resistance state) of the first resistance change element. Similarly, when the second resistance change element is selected and read (B2 and B4), a corresponding second voltage of V21 or V22 can be obtained from the second source line SL2 under a corresponding reading voltage according to the storage state (second high resistance state or second low resistance state) of the second resistance change element. It can be easily understood that, since the electrical parameters of the first resistance change element and the second resistance change element are different, the obtained first voltage and second voltage can be different.

[0047] On the basis of the above, the scanning of the first resistance change element and the scanning of the second resistance change element can also be regarded as a large clock, that is, the result of the combined operation of the first voltage for selecting the first resistance change element and the second voltage for selecting the second resistance change element is taken as the result after scanning the resistance change storage unit under the large clock. Four combinations of V11 and V21, V11 and V22, V12 and V21, and V12 and V22 are obtained by the first voltage including V11 and V12 and the second voltage including V21 and V22, and the specific combined operation can be, for example, a differential operation, so that the resistance change storage unit composed of the MOS transistor, the first resistance change element and the second resistance change element can realize four-value (four data) storage, and the storage density can be further improved compared with the first embodiment.

[0048] In a preferred embodiment, the reading voltage of the first resistive switching element can be the same as or as close as possible to the reading voltage of the second resistive switching element (e.g., Vdlin1) to simplify the level setting of the circuit and facilitate the combined operation of the first voltage and the second voltage.

[0049] Example 3

[0050] Figure 5 This is a schematic diagram of the storage array provided in Embodiment 3.

[0051] The storage array provided in this embodiment includes multiple resistive switching memory cells arranged in an array as described above (Embodiment 1 or Embodiment 2). In this storage array, the resistive switching memory cells in the i-th row and j-th column (e.g., Figure 4 Taking the first row and first column of the resistive switching memory cell as an example, it includes a word line WL arranged along the row direction. i Two bit lines BL set along the column direction j and BL j+1 and two source lines SL set along the column direction j and SL j+1 Specifically, multiple resistive switching memory cells are arranged in rows and columns to form a memory array, wherein multiple resistive switching memory cells located in the i-th row are connected to word lines WL extending in the row direction. i The first line of multiple resistive switching memory cells located in the j-th column is connected to the BL extending in the column direction. j The second bit lines of multiple resistive switching memory cells located in the j-th column are connected to the BL extending in the column direction. j+1 The first source lines of multiple resistive switching memory cells located in the j-th column are connected to SL extending in the column direction. j The second source lines of multiple resistive switching memory cells located in the j-th column are connected to SL extending in the column direction. j+1 Both i and j are positive integers. The control method can be found in the resistive variable memory cell, and will not be elaborated upon here.

[0052] In summary, the resistive switching memory cell and memory array provided by the present invention, by setting a resistive switching element at each of the first and second ends of a bidirectional MOS transistor, with the first and second resistive switching elements both located above the MOS transistor, and then bringing out a total of five ports from the MOS transistor, the first and second resistive switching elements can be used to select the first or second resistive switching element. This allows the 1T2R structure resistive switching memory cell of this embodiment to store at least two values ​​(at least two pieces of information) while occupying only the area of ​​one MOS transistor, and also has the advantages of simple structure and easy implementation.

[0053] The above description is only the description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any change and modification made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A resistive switching memory cell, comprising: The resistance change memory cell is connected with a word line, a first bit line, a second bit line, a first source line and a second source line, and comprises: a first resistance change element having a first end and a second end; a second resistance change element having a first end and a second end; and a MOS transistor having a gate, a first end and a second end; wherein the MOS transistor is a bidirectional transistor, the first resistance change element and the second resistance change element are located above the MOS transistor, the gate of the MOS transistor is connected with the word line, the first end of the MOS transistor is connected with the first source line, and the second end of the MOS transistor is connected with the second source line; the first end of the first resistance change element is connected with the first bit line, and the second end of the first resistance change element is connected with the second source line; the first end of the second resistance change element is connected with the second bit line, and the second end of the second resistance change element is connected with the first source line; the resistance change memory cell is configured such that at most one of the first resistance change element and the second resistance change element is selected at the same time, wherein the second source line is in a floating state, the second bit line has the same potential as the first source line, and the word line is in an open state to select the first resistance change element.

2. The resistive switching memory cell of claim 1, wherein, When the first resistance change element is selected, the resistance change memory cell is configured as the storage state of the first resistance change element, and the storage state of the first resistance change element is read or controlled by using the first bit line and the first source line.

3. The resistive switching memory cell of claim 1, wherein, When the first source line is in a floating state, the first bit line has the same potential as the second source line, and the word line is in an open state to select the second resistance change element.

4. The resistive switching memory cell of claim 3, wherein, When the second resistance change element is selected, the resistance change memory cell is configured as the storage state of the second resistance change element, and the storage state of the second resistance change element is read or controlled by using the second bit line and the second source line.

5. The resistive switching memory cell of claim 1, wherein, The MOS transistor has a symmetrical source-drain structure.

6. The resistive switching memory cell of any one of claims 1 to 5, wherein, The first resistance change element and the second resistance change element are both MIM structures formed in an interconnection structure on the MOS transistor, the MIM structure comprises an upper plate, a resistance change layer and a lower plate, the upper plate of the MIM structure serves as the first end of the first resistance change element and the second resistance change element, and the lower plate of the MIM structure serves as the second end of the first resistance change element and the second resistance change element.

7. The resistive switching memory cell of claim 6, wherein, The electrical parameters of the first resistance change element and the second resistance change element are the same, and two-value storage is realized by using the resistance state information of the first resistance change element and the second resistance change element.

8. The resistive switching memory cell of claim 6, wherein, The electrical parameters of the first resistance change element and the second resistance change element are different, and four-value storage is realized by using the combination of the resistance state information of the first resistance change element and the second resistance change element.

9. A memory array comprising: The resistive random access memory cell as claimed in any one of claims 1 to 8, a plurality of the resistive random access memory cells are arranged in rows and columns to form a memory array, wherein the resistive random access memory cells in the i-th row are connected to a word line WL extending in a row direction i , the first bit lines of the resistive random access memory cells in the j-th column are connected to a BL extending in a column direction j , the second bit lines of the resistive random access memory cells in the j-th column are connected to a BL extending in a column direction j+1 , the first source lines of the resistive random access memory cells in the j-th column are connected to a SL extending in a column direction j , the second source lines of the resistive random access memory cells in the j-th column are connected to a SL extending in a column direction j+1 , i and j are positive integers.

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