Sample stage and system and method for modifying a sample

Abstract

Embodiments of the present invention relate to sample stages and systems and methods for modifying samples. A sample stage is provided that includes a base and a first sample post. The base has a first surface. The first sample post is disposed on the first surface of the base, and a top surface of the first sample post has a groove for placing a sample. Systems and methods for sample modification using the sample stage are also provided.

Description

Technical Field

[0001] The present invention relates to a sample stage, a system and method for modifying samples, and particularly to a system and method for modifying samples using a processed sample stage. Background Technology

[0002] In semiconductor manufacturing, the performance of measurement equipment directly impacts process modulation capabilities and yield increases. Semiconductor manufacturers and equipment suppliers must ensure that their measurement results are within tolerances and comply with ISO and quality system certifications. As component dimensions and tolerances continue to shrink, the difficulty of measurement work also increases. With the semiconductor industry constantly seeking various methods to meet increasingly stringent measurement demands, numerous measurement tools have been developed to address these needs, such as measuring the critical dimension (CD) value, thickness, surface morphology, doping concentration, and performing defect analysis of semiconductor components.

[0003] Traditionally, defect detection in semiconductor devices is performed using transmission electron microscopy (TEM) or scanning transmission electron microscopy (STEM). Taking TEM as an example, it uses a high-energy electron beam to irradiate an ultrathin TEM sample, which is then magnified to obtain a 2D image of the sample. The image resolution can reach the atomic level of 0.1 nanometers, used to observe the microstructure or lattice defects of the material. Because TEM involves penetrating the TEM sample with an electron beam, the thickness of the area to be observed must be sufficient for the electron beam to penetrate, for example, less than 2 angstroms. This makes the application of TEM susceptible to limitations in sample preparation. For example, whether the structural defects of the semiconductor device to be observed are indeed located on the ultrathin TEM sample, or whether the prepared TEM sample can present a region of interest (ROI), are practical technical bottlenecks reflected in the application of TEM for detection. Summary of the Invention

[0004] One embodiment of the present invention relates to a sample stage, which includes a base and a first sample support. The base has a first surface. The first sample support is disposed on the first surface of the base, and the top surface of the first sample support has a groove for placing a sample.

[0005] Another embodiment of the present invention relates to a system for modifying a sample, comprising an electron beam source, a sample stage, an ion beam source, and a detector. The electron beam source generates an electron beam. The sample stage is disposed below the electron beam source and has a sample support with a groove on its top surface for placing a sample. The ion beam source generates an ion beam to cut the sample placed on the sample stage. The detector is disposed below the sample stage. The sample stage can be adjusted to change its angle relative to the electron beam source, allowing the electron beam generated by the electron beam source to penetrate the sample and be detected by the detector.

[0006] Another embodiment of the present invention relates to a method for modifying a sample, comprising the steps of: placing a sample on a sample support of a sample stage, the top surface of the sample support having a groove extending to two opposite edges of the top surface such that the sides of the sample are substantially unobstructed by the sample support; and cutting the sample using an ion beam to give the sample a conical profile. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand aspects of this disclosure. It should be noted that, in accordance with standard industry practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures can be arbitrarily increased or decreased for clarity of illustration.

[0008] Figure 1A This is a top view of a sample stage according to some embodiments of the present disclosure.

[0009] Figure 1B This is a side view of a sample stage according to some embodiments of this disclosure.

[0010] Figure 2A This is a schematic diagram of the system structure of a modified sample according to some embodiments of the present disclosure.

[0011] Figure 2B This is a top view of a sample stage according to some embodiments of this disclosure.

[0012] Figure 2C These are sample supports and sample schematic diagrams according to some embodiments of this disclosure.

[0013] Figure 3A and Figure 3B This is a top view of a sample stage according to some embodiments of this disclosure.

[0014] Figure 4A and Figure 4B This is a top view of a semiconductor element according to some embodiments of the present disclosure.

[0015] Figure 4C This is a side view of a semiconductor element according to some embodiments of this disclosure.

[0016] Figure 5A This is a top view of a semiconductor element according to some embodiments of the present disclosure.

[0017] Figure 5B and Figure 5C This is a schematic diagram of a sample according to some embodiments of the present disclosure.

[0018] Figure 6A and Figure 6B These are sample supports and sample schematic diagrams according to some embodiments of this disclosure.

[0019] Figure 7 This is a flowchart of steps according to some embodiments of the present disclosure. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances of various components for implementing the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the first component formed above or on a second component in the following description may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact. Additionally, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “on,” and similar terms may be used herein to describe the relationship of one element or component to another element or component(s), as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise) and therefore the spatial relative descriptors used herein may be interpreted in the same way.

[0022] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or segments, but these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, area, layer, or segment from another. Unless clearly indicated by the context, terms such as “first,” “second,” and “third” as used herein do not imply a sequence or order.

[0023] This disclosure discloses embodiments for locating and observing the three-dimensional structure of defects in semiconductor devices. This includes providing a sample stage whose structure facilitates two-dimensional observation of the sample using a modified sample system, such as STEM, and allows for the sharpening and modification of the sample to enable further analysis of the three-dimensional structure and elemental composition of the defects using atomic probe tomography.

[0024] like Figure 1A The top-down angle and Figure 1B As shown in the side view, in some embodiments, the sample stage 10 includes a base 11 and a first sample support 12. The base 11 has a first surface 11A. The first sample support 12 is disposed on the first surface 11A of the base 11. In some embodiments, the top surface 12A of the first sample support 12 has a groove 13 for placing a sample 14.

[0025] One purpose of the first sample support 12 is to position the sample 14. Since the size of the sample 14 is approximately 100 nm, while the size of the base 11 can range from several micrometers to several millimeters, when the sample 14 is much smaller than the base 11, it is necessary to place the sample 14 on a specific sample support to correctly identify the position of the sample 14 on the sample stage 10, rather than placing the sample 14 directly on the first surface 11A of the base 11. Furthermore, in some embodiments, the groove 13 of the first sample support 12 further provides positioning for the sample 14, for example, by placing the sample 14 at the center of the groove 13, so that the sample 14 can be observed through the position of the groove 13.

[0026] However, considering that when the sample is placed in a trench that is not part of this embodiment, the sample is largely hidden within the trench due to its depth, meaning it can only be observed from a top-down perspective, this means that even if the electron beam penetrates the sample at any angle, it will be blocked by the structure of the sample support and cannot reach the detector, severely affecting the resolution of the sample image. The trench design of this embodiment avoids the aforementioned situation where the electron beam is blocked and cannot reach the detector.

[0027] Regarding the positional relationship between the electron beam and the sample stage, for example in Figure 2AThe illustrated sample modification system, such as a STEM, is shown in the schematic diagram. An electron beam source 21 is located above the sample stage 10 and is used to generate an electron beam to irradiate the sample. In some embodiments, the electron beam source 21 may include components such as a high-voltage system, an electron gun, and a condenser lens (not shown). For example, the high-voltage system can generate an accelerating voltage of 100 keV to 1 MeV, which is fed into the electron gun at the upper end of the microscope tube. This allows the field emission electron gun to heat up and emit a high-brightness electron beam, which then passes through the condenser lens and reaches and penetrates the sample 14.

[0028] The sample stage 10 located below the electron beam source 21, except for its first surface 11A (see above) Figure 1B In addition to having a first sample support 12, in some embodiments, the base 11 of the sample stage 10 may be connected to a clamp 31 relative to its second surface 11B of the first surface 11A (e.g., Figure 2A (As shown in the side view on the right), the clamp 31 is used to move or rotate the sample stage 10 to adjust the angle of the sample stage 10 relative to the electron beam source 21, for example, to make the angle between the electron beam generated by the electron beam source 21 and the first surface 11A less than or equal to 90 degrees, thereby allowing the sample 14, which is partially exposed outside the first sample support 12 through the groove 13, to be penetrated by the electron beam generated by the electron beam source 21. In some embodiments, the sample stage 10 has only a single first sample support 12, or multiple first sample supports 12 arranged in a single row, and when the electron beam irradiates the sample 14 on the first sample support 12, the arrangement direction of the first sample supports 12 is approximately orthogonal to the irradiation direction of the electron beam. In other words, after the electron beam passes through the sample 14 on any one of the first sample supports 12, the electron beam is not blocked by other first sample supports 12 in its path.

[0029] Further reference Figure 2B , Figure 2C These are, respectively, a top view of the sample stage 10 with its tilt angle adjusted by the clamp, and a three-dimensional schematic diagram of the first sample support 12. As shown in the figure, the electron beam generated by the aforementioned electron beam source 21 has a travel path D. E It can irradiate the sample 14 from a position higher than the top surface 12A of the first sample support 12 without being blocked by the structure of the first sample support 12; however, when irradiating the sample 14 from a position lower than the top surface 12A of the first sample support 12, it is necessary to use the openings at the two edges of the groove located on the top surface 12A of the first sample support 12, for example, to make the electron beam's path D E Parallel to the direction of the groove 13, the electron beam can directly irradiate the sample 14 through the electron beam inlet 13A and the electron beam outlet 13B, and pass through the sample stage 10 unobstructed after penetrating the sample 14.

[0030] In some embodiments disclosed herein, the groove 13 formed on the top surface 12A of the first sample support 12 may be structurally further divided into multiple grooves, for example, using Figure 2B Taking the leftmost sample support pillar 12 as an example, its top surface has a first groove 131 and a second groove 132 orthogonal to the first groove 131, forming a cross-shaped recess. The sample 14 is placed at the position where the first groove 131 and the second groove 132 intersect. In some embodiments, the top surface 12A of the first sample support pillar 12 has a plurality of grooves 13, wherein at least one groove extends to the two opposite edges of the top surface 12A to form the aforementioned electron beam inlet 13A and electron beam outlet 13B.

[0031] In some embodiments, the electron beam passing through sample 14 can then pass through multiple magnification elements (not shown) such as objectives, intermediate mirrors, and projection mirrors before reaching detector 22 located under sample stage 10. Detector 22 located under sample stage 10 can be a bright-field scanning transmission microscope detector. When the electron beam generated by electron beam source 21 passes through sample 14, the electron beam interacts with the crystal of sample 14 and generates various scattered electrons below sample stage 10. Electrons with smaller scattering angles enter detector 22 to form a transmitted bright-field image for observation of the two-dimensional structure of sample 14. In some embodiments, electrons penetrating sample 14 may further pass through one or more aperture diaphragms. In some embodiments, detector 22 may include a fluorescent plate, camera, or charge-coupled device (CCD).

[0032] In addition to having a single first sample support 12 or a single row of first sample supports 12, such as Figure 3A As shown, in some embodiments, the sample stage 10 may further include one or more second sample supports 15. The second sample supports 15 are also disposed on the first surface 11A of the base 11 of the sample stage 10, and are not located in the same row as the first sample supports 12, thus giving the sample stage 10 a multi-row sample support structure. Since the electron beam penetrating the sample still needs to travel to the detector 22, the second sample supports 15 are offset from the first sample supports 12 in the direction of electron beam travel to avoid obstructing the electron beam's path. In some embodiments, such as Figure 3A , Figure 3B As shown, the second sample support 15 can be arranged in a single or multiple rows, so that the sample stage as a whole has two, three or more rows of sample supports. However, when setting the second sample support 15, it is necessary to avoid overlapping with the first sample support or other second sample supports 15 in the direction of electron beam travel.

[0033] Traditionally, STEM sample stages are made of copper and are formed using computer numerical control (CNC) processes. However, considering that copper may interfere with elemental analysis of samples, such as generating excessive background noise during mass spectrometry analysis and affecting the determination of sample composition, this disclosure uses silicon as the material for the sample stage 10 in some embodiments. In some embodiments, the base 11 and the first and second sample supports 12 and 15 of the sample stage 10 are all made of silicon, for example, by processing the silicon wafer with a laser to engrave the structure of the sample supports on one side of the silicon wafer and to create grooves on the top surface of the sample supports. In this embodiment, the base 11 and the first and second sample supports 12 and 15 of the sample stage 10 can also be considered as integrally formed. In the example of silicon wafer processing, the silicon wafer can be cut after the sample supports are formed to obtain the required base area size.

[0034] If only STEM is used to observe the two-dimensional structure of the sample, the sample does not need to be processed to have a conical profile. However, one of the purposes of this disclosure is to enable the sample stage 10 and the sample 14 on it to be observed in three dimensions and quantitatively identified in chemical composition using atomic probe tomography (APT) technology. Therefore, in some embodiments, as follows Figure 2A As shown, the sample 14 is further processed and modified using the ion beam source 23, that is, the ion beam generated by the ion beam source 23 is used to cut the sample 14 on the sample stage 10 to give the sample 14 a conical profile. In some embodiments, the ion beam source 23 is disposed above the sample stage 10 and has an angle with the electron beam source 21, the angle being approximately 52 degrees.

[0035] In detail, APT is an atomic-level material analysis technique that can provide three-dimensional images and quantitative chemical composition identification, with high sensitivity. The technique relies on the ionization of individual atoms / clusters on the sample surface and subsequent field evaporation. The sample is prepared in the form of a conical tip. Generally, in order to maintain analytical quality, the sample must meet several requirements: (1) the sample is conical with a vertex radius of less than 100 nm; (2) the sample shape must be symmetrical to avoid forming an elliptical cone; (3) the sample shape angle cannot be too large; and (4) the conical body of the sample must avoid the appearance of microcracks. As for sample preparation technology, it is currently mainly through the use of focused ion beam (FIB). For example, for the target analytical area of ​​semiconductor devices, a protective layer is first deposited with platinum (Pt), nickel (Ni) or other materials, and then a wedge-shaped strip sample is cut out with a width of about 1 to 2 μm and a length of about 15 to 20 μm. First, one end of the sample is cut off and plated onto the manipulator. Then, the other end is cut off, and the sample is removed from the semiconductor device body. Next, the sample is plated onto the sample stage. Afterward, the sample radius is reduced to less than about 100 nm using Annular Milling. Finally, it is cleaned with a low voltage to remove damage layers caused by, for example, gallium (Ga) ions.

[0036] Samples prepared using the above method can be applied to atomic probe tomography (APT) to perform three-dimensional structural scanning of the samples, thereby observing the defects of semiconductor devices from a three-dimensional perspective, including observing the morphology of the defects and analyzing the elemental composition at the location of the defects.

[0037] Therefore, in some embodiments disclosed herein, the ion beam source 23 is used to provide a focused ion beam. For example, gallium can be used as the ion source for the ion beam source 23, taking into account the advantages of gallium, such as its low melting point, low vapor pressure, and good oxidation resistance. When in use, an external electric field is applied to the ion beam source 23 to form a fine tip from liquid gallium. For example, the liquid gallium is drawn into a Taylor cone with a radius of curvature smaller than a threshold radius, causing the gallium to be ionized and ejected, forming a gallium ion beam. The extracted gallium ion beam can be focused using an electric lens, passing through a series of varying apertures to determine the size of the ion beam, and then refocused onto the sample surface, using physical collision to achieve the purpose of cutting. Generally, the size of the ion beam formed by this method is less than 10 nm, which can be used as a tool for precise nanostructure fabrication.

[0038] Furthermore, the samples used in this disclosure can also be used with the ion beam source 23 to mark defects in semiconductor devices. To reduce power consumption, improve performance, and increase transistor density, semiconductor devices have been miniaturized to the nanoscale. Not only are defects difficult to observe directly with the naked eye, but they can also be precisely identified through electrical testing using probes, such as detecting anomalies in electronic components at specific coordinates. However, even if an electrical anomaly is detected through probe testing, and the location of the anomaly is known, it is not as direct as directly locating the electrical anomaly for defect observation. Traditional TEM or STEM requires thinning the sample for observation, but the thinned area may not accurately correspond to the defect location, forcing the operator to search for the defect structure under the microscope, much like looking for a needle in a haystack, even when an electrical anomaly is detected in the semiconductor device.

[0039] In some embodiments disclosed herein, markings can be fabricated using an ion beam source 23, for example, by depositing metal wires onto the surface of a sample using a focused ion beam. Figure 4A The top view of the semiconductor device shown allows for the detection of electrical anomalies in the semiconductor device 40 through electrical testing, that is, the precise location of the defect point 41 can be determined through electrical testing. However, the sample observed in a two-dimensional STEM may be located at other locations of the semiconductor device 40, such as region A, region B, region C, etc., which are not the location of the defect point 41. Therefore, in some embodiments disclosed herein, such as... Figure 4B As shown, after electrical testing, multiple metal lines are deposited directly around the defect point 41 as positioning marks 42 using focused ion beam deposition (FIB). Traditionally, FIB is used to deposit metal lines for rewiring during circuit modifications or to adjust the resistivity of components. In this embodiment, the positioning mark line 42 is used to mark the defect point 41. In some embodiments, the positioning mark 42 is made of platinum (Pt), which provides better contrast and is easier to observe compared to carbon-based materials. The principle of FIB deposition involves supplying a small amount of metal-based precursor gas to the surface of the semiconductor element 40 via a metal tube. The precursor is decomposed by ion beam bombardment, resulting in metal deposition. This can be classified as a type of ion beam-induced deposition (IBID). In some embodiments, similar electron beam-induced deposition (EBID) can also be used to deposit the positioning mark 42.

[0040] like Figure 4BThe diagram shows a top view of a semiconductor element with positioning marks. In some embodiments, the positioning mark 42 may have multiple marking lines 42a, 42b, 42c, and 42d pointing to the defect point 41. In some embodiments, the marking lines 42(ad) within the positioning mark 41 are arranged in a cross shape, with the center of the cross shape indicating the location of the defect point 41. In some embodiments, the marking lines 42(ad) do not touch each other, leaving the defect point 41 uncovered by the marking lines 42(ad). For example, marking lines in the same direction, such as marking lines 42a, 42c, or a combination of marking lines 42b and 42d, have a spacing of less than about 30 nm. Therefore, in some embodiments, the defect point 41 is located within an area of ​​about 30 nm x 30 nm and is surrounded by the positioning mark 42.

[0041] like Figure 4C The cross-sectional view of the semiconductor device shown is along... Figure 4B The line segment FF' is shown in cross-section. In some embodiments, the marker line 42b (and other marker lines) may have a generally square or rectangular cross-sectional structure. In some embodiments, the aspect ratio of the marker line is about 1:1 to about 1:3. In some embodiments, after the positioning mark 42 is made through FIB, an organic colloid (not shown) can be further coated to cover the marker line 42(ad) of the positioning mark 42 as a protective layer for the positioning mark, which can maintain the aspect ratio of the aforementioned marker line 42(ad) without collapsing into a flat shape.

[0042] In some embodiments disclosed herein, after the semiconductor element 40 is confirmed to have a defect point 41 by electrical testing, a positioning mark 42 can be deposited first to locate the defect point 41. Then, in order to further observe the three-dimensional structure of the defect point 41 in a fixed-point manner, the semiconductor element 40 can be cut to obtain a strip sample as described above regarding the preparation method of APT sample, and then plated onto the sample support (e.g., the first sample support 12) of the sample stage 10.

[0043] like Figure 5A A top view of a semiconductor element with positioning marks and Figure 5BThe three-dimensional schematic diagram of the sample disclosed herein shows that, in some embodiments, the sample 51 obtained after cutting the sample region 50 includes at least a portion of the positioning mark 42, which can be plated onto the sample support of the sample stage. In some embodiments, after the positioning mark 42 is formed on the surface of the semiconductor element 40, in addition to the aforementioned organic colloid, other structures may be formed on the surface, such as forming a capping layer or sacrificial layer 43 (see Figure 6 below) to protect the underlying region of interest (ROI), such as the structure containing the defect point 41, from gallium damage. In this embodiment, although the positioning mark 42 is covered, the positioning mark 42 can still locate the defect point 41 during the preparation of the APT sample.

[0044] like Figure 5B As shown, regardless of whether the positioning mark 42 on sample 51 is covered by other structures, the side 420 of the positioning mark 42 can be observed, therefore, in such cases... Figure 5C , Figure 6A and Figure 6B As shown, during the process of gradually cutting the sample radius into a conical profile, the side 420 of the positioning mark 42 can be continuously observed and tracked from the side of the sample 51. This indicates that the sample 51 is still gradually moving closer to the location of the defect point 41 during the cutting process into a conical profile. As mentioned earlier, the material of the positioning mark 42 contains platinum, and it exhibits good contrast with other surrounding materials (e.g., Figure 6A (as shown in the illustration), therefore, the cross-section of the marking line 42(ad) of the positioning mark 42 can be used as the positioning target more clearly. Furthermore, since one end of the marking line 42(ad) points to the defect point 41 but does not cover its position, during the cutting of the sample 51 into a conical profile, it was observed that the side surface of the cone changed from having the marking line 42(ad) to no longer having the marking line, for example... Figure 6A and Figure 6B The illustration indicates that the cut and modified sample 51 has reached or is close to the defect point 41, and the sample 51, along with the sample stage 10, can be moved to perform APT (Aspect-to-Physical Transformation) analysis, which involves three-dimensional image observation and quantitative chemical composition identification of the defect point. In some embodiments, the modified sample 51 has a height of approximately 40 nm, a bottom width of approximately 20 to 30 nm, and a top width of approximately 10 nm.

[0045] Based on the above, as Figure 7As shown, in some embodiments of this disclosure, a method for modifying a sample is disclosed, comprising at least step 601: placing the sample on a sample support of a sample stage, the top surface of the sample support having a groove extending to opposite edges of the top surface so that the sides of the sample are substantially unobstructed by the sample support; and step 602: cutting the sample using an ion beam to give the sample a conical profile. Furthermore, in some embodiments, before placing the sample on the sample stage, this disclosure may measure the electrical properties of the semiconductor element to identify defects and form positioning marks on the semiconductor element, using multiple marking lines of the positioning marks to point to the defects, and then cutting the semiconductor element to obtain the sample, at which point the sample at least includes a portion of the positioning marks. Then, in the step of cutting the sample using an ion beam, portions of the marking lines of the positioning marks are cut to expose their cross-sections, and the locations of the defects are identified using these cross-sections.

[0046] In summary, this disclosure provides a method for three-dimensional structural observation of semiconductor device defects in some embodiments. This method, combined with a novel sample stage structure, allows samples on the stage to be observed not only in two dimensions using electron beams and detectors, but also to be processed by ion beams to cut and modify them into a conical profile for three-dimensional observation and elemental analysis using APT (Alternating Perspective). To improve the accuracy of elemental analysis, this disclosure uses silicon to fabricate the sample stage. Furthermore, to ensure accurate location and precise observation of defects, this disclosure uses positioning markers containing platinum, allowing the position of defects to be confirmed during the process of cutting the sample into a conical profile.

[0047] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0048] Symbol Explanation

[0049] 10: Sample stage

[0050] 11: Base

[0051] 11A: First surface

[0052] 11B: Second surface

[0053] 12: First Sample Support

[0054] 12A: Top surface

[0055] 13: Trench

[0056] 13A: Electron beam inlet

[0057] 13B: Electron beam exit

[0058] 131: First trench

[0059] 132: Second trench

[0060] 14: Sample

[0061] 15: Second Sample Support

[0062] 21: Electron Beam Source

[0063] 22: Detector

[0064] 23: Ion beam source

[0065] 31: Fixture

[0066] 40: Semiconductor components

[0067] 41: Defect Points

[0068] 42: Location Marker

[0069] 42a: Marker line

[0070] 42b: Marker line

[0071] 42c: Marker line

[0072] 42d: Marker line

[0073] 420: Side View

[0074] 43: Sacrificial Layer

[0075] 50: Sample area

[0076] 51: Sample

[0077] 601: Steps

[0078] 602: Steps

[0079] A: Area

[0080] B: Region

[0081] C: Region

[0082] D E : Travel path

[0083] FF': Line segment.

Claims

1. A sample stage, comprising: a base having a first surface; and a first sample pillar disposed on the first surface of the base, a top surface of the first sample pillar having a first trench for placing a sample, wherein the top surface of the first sample pillar further has a second trench orthogonal to the first trench, and a position where the first trench and the second trench are staggered is for placing the sample, wherein the first trench and the second trench each extend to opposite edges of the top surface such that both sides of the sample are substantially unobstructed by the first sample pillar.

2. The sample stage of claim 1, wherein the first trench extends to opposite edges of the top surface.

3. The sample stage of claim 1, wherein the base and the first sample pillar are comprised of silicon.

4. The sample stage of claim 1, further comprising a plurality of second sample pillars disposed on the first surface of the base, and the plurality of second sample pillars are not in the same column as the first sample pillar.

5. A system for modifying a sample, comprising: an electron beam source for generating an electron beam; a sample stage disposed under the electron beam source, having a sample pillar, a top surface of the sample pillar having a first trench and a second trench for placing a sample, the second trench being orthogonal to the first trench; an ion beam source for generating an ion beam to cut the sample placed on the sample stage; and a detector disposed under the sample stage; wherein the sample stage is adjustable to change its angle relative to the electron beam source, such that the electron beam generated by the electron beam source can penetrate the sample along the extension of the first trench or the second trench and be detected by the detector.

6. The system of claim 5, further comprising a clamp connected to the sample stage for moving or rotating the sample stage.

7. A method for modifying a sample, comprising: placing a sample on a sample pillar of a sample stage, a top surface of the sample pillar having a trench extending to opposite edges of the top surface such that both sides of the sample are substantially unobstructed by the sample pillar; and cutting the sample using an ion beam to have a conical profile, wherein before placing the sample on the sample pillar of the sample stage, the method further comprises: forming a positioning mark on a semiconductor device, the positioning mark having a plurality of mark lines pointing to a defect point; wherein in the step of cutting the sample using the ion beam, a portion of the mark lines is cut to expose side surfaces of the mark lines, respectively, and the position of the defect point is identified using a transition from the portion with the mark lines to the portion without the mark lines.

8. The method of claim 7, wherein before placing the sample on the sample pillar of the sample stage, the method further comprises: measuring an electrical property of the semiconductor device to determine the defect point.

9. The method of claim 8, wherein the method further comprises forming a cap layer or a sacrificial layer to cover the mark lines.

10. The method of claim 8, wherein the method further comprises coating the marking lines with an organic colloid.

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