Photoelectric conversion device

Abstract

A photoelectric conversion apparatus is disclosed. A photoelectric conversion apparatus including a pixel array including a first pixel and a second pixel is provided. The first pixel includes a photoelectric conversion unit and photoelectrically converts incident light to generate a signal corresponding to the incident light, the photoelectric conversion unit including a first semiconductor region of a first conductivity type as a charge accumulation layer, and the second pixel includes a second semiconductor region of the first conductivity type and a transistor including a gate and a first main electrode formed of a third semiconductor region connected to the second semiconductor region.

Description

Technical Field

[0001] This disclosure relates to photoelectric conversion equipment. Background Technology

[0002] Japanese Patent Application Publication No. 2002-110955 discloses a photoelectric conversion device in which a noise charge absorption region is arranged inside a unit array to reduce the influence of noise charge. In such a noise charge absorption region, the potential of the semiconductor region is fixed at a constant potential.

[0003] For pixel configurations such as those disclosed in Japanese Patent Application Publication No. 2002-110955, which include structures that discharge noise charges from semiconductor regions that may cause noise, there may be room for further performance improvements. Summary of the Invention

[0004] The present disclosure aims to provide a photoelectric conversion device that can more properly discharge noise charge.

[0005] According to one aspect of this disclosure, a photoelectric conversion device is provided, comprising: a pixel array including a first pixel and a second pixel; a scanning circuit that outputs a control signal to the pixel array; and an output line connected to the first pixel and the second pixel. The first pixel includes a photoelectric conversion unit that performs photoelectric conversion on incident light to output a signal corresponding to the incident light to the output line. The photoelectric conversion unit includes a first semiconductor region of a first conductivity type as a charge accumulation layer. The second pixel includes: a second semiconductor region of the first conductivity type; a transistor including a first main electrode formed by a third semiconductor region connected to the second semiconductor region, a gate connected to the scanning circuit, and a second main electrode formed by a fourth semiconductor region; a first contact connected between the fourth semiconductor region and the output line; and a second contact supplied with a power potential and connected to the third semiconductor region.

[0006] According to one aspect of this disclosure, a photoelectric conversion device including a pixel array is provided, the pixel array including a first pixel and a second pixel. The first pixel includes a photoelectric conversion unit and performs photoelectric conversion on incident light to output a signal corresponding to the incident light, the photoelectric conversion unit including a first semiconductor region of a first conductivity type as a charge accumulation layer. The second pixel includes: a second semiconductor region of the first conductivity type; a transistor including a first main electrode and a gate formed by a third semiconductor region connected to the second semiconductor region; an insulating layer having a first hole and a second hole; a first conductive member disposed through the first hole and connected between a power supply wiring supplied with a power potential and the third semiconductor region; and a second conductive member disposed through the second hole and connected between the power supply wiring and the gate.

[0007] Other features of the various embodiments will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a schematic configuration of a photoelectric conversion device according to the first embodiment.

[0009] Figure 2A This is a circuit diagram of the effective pixels according to the first embodiment.

[0010] Figure 2B This is a circuit diagram of the charge discharge pixel according to the first embodiment.

[0011] Figure 3A It is a schematic plan view of the effective pixels according to the first embodiment.

[0012] Figure 3B , Figure 3C and Figure 3D This is a schematic cross-sectional view of the effective pixels according to the first embodiment.

[0013] Figure 4A This is a schematic plan view of the charge discharge pixel according to the first embodiment.

[0014] Figure 4B , Figure 4C and Figure 4D This is a schematic cross-sectional view of the charge discharge pixel according to the first embodiment.

[0015] Figure 5 This is a schematic diagram illustrating the layout of the photoelectric conversion device according to the second embodiment.

[0016] Figure 6 This is a circuit diagram of a charge discharge pixel according to the third embodiment.

[0017] Figure 7A This is a schematic plan view of a charge discharge pixel according to the third embodiment.

[0018] Figure 7B , Figure 7C and Figure 7D This is a schematic cross-sectional view of a charge discharge pixel according to the third embodiment.

[0019] Figure 8 This is a schematic diagram illustrating the layout of the photoelectric conversion device according to the fourth embodiment.

[0020] Figure 9A This is a circuit diagram of the effective pixels according to the fifth embodiment.

[0021] Figure 9B This is a circuit diagram of a charge discharge pixel according to the fifth embodiment.

[0022] Figure 10A This is a schematic plan view of the effective pixels according to the fifth embodiment.

[0023] Figure 10B This is a schematic plan view of the charge discharge pixel according to the fifth embodiment.

[0024] Figure 11 This is a circuit diagram of the effective pixels according to the sixth embodiment.

[0025] Figure 12 This is a circuit diagram of the effective pixels according to the sixth embodiment.

[0026] Figure 13A , Figure 13B and Figure 13C This is a schematic plan view of the effective pixels according to the sixth embodiment.

[0027] Figure 14 It is a table listing the capacitance of each portion of the effective pixels according to the sixth embodiment.

[0028] Figure 15 This is a block diagram of the apparatus according to the sixth embodiment.

[0029] Figure 16A and Figure 16B This is a block diagram of the apparatus according to the seventh embodiment. Detailed Implementation

[0030] Example embodiments will now be described in detail with reference to the accompanying drawings. Throughout the drawings, the same or corresponding elements are labeled with common reference numerals, and their descriptions may be omitted or simplified.

[0031] First Embodiment

[0032] Figure 1 This is a block diagram illustrating a general configuration of the photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a pixel array 10, a vertical scanning circuit 16, a column amplifier circuit 18, a horizontal scanning circuit 20, an output circuit 24, and a control circuit 22. These circuits can be formed on a semiconductor substrate such as a silicon substrate. It should be noted that although the photoelectric conversion device of this embodiment is assumed to be configured as an imaging device for acquiring images, the photoelectric conversion device is not limited thereto. For example, the photoelectric conversion device may be a focus detection device, a ranging device, a time-of-flight (TOF) camera, etc.

[0033] The pixel array 10 includes a plurality of pixels 100 arranged to form a plurality of rows and a plurality of columns. Note that, as described below, a pixel 100 can be any of an effective pixel, a charge-discharge pixel, and an optical black (OB) pixel.

[0034] The vertical scanning circuit 16 is a scanning circuit that supplies control signals via control signal lines 14 provided on each row of pixels 100, and the control signals are used to control the transistors included in pixels 100 to be turned on (on state) or off (off state). The vertical scanning circuit 16 can be formed by logic circuits such as shift registers, address decoders, etc. Here, since the control signals supplied to each pixel 100 can include various types of control signals, the control signal lines 14 on each row can be formed by a set of multiple drive wirings. Output lines 12 are provided on each column of pixels 100, and signals from pixels 100 are read column by column onto the output lines 12.

[0035] The column amplifier circuit 18 amplifies the signal output to the output line 12. Additionally, the column amplifier circuit 18 can perform correlated double sampling processing using an N signal based on the reset state of pixel 100 and an S signal generated by photoelectric conversion at pixel 100. The horizontal scan circuit 20 supplies control signals to control the switches connected to the amplifiers of the column amplifier circuit 18 to turn them on or off. The horizontal scan circuit 20 can be formed by logic circuits such as shift registers and address decoders. The output circuit 24 is formed by buffer amplifiers, differential amplifiers, etc., and outputs the signal from the column amplifier circuit 18 to a signal processing unit outside the photoelectric conversion device. Note that the photoelectric conversion device can be configured to also have an AD conversion unit, thereby outputting a digital image signal. The control circuit 22 controls the timing of the operation of the vertical scan circuit 16, the column amplifier circuit 18, and the horizontal scan circuit 20.

[0036] Figure 2A This is a circuit diagram of the effective pixel 100a according to this embodiment, and Figure 2B This is a circuit diagram of the charge discharge pixel 100b according to this embodiment. The effective pixel 100a and the charge discharge pixel 100b are... Figure 1 An example of pixel 100 is shown in the diagram. Effective pixel 100a (first pixel) is a pixel that photoelectrically converts incident light and outputs a signal corresponding to the incident light. Charge-discharging pixel 100b (second pixel) is a pixel that includes a semiconductor region supplied with a power supply potential and discharges noise charge to power wiring. Effective pixels 100a and charge-discharging pixels 100b are arranged in pixel array 10. Figure 2A and Figure 2B The illustration shows a single active pixel 100a and a single charge-discharging pixel 100b arranged in pixel array 10 as an example. Note that in the following description, it is assumed that the signal charge is an electron. However, the signal charge can be a hole, and in this case, the conductivity type of each semiconductor region will be reversed.

[0037] First, refer to Figure 2AThe configuration of effective pixel 100a is described. Effective pixel 100a includes a photoelectric conversion unit PD, a floating diffuser FD, a transfer transistor M1, a reset transistor M2, an amplifier transistor M3, and a selection transistor M4. Each of these transistors is formed from a MOS transistor with a gate as a control electrode. Control signals PTX(n), PRES(n), and PSEL(n) for controlling the transfer transistor M1, reset transistor M2, and selection transistor M4 are input to the gates of these transistors from the vertical scan circuit 16 via control signal line 14. Note that "n" in parentheses indicates the row number of the effective pixel 100a to which these signals are input.

[0038] A photoelectric conversion unit (PD) is a photoelectric conversion element that performs photoelectric conversion to generate and accumulate charges corresponding to incident light. The PD can be formed from a photodiode formed inside a semiconductor substrate. The anode of the photodiode forming the PD is connected to a grounding wire supplied with a ground potential, and the cathode is connected to the source of the transmission transistor M1.

[0039] The drain of transfer transistor M1, the source of reset transistor M2, and the gate of amplifier transistor M3 are connected to the floating diffuser FD. When turned on, transfer transistor M1 transfers the charge of photoelectric conversion unit PD to the floating diffuser FD. Due to the capacitance of the floating diffuser FD, its potential varies according to the charge transferred from photoelectric conversion unit PD.

[0040] The drains of reset transistor M2 and amplifier transistor M3 are connected to a power supply line with a power supply potential. The source of amplifier transistor M3 is connected to the drain of select transistor M4. The source of select transistor M4 is connected to output line 12 at node N1. Amplifier transistor M3, together with a constant current source (not shown) connected to output line 12, forms a source follower circuit. This source follower circuit outputs a signal based on the potential of the floating diffuser FD to output line 12 via select transistor M4. When turned on, reset transistor M2 resets the potential of the floating diffuser FD.

[0041] The effective pixel 100a has a microlens and a color filter arranged in the optical path until the incident light is guided to the photoelectric conversion unit PD. The microlens focuses the incident light into the photoelectric conversion unit PD. The color filter selectively allows light of a predetermined color to pass through.

[0042] Next, we will refer to Figure 2B Describe the configuration of charge discharge pixel 100b. For example... Figure 2BAs illustrated, charge discharge pixel 100b has a circuit configuration that excludes effective pixel 100a, including transmission transistor M1, reset transistor M2, and amplifier transistor M3. The anode of the photodiode forming the photoelectric conversion unit PD is connected to a ground wiring supplied with a ground potential, and the cathode is connected to a power supply wiring with a power supply potential and the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line 12 at node N1. Therefore, when the selection transistor M4 is turned on according to the control signal PSEL(n), a potential based on the power supply potential is output to the output line 12.

[0043] Figure 3A This is a schematic plan view of the effective pixel 100a according to this embodiment. Figure 3A The diagram illustrates the planar layout of effective pixels 100a relative to a planar view of a semiconductor substrate on which photoelectric conversion devices are formed. Figure 3B , Figure 3C and Figure 3D This is a schematic cross-sectional view of the effective pixel 100a according to this embodiment. Figure 3B , Figure 3C and Figure 3D The schematic diagram shows the respective directions along Figure 3A The figures show cross-sectional views taken along lines A-A', B-B', and C-C'. The structure of the effective pixel 100a will be described with reference to these figures.

[0044] The effective pixel 100a has semiconductor regions 101, 102, 103, 104, 105, and 121 disposed in the semiconductor substrate 120, and a device isolation region 106. Additionally, the effective pixel 100a has gates 107, 108, 109, and 110, contacts 111, 112, 113, 114, 115, 116, and 117, wiring 118, and an insulating layer 122 disposed on or above the semiconductor substrate 120. Each of these contacts is formed from a conductive member arranged to pass through a hole penetrating the insulating layer 122.

[0045] Semiconductor region 101 (first semiconductor region) is an n-type (first conductivity type) semiconductor region. Semiconductor region 121, disposed on the front side of semiconductor substrate 120 opposite to semiconductor region 101, is a p-type semiconductor region. Semiconductor region 101 and semiconductor region 121 form a pn junction, which is formed with... Figure 2A The embedded photodiode corresponds to the photoelectric conversion unit PD in the image. Semiconductor region 101 serves as a charge accumulation layer. Additionally, semiconductor region 121 serves as a surface protective layer for the embedded photodiode. Using such an embedded photodiode can reduce noise that may occur at interfaces such as the substrate surface. Note that in... Figure 3A The semiconductor region 121 is omitted in the text.

[0046] Gates 107, 108, 109, and 110 correspond to the gates of the transfer transistor M1, the reset transistor M2, the amplifier transistor M3, and the select transistor M4, respectively. Contacts 111, 113, and 116 are connected to gates 107, 108, and 110, respectively, and control signals are input to gates 107, 108, and 110 via these contacts. Semiconductor region 102 is an n-type semiconductor region forming a floating diffuse FD. Semiconductor region 102 also forms the drain of transfer transistor M1 and the source of reset transistor M2. Contact 112 is connected to semiconductor region 102, and contact 115 is connected to gate 109. Contacts 112 and 115 are interconnected via wiring 118 arranged in a wiring layer laminated on insulating layer 122.

[0047] Semiconductor region 103 is an n-type semiconductor region that forms the drain of reset transistor M2 and the drain of amplifier transistor M3. Contact 114 is connected to semiconductor region 103 and to power supply wiring disposed in a layer on insulating layer 122.

[0048] Semiconductor region 104 is an n-type semiconductor region forming the source of amplifier transistor M3 and the drain of select transistor M4. Semiconductor region 105 is an n-type semiconductor region forming the source of select transistor M4. Contact 117 is connected to semiconductor region 105 and to output line 12. That is, contact 117 corresponds to... Figure 2A Node N1 in the diagram.

[0049] It should be noted that semiconductor regions 102, 103, 104, and 105 are each n-type semiconductor regions with a higher impurity concentration than semiconductor region 101. This reduces resistance. Component isolation region 106 can be shallow trench isolation (STI), localized oxidation of silicon (LOCOS), etc.

[0050] Figure 4A This is a schematic plan view of the charge discharge pixel 100b according to this embodiment. Figure 4A The diagram illustrates the planar layout of charge discharge pixels 100b relative to a planar view of a semiconductor substrate on which photoelectric conversion devices are formed. Figure 4B , Figure 4C and Figure 4D This is a schematic cross-sectional view of the charge discharge pixel 100b according to this embodiment. Figure 4B , Figure 4C and Figure 4D The schematic diagram shows the respective directions along Figure 4A The figures show cross-sectional views taken along lines D-D', E-E', and F-F'. The structure of charge-discharging pixel 100b will be described with reference to these figures. Note that descriptions of features common to the effective pixels 100a may be omitted.

[0051] The charge discharge pixel 100b has semiconductor regions 131, 132, 133, and 105 disposed in the semiconductor substrate 120, and a device isolation region 106. Additionally, the charge discharge pixel 100b has a gate 110, contacts 114, 116, and 117 disposed on or above the semiconductor substrate 120, and an insulating layer 122. These contacts are each formed from a conductive member arranged to pass through a hole penetrating the insulating layer 122. (See reference...) Figure 2B As described, no transmission transistor M1, reset transistor M2, or amplifier transistor M3 are arranged in the charge discharge pixel 100b, nor are their corresponding gates arranged there.

[0052] Semiconductor region 131 (the second semiconductor region) is an n-type semiconductor region. Semiconductor region 133, disposed on the front side of the semiconductor substrate 120 opposite to semiconductor region 131, is a p-type semiconductor region. Note that in... Figure 4A The depiction of semiconductor region 133 is omitted. Semiconductor region 132 (the third semiconductor region) is an n-type semiconductor region and is connected to semiconductor region 131. Note that... Figure 4A The dashed line between semiconductor region 131 and semiconductor region 132 in the diagram represents the end of semiconductor region 131.

[0053] Gate 110 corresponds to the gate of select transistor M4. Contact 116 is connected to gate 110, and a control signal is input to gate 110 via contact 116. Semiconductor region 132 extends from the gate of select transistor M4 to semiconductor region 131 and forms the drain (first main electrode) of select transistor M4. In addition, contact 114 (second contact) is connected to semiconductor region 132 and to power wiring disposed in a layer above insulating layer 122.

[0054] Semiconductor region 105 (fourth semiconductor region) is an n-type semiconductor region that forms the source (second main electrode) of selection transistor M4. Contact 117 (first contact) is connected to semiconductor region 105 and to output line 12. That is, contact 117 corresponds to... Figure 2B Node N1 in the diagram.

[0055] It should be noted that semiconductor region 132 is an n-type semiconductor region with a higher impurity concentration than semiconductor region 131. Therefore, the contact 114 supplied with power potential and semiconductor region 132 can be connected to each other with low resistance, which improves charge discharge performance. Additionally, semiconductor region 105 is also an n-type semiconductor region with a higher impurity concentration than semiconductor region 101. This reduces resistance.

[0056] Unlike the effective pixel 100a, in the charge discharge pixel 100b, the semiconductor region 133 is only disposed near the element isolation region 106. This reduces the impact of junction leakage that may occur when a pn junction exists between the high-concentration n-type semiconductor region 132 and the high-concentration p-type semiconductor region 133. Note that the p-type semiconductor region 133 may not be disposed in the charge discharge pixel 100b, and the same effect is achieved in this case.

[0057] As described above, the photoelectric conversion device of this embodiment has a charge discharge pixel 100b, which has a circuit configuration in which the effective pixel 100a is excluded, excluding the transmission transistor M1, the reset transistor M2, and the amplifier transistor M3. The charge discharge pixel 100b can discharge nearby noise charge from the semiconductor region 131 via the semiconductor region 132 and the contact 114 to the power supply wiring. Therefore, according to this embodiment, a photoelectric conversion device that can more appropriately discharge noise charge can be provided.

[0058] It should be noted that, although in Figure 4A , Figure 4C and Figure 4D The illustration shows an example where the contact 114 of the charge discharge pixel 100b is arranged at the same location as the contact of the active pixel 100a, but the embodiment is not limited to this. For example, the contact connected to the power supply wiring can be directly connected to the semiconductor region 131. Alternatively, multiple contacts connected to the power supply wiring can be arranged.

[0059] Furthermore, transistor M4 is arranged in the charge discharge pixel 100b of this embodiment in the same manner as the effective pixel 100a. This enables the charge discharge pixel 100b to output a signal whose level corresponds to the power supply potential in response to the control signal PSEL(n). The signal whose level corresponds to the power supply potential can be used, for example, for signal correction.

[0060] Ideally, the semiconductor region 101 of the effective pixel 100a and the semiconductor region 131 of the charge-discharge pixel 100b should have the same shape in the plan view. This identical shape reduces the inter-pixel characteristic variations that would otherwise result from manufacturing process inhomogeneities caused by differences in the layout of neighboring elements between the case where another effective pixel 100a is arranged near an effective pixel 100a and the case where the charge-discharge pixel 100b is arranged near an effective pixel 100a.

[0061] Second Embodiment

[0062] In this embodiment, an example of the layout when the OB pixels are arranged inside the pixel array 10 will be described. Since the configuration of the circuit blocks of the photoelectric conversion device, the structure of the effective pixel 100a and the charge discharge pixel 100b, etc., are the same as those in the first embodiment, their description will be omitted.

[0063] Figure 5 This is a schematic diagram illustrating the layout of the photoelectric conversion device according to this embodiment. Figure 5 As illustrated, pixel array 10, vertical scanning circuit 16, column amplifier circuit 18, horizontal scanning circuit 20, and control circuit 22 are arranged on a semiconductor substrate. The vertical scanning circuit 16, column amplifier circuit 18, horizontal scanning circuit 20, and control circuit 22 represent examples of peripheral circuitry arranged around pixel array 10, and the arrangement of these circuits is not limited to those illustrated. Furthermore, circuitry other than these may be arranged around pixel array 10.

[0064] The pixel array 10 has an effective pixel region R1, a charge discharge pixel region R2, and an OB pixel region R3. The effective pixel region R1 (first pixel region) is the region in which the effective pixels 100a described in the first embodiment are arranged to form multiple rows and multiple columns.

[0065] The OB pixel region R3 (third pixel region) is the region where OB pixels are arranged to form multiple rows and multiple columns. The OB pixel has the same circuit configuration as the effective pixel 100a described in the first embodiment, and is a pixel where the photoelectric conversion unit PD is covered by a light-shielding film such as a metal film. Therefore, since light does not enter the photoelectric conversion unit PD of the OB pixel, the OB pixel can output a black level signal. For example, this black level signal can be used for signal correction. The OB pixel region R3 is arranged on the outer periphery of the effective pixel region R1. For example, the OB pixel region R3 can be arranged as follows: Figure 5 The pixels are arranged as shown in the diagram along both sides of the effective pixel area R1, or they can be arranged along three or four sides of the effective pixel area R1.

[0066] The charge discharge pixel region R2 (second pixel region) is the region in the first embodiment where the charge discharge pixels 100b are arranged to form multiple rows and multiple columns. The charge discharge pixel region R2 is arranged around the periphery of the effective pixel region R1 and the OB pixel region R3 to surround these regions.

[0067] In this embodiment, the charge discharge pixel region R2 is arranged on the outer periphery of the OB pixel region R3. The charge discharge pixel 100b inside the charge discharge pixel region R2 discharges noise charge, thereby, in particular, reducing the inflow of noise charge from the outer periphery of the OB pixel region R3 into the OB pixel. Therefore, in this embodiment, in addition to the advantageous effects described in the first embodiment, the generation of black level signals from the OB pixel can be achieved more accurately.

[0068] Third Embodiment

[0069] In this embodiment, a variation of the circuit configuration and structure of the charge discharge pixel 100b in the first embodiment will be described. Since the configuration of the circuit blocks of the photoelectric conversion device, the structure of the effective pixel 100a, etc., are the same as those in the first embodiment, their description will be omitted.

[0070] Figure 6 This is a circuit diagram of the charge discharge pixel 100c according to this embodiment. The charge discharge pixel 100c (the second pixel) is the same as the charge discharge pixel 100b in the first embodiment in that both pixels discharge noise charge from the semiconductor region supplied with power potential, but it differs from the charge discharge pixel 100b in circuit configuration and structure.

[0071] like Figure 6 As illustrated, charge discharge pixel 100c has a circuit configuration that excludes the effective pixel 100a, which includes the transmission transistor M1 and the reset transistor M2. In other words, charge discharge pixel 100c has a circuit configuration that includes the charge discharge pixel 100b, which includes the amplifier transistor M3.

[0072] The anode of the photodiode forming the photoelectric conversion unit PD is connected to a grounding wire supplied with a ground potential. The cathode of the photodiode, the gate of amplifier transistor M3, and the drain of amplifier transistor M3 are connected to a power supply wire with a power supply potential. The source of amplifier transistor M3 is connected to the drain of select transistor M4. The source of select transistor M4 is connected to output line 12 at node N1. Amplifier transistor M3, together with a constant current source (not shown) connected to output line 12, forms a source follower circuit. Therefore, when select transistor M4 is turned on in response to the control signal PSEL(n), a potential based on the power supply potential is output to output line 12.

[0073] Figure 7A This is a schematic plan view of the charge discharge pixel 100c according to this embodiment. Figure 7A The diagram illustrates the planar layout of charge discharge pixels 100c relative to a planar view of a semiconductor substrate on which photoelectric conversion devices are formed. Figure 7B , Figure 7C and Figure 7DThis is a schematic cross-sectional view of the charge discharge pixel 100c according to this embodiment. Figure 7B , Figure 7C and Figure 7D The schematic diagram shows the respective directions along Figure 7A The figures show cross-sectional views taken along lines G-G', H-H', and I-I'. The structure of charge-discharging pixel 100c will be described with reference to these figures. Note that descriptions of features common to effective pixel 100a or charge-discharging pixel 100b may be omitted.

[0074] The charge discharge pixel 100c has semiconductor regions 131, 133, 142, 104, and 105 disposed in the semiconductor substrate 120, and a device isolation region 106. Additionally, the charge discharge pixel 100c has gates 109 and 110, contacts 112, 143, 115, 116, and 117 disposed on or above the semiconductor substrate 120, and an insulating layer 122. These contacts are each formed from a conductive member arranged to pass through a hole penetrating the insulating layer 122. (See reference...) Figure 6 As described, no transmission transistor M1 and reset transistor M2 are arranged in the charge discharge pixel 100c, and no corresponding gate is arranged there.

[0075] Semiconductor region 131 (the second semiconductor region) is an n-type semiconductor region. Semiconductor region 133, disposed on the front side of the semiconductor substrate 120 opposite to semiconductor region 131, is a p-type semiconductor region. Note that in... Figure 7A The depiction of semiconductor region 133 is omitted. Semiconductor region 142 (the third semiconductor region) is an n-type semiconductor region and is connected to semiconductor region 131. Note that... Figure 7A The dashed line between semiconductor region 131 and semiconductor region 142 in the diagram represents the end of semiconductor region 131.

[0076] Gates 109 and 110 correspond to the gates of amplifier transistor M3 and select transistor M4, respectively. Contact 116 is connected to gate 110, and a control signal is input via contact 116. Semiconductor region 142 extends from gate 109 of amplifier transistor M3 to semiconductor region 131 and forms the drain (first main electrode) of amplifier transistor M3. Additionally, contacts 112 and 143 (first conductive members passing through a first hole) are connected to semiconductor region 142, and contact 115 (second conductive member passing through a second hole) is connected to gate 109. Contacts 112, 143, and 115 are interconnected via wiring 118 arranged in a wiring layer laminated on insulating layer 122. A power supply potential is provided to wiring 118 (power supply wiring).

[0077] Semiconductor region 104 is an n-type semiconductor region forming the source of amplifier transistor M3 and the drain of select transistor M4. Semiconductor region 105 is an n-type semiconductor region forming the source of select transistor M4. Contact 117 is connected to semiconductor region 105 and to output line 12. That is, contact 117 corresponds to... Figure 6 Node N1 in the diagram.

[0078] It should be noted that semiconductor region 142 is an n-type semiconductor region with a higher impurity concentration than semiconductor region 132. Therefore, the contact 112 or contact 143, which is supplied with a power potential, and semiconductor region 142 can be connected to each other with low resistance, which improves charge discharge performance. Additionally, semiconductor regions 104 and 105 are also n-type semiconductor regions with a higher impurity concentration than semiconductor region 101. This reduces resistance.

[0079] As described above, the photoelectric conversion device of this embodiment has a charge discharge pixel 100c, which has a circuit configuration in which the effective pixel 100a is excluded from the transmission transistor M1 and the reset transistor M2. The charge discharge pixel 100c can discharge nearby noise charge from the semiconductor region 131 via the semiconductor region 142 and contacts 112 and 143 to the wiring 118 in the same manner as in the first embodiment. Therefore, according to this embodiment, a photoelectric conversion device that can more effectively discharge noise charge can be provided.

[0080] In the charge-discharge pixel 100c of this embodiment, the amplifier transistor M3 and the selection transistor M4 are arranged in the same manner as in the effective pixel 100a. Therefore, in response to the control signal PSEL(n), the charge-discharge pixel 100c can output a potential that is substantially the same as the N signal having a level based on the pixel's reset state. For example, this output signal can be used for signal correction. In this embodiment, because the N signal output by the effective pixel 100a and the signal output by the charge-discharge pixel 100c are at substantially the same level, this reduces the effects of potential changes, etc., between the case where the effective pixel 100a is connected to the output line 12 and the case where the charge-discharge pixel 100c is connected to the same output line 12.

[0081] It should be noted that, for the same reasons as described in the first embodiment, it is desirable that, in this embodiment, the semiconductor region 101 of the effective pixel 100a and the semiconductor region 131 of the charge discharge pixel 100c also have the same shape in the plan view. Furthermore, the charge discharge pixel 100c of this embodiment can be arranged in the charge discharge pixel region R2 of the second embodiment, and obtain the same advantageous effects as described in the second embodiment.

[0082] Fourth embodiment

[0083] In this embodiment, a variation of the layout of the pixel array 10 in the second embodiment will be described. Since other features are the same as those in the second embodiment, their description will be omitted.

[0084] Figure 8 This is a schematic diagram illustrating the layout of the photoelectric conversion device according to this embodiment. Figure 8 In the second embodiment Figure 5 The difference in the pixel array 10 shown in the diagram lies in the arrangement of the effective pixel region R1, the charge discharge pixel region R2, and the OB pixel region R3. For example... Figure 8 As illustrated in the diagram, in this embodiment, a charge discharge pixel region R2 (second pixel region) is also arranged between the effective pixel region R1 (first pixel region) and the OB pixel region R3 (third pixel region). Therefore, in this embodiment, in addition to the advantageous effects of the second embodiment, noise charge flowing from the effective pixel region R1 into the OB pixel is reduced. Therefore, in this embodiment, compared with the second embodiment, the generation of black level signals from the OB pixel can be achieved more accurately.

[0085] It should be noted that in this embodiment, the charge discharge pixel 100b of the first embodiment can be arranged in the charge discharge pixel region R2, or the charge discharge pixel 100c of the third embodiment can be arranged in the charge discharge pixel region R2.

[0086] Fifth Embodiment

[0087] In this embodiment, variations of the circuit configuration and structure of the effective pixel 100a and charge discharge pixels 100b and 100c in the first and third embodiments will be described. Since the configuration of the circuit blocks of the photoelectric conversion device is the same as that in the first embodiment, its description will be omitted.

[0088] Figure 9A This is a circuit diagram of the effective pixel 100d according to this embodiment, and Figure 9B This is a circuit diagram of the charge discharge pixel 100e according to this embodiment. First, in the configuration of the effective pixel 100d, reference will be made to... Figure 9A Features that differ from the effective pixel 100a in the first embodiment are described.

[0089] The effective pixel 100d (first pixel) of this embodiment differs from the effective pixel 100a of the first embodiment in that two photoelectric conversion units PDa and PDb, and two transmission transistors M1a and M1b are arranged in a single effective pixel 100d. The anodes of the photoelectric conversion units PDa and PDb are connected to a grounding wire supplied with a ground potential. The cathode of the photoelectric conversion unit PDa is connected to the source of the transmission transistor M1a, and the cathode of the photoelectric conversion unit PDb is connected to the source of the transmission transistor M1b. Control signals PTXa(n) and PTXb(n) are input from the vertical scanning circuit 16 to the gates of the transmission transistors M1a and M1b via control signal line 14, respectively. The drain of the transmission transistor M1a, the drain of the transmission transistor M1b, the source of the reset transistor M2, and the gate of the amplifier transistor M3 are connected to the floating diffusion FD.

[0090] The effective pixel 100d has a microlens and a color filter arranged in the optical path until the incident light is guided to the photoelectric conversion unit PD. The microlens converges the incident light into the photoelectric conversion units PDa and PDb. The color filter selectively allows light of a predetermined color to pass through. In this embodiment, the two PDa and PDb are configured to share a single microlens. Therefore, since light passing through different pupil regions of the same microlens enters the two PDa and PDb, the signals generated by the photoelectric conversion units PDa and PDb respectively can be used as ranging signals.

[0091] Next, in the configuration of the charge discharge pixel 100e, reference will be made to Figure 9B Features that differ from the charge discharge pixel 100c of the third embodiment are described. For example... Figure 9B As illustrated, charge discharge pixel 100e (the second pixel) has a circuit configuration that excludes the effective pixel 100d, which is composed of transmission transistors M1a and M1b and reset transistor M2. The anodes of the two photodiodes forming photoelectric conversion units PDa and PDb are connected to a ground wiring supplied with a ground potential. The cathodes of the two photodiodes, the gate of amplifier transistor M3, and the drain of amplifier transistor M3 are connected to a power supply wiring with a power supply potential.

[0092] Figure 10A This is a schematic plan view of the effective pixel 100d according to this embodiment, and illustrates the planar layout of the effective pixel 100d relative to the plan view of the semiconductor substrate on which the photoelectric conversion device is formed. Figure 10B This is a schematic plan view of the charge discharge pixel 100e according to this embodiment, illustrating the planar layout of the charge discharge pixel 100e relative to a plan view of a semiconductor substrate on which a photoelectric conversion device is formed. First, refer to Figure 10ADescribe the structure of effective pixel 100d. Note that the description of features common to effective pixel 100a can be omitted.

[0093] The effective pixel 100d has semiconductor regions 201a, 201b, 202, 203a, 203b, 204a, 204b, and 205 disposed in a semiconductor substrate, and a device isolation region 206. Additionally, the effective pixel 100d has gates 207a, 207b, 208, 209, and 210, contacts 211a, 211b, 212, 213, 214a, 214b, 215, 216, 217, 250a, and 250b, and wiring 218 disposed on or above the semiconductor substrate. Each of these contacts is formed from a conductive member, which is arranged as a hole penetrating an insulating layer.

[0094] Semiconductor regions 201a and 201b (first semiconductor regions) are n-type semiconductor regions. In the same manner as in the first embodiment, p-type semiconductor regions (not shown) can be arranged on the front side of the semiconductor substrate relative to semiconductor regions 201a and 201b, and the photodiode in this embodiment can also be an embedded photodiode.

[0095] Gates 207a, 208b, 208, 209, and 210 correspond to the gates of transfer transistors M1a, M1b, reset transistor M2, amplifier transistor M3, and select transistor M4, respectively. Contacts 211a, 211b, 213, and 216 are connected to gates 207a, 207b, 208, and 210, respectively, and control signals are input via these contacts. Semiconductor region 202 is an n-type semiconductor region forming a floating diffuse FD. Additionally, semiconductor region 202 also forms the drains of transfer transistors M1a and M1b and the source of reset transistor M2. Contact 212 is connected to semiconductor region 202, and contact 215 is connected to gate 209. Contacts 212 and 215 are interconnected via wiring arranged in a wiring layer laminated on an insulating layer.

[0096] Semiconductor region 203a is an n-type semiconductor region forming the drain of reset transistor M2, and semiconductor region 203b is an n-type semiconductor region forming the drain of amplifier transistor M3. Contact 214a is connected to semiconductor region 203a, and contact 214b is connected to semiconductor region 203b. Contacts 214a and 214b are connected to wiring 218, which is a power supply wiring disposed in a layer on an insulating layer.

[0097] Semiconductor region 204a is an n-type semiconductor region forming the source of amplifier transistor M3, and semiconductor region 204b is an n-type semiconductor region forming the drain of selection transistor M4. Contact 250a is connected to semiconductor region 204a, and contact 250b is connected to semiconductor region 204b. Contacts 250a and 250b are connected to each other by wiring disposed in a layer on an insulating layer.

[0098] Semiconductor region 205 is an n-type semiconductor region that forms the source of selection transistor M4. Contact 217 is connected to semiconductor region 205 and also to output line 12. That is, contact 217 corresponds to... Figure 9A Node N1 in the diagram.

[0099] It should be noted that semiconductor regions 202, 203a, 203b, 204a, 204b, and 205 are n-type semiconductor regions with a higher impurity concentration than semiconductor regions 201a and 201b. This reduces resistance. Component isolation region 106 can be STI, LOCOS, etc.

[0100] Next, we will refer to Figure 10B This describes the structure of charge discharge pixel 100e. Note that descriptions of features common to charge discharge pixel 100e or effective pixel 100d can be omitted.

[0101] The charge discharge pixel 100e has semiconductor regions 201a, 201b, 202, 203b, 204a, 204b, and 205 disposed in a semiconductor substrate, and a device isolation region 206. Additionally, the charge discharge pixel 100e has gates 209 and 210 disposed on or above the semiconductor substrate, and contacts 214a, 214b, 215, 216, 217, 250a, and 250b. These contacts are each formed from a conductive member arranged as a hole penetrating an insulating layer. (See reference...) Figure 9B As shown in the figure, no transmission transistor M1a or M1b or reset transistor M2 is arranged in the charge discharge pixel 100e, nor is its corresponding gate arranged there.

[0102] Semiconductor regions 201a and 201b (second semiconductor regions) are n-type semiconductor regions. Semiconductor region 202 is an n-type semiconductor region and is connected to semiconductor regions 201a and 201b. Contact 214a is connected to semiconductor region 202. Contact 215 (a second conductive member passing through a second hole) is connected to gate 209 corresponding to the gate of amplifier transistor M3. Semiconductor region 203b (third semiconductor region) is an n-type semiconductor region forming the drain (first main electrode) of amplifier transistor M3. Contact 214b (a first conductive member passing through a first hole) is connected to semiconductor region 203b. Contacts 214a, 214b, and 215 are connected to each other via wiring 218 arranged in a wiring layer laminated on an insulating layer. Power supply potential is provided to wiring 218 (power supply wiring). Since features other than those described above are the same as those of effective pixel 100d, their description will be omitted.

[0103] It should be noted that semiconductor region 202 is an n-type semiconductor region with a higher impurity concentration than semiconductor regions 201a and 201b. Therefore, the contact 214a, to which the power supply potential is provided, and semiconductor regions 201a and 201b can be connected to each other with low resistance, which improves charge discharge efficiency. Additionally, semiconductor regions 203b, 204a, 204b, and 205 are also n-type semiconductor regions with a higher impurity concentration than semiconductor regions 201a and 201b. This reduces resistance.

[0104] As described above, the photoelectric conversion device of this embodiment has a charge discharge pixel 100e, which has a circuit configuration in which the transmission transistors M1a and M1b and the reset transistor M2 are excluded from the effective pixel 100d. The charge discharge pixel 100e can discharge nearby noise charge to the wiring 118 in the same manner as in the first or third embodiment. Therefore, according to this embodiment, a photoelectric conversion device that can more effectively discharge noise charge can be provided.

[0105] In the charge discharge pixel 100e of this embodiment, the amplifier transistor M3 and the selection transistor M4 are arranged in the same manner as in the effective pixel 100d. Therefore, for the same reasons as described in the third embodiment, the effects of potential changes, etc., between the case where the effective pixel 100d is connected to the output line 12 and the case where the charge discharge pixel 100e is connected to the same output line 12 are reduced.

[0106] It should be noted that, for the same reasons as described in the first embodiment, it is desirable that, in this embodiment, the semiconductor region 201a of the effective pixel 100d and the semiconductor region 201a of the charge discharge pixel 100e also have the same shape in the planar view. Additionally, it is also desirable that the semiconductor region 201b of the effective pixel 100d and the semiconductor region 201b of the charge discharge pixel 100e have the same shape in the planar view. The charge discharge pixel 100e of this embodiment can be arranged in the charge discharge pixel region R2 of the second or fourth embodiment, and achieves the same advantageous effects as described in the second or fourth embodiment.

[0107] Sixth Embodiment

[0108] In this embodiment, three variations of the circuit configuration and structure of the effective pixel 100a in the first embodiment will be described. Since the configuration of the circuit blocks of the photoelectric conversion device, the structure of the charge discharge pixel 100b, etc., are the same as those in the first embodiment, their descriptions will be omitted.

[0109] Figure 11 This is a circuit diagram of the effective pixel 100f according to this embodiment. In the configuration of the effective pixel 100f, reference will be made to... Figure 11 Features that differ from the effective pixel 100a in the first embodiment are described.

[0110] The difference between the effective pixel 100f in this embodiment and the effective pixel 100a in the first embodiment is that a first capacitor-added transistor M5 (first transistor) is also arranged. The source of the first capacitor-added transistor M5 is connected to the floating diffuser FD. The drain of the first capacitor-added transistor M5 is connected to the source of the reset transistor M2. The control signal PFDINC1(n) is input from the vertical scan circuit 16 to the gate of the first capacitor-added transistor M5 via the control signal line 14. Note that... Figure 11 In the attached diagram, reference numeral "n1" indicates the first node corresponding to the node of the floating diffuser FD. Reference numeral "n2" indicates the second node corresponding to the connection point between the drain of the first capacitor-attached transistor M5 and the source of the reset transistor M2.

[0111] The first capacitor-adding transistor M5 functions to add capacitance to the floating diffuser FD. When the control signal PFDINC1(n) is high, the first capacitor-adding transistor M5 is turned on. When the first capacitor-adding transistor M5 is turned on, a channel is formed in it, and the capacitance (MOS capacitance) caused by this channel is added to the capacitance of the floating diffuser FD. Additionally, the parasitic capacitance on the other electrode (drain) of the first capacitor-adding transistor M5 is also added to the capacitance of the floating diffuser FD. Examples of such parasitic capacitances include the capacitance between the gate electrode and the other electrode (drain), the pn junction capacitance of the semiconductor region forming the other electrode, and capacitance relative to surrounding wiring. In this way, the capacitance of the first capacitor-adding transistor M5 is added to the floating diffuser FD, resulting in an increase in overall capacitance, thereby increasing the charge that can be retained and expanding the dynamic range. Conversely, when the control signal PFDINC1(n) is low and the first capacitor-adding transistor M5 is therefore off, the capacitance of the first capacitor-adding transistor M5 is not added to the floating diffuser FD. In this case, the sensitivity of the effective pixel 100f can be increased (e.g., the amount of voltage change per single charge (charge-voltage conversion efficiency)). In this way, the sensitivity of the effective pixel 100f in this embodiment can be changed by controlling the first capacitor-attached transistor M5.

[0112] It should be noted that the first capacitor-added transistor M5 can be arranged in parallel with the reset transistor M2. In this case, since the parasitic capacitance on the floating diffuser FD increases when the first capacitor-added transistor M5 is in the off state, the charge-to-voltage conversion efficiency decreases when no capacitor is added. Therefore, it is desirable that the first capacitor-added transistor M5 and the reset transistor M2 are connected in series with the floating diffuser FD.

[0113] Next, another variation of the circuit configuration and structure of the effective pixel 100a in the first embodiment will be described. Figure 12 This is a circuit diagram of the effective pixels 100g and 100h according to this embodiment. In the configuration of the effective pixels 100g and 100h, reference will be made to... Figure 12 Features that differ from the effective pixel 100a in the first embodiment are described.

[0114] The effective pixels 100g and 100h in this embodiment differ from the effective pixel 100a in the first embodiment in that a first capacitor-added transistor M5 and a second capacitor-added transistor M6 (second transistor) are also arranged. The source of the first capacitor-added transistor M5 is connected to the floating diffuser FD. The drain of the first capacitor-added transistor M5 is connected to the source of the second capacitor-added transistor M6. The drain of the second capacitor-added transistor M6 is connected to the source of the reset transistor M2. The control signal PFDINC1(n) is input from the vertical scan circuit 16 to the gate of the first capacitor-added transistor M5 via the control signal line 14. The control signal PFDINC2(n) is input from the vertical scan circuit 16 to the gate of the second capacitor-added transistor M6 via the control signal line 14. Note that... Figure 11 In the attached diagram, reference numeral "n1" indicates the first node corresponding to the node of the floating diffuse FD. Reference numeral "n2" indicates the second node corresponding to the connection point between the drain of the first capacitor-attached transistor M5 and the source of the second capacitor-attached transistor M6. Reference numeral "n3" indicates the third node corresponding to the connection point between the drain of the second capacitor-attached transistor M6 and the source of the reset transistor M2.

[0115] When control signal PFDINC1(n) is high and control signal PFDINC2(n) is low, the first capacitor-added transistor M5 is in the on state, and the second capacitor-added transistor M6 is in the off state. Therefore, the capacitance of the first capacitor-added transistor M5 is added to the floating diffusion FD. When control signals PFDINC1(n) and PFDINC2(n) are high, the first capacitor-added transistor M5 and the second capacitor-added transistor M6 are in the on state. Therefore, the capacitance of the first capacitor-added transistor M5 and the second capacitor-added transistor M6 is added to the floating diffusion FD. When control signals PFDINC1(n) and PFDINC2(n) are high, the first capacitor-added transistor M5 and the second capacitor-added transistor M6 are in the off state. At this time, the capacitance of the first capacitor-added transistor M5 and the second capacitor-added transistor M6 is not added to the floating diffusion FD. In this way, the sensitivity of the effective pixel 100g in this variant example can be changed in three levels by controlling the capacitance of the first capacitor-added transistor M5 and the second capacitor-added transistor M6.

[0116] It should be noted that the difference between effective pixel 100g and effective pixel 100h lies in the capacitance (level) relationship between the first capacitor-attached transistor M5 and the second capacitor-attached transistor M6. Therefore, as... Figure 12 The circuit diagrams for effective pixels 100g and 100h shown in the figure are shared by each other.

[0117] Figure 13A This is a schematic plan view of the effective pixel 100f according to this embodiment. Figure 13B This is a schematic plan view of the effective pixels 100g according to this embodiment. Figure 13C This is a schematic plan view of the effective pixel 100h according to this embodiment. The configuration of the first capacitor-attached transistor M5 and the second capacitor-attached transistor M6 will be described with primary reference to these schematic plan views. Since the components other than the first capacitor-attached transistor M5 and the second capacitor-attached transistor M6 are generally the same as those described in the first embodiment, their descriptions will be omitted or simplified.

[0118] Effective pixel 100g has a semiconductor region 101 disposed in semiconductor substrate 120. Additionally, effective pixel 100g has gates 107, 108, 109, 110, and 160, and contacts 112 and 114 disposed on or above semiconductor substrate 120. Furthermore, in addition to the configuration of effective pixel 100g, effective pixels 100g and 100h also have a gate 161. Gates 107, 108, 109, and 110 correspond to the gates of transmission transistor M1, reset transistor M2, amplifier transistor M3, and selection transistor M4, respectively. Additionally, gates 160 and 161 correspond to the gates of first capacitor-attached transistor M5 and second capacitor-attached transistor M6, respectively. Contact 112 is connected to the semiconductor region forming a floating diffusion FD. Contact 114 is connected to a power supply wiring.

[0119] The difference between effective pixel 100g and effective pixel 100h lies in the capacitance relationship between the first capacitor-attached transistor M5 and the second capacitor-attached transistor M6. In effective pixel 100g, the capacitance of the first capacitor-attached transistor M5 is greater than the capacitance of the second capacitor-attached transistor M6. In contrast, in effective pixel 100h, the capacitance of the second capacitor-attached transistor M6 is greater than the capacitance of the first capacitor-attached transistor M5. In this paper, the capacitances of the first capacitor-attached transistor M5 and the second capacitor-attached transistor M6 can be proportional to their gate lengths. Figure 13B As illustrated in the diagram, in effective pixel 100g, the gate length of the first capacitor-attached transistor M5 (gate 160) is greater than the gate length of the second capacitor-attached transistor M6 (gate 161). In contrast, as... Figure 13C As illustrated in the diagram, in effective pixel 100h, the gate length of the second capacitor-attached transistor M6 (gate 161) is greater than the gate length of the first capacitor-attached transistor M5 (gate 160). Figure 13B and Figure 13C In the first capacitor-attached transistor M5 and the second capacitor-attached transistor M6, the gate widths are the same, but they can be different from each other.

[0120] Figure 14It is a table listing the capacitance of each portion of the effective pixels 100f, 100g, and 100h according to the sixth embodiment. Figure 14 The capacitances of the floating diffuser FD, the first capacitor-attached transistor M5, and the second capacitor-attached transistor M6 in effective pixels 100f, 100g, and 100h are listed. Note that... Figure 14 The capacitance values ​​listed are expressed in arbitrary units and normalized so that the sum of all capacitances in each section equals 1. Figure 14 In the example, in effective pixel 100f, the capacitance of the floating diffusion FD is 0.25, and the capacitance of the first capacitor-attached transistor M5 is 0.75. In effective pixel 100g, the capacitance of the floating diffusion FD is 0.25, the capacitance of the first capacitor-attached transistor M5 is 0.50, and the capacitance of the second capacitor-attached transistor M6 is 0.25. In effective pixel 100h, the capacitance of the floating diffusion FD is 0.25, the capacitance of the first capacitor-attached transistor M5 is 0.25, and the capacitance of the second capacitor-attached transistor M6 is 0.50. In this way, Figure 14 The illustration shows an example of an effective pixel 100g where the capacitance of the first capacitor-attached transistor M5 is greater than the capacitance of the second capacitor-attached transistor M6, and an example of an effective pixel 100h where the capacitance of the second capacitor-attached transistor M6 is greater than the capacitance of the first capacitor-attached transistor M5.

[0121] In effective pixel 100g, the total capacitance can be varied in three ways: 0.25, 0.75, and 1, depending on the control signals PFDINC1(n) and PFDINC2(n). Similarly, in effective pixel 100h, the total capacitance can be varied in three ways: 0.25, 0.50, and 1, depending on the control signals PFDINC1(n) and PFDINC2(n). For example, suppose this capacitance switching is used in the following application: the gain of the photoelectric conversion device (gain outside the pixel, such as column amplifier circuit 18) is set in three ways: four times, two times, and one times, and these three capacitance settings are used to change the sensitivity of the pixel. In this application, the signal can be output at an appropriate level while avoiding signal saturation. In this paper, the noise included in the output signal is proportional to both the gain and the capacitance, i.e., proportional to the product of the gain and the capacitance. When using an effective pixel 100h with a configuration where the capacitance of the second capacitor-attached transistor M6 is greater than the capacitance of the first capacitor-attached transistor M5, the relationship between the gain and the total capacitance is closer to inversely proportional. Therefore, since the product of gain and total capacitance can be made closer to constant, this allows for uniform noise across various gains, thus improving the signal-to-noise ratio. However, this is just an example, and the appropriate size relationship and ratio between the first capacitor-attached transistor M5 and the second capacitor-attached transistor M6 can vary depending on the design.

[0122] According to this embodiment, a photoelectric conversion device capable of varying charge-to-voltage conversion efficiency can be provided. Furthermore, according to a modified example with 100g and 100h effective pixels, a photoelectric conversion device capable of varying charge-to-voltage conversion efficiency in three levels can be provided.

[0123] Seventh Embodiment

[0124] Each photoelectric conversion device in the above embodiments is applicable to various devices. Such devices can be digital still cameras, digital video cameras, camera lenses, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, surveillance cameras, etc. Figure 15 The diagram illustrates a block diagram of a digital still camera as an example of a device.

[0125] Figure 15The apparatus 7 shown includes a baffle 706, a lens 702, an aperture 704, and an imaging device 70 (an example of a photoelectric conversion device). The apparatus 7 also includes a signal processing unit (processing device) 708, a timing generation unit 720, a general control / operation unit 718 (control device), a memory unit 710 (storage device), a storage medium control I / F unit 716, a storage medium 714, and an external I / F unit 712. At least one of the baffle 706, lens 702, and aperture 704 is an optical device suitable for this apparatus. The baffle 706 protects the lens 702, and the lens 702 captures the optical image of the subject onto the imaging device 70. The aperture 704 changes the amount of light that has passed through the lens 702. The imaging device 70 is configured as described in the above embodiment and converts the optical image captured by the lens 702 into image data (image signal). In this document, an analog-to-digital (AD) conversion unit is formed on the semiconductor substrate of the imaging device 70. The signal processing unit 708 performs various corrections, data compression, etc., on the imaging data output from the imaging device 70. The timing generation unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The general control / operation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The storage medium control I / F unit 716 is an interface for storing or retrieving image data on the storage medium 714, and the storage medium 714 is a removable storage medium such as a semiconductor memory for storing or retrieving imaging data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals, etc., can be input from outside the device. In addition, the device 7 may include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device includes at least a photoelectric conversion device. The device 7 also includes at least one of optical devices, control devices, processing devices, display devices, storage devices, and mechanical devices that operate based on information obtained by the photoelectric conversion device. The mechanical device is a movable unit (e.g., a robotic arm) that operates in response to signals from the photoelectric conversion device.

[0126] Although in this embodiment the imaging device 70 and the AD conversion unit are disposed on separate semiconductor substrates, the imaging device 70 and the AD conversion unit can be formed on the same semiconductor substrate. Additionally, the imaging device 70 and the signal processing unit 708 can be formed on the same semiconductor substrate.

[0127] Additionally, for example, as in the fifth embodiment, each pixel may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process pixel signals based on the charge generated by the first photoelectric conversion unit and pixel signals based on the charge generated by the second photoelectric conversion unit, and to acquire distance information from the imaging device 70 to the subject.

[0128] Eighth embodiment

[0129] Figure 16A and Figure 16B This is a block diagram of the device related to the vehicle-mounted camera in this embodiment. The device 8 includes an imaging device 80 (an example of a photoelectric conversion device) from any of the above embodiments and a signal processing device (processing device) that processes signals from the imaging device 80. The device 8 includes an image processing unit 801 that performs image processing on multiple image data acquired by the imaging device 80, and a disparity calculation unit 802 that calculates disparity (phase difference of a disparity image) from the multiple image data acquired by the device 8. Additionally, the device 8 includes a distance measurement unit 803 that calculates the distance to an object based on the calculated disparity, and a collision determination unit 804 that determines the possibility of a collision based on the calculated distance. Here, the disparity calculation unit 802 and the distance measurement unit 803 represent examples of a distance information acquisition unit that acquires distance information about the distance to an object. That is, the distance information is information about disparity, defocus, distance to an object, etc. The collision determination unit 804 can use any distance information to determine the possibility of a collision. The distance information acquisition unit can be implemented by specially designed hardware or by a software module. In addition, the distance information acquisition unit can be implemented by a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), or a combination thereof.

[0130] Device 8 is connected to vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Additionally, device 8 is connected to control ECU 820, which is a control device that outputs control signals to apply braking force to the vehicle based on the determination results from collision determination unit 804. Furthermore, device 8 is also connected to alarm device 830, which issues an alarm to the driver based on the determination results from collision determination unit 804. For example, when the determination results from collision determination unit 804 indicate a high probability of collision, control ECU 820 performs vehicle control to avoid a collision or reduce damage by applying brakes, pushing the accelerator backward, or suppressing engine power. Alarm device 830 warns the user by emitting alarms such as sounds, displaying alarm information on a display such as a car navigation system, or providing vibration to the seat belt or steering wheel. As described above, device 8 serves as a control unit for controlling the operation of the vehicle.

[0131] In this embodiment, the device 8 is used to capture images of the area around the vehicle, such as the area in front or behind. Figure 16BThe diagram illustrates the apparatus when an image of the area in front of the vehicle (capture area 850) is captured. The vehicle information acquisition device 810, which serves as the imaging control unit, instructs the device 8 or imaging device 80 to perform the imaging operation. This configuration can further improve ranging accuracy.

[0132] While examples of controls for avoiding collisions with other vehicles have been described above, this embodiment is applicable to autonomous driving controls that follow other vehicles, autonomous driving controls that do not leave their lanes, and the like. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to, for example, mobile bodies (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. Additionally, the device can be widely applied to devices that utilize object recognition or biometric authentication, such as intelligent transportation systems (ITS) and surveillance systems, and is not limited to mobile bodies.

[0133] Modified embodiments

[0134] This disclosure can be modified in various ways, and is not limited to the embodiments described above. For example, examples of adding a portion of the configuration of any embodiment to another embodiment, or replacing a portion of the configuration of any embodiment with a portion of the configuration of another embodiment, are also examples of embodiments of this disclosure.

[0135] Some embodiments can also be implemented by a computer that reads and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more fully referred to as a "non-transient computer-readable storage medium") to perform the functions of one or more embodiments described above and / or includes one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing the functions of one or more embodiments described above, and by a method executed by a computer of a system or device, for example, by reading and executing computer-executable instructions from a storage medium to perform the functions of one or more embodiments described above and / or controlling one or more circuits to perform the functions of one or more embodiments described above. The computer may include one or more processors (e.g., a central processing unit (CPU), a microprocessor unit (MPU)) and may include a network of individual computers or individual processors to read and execute computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or storage medium. The storage medium may include, for example, a hard disk, random access memory (RAM), read-only memory (ROM), storage devices for distributed computing systems, optical discs (such as CDs, DVDs, or Blu-ray discs). TM One or more of the following: flash memory devices, memory cards, etc.

[0136] Other embodiments

[0137] The embodiments of the present invention can also be implemented by providing software (programs) that perform the functions of the above embodiments to a system or device via a network or various storage media, and the computer or central processing unit (CPU) or microprocessor unit (MPU) of the system or device reads out and executes the program.

[0138] While exemplary embodiments have been described in this disclosure, it is to be understood that some embodiments are not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to include all such modifications as well as equivalent structures and functions.

Claims

1. A photoelectric conversion device, comprising: A pixel array, including a first pixel and a second pixel; The scanning circuit outputs control signals to the pixel array; as well as The output line connects to the first pixel and the second pixel. The first pixel includes a photoelectric conversion unit that performs photoelectric conversion on the incident light to output a signal corresponding to the incident light to an output line. The photoelectric conversion unit includes a first semiconductor region of a first conductivity type as a charge accumulation layer. The second pixel includes The second semiconductor region of the first conductivity type. The transistor includes a first main electrode formed by a third semiconductor region connected to a second semiconductor region, a gate connected to a scan circuit, and a second main electrode formed by a fourth semiconductor region. The first contact is connected between the fourth semiconductor region and the output line, and The second contact is supplied with a power potential and connected to the third semiconductor region.

2. The photoelectric conversion device according to claim 1, wherein, The pixel array includes a first pixel region and a second pixel region. In the first pixel region, multiple first pixels are arranged to form multiple rows and multiple columns. The second pixel region is located outside the first pixel region and second pixels are arranged in the second pixel region.

3. The photoelectric conversion device according to claim 2, wherein, The pixel array also includes a third pixel region, which includes a third pixel containing a light-blocked photoelectric conversion unit and outputting a black level signal.

4. The photoelectric conversion device according to claim 3, wherein, The second pixel region is located on the periphery of the third pixel region.

5. The photoelectric conversion device according to claim 3 or 4, wherein, The second pixel region is arranged to surround the first pixel region and the third pixel region.

6. The photoelectric conversion device according to claim 3 or 4, wherein, The second pixel region is positioned between the first pixel region and the third pixel region.

7. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The first semiconductor region and the second semiconductor region have the same shape in the plan view.

8. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The impurity concentration in the third semiconductor region is higher than that in the second semiconductor region.

9. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The first pixel includes multiple photoelectric conversion units, and light passing through a single microlens enters the multiple photoelectric conversion units.

10. The photoelectric conversion device according to any one of claims 1 to 4, in, The first pixel includes: The photoelectric conversion unit The first node is supplied with charge from the photoelectric conversion unit. The amplifier transistor outputs a signal corresponding to the voltage at the first node, and The first transistor disconnects and closes the path between the first node and the second node, which is not included in the path from the photoelectric conversion unit to the first node. When the first transistor is turned on, a capacitor is added to the first node.

11. The photoelectric conversion device according to any one of claims 1 to 4, in, The first pixel includes: The photoelectric conversion unit The first node is supplied with charge from the photoelectric conversion unit. The amplifier transistor outputs a signal corresponding to the voltage at the first node. The first transistor disconnects and closes the path between the first node and the second node, which is not included in the path from the photoelectric conversion unit to the first node, and The second transistor disconnects and closes the path between the second node and the third node, and Specifically, when the second transistor is turned on, the second capacitor added to the second node is greater than the first capacitor added to the first node when the first transistor is turned on.

12. A photoelectric conversion device, the photoelectric conversion device comprising a pixel array, the pixel array comprising a first pixel and a second pixel, in, The first pixel includes a photoelectric conversion unit that performs photoelectric conversion on incident light to output a signal corresponding to the incident light. The photoelectric conversion unit includes a first semiconductor region of a first conductivity type as a charge accumulation layer. The second pixel includes The second semiconductor region of the first conductivity type. A transistor includes a gate and a first main electrode formed by a third semiconductor region connected to a second semiconductor region. An insulating layer having a first hole and a second hole, A first conductive member is arranged to pass through a first hole and connect between a third semiconductor region and a power supply wiring at a supplied power potential. A second conductive member is arranged to pass through a second hole and connect between the power supply wiring and the gate.

13. The photoelectric conversion device according to claim 12 further includes an output line connected to the first pixel and the second pixel. in, The first pixel and the second pixel output signals to the output line.

14. An apparatus including a photoelectric conversion device, comprising: The photoelectric conversion device according to any one of claims 1 to 13; as well as At least one of the following: Optical equipment, suitable for photoelectric conversion devices. The control device is configured to control the photoelectric conversion device. The processing device is configured to process the signal output from the photoelectric conversion device. The display device is configured to display information obtained from the photoelectric conversion device. Storage devices are configured to store information obtained from photoelectric conversion devices, and Mechanical equipment is configured to operate based on information obtained from photoelectric conversion devices.

15. The apparatus according to claim 14, wherein, The processing device processes the image signals generated by multiple photoelectric conversion units and acquires distance information about the distance from the photoelectric conversion device to the subject.

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