semiconductor devices

Abstract

The semiconductor device of an embodiment of the present application includes a first transistor, a second transistor, a third electrode and a control layer. The first transistor includes a first region of a semiconductor layer, a first electrode and a first gate electrode, wherein the first region of the semiconductor layer includes a first surface and a second surface. The first electrode is electrically connected to the second surface of the first region. The first gate electrode is arranged in the first region. The second transistor includes a second region of a semiconductor layer, a second gate electrode and a second electrode, wherein the second region of the semiconductor layer is arranged adjacent to the first region. The second gate electrode is arranged in the second region. The second electrode is electrically connected to the second surface of the second region. The third electrode is arranged on the side of the first surface and is electrically connected to the first transistor and the second transistor. The control layer is arranged in such a way that the third electrode is located between the first surface and has a smaller linear expansion coefficient than that of the third electrode.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2021-57051 (filing date: March 30, 2021), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] There is a technology that forms two transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), on a single semiconductor chip. The two MOSFETs have a common drain electrode.

[0005] The metal layer of the common drain electrode is formed thick to reduce resistance during on-state operation. Meanwhile, the semiconductor element region of a semiconductor device tends to be thinner to reduce resistance during on-state operation. Consequently, the semiconductor element region may warp and crack during the semiconductor device manufacturing process or when the semiconductor device is mounted on a wiring substrate. Summary of the Invention

[0006] A semiconductor device according to an embodiment includes a first transistor, a second transistor, a third electrode, and a control layer. The first transistor includes a first region of a semiconductor layer, a first electrode, and a first gate electrode. The first region of the semiconductor layer includes a first surface and a second surface facing the first surface in a first direction. The first electrode is electrically connected to the second surface of the first region. The first gate electrode is provided in the first region. The second transistor includes a second region of the semiconductor layer, a second gate electrode, and a second electrode. The second region of the semiconductor layer is provided adjacent to the first region in a second direction intersecting the first direction, and includes a first surface and a second surface. The second gate electrode is provided in the second region. The second electrode is electrically connected to the second surface of the second region and is provided separately from the first electrode. The third electrode is provided on the first surface side and is electrically connected to the first transistor and the second transistor. The control layer is provided so that the third electrode is located between the first surface and the third electrode, and has a smaller linear expansion coefficient than that of the third electrode.

[0007] According to the embodiment, a semiconductor device capable of suppressing warping and cracking of a semiconductor element can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a cross-sectional view of the semiconductor device 100 according to the first embodiment.

[0009] Figure 2 This is a graph showing the linear expansion coefficients of materials used for the drain electrode and the control layer.

[0010] Figure 3 It is a top view of the semiconductor device 100 according to the first embodiment.

[0011] Figure 4 1 is an equivalent circuit diagram of the semiconductor device 100 according to the first embodiment.

[0012] Figures 5A to 8 It is a diagram showing a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0013] Figure 9 FIG. 1 is a schematic diagram showing the semiconductor device 100 according to the first embodiment mounted on a wiring substrate.

[0014] Figure 10 is a cross-sectional view of a semiconductor device 300 according to a comparative example. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In this description, common reference numerals are assigned to common parts throughout the figures. Furthermore, the dimensional ratios in the drawings are not limited to those shown. Furthermore, this embodiment does not limit the present invention.

[0016] [First embodiment]

[0017] (Structure of Semiconductor Device 100)

[0018] Reference Figure 1 、 Figure 2 and Figure 3 The detailed structure of the semiconductor device 100 according to the first embodiment will be described. Figure 1 It is a cross-sectional view of the semiconductor device 100 according to the first embodiment. Figure 2 The linear expansion coefficients of the materials used for the drain electrode 40 and the control layer 50 are shown. Figure 3 It is a top view of the semiconductor device 100 according to the first embodiment.

[0019] In the following description, n + 、n、n - and p + ,p,p - This expression indicates the relative high and low impurity concentrations of each conductivity type. + Compared with n, the n-type impurity concentration is relatively high. - Indicates that the n-type impurity concentration is relatively low compared to n. + The p-type impurity concentration is relatively high compared to the p-type. -Indicates that the p-type impurity concentration is relatively low compared to the p-type. In addition, n is sometimes + Type, n - The type is simply recorded as n type, and the p + Type, p - The type is simply recorded as p type.

[0020] Figure 1 The semiconductor device 100 of the first embodiment is a switching device that controls the flow of bidirectional current. The semiconductor device 100 of the first embodiment is used, for example, in a battery protection circuit. The semiconductor device 100 of the first embodiment has two trench-gate MOSFETs connected so that their drain electrodes are common.

[0021] The semiconductor device 100 of the first embodiment has a semiconductor layer 10, a first source electrode (first electrode) 21, a second source electrode (second electrode) 22, a first gate electrode 31, a second gate electrode 32, a drain electrode (third electrode) 40, a control layer 50, a first source electrode pad 81, a second source electrode pad 82, a first gate electrode pad 91 and a second gate electrode pad 92.

[0022] The semiconductor layer 10 has a first surface P1 , a second surface P2 , a first region 10 a , and a second region 10 b . Figure 1 , the first region 10a is indicated by a dot-dash line, and the second region 10b is indicated by a single-dot-dash line.

[0023] The direction from the first plane P1 toward the second plane P2 is the Z direction (first direction), the direction perpendicular to the Z direction is the X direction (second direction), and the direction perpendicular to the X and Z directions is the Y direction (third direction). Figure 1 and Figure 2 The semiconductor device 100 shown is a cross-sectional view taken along the XZ plane. For purposes of description, the direction from the first plane P1 toward the second plane P2 is referred to as "upper," and the opposite direction is referred to as "lower."

[0024] First region 10a is a region provided in semiconductor layer 10 having first surface P1 and second surface P2. Second region 10b has first surface P1 and second surface P2 and is provided adjacent to first region 10a in the X direction.

[0025] The first region 10a has n + Type drain region 11, n - type drift region 12, p-type first base region 13a and n-type + Type first source region 14a.

[0026] n + The type drain region 11 is provided on the first plane P1 side of the semiconductor layer 10.- The drift region 12 is arranged in the Z direction at n + type drain region 11.

[0027] A plurality of p-type first base regions 13a are provided in the first region 10a. The plurality of p-type first base regions 13a are adjacent to each other in the X direction via a first insulating film 61 described later, and are provided in the n-type region 10a. - Above the drift region 12 of the type.

[0028] n + The n-type first source region 14a is provided on the p-type first base region 13a in the Z direction. + The type first source region 14 a is provided on the second plane P2 side of the first region 10 a.

[0029] The second region 10b has n + Type drain region 11, n - Type drift region 12, p-type second base region 13b and n + Type second source region 14b.

[0030] A plurality of p-type second base regions 13b are provided in the second region 10b. The plurality of p-type second base regions 13b are provided separately along the X direction at the n-type portions of the second region 10b. - Above the drift region 12 of the type.

[0031] n + The n-type second source region 14b is provided on the p-type second base region 13b in the Z direction. + The type first source region 14a is provided on the second plane P2 side of the second region 10b.

[0032] The semiconductor layer 10 includes, for example, silicon (Si) or silicon carbide (SiC) as a semiconductor material. When silicon is used as the semiconductor material, the thickness of the semiconductor layer 10 in the Z direction is 100 μm or less.

[0033] The first source electrode 21 is provided at n + The first source electrode 21 is connected to the n-type first source region 14a. + The first source region 14a of the type is electrically connected.

[0034] A plurality of first gate electrodes 31 are provided in the first region 10 a . The first gate electrodes 31 are provided adjacent to the p-type first base region 13 a along the X direction. A first insulating film 61 is provided between the first gate electrodes 31 and the semiconductor layer 10 .

[0035] The second source electrode 22 is provided at n +The second source electrode 22 is connected to the n type second source region 14b. + The second source region 14b of the type is electrically connected.

[0036] A plurality of second gate electrodes 32 are provided in the second region 10 b . The second gate electrodes 32 are provided adjacent to the p-type second base region 13 b along the X direction. A second insulating film 62 is provided between the second gate electrodes 32 and the semiconductor layer 10 .

[0037] A portion of the first source electrode 21 , a portion of the second source electrode 22 , and a portion of the semiconductor layer 10 are covered by the insulating film 60 .

[0038] like Figure 2 As shown, the drain electrode 40 comprises a first metal layer 41, a second metal layer 42, a third metal layer 43 and a fourth metal layer 44. The drain electrode 40 is provided at n + type drain region 11, and with n + The drain region 11 of the type is electrically connected.

[0039] The first metal layer 41 is the main path for current flowing when the semiconductor device 100 is turned on, and has the thickest thickness in the Z direction among the metal layers of the drain electrode 40. The thickness of the first metal layer 41 in the Z direction is, for example, 10 μm or more. The first metal layer 41 is, for example, silver (Ag) or copper (Cu). The second metal layer 42 is provided on the n + The second metal layer 42 is made of a metal that improves adhesion to the semiconductor layer 10, such as titanium (Ti). The thickness of the second metal layer 42 in the Z direction is, for example, 1 μm or less. The third metal layer 43 is provided between the first metal layer 41 and the second metal layer 42. The third metal layer 43 is provided to prevent the semiconductor layer (such as n + The third metal layer 43 is a barrier metal layer that prevents oxidation of the drain region 11 or diffusion of metal into the semiconductor layer. For example, nickel (Ni) is used. The thickness of the third metal layer 43 in the Z direction is, for example, 1 μm. The fourth metal layer 44 is provided below the first metal layer 41. The fourth metal layer 44 is an anti-corrosion layer that prevents corrosion of the first metal layer 41. For example, nickel (Ni) is used. The thickness of the fourth metal layer 44 in the Z direction is, for example, 1 μm. Furthermore, the present invention can be implemented even without the second metal layer 42, the third metal layer 43, and the fourth metal layer 44.

[0040] The control layer 50 is provided below the fourth metal layer 44. The control layer 50 is made of the metal layer having the thickest thickness in the Z direction among the metal layers of the drain electrode 40, i.e., a material having a smaller linear expansion coefficient than the first metal layer 41. Examples of materials used for the control layer 50 include Si, tungsten (W), molybdenum (Mo), and chromium (Cr). The linear expansion coefficients of the materials used for the metal layers of the drain electrode 40 and the control layer 50 are as follows: Figure 2Furthermore, the control layer 50 is preferably a hard material.

[0041] In the semiconductor device 100 of the first embodiment, the structure described above forms a first transistor 71 and a second transistor 72. The first transistor 71 includes a first region 10a, a first source electrode 21, a first gate electrode 31, a first insulating film 61, and a drain electrode 40. The second transistor 72 includes a second region 10b, a second source electrode 22, a second gate electrode 32, a second insulating film 62, and a drain electrode 40. In other words, the first transistor 71 and the second transistor 72 share a common drain electrode 40.

[0042] The first gate electrode 31 and the second gate electrode 32 extend in the Y direction. Similar to the first gate electrode 31 and the second gate electrode 32, each region provided in the semiconductor device 100, such as the first base region 13a, the second base region 13b, the first source region 14a, and the second source region 14b, extends in the Y direction.

[0043] Figure 4 FIG. 1 shows a top view of the semiconductor device 100 according to the first embodiment in the XY plane. Figure 4 The cross-sectional view obtained by the A-A' line is Figure 1 A first source electrode pad 81 and a first gate electrode pad 91 are provided on the upper portion of the first transistor 71, exposed to the outside of the insulating film 60. The first source electrode pad 81 is electrically connected to the first source electrode 21. The first gate electrode pad 91 is electrically connected to the first gate electrode 31. A second source electrode pad 82 and a second gate electrode pad 92 are provided on the upper portion of the second transistor 72, exposed to the outside of the insulating film 60. The second source electrode pad 82 is electrically connected to the second source electrode 22. The second gate electrode pad 92 is electrically connected to the second gate electrode 32.

[0044] (Operation of Semiconductor Device 100)

[0045] Reference Figure 3 The operation of the semiconductor device 100 will be described. Figure 3 An equivalent circuit diagram of the semiconductor device 100 according to the first embodiment is shown.

[0046] As described above, the semiconductor device 100 according to the first embodiment is used in, for example, a battery protection circuit.

[0047] During charging and discharging, a voltage above the threshold is applied to the first gate electrode 31 and the second gate electrode, turning on the first transistor 71 and the second transistor 72. During charging, current flows from the first source electrode 21 to the drain electrode 40. The current then flows in the X direction through the first metal layer 41 of the drain electrode 40 and reaches the second transistor 72. During discharging, current flows from the second source electrode 22 to the drain electrode 40. The current then flows in the X direction through the first metal layer 41 of the drain electrode 40 and reaches the first transistor 71.

[0048] During overcharging or overdischarging, a control circuit (not shown) turns on either the first transistor 71 or the second transistor 72 .

[0049] As described above, the semiconductor device 100 controls the direction of bidirectional current flow.

[0050] (Method of Manufacturing Semiconductor Device 100)

[0051] 5 to 7 are cross-sectional views showing the steps of manufacturing the semiconductor device 100 according to the first embodiment. An example of a method of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIG5 to FIG7 .

[0052] First, prepare n + The semiconductor substrate 11 is the semiconductor substrate 11. + Then, in the Z direction, by + The n-type semiconductor substrate 11 is epitaxially grown to form n - Type drift region 12.

[0053] like Figure 5A As shown, a first base region 13a, a second base region 13b, a first source region 14a, a second source region 14b, a first gate electrode 31, a second gate electrode 32, a first insulating film 61, a second insulating film 62, a first source electrode 21, a second source electrode 22, a first source electrode pad 81, a second source electrode pad 82, a first gate electrode pad 91, a second gate electrode pad 92 and an insulating film 60 are formed in the drift region 12.

[0054] like Figure 5B As shown, for n + The semiconductor substrate 11 of the type is ground to reduce the thickness of the semiconductor layer 10 in the Z direction.

[0055] like Figure 6A As shown, the second metal layer 42 and the third metal layer 43 are formed by, for example, sputtering.

[0056] like Figure 6BAs shown in FIG. 4 , a portion of the first metal layer 41 is formed by sputtering. Figure 7A As shown, the first metal layer 41 is formed by plating.

[0057] like Figure 7B As shown, the fourth metal layer 44 is formed by, for example, plating.

[0058] like Figure 8 As shown, the control layer 50 is formed, for example, by sputtering.

[0059] (Effects of the First Embodiment)

[0060] The effects of the semiconductor device 100 according to the first embodiment will be described using a semiconductor device 300 according to a comparative example. Figure 10 FIG2 shows a cross-sectional view of a semiconductor device 300 according to a comparative example. The semiconductor device 300 according to the comparative example differs from the semiconductor device 100 according to the first embodiment in that the control layer 50 is not provided.

[0061] like Figure 9 As shown, the semiconductor device 300 of the comparative example and the semiconductor device 100 of the first embodiment are mounted on the wiring substrate 200 in a state where the drain electrode 40 faces upward. That is, the first source electrode pad 81, the second source electrode pad 82, the first gate electrode pad 91, and the second gate electrode pad 92 of the semiconductor device 100 are bonded to the conductor portion 220 of the wiring substrate 200 via the bonding material 210. The bonding material 210 is, for example, solder. In addition, the semiconductor device 100 is sealed with resin or the like, but Figure 9 The resin is omitted and shown.

[0062] In order to connect the first source electrode pad 81 , the second source electrode pad 82 , the first gate electrode pad 91 , and the second gate electrode pad 92 of the semiconductor device 100 with the bonding material 210 , the temperature of the reflow furnace is increased.

[0063] At this time, the drain electrode 40 thermally expands due to the temperature rise. The semiconductor layer 10 also thermally expands, but the linear expansion coefficient of the drain electrode 40 is generally larger than that of the semiconductor layer 10, so the expansion of the drain electrode 40 is larger than that of the semiconductor layer 10. For example, when the main material of the semiconductor layer 10 is Si and the main material of the first metal layer 41, which is the thickest in the Z direction among the metal layers of the drain electrode 40, is Ag, the linear expansion coefficient of Si is 2.8×10 -6 The linear expansion coefficient of Ag is 19.7×10 -6 The semiconductor layer 10 and the first metal layer 41 of the drain electrode 40 are bonded to each other via the second metal layer 42 and the third metal layer 43 . Therefore, the area of ​​the bonded portion of the semiconductor layer 10 and the drain electrode 40 must be constant.

[0064] Therefore, the drain electrode 40 with a large expansion increases in area, generating bending stress, and the semiconductor layer 10 and the drain electrode 40 warp toward the drain electrode 40. The warping caused by the bending stress may cause cracks in the semiconductor layer 10.

[0065] To reduce the resistance of semiconductor device 100 during on-state operation, the thickness of semiconductor layer 10 is reduced, while the thickness of first metal layer 41, which serves as the main current path for drain electrode 40, is increased. In particular, when semiconductor layer 10 is 100 μm or less, warpage increases, making cracks more likely to form in semiconductor layer 10.

[0066] In view of the above, the effects of the semiconductor device 100 according to the first embodiment will be described. The semiconductor device 100 according to the first embodiment includes a control layer 50 having a smaller linear expansion coefficient than the drain electrode 40, provided below the drain electrode 40. The temperature of the reflow furnace is increased while the drain electrode 40 is sandwiched between the semiconductor layer 10 and the control layer 50.

[0067] The drain electrode 40, which is susceptible to bending stress, is sandwiched between the semiconductor layer 10, which has a smaller linear expansion coefficient than the drain electrode 40, and the control layer 50. This suppresses bending stress caused by the difference in linear expansion coefficients. Therefore, by providing the control layer 50, low resistance during on-state operation can be maintained while suppressing crack formation in the semiconductor layer 10, thereby suppressing warping of the convex shape of the semiconductor layer 10 and the drain electrode 40 due to bending stress.

[0068] When the semiconductor device 100 of the first embodiment is used, heat may be generated, raising the temperature around the semiconductor device 100. In this case, cracks may form in the semiconductor layer 10 due to warping caused by bending stress. However, the provision of the control layer 50 can suppress the formation of cracks in the semiconductor layer 10.

[0069] Furthermore, when manufacturing the semiconductor device 300 of the comparative example, sputtering is used to form the second metal layer 42, the third metal layer 43, and a portion of the first metal layer 41 on the first surface P1 of the semiconductor layer 10. When sputtering is used, high-energy particles collide with the semiconductor layer 10, so the second metal layer 42, the third metal layer 43, and a portion of the first metal layer 41 are formed while the temperature of the semiconductor layer 10 is elevated. Next, the first metal layer 41 and the fourth metal layer 44 are formed by plating. When plating is used, the metal layers are formed at a temperature close to room temperature. Therefore, the temperature of the semiconductor layer 10 and the metal layers decreases during the process from forming the second metal layer 42, the third metal layer 43, and a portion of the first metal layer 41 to forming the first metal layer 41 and the fourth metal layer 44. As described above, since the linear expansion coefficient of the drain electrode 40 is generally greater than that of the semiconductor layer 10, the drain electrode 40 shrinks more than the semiconductor layer 10. Therefore, the area of ​​the drain electrode 40, which has shrunk significantly, is reduced, generating bending stress, causing the semiconductor layer 10 and the drain electrode 40 to deform into a convex shape on the semiconductor layer 10 side. If warping occurs in the plate state, singulation becomes difficult, and even after singulation, the warping remains, potentially causing mounting failures when the semiconductor device 100 is mounted on the wiring substrate 200.

[0070] On the other hand, in the semiconductor device 100 of the first embodiment, the control layer 50 is formed after the fourth metal layer 44 is formed. Since the control layer 50 is formed by sputtering, the temperature of the semiconductor layer 10 and the drain electrode 40 increases. The warping that occurs when the drain electrode 40 is formed is eliminated by the temperature increase. After the control layer 50 is formed, the temperature drops, but the drain electrode 40, which is prone to bending stress, is sandwiched between the semiconductor layer 10, which has a smaller linear expansion coefficient than the drain electrode 40, and the control layer 50. This suppresses the generation of bending stress caused by the difference in linear expansion coefficient. Thus, the provision of the control layer 50 can suppress convex warping of the semiconductor layer 10 and the drain electrode 40 caused by bending stress.

[0071] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention recited in the claims and their equivalents.

Claims

1. A semiconductor device comprising a first transistor, a second transistor, a third electrode, and a control layer, The first transistor includes a first region of a semiconductor layer, a first electrode, and a first gate electrode. The first region of the semiconductor layer includes a first surface and a second surface facing the first surface in a first direction. The first electrode is electrically connected to the second surface of the first region. The first gate electrode is provided in the first region. The second transistor includes a second region of the semiconductor layer, a second gate electrode, and a second electrode. The second region of the semiconductor layer is provided adjacent to the first region in a second direction intersecting the first direction and has the first surface and the second surface. The second gate electrode is provided in the second region. The second electrode is electrically connected to the second surface of the second region and provided separately from the first electrode. The third electrode is provided on the first surface side and is electrically connected to the first transistor and the second transistor. The control layer is arranged in such a manner that the third electrode is located between the control layer and the first surface. The third electrode includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, wherein the second metal layer is disposed closer to the second surface than the first metal layer, the third metal layer is disposed between the first metal layer and the second metal layer, and the fourth metal layer is disposed between the first metal layer and the control layer. The first metal layer in the third electrode is thickest in the first direction, The control layer has a smaller linear expansion coefficient than the first metal layer. 2 . The semiconductor device according to claim 1 , wherein a thickness of the first metal layer in the first direction is 10 μm or more, and a thickness of the semiconductor layer in the first direction is 100 μm or less.

3. The semiconductor device according to claim 1 or 2, wherein The first metal layer includes any one of silver and copper.

4. The semiconductor device according to claim 1 or 2, wherein The control layer includes any one of silicon, tungsten, molybdenum, and chromium.

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