Complex and transistor

Abstract

The present invention provides a novel material. The present invention is a composite oxide semiconductor comprising a first region and a plurality of second regions. The first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc, and the plurality of second regions contain indium and zinc. Because the plurality of second regions have a higher indium concentration than the first region, the plurality of second regions have a higher conductivity than the first region. An end portion of one of the plurality of second regions overlaps an end portion of another of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded by the first region.

Description

[0001] This application is a divisional application of the invention patent application with the application date of February 27, 2017, application number 201780016678.0 (PCT / IB2017 / 051114), and the invention name being “Compound and Transistor”. Technical Field

[0002] The present invention relates to an object, method, or manufacturing method. The present invention relates to a process, machine, product, or composition of matter. One embodiment of the present invention particularly relates to an oxide semiconductor or a method for manufacturing the oxide semiconductor. One embodiment of the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification, the term "semiconductor device" refers to any device that can operate by utilizing semiconductor properties. Semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are all examples of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells and organic thin-film solar cells), and electronic devices sometimes include semiconductor devices. Background Art

[0004] Non-patent document 1 discloses a method for 1-x Ga 1+x O3(ZnO) m (-1≤x≤1, m is a natural number) represents a homologous series. In addition, Non-Patent Document 1 discloses the solid solution range of the homologous phase. For example, in the solid solution range of the homologous phase when m=1, x is in the range of -0.33 to 0.08, and in the solid solution range of the homologous phase when m=2, x is in the range of -0.68 to 0.32.

[0005] A technology for forming a transistor using an In—Ga—Zn-based oxide semiconductor has been disclosed (for example, see Patent Document 1).

[0006] [References]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2007-96055

[0009] [Non-patent literature]

[0010] [Non-patent document 1] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350°C”, J. Solid State Chem., 1991, Vol. 93, pp. 298-315 Summary of the Invention

[0011] Non-patent document 1 discloses In x Zn y Ga z O w For example, when x, y, and z are set to obtain a composition near ZnGa2O4, that is, when x, y, and z are close to 0, 1, and 2, respectively, a spinel-type crystal structure is easily formed or mixed. As a compound having a spinel-type crystal structure, a compound represented by AB2O4 (A and B are metals) is known.

[0012] However, when a spinel crystal structure is formed in or mixed in an In-Ga-Zn oxide semiconductor, the electrical characteristics or reliability of a semiconductor device (e.g., a transistor) containing the In-Ga-Zn oxide semiconductor may be adversely affected by the spinel crystal structure.

[0013] In view of the above problems, an object of one embodiment of the present invention is to provide a novel oxide semiconductor. Another object of one embodiment of the present invention is to provide a semiconductor device with excellent electrical characteristics. Another object is to provide a semiconductor device with high reliability. Another object is to provide a semiconductor device with a novel structure. Another object is to provide a display device with a novel structure.

[0014] Note that the inclusion of these objectives does not preclude the existence of other objectives. In one embodiment of the present invention, not all of the above objectives need to be achieved. Other objectives are obvious and readily apparent from the description, drawings, and claims, and can be extracted from the description.

[0015] One embodiment of the present invention is a composite oxide semiconductor comprising a first region and a plurality of second regions. The first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc. The plurality of second regions contain indium and zinc. The plurality of second regions have a higher indium concentration than the first region. The plurality of second regions have a higher conductivity than the first region. An end of one of the plurality of second regions overlaps an end of another of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded by the first region.

[0016] In the composite oxide semiconductor of the above embodiment, the atomic ratio of indium, element M, and zinc (In:M:Zn) is 5:1:6 or in the vicinity thereof.

[0017] In the above embodiment, the atomic ratio of indium, element M, and zinc (In:M:Zn) in the first region is 4:2:3 or in the vicinity thereof.

[0018] In the above embodiment, the atomic ratio of indium, element M, and zinc (In:M:Zn) in the plurality of second regions is 2:0:3 or in the vicinity thereof.

[0019] In the composite oxide semiconductor of the above embodiment, the atomic ratio of indium, element M, and zinc (In:M:Zn) is 4:2:3 or in the vicinity thereof.

[0020] In the above embodiment, the atomic ratio of indium, element M, and zinc (In:M:Zn) in the first region is 1:1:1 or in the vicinity thereof.

[0021] In the above embodiment, the atomic ratio of indium, element M, and zinc (In:M:Zn) in the plurality of second regions is 2:0:1 or in the vicinity thereof.

[0022] In the above embodiment, the thickness of the plurality of second regions in the c-axis direction is greater than or equal to 0.1 nm and less than 1 nm.

[0023] In the above embodiment, the first region is non-single crystal.

[0024] In the above embodiment, the first region includes a crystal portion and has a portion where the c-axis of the crystal portion is parallel to the normal vector of the surface of the film on which the complex oxide semiconductor is formed.

[0025] In the above embodiment, the plurality of second regions are non-single-crystal.

[0026] Another embodiment of the present invention is a It is characterized by A transistor including the complex oxide semiconductor of the above embodiment.

[0027] Another embodiment of the present invention is a display device comprising: the oxide semiconductor according to any of the above embodiments and a display element. Another embodiment of the present invention is a display module comprising: the above display device and a touch sensor. Another embodiment of the present invention is an electronic device comprising: the oxide semiconductor according to any of the above embodiments, the semiconductor device, the display device, or the display module; and an operation key or a battery.

[0028] One embodiment of the present invention can provide a novel oxide semiconductor. One embodiment of the present invention can provide a semiconductor device with excellent electrical characteristics. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a semiconductor device with a novel structure can be provided. Furthermore, a display device with a novel structure can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all of the above effects. Other purposes are obvious from the description of the specification, drawings, and claims, and are extracted from the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A and Figure 1B is a schematic diagram of the structure of an oxide semiconductor.

[0031] Figure 2A and Figure 2B is a schematic diagram of the structure of an oxide semiconductor.

[0032] Figure 3A and Figure 3B is a schematic diagram of the structure of an oxide semiconductor.

[0033] Figure 4A and Figure 4B is a schematic diagram of the structure of an oxide semiconductor.

[0034] Figure 5 The atomic ratio of the oxide semiconductor is described.

[0035] Figure 6A and Figure 6B The sputtering apparatus will be described.

[0036] Figure 7A and Figure 7B The sputtering apparatus will be described.

[0037] Figures 8A to 8C The sputtering apparatus will be described.

[0038] Figure 9A and Figure 9B The sputtering apparatus will be described.

[0039] Figure 10 It is a top view showing an example of a film forming apparatus.

[0040] Figures 11A to 11C This is a cross-sectional view showing an example of a film forming apparatus.

[0041] 12A to 12C A top view and a cross-sectional structure of a transistor according to one embodiment will be described.

[0042] 13A to 13C A top view and a cross-sectional structure of a transistor according to one embodiment will be described.

[0043] 14A to 14C A top view and a cross-sectional structure of a transistor according to one embodiment will be described.

[0044] Figures 15A to 15C A top view and a cross-sectional structure of a transistor according to one embodiment will be described.

[0045] 16A to 16C A top view and a cross-sectional structure of a transistor according to one embodiment will be described.

[0046] 17A to 17C A top view and a cross-sectional structure of a transistor according to one embodiment will be described.

[0047] 18A to 18C A top view and a cross-sectional structure of a transistor according to one embodiment will be described.

[0048] Figures 19A to 19E An example of a method for manufacturing a transistor according to one embodiment will be described.

[0049] 20A to 20D An example of a method for manufacturing a transistor according to one embodiment will be described.

[0050] Figures 21A to 21C An example of a method for manufacturing a transistor according to one embodiment will be described.

[0051] Figures 22A to 22C An example of a method for manufacturing a transistor according to one embodiment will be described.

[0052] Figure 23 A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0053] Figure 24 A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0054] Figure 25 A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0055] Figure 26 A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0056] Figure 27 A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0057] Figure 28 A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0058] Figure 29A and Figure 29BA cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0059] Figure 30A and Figure 30B This is a circuit diagram of a semiconductor device according to one embodiment.

[0060] Figure 31A and Figure 31B A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0061] Figure 32A and Figure 32B A circuit diagram and a cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0062] Figure 33 A cross-sectional structure of a semiconductor device according to one embodiment will be described.

[0063] Figure 34 This is a circuit diagram showing a storage device according to one embodiment of the present invention.

[0064] Figure 35 This is a circuit diagram showing a storage device according to one embodiment of the present invention.

[0065] Figures 36A to 36C It is a circuit diagram and a timing chart illustrating one embodiment of the present invention.

[0066] Figures 37A to 37C It is a graph and a circuit diagram explaining one embodiment of the present invention.

[0067] Figure 38A and Figure 38B It is a circuit diagram and a timing chart illustrating one embodiment of the present invention.

[0068] Figure 39A and Figure 39B It is a circuit diagram and a timing chart illustrating one embodiment of the present invention.

[0069] Figures 40A to 40E It is a block diagram, a circuit diagram, and a waveform diagram illustrating one embodiment of the present invention.

[0070] Figure 41A and Figure 41B It is a circuit diagram and a timing chart illustrating one embodiment of the present invention.

[0071] Figure 42A and Figure 42B Each of them is a circuit diagram illustrating one embodiment of the present invention.

[0072] Figures 43A to 43C Each of them is a circuit diagram illustrating one embodiment of the present invention.

[0073] Figure 44A and Figure 44B Each of them is a circuit diagram illustrating one embodiment of the present invention.

[0074] Figures 45A to 45C Each of them is a circuit diagram illustrating one embodiment of the present invention.

[0075] Figure 46A and Figure 46B Each of them is a circuit diagram illustrating one embodiment of the present invention.

[0076] Figure 47 This is a block diagram showing a semiconductor device according to one embodiment of the present invention.

[0077] Figure 48 This is a circuit diagram showing a semiconductor device according to one embodiment of the present invention.

[0078] Figure 49A and Figure 49B Each of them is a top view showing a semiconductor device according to an embodiment of the present invention.

[0079] Figure 50A and Figure 50B This is a block diagram showing a semiconductor device according to one embodiment of the present invention.

[0080] Figure 51A and Figure 51B Each of them is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0081] Figure 52 This is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention.

[0082] Figure 53A and Figure 53B This is a plan view showing a semiconductor device according to one embodiment of the present invention.

[0083] Figure 54A and Figure 54B It is a flowchart explaining one embodiment of the present invention and a perspective view explaining a semiconductor device.

[0084] Figures 55A to 55F Each of them is a perspective view showing an electronic device according to an embodiment of the present invention.

[0085] Figure 56 The EDX surface analysis image of a cross section of a sample of an example is shown.

[0086] Figure 57A and Figure 57B is a BF-STEM image of a cross section of a sample of an example.

[0087] Figure 58A and Figure 58B The XRD measurement results and XRD analysis positions of a sample of one example are shown. DETAILED DESCRIPTION

[0088] The following describes the embodiments with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. Those skilled in the art will readily appreciate that the methods and details can be transformed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0089] In the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, embodiments of the present invention are not necessarily limited to the aforementioned dimensions. Furthermore, the drawings schematically illustrate idealized examples, and therefore, embodiments of the present invention are not limited to the shapes or values ​​shown in the drawings.

[0090] In this specification, ordinal numbers such as “first”, “second”, and “third” are used to avoid confusion among constituent elements, and are not intended to limit the number.

[0091] For convenience, this specification uses terms such as "upper" and "lower" to describe the positional relationships of components with reference to the accompanying drawings. The positional relationships of the components vary depending on the orientation in which they are described. Therefore, the description is not limited to the terms used in this specification and may be appropriately adapted to the circumstances.

[0092] In this specification, etc., a transistor refers to an element comprising at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain terminal, drain region, or drain electrode) and a source (source terminal, source region, or source electrode), and current can flow between the drain and source through the channel region. Note that in this specification, etc., the channel region refers to the region through which current primarily flows.

[0093] For example, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of "source" and "drain" may be interchanged. Therefore, in this specification, "source" and "drain" may be interchanged.

[0094] In this specification, "electrically connected" includes components connected together via "an element having some electrical function." This "element having some electrical function" is not particularly limited as long as it enables the transfer of electrical signals between the connected elements. Examples of "element having some electrical function" include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0095] In this specification and the like, a “silicon oxynitride film” refers to a film containing more oxygen than nitrogen, and a “silicon nitride oxide film” refers to a film containing more nitrogen than oxygen.

[0096] In this specification and the like, in describing the embodiments of the present invention using the drawings, the same components in different drawings may be denoted by the same reference numerals.

[0097] In this specification, etc., "parallel" refers to a state in which the angle formed between two straight lines is greater than -10° and less than 10°, and therefore also includes a state in which the angle is greater than -5° and less than 5°. In addition, "approximately parallel" refers to a state in which the angle formed between two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state in which the angle formed between two straight lines is greater than 80° and less than 100°, and therefore also includes a state in which the angle is greater than 85° and less than 95°. In addition, "approximately perpendicular" refers to a state in which the angle formed between two straight lines is greater than 60° and less than 120°.

[0098] In this specification, "film" and "layer" may be interchanged depending on the situation. For example, "conductive layer" may be replaced with "conductive film" or "insulating film" may be replaced with "insulating layer".

[0099] Note that, for example, when conductivity is sufficiently low, the term "semiconductor" sometimes includes the characteristics of an "insulator." Furthermore, the boundary between "semiconductor" and "insulator" is unclear, making it difficult to accurately distinguish between the two. Therefore, in this specification, "semiconductor" may sometimes be replaced with "insulator." Similarly, in this specification, "insulator" may sometimes be replaced with "semiconductor."

[0100] Implementation Method 1

[0101] In this embodiment, an oxide semiconductor which is one embodiment of the present invention is described.

[0102] The oxide semiconductor preferably contains at least indium. Indium and zinc are particularly preferred. Furthermore, it preferably contains aluminum, gallium, yttrium, or tin. Furthermore, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0103] Here, consider the case where the oxide semiconductor contains indium, element M and zinc. Element M is aluminum, gallium, yttrium or tin, etc. Alternatively, element M can be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In addition, a combination of two or more of the above elements can also be used as element M. In addition, the atomic number ratios of indium, element M and zinc in the oxide semiconductor are referred to as [In], [M], and [Zn], respectively.

[0104] <Structure of Oxide Semiconductor>

[0105] Figure 1A and Figure 1B 、 Figure 2A and Figure 2B 、 Figure 3A and Figure 3B as well as Figure 4A and Figure 4B A schematic diagram showing the oxide semiconductor of the present invention.

[0106] Figures 1A to 4B A schematic diagram showing the oxide semiconductor of the present invention. Figure 1A 、 Figure 2A 、 Figure 3A and Figure 4A These are schematic diagrams of the top surface of the oxide semiconductor (here referred to as the ab plane direction). Figure 1B 、 Figure 2B 、 Figure 3B and Figure 4B Each of them is a schematic diagram of a cross section (here referred to as the c-axis direction) of an oxide semiconductor formed on a substrate Sub.

[0107] Figures 1A to 4B Although an example of an oxide semiconductor being formed on a substrate is shown, one embodiment of the present invention is not limited to this example. An insulating film such as a base film or an interlayer film, or another semiconductor film such as an oxide semiconductor, may be formed between the substrate and the oxide semiconductor.

[0108] like Figure 1A and Figure 1B As shown, the oxide semiconductor of the present invention is a composite oxide semiconductor having a structure in which regions A1 and B1 are mixed. Region A1 is a region rich in In, where [In]:[M]:[Zn] = x:y:z (x>0, y≥0, z≥0). On the other hand, region B1 is a region poor in In, where [In]:[M]:[Zn] = a:b:c (a>0, b>0, c>0).

[0109] In this specification, when the atomic number ratio of In to element M in region A1 is greater than the atomic number ratio of In to element M in region B1, region A1 has a higher In concentration than region B1. Therefore, in this specification, region A1 is also referred to as an In-rich region, and region B1 is also referred to as an In-poor region.

[0110] For example, the In concentration of region A1 is 1.1 times or more, and preferably 2 to 10 times, the In concentration of region B1. Region A1 is an oxide containing at least In, and does not necessarily contain elements M and Zn.

[0111] <Atom Number Ratio>

[0112] Next, the atomic number ratio of elements contained in the complex oxide semiconductor according to one embodiment of the present invention will be described.

[0113] When the region A1 in the oxide semiconductor of the present invention contains In, element M, and Zn, the atomic number ratio of each element can be Figure 5 The atomic ratio of In, element M and Zn is represented as x:y:z. Figure 5 The coordinates (x:y:z) in . Note that Figure 5 The ratio of oxygen atoms is not shown.

[0114] exist Figure 5 In the figure, the dotted lines correspond to the line representing the atomic number ratio (-1≤α≤1) of [In]:[M]:[Zn]=(1+α):(1-α):1, the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):3, the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):4, and the line representing the atomic number ratio of [In]:[M]:[Zn]=(1+α):(1-α):5.

[0115] The dotted lines correspond to the line representing the atomic number ratio of [In]:[M]:[Zn]=1:1:β (β≥0), the line representing the atomic number ratio of [In]:[M]:[Zn]=1:2:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=1:3:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=1:4:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=1:7:β, the line representing the atomic number ratio of [In]:[M]:[Zn]=2:1:β and the line representing the atomic number ratio of [In]:[M]:[Zn]=5:1:β.

[0116] Figure 5 An oxide semiconductor having an atomic ratio of [In]:[M]:[Zn]=0:2:1 or in the vicinity thereof tends to have a spinel crystal structure.

[0117] Figure 5 Region A2 shows an example of a preferred range of the atomic ratio of indium, element M, and zinc contained in region A1. Region A2 also includes the atomic ratio on the line representing the atomic ratio of [In]:[M]:[Zn]=(1+γ):0:(1-γ) (-1≤γ≤1).

[0118] Figure 5 Region B2 shows an example of a preferred range of atomic ratios of indium, element M, and zinc within region B1. Region B2 includes atomic ratios ranging from [In]:[M]:[Zn] = 4:2:3 to [In]:[M]:[Zn] = 4:2:4.1 and their vicinity. This vicinity includes an atomic ratio of [In]:[M]:[Zn] = 5:3:4. Region B2 also includes an atomic ratio of [In]:[M]:[Zn] = 5:1:6 and its vicinity.

[0119] Region A2 with a high In concentration exhibits higher conductivity than region B2, thereby improving carrier mobility (field effect mobility). Therefore, the on-state current and carrier mobility of a transistor using an oxide semiconductor having region A1 are improved.

[0120] On the other hand, the region B2 having a low In concentration exhibits lower conductivity than the region A2 and thus has a function of reducing leakage current. Therefore, the off-state current of the transistor using the oxide semiconductor having the region B1 is reduced.

[0121] In the oxide semiconductor of the present invention, region A1 and region B1 form a complex. That is, carrier migration occurs easily in region A1, but not easily in region B1. Therefore, the oxide semiconductor of the present invention can be used as a material with high carrier mobility, extremely high switching characteristics, and excellent semiconductor properties.

[0122] In one example, Figure 1A As shown in FIG. 1 , the region A1 is formed in a substantially circular shape in the ab plane direction. Figure 1B As shown, region A1 is formed in a substantially elliptical shape in the c-axis direction. Therefore, region A1 is island-shaped and can be three-dimensionally surrounded by region B1. In other words, region A1 is surrounded by region B1.

[0123] like Figure 1A and Figure 1BAs shown in FIG. 1 , the regions A1 are unevenly distributed in the region B1. Therefore, there may be a plurality of regions A1 connected to each other. That is, sometimes the plurality of regions A1 may have a shape in which circles overlap in the ab plane direction or an ellipse has ends connected to each other in the c-axis direction. When all the regions A1 are connected in the ab plane direction, the switching characteristics of the transistor, for example, the off-state current of the transistor increases. Therefore, it is preferable to Figure 1A and Figure 1B As shown, the region A1 is interspersed within the region B1.

[0124] The dispersion ratio of the region A1 can be adjusted by changing the formation conditions or composition of the composite oxide semiconductor. For example, Figure 2A and Figure 2B The region A1 shown has a low ratio of a composite oxide semiconductor or Figure 3A and Figure 3B The composite oxide semiconductor shown has a high ratio of region A1. The composite oxide semiconductor of the present invention does not necessarily need a low ratio of region A1 relative to region B1. In a composite oxide semiconductor with a very high ratio of region A1, region B1 may be formed within region A1 depending on the observation range.

[0125] For example, the size of the island shape of the region A1 can be appropriately adjusted by changing the formation conditions or composition of the composite oxide semiconductor. Figures 1A to 3B The islands in the diagram have various sizes, but sometimes Figure 4A and Figure 4B As shown, there are regions A1 of approximately the same size scattered around.

[0126] Sometimes, a clear interface between region A1 and region B1 cannot be observed. The sizes of region A1 and region B1 can be determined using EDX surface analysis. For example, the thickness (also referred to as the diameter) of region A1 in a cross-sectional EDX surface analysis image may be between 0.1 nm and 5 nm, or between 0.3 nm and 3 nm. The thickness of region A1 is preferably between 0.1 nm and 1 nm.

[0127] Thus, the oxide semiconductor of one embodiment of the present invention is a composite oxide semiconductor in which region A1 and region B1 are mixed, and region A1 and region B1 have different and complementary functions. For example, when the oxide semiconductor of one embodiment of the present invention is an In-Ga-Zn oxide (hereinafter referred to as IGZO) using Ga as the element M, the oxide semiconductor can be referred to as complementary IGZO (abbreviated as C / IGZO).

[0128] On the other hand, for example, when regions A1 and B1 are stacked in layers, there is no interaction or interaction is unlikely between regions A1 and B1, so the functions of region A1 and region B1 may be independently performed. In this case, even if the carrier mobility is improved by region A1, the off-state current of the transistor may also be increased. Therefore, when using the above-mentioned composite oxide semiconductor or C / IGZO, it is possible to simultaneously achieve high carrier mobility and excellent switching characteristics. This is an excellent effect achieved by using the composite oxide semiconductor of the present invention.

[0129] When an oxide semiconductor is formed using a sputtering device, the resulting film has a slightly different atomic ratio than that of the target. In particular, the atomic ratio of zinc in the resulting film may be lower than that of the target, depending on the substrate temperature during film formation.

[0130] The properties of the composite oxide semiconductor according to one embodiment of the present invention are not determined solely by the atomic ratio. Therefore, the illustrated regions show the preferred atomic ratios of regions A1 and B1 of the composite oxide semiconductor, and their interfaces are unclear.

[0131] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include c-axis aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors, and amorphous oxide semiconductors.

[0132] CAAC-OS has c-axis orientation, and its multiple nanocrystals are linked in the ab plane direction, and its crystal structure has distortion.

[0133] In nc-OS, tiny regions (e.g., regions between 1 nm and 10 nm, and particularly between 1 nm and 3 nm) have periodic atomic arrangements. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, the orientation of the entire film cannot be observed. Consequently, depending on the analytical method, it is sometimes impossible to distinguish nc-OS from a-like OS or amorphous oxide semiconductors.

[0134] The a-like OS has a structure intermediate between nc-OS and amorphous oxide semiconductors. It contains voids or low-density regions. This means it has an unstable structure compared to nc-OS and CAAC-OS.

[0135] Oxide semiconductors have various structures and properties. The oxide semiconductor of the present invention may also be a composite oxide semiconductor including two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0136] For example, region A1 is preferably non-single-crystal. Region B1 preferably includes at least one of CAAC-OS, polycrystalline oxide semiconductor, and nc-OS. Region A1 and region B1 may also have different crystallinity.

[0137] <Transistor Having Oxide Semiconductor>

[0138] Next, a case where the above-described oxide semiconductor is used in a transistor will be described.

[0139] When the composite oxide semiconductor is used in a transistor, the transistor can have high carrier mobility and extremely high switching characteristics. In addition, the transistor can have high reliability.

[0140] It is preferable to use an oxide semiconductor with a low carrier density for transistors. For example, an oxide semiconductor with a carrier density of less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 And 1×10 -9 / cm 3 above oxide semiconductors.

[0141] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have fewer carrier generation sources and can therefore achieve low carrier density. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density and therefore may have a low trap state density.

[0142] Charge trapped in trap states in an oxide semiconductor takes a long time to be released, and sometimes behaves like fixed charge. Therefore, a transistor having a channel region formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

[0143] To achieve stable electrical characteristics for the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the film near the oxide semiconductor. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0144] Here, the influence of each impurity in the oxide semiconductor is described.

[0145] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed. Therefore, the concentration of silicon or carbon in the oxide semiconductor and near the interface of the oxide semiconductor (measured by secondary ion mass spectrometry (SIMS)) is 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0146] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect energy level is sometimes formed to generate carriers. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0147] When an oxide semiconductor contains nitrogen, electrons are generated as carriers, and the carrier density increases, so that the oxide semiconductor tends to become n-type. Therefore, a transistor including an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, it is preferable to reduce nitrogen in the oxide semiconductor as much as possible, for example, the nitrogen concentration measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0148] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, and thus oxygen vacancies (Vo When hydrogen enters the oxygen vacancy (V o ), sometimes electrons as carriers are generated. In addition, sometimes part of the hydrogen is bonded to the oxygen bonded to the metal atom, thereby generating electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0149] By introducing oxygen into an oxide semiconductor, the oxygen vacancies (V o In other words, when the oxygen vacancy (V o ) is filled with oxygen, the oxygen vacancy (V o ) disappears. Therefore, by diffusing oxygen into the oxide semiconductor, the oxygen vacancies (V o ), thereby improving the reliability of the transistor.

[0150] As a method of introducing oxygen into an oxide semiconductor, for example, an oxide containing oxygen exceeding the stoichiometric composition is provided in contact with the oxide semiconductor. That is, in the above-mentioned oxide, a region containing oxygen exceeding the stoichiometric composition (hereinafter also referred to as an oxygen excess region) is preferably formed. In particular, when an oxide semiconductor is used for a transistor, by providing an oxide having an oxygen excess region in a base film or an interlayer film near the transistor, the oxygen vacancies of the transistor can be reduced, thereby improving reliability.

[0151] When an oxide semiconductor having a sufficiently reduced impurity concentration is used for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0152] <Oxide Semiconductor Film Formation Method>

[0153] An example of a method of forming an oxide semiconductor using a sputtering method is described below.

[0154] The oxide semiconductor is preferably formed at a temperature of room temperature or higher and lower than 140° C. Note that room temperature includes not only the case where temperature control is not performed but also the case where temperature control is performed.

[0155] As the sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is suitably used. When a mixed gas is used, the ratio of oxygen to the rare gas is 5% to 30%, preferably 7% to 20%.

[0156] When the sputtering gas contains oxygen, oxygen can be added to the film below the oxide semiconductor while the oxide semiconductor is formed, and an oxygen excess region can be formed. In addition, the purity of the sputtering gas needs to be improved. For example, when a high-purity gas with a dew point of below -40°C, preferably below -80°C, more preferably below -100°C, and further preferably below -120°C is used as the sputtering gas (i.e., oxygen gas or argon gas), it is possible to prevent moisture and the like from mixing into the oxide semiconductor as much as possible.

[0157] When forming an oxide semiconductor by sputtering, it is preferable to evacuate the chamber of the sputtering apparatus to a high vacuum state (to 5×10 -7 Pa to 1×10 -4 Alternatively, it is preferred to combine a turbomolecular pump and a cold trap to prevent gas backflow, especially gas containing carbon or hydrogen from flowing back into the chamber from the exhaust system.

[0158] As the target, an In—Ga—Zn metal oxide target can be used. For example, a metal oxide target having an atomic ratio of [In]:[Ga]:[Zn]=4:2:4.1, [In]:[Ga]:[Zn]=5:1:6, or a target having an atomic ratio in the vicinity thereof is preferably used.

[0159] In the sputtering device, the target material can also be rotated or moved. For example, by swinging the magnet unit in the up and down and / or left and right directions during film formation, the composite oxide semiconductor of the present invention can be formed. For example, the target material can be rotated or moved at a beat (also known as rhythm, pulse, frequency, period or cycle, etc.) of 0.1 Hz or more and 1 kHz or less. Alternatively, the magnet unit can be shaken at a beat of 0.1 Hz or more and 1 kHz or less. Details of the sputtering device will be described in the following embodiments.

[0160] For example, the oxide semiconductor of the present invention can be formed by: using a mixed gas of oxygen and a rare gas with an oxygen ratio of about 10%; the substrate temperature is 130°C; and shaking an In-Ga-Zn metal oxide target with an atomic number ratio of [In]: [Ga]: [Zn] = 4:2:4.1 during film formation.

[0161] First, in the film formation chamber, a rare gas or oxygen is ionized into cations and electrons, forming a plasma. The cations in the plasma are accelerated toward the target by a potential applied to the target holder. When the cations collide with the In-Ga-Zn metal oxide target, sputtered particles are generated, which are deposited on the substrate.

[0162] When cations collide with the In-Ga-Zn metal oxide target, Ga and Zn, whose relative atomic masses are lower than In, are ejected from the target first. The ejected In, Ga, and Zn then bond with oxygen and deposit on the substrate, forming region B1. At this point, In is segregated on the target surface.

[0163] Next, the segregated In on the target surface is ejected from the target in a multi-particle structure. The segregated In, with its multi-particle structure, bonds with oxygen and initially collides with the formed region B1, expanding into a nearly circular shape before depositing in the island-shaped region A1. This ejection of the segregated In leaves the In, Ga, and Zn atoms on the target surface in a state close to their original atomic ratios.

[0164] When the cations collide with the target again, Ga and Zn, whose relative atomic masses are lower than In, are ejected from the target first. At this point, In is segregated on the target surface. Region B1 is repeatedly deposited on previously formed Region B1 and Region A1, forming Region B1 sandwiching Region A1.

[0165] Furthermore, In segregates in one region of the target surface, while the segregated In is ejected in another region. In other words, the In segregation and ejection mechanisms occur simultaneously, forming an irregular segregation structure with region A1 surrounded by region B1.

[0166] It can be considered that after the above film forming model is formed Figure 1A and Figure 1B 、 Figure 2A and Figure 2B 、 Figure 3A and Figure 3B or Figure 4A and Figure 4B The illustrated region A1 and region B1 are mixed with a composite oxide semiconductor.

[0167] In the oxide semiconductor of the present invention, a region A1 having an atomic ratio shown in region A2 and a high content of In, and a region B1 having an atomic ratio shown in region B2 and a low content of In, are mixed together to form a composite oxide semiconductor. In other words, carrier migration is more likely to occur in region A1, while it is less likely to occur in region B1. Therefore, the oxide semiconductor of the present invention can be used as a material with high carrier mobility, extremely high switching characteristics, and excellent semiconductor properties.

[0168] The structure described in this embodiment mode can be appropriately combined with the structures described in other embodiment modes and examples.

[0169] Implementation Method 2

[0170] In this embodiment, referring to Figure 6A and Figure 6B 、 Figure 7A and Figure 7B 、 Figures 8A to 8C 、 Figure 9A and Figure 9B 、 Figure 10 as well as Figures 11A to 11C A sputtering apparatus and film-forming apparatus capable of forming an oxide according to an embodiment of the present invention will be described. To facilitate understanding and explanation of film-forming operations, the following description assumes that the sputtering apparatus is configured with a substrate, target, and other components. Note that the substrate, target, and other components are user-configured, so the sputtering apparatus according to an embodiment of the present invention does not necessarily need to include a substrate and target.

[0171] <Sputtering device>

[0172] Examples of sputtering devices include parallel plate sputtering devices and opposed target sputtering devices. Note that film formation using a parallel plate sputtering device can be referred to as parallel electrode sputtering (PESP), while film formation using an opposed target sputtering device can also be referred to as vapor deposition sputtering (VDSP).

[0173] [Parallel Plate Sputtering System (PESP)]

[0174] First, a parallel plate sputtering device will be described. Figure 6A It is a cross-sectional view of a film forming chamber 601 of a parallel plate sputtering device. Figure 6AThe film forming chamber 601 includes a target holder 620, a pad 610, a target 600, a magnet unit 630, and a substrate holder 670. In addition, the target 600 is arranged on the pad 610. The pad 610 is arranged on the target holder 620. The magnet unit 630 is arranged under the target 600 across the pad 610. The substrate holder 670 faces the target 600. In addition, in this specification, the magnet unit refers to a combination of multiple magnets. "Magnet unit" may also be referred to as "cathode", "cathode magnet", "magnetic component", "magnetic part", etc. The magnet unit 630 includes a magnet 630N, a magnet 630S, and a magnet holder 632. In addition, in the magnet unit 630, the magnet 630N and the magnet 630S are arranged on the magnet holder 632. The magnet 630N is spaced apart from the magnet 630S. When the substrate 660 is moved into the film forming chamber 601, the substrate 660 is set on the substrate holder 670.

[0175] The target holder 620 and the backing plate 610 are fixed to each other by screws (eg, bolts) and have the same potential. The target holder 620 has a function of supporting the target 600 via the backing plate 610 .

[0176] The target 600 is fixed to the backing plate 610. For example, the target 600 can be fixed to the backing plate 610 using an adhesive member containing a low melting point metal such as indium.

[0177] Figure 6A Magnetic lines of force 680 a and 680 b formed by the magnet unit 630 are shown.

[0178] The magnetic field line 680a is one of the magnetic field lines forming the horizontal magnetic field near the top surface of the target 600. The vicinity of the top surface of the target 600 corresponds to, for example, a region with a vertical distance from the target 600 of 0 mm to 10 mm, particularly 0 mm to 5 mm.

[0179] Magnetic line 680b is one of the magnetic lines that form a horizontal magnetic field in a plane perpendicularly spaced d from the top surface of magnet unit 630. Perpendicular distance d is, for example, 0 mm to 20 mm, or 5 mm to 15 mm.

[0180] Here, by using magnets 630N and 630S with high magnetic force, a large magnetic field can be generated near the top surface of substrate 660. Specifically, the magnetic flux density of the horizontal magnetic field near the top surface of substrate 660 can be greater than 10G and less than 100G, preferably greater than 15G and less than 60G, and more preferably greater than 20G and less than 40G.

[0181] Note that the magnetic flux density of the horizontal magnetic field may be a value measured when the magnetic flux density of the vertical magnetic field is 0 G.

[0182] By setting the magnetic flux density of the magnetic field in the film forming chamber 601 to the above range, a high-density and high-crystalline oxide can be formed. The formed oxide contains almost no multiple crystal phases and has a substantially single crystal phase.

[0183] Figure 6B 6 is a top view of magnet unit 630. In magnet unit 630, a circular or substantially circular magnet 630N and a circular or substantially circular magnet 630S are fixed to magnet holder 632. Magnet unit 630 can rotate about a normal vector at the center of the top surface of magnet unit 630 or a normal vector at the approximate center of the top surface of magnet unit 630 as the rotation axis. For example, magnet unit 630 can rotate at a beat (also known as a rhythm, pulse, frequency, period, or cycle) of 0.1 Hz or higher and 1 kHz or lower.

[0184] Therefore, the area of ​​the target 600 where the magnetic field is strong changes with the rotation of the magnet unit 630. The area where the magnetic field is strong is a high-density plasma area, so sputtering of the target 600 is likely to occur near this area. For example, when the area where the magnetic field is strong is fixed, only a specific area of ​​the target 600 is used. In contrast, Figure 6B As shown, when the magnet unit 630 is rotated, plasma 640 is generated between the target 600 and the substrate 660, thereby making it possible to uniformly use the target 600. By rotating the magnet unit 630, a film having uniform thickness and uniform quality can be formed.

[0185] By rotating the magnet unit 630 , the direction of the magnetic field lines on the top surface of the substrate 660 can also be changed.

[0186] Although the magnet unit 630 is rotated in this example, one embodiment of the present invention is not limited to this example. For example, the magnet unit 630 may be shaken in the up and down and / or left and right directions. For example, the magnet unit 630 may be shaken at a beat of 0.1 Hz or more and 1 kHz or less. Alternatively, the target 600 may be rotated or moved. For example, the target 600 may be rotated or moved at a beat of 0.1 Hz or more and 1 kHz or less. Alternatively, by rotating the substrate 660, the direction of the magnetic field lines on the top surface of the substrate 660 may be relatively changed. Alternatively, the above methods may be combined.

[0187] The film forming chamber 601 may also have a water channel inside or below the backing plate 610. By flowing a fluid (air, nitrogen, rare gas, water, oil, etc.) through this water channel, damage to the film forming chamber 601 caused by abnormal discharge due to temperature rise of the target 600 during sputtering or deformation of components can be suppressed. In this case, it is preferable to bond the backing plate 610 and the target 600 together with an adhesive member to improve cooling performance.

[0188] It is preferable to provide a gasket between the target holder 620 and the backing plate 610 . In this case, impurities are less likely to enter the film forming chamber 601 from the outside or the water channel.

[0189] In the magnet unit 630, the magnet 630N and the magnet 630S are arranged so that the surface on one side of the target 600 has opposite polarities. Here, the polarity of the magnet 630N on the target 600 side is the N pole, and the polarity of the magnet 630S on the target 600 side is the S pole. Note that the arrangement of the magnets and polarities in the magnet unit 630 is not limited to the arrangement or arrangement described here. Figure 6A Configuration shown.

[0190] When film formation is performed, the potential V1 applied to the terminal V1 connected to the target holder 620 is, for example, lower than the potential V2 applied to the terminal V2 connected to the substrate holder 670. The potential V2 applied to the terminal V2 connected to the substrate holder 670 is, for example, the ground potential. The potential V3 applied to the terminal V3 connected to the magnet holder 632 is, for example, the ground potential. Note that the potentials applied to the terminals V1, V2, and V3 are not limited to the potentials described above. It is not necessary to apply potentials to all of the target holder 620, the substrate holder 670, and the magnet holder 632. For example, the substrate holder 670 may also be in an electrically floating state. Although in Figure 6A In the illustrated example, a potential V1 is applied to a terminal V1 connected to the target holder 620 (i.e., DC sputtering is employed). However, one embodiment of the present invention is not limited thereto. For example, a so-called RF sputtering method may be employed, in which a high-frequency power source having a frequency of, for example, 13.56 MHz or 27.12 MHz is connected to the target holder 620.

[0191] Figure 6A Although the example in which the backing plate 610 and the target holder 620 are not electrically connected to the magnet unit 630 and the magnet holder 632 is shown, the electrical connection is not limited to this. For example, the backing plate 610 and the target holder 620 may be electrically connected to the magnet unit 630 and the magnet holder 632, and the backing plate 610, the target holder 620, the magnet unit 630 and the magnet holder 632 may have the same potential.

[0192] To improve the crystallinity of the resulting oxide, the temperature of substrate 660 can be increased. Increasing the temperature of substrate 660 can promote the migration of sputtered particles on the top surface of substrate 660. Consequently, an oxide with higher density and higher crystallinity can be formed. For example, the temperature of substrate 660 is 100°C to 450°C, preferably 150°C to 400°C, and more preferably 170°C to 350°C.

[0193] When the oxygen partial pressure in the film-forming gas is too high, oxides containing multiple crystalline phases are easily formed. Therefore, it is preferable to use a mixture of a rare gas such as argon (other examples of rare gases include helium, neon, krypton, and xenon) and oxygen as the film-forming gas. For example, the oxygen ratio in the entire film-forming gas should be less than 50 vol%, preferably less than 33 vol%, more preferably less than 20 vol%, and even more preferably less than 15 vol%.

[0194] The vertical distance between the target 600 and the substrate 660 is 10 mm to 600 mm, preferably 20 mm to 400 mm, more preferably 30 mm to 200 mm, and even more preferably 40 mm to 100 mm. By reducing the vertical distance between the target 600 and the substrate 660 within the above range, it is sometimes possible to suppress the energy reduction of the sputtered particles before they reach the substrate 660. By increasing the vertical distance between the target 600 and the substrate 660 within the above range, it is sometimes possible to make the direction of the sputtered particles incident on the substrate 660 close to vertical, thereby reducing damage to the substrate 660 caused by the collision of the sputtered particles.

[0195] Figure 7A Shown with Figure 6A Examples of different film forming chambers.

[0196] Figure 7A The film forming chamber 601 includes a target holder 620a, a target holder 620b, a backing plate 610a, a backing plate 610b, a target 600a, a target 600b, a magnet unit 630a, a magnet unit 630b, a component 642, and a substrate holder 670. The target 600a is arranged on the backing plate 610a. The backing plate 610a is arranged on the target holder 620a. The magnet unit 630a is arranged below the target 600a with the backing plate 610a interposed therebetween. The target 600b is arranged on the backing plate 610b. The backing plate 610b is arranged on the target holder 620b. The magnet unit 630b is arranged below the target 600b with the backing plate 610b interposed therebetween.

[0197] The magnet unit 630a includes a magnet 630N1, a magnet 630N2, a magnet 630S, and a magnet holder 632. In the magnet unit 630a, the magnets 630N1, 630N2, and 630S are arranged on the magnet holder 632. The magnets 630N1 and 630N2 are spaced apart from the magnet 630S. The magnet unit 630b has the same structure as the magnet unit 630a. When the substrate 660 is loaded into the film forming chamber 601, the substrate 660 is placed on the substrate holder 670.

[0198] The target 600a, backing plate 610a, and target holder 620a are separated from the target 600b, backing plate 610b, and target holder 620b by a member 642. The member 642 is preferably an insulator. However, the member 642 may also be a conductor or semiconductor. The member 642 may also be a conductor or semiconductor whose surface is covered with an insulator.

[0199] The target holder 620a and the backing plate 610a are fixed to each other by screws (e.g., bolts) and have the same potential. The target holder 620a has the function of supporting the target 600a via the backing plate 610a. The target holder 620b and the backing plate 610b are fixed to each other by screws (e.g., bolts) and have the same potential. The target holder 620b has the function of supporting the target 600b via the backing plate 610b.

[0200] The backing plate 610a has a function of fixing the target 600a. The backing plate 610b has a function of fixing the target 600b.

[0201] Figure 7A Magnetic lines of force 680a and magnetic lines of force 680b formed by the magnet unit 630a are shown.

[0202] Magnetic line 680a is one of the magnetic lines of force that form the horizontal magnetic field near the top surface of target 600a. The vicinity of the top surface of target 600a corresponds to, for example, a region with a vertical distance from target 600a of 0 mm to 10 mm, particularly 0 mm to 5 mm.

[0203] Magnetic line 680b is one of the magnetic lines that form a horizontal magnetic field in a plane perpendicular to the top surface of magnet unit 630a. Perpendicular distance d is, for example, 0 mm to 20 mm or 5 mm to 15 mm.

[0204] Here, by using the magnet 630N1, the magnet 630N2, and the magnet 630S with large magnetic force, a large magnetic field can be generated near the top surface of the substrate 660. Specifically, the magnetic flux density of the horizontal magnetic field near the top surface of the substrate 660 can be greater than 10G and less than 100G, preferably greater than 15G and less than 60G, and more preferably greater than 20G and less than 40G.

[0205] By setting the magnetic flux density of the magnetic field in the film forming chamber 601 to the above range, a high-density and high-crystalline oxide can be formed. The formed oxide contains almost no multiple crystal phases and has a substantially single crystal phase.

[0206] The magnet unit 630b forms the same magnetic lines of force as those formed by the magnet unit 630a.

[0207] Figure 7BFIG is a top view of the magnet units 630a and 630b. In the magnet unit 630a, a square or substantially square magnet 630N1, a square or substantially square magnet 630N2, and a square or substantially square magnet 630S are fixed to the magnet frame 632. Figure 7B As shown, the magnet unit 630a can be shaken in the left-right direction. For example, the magnet unit 630a can be shaken at a beat of 0.1 Hz or more and 1 kHz or less.

[0208] Therefore, the area with a strong magnetic field on the target 600a changes as the magnet unit 630a swings. The area with a strong magnetic field is a high-density plasma area, so sputtering of the target 600a is likely to occur near this area. For example, when the area with a strong magnetic field is fixed, only a specific area of ​​the target 600a is used. In contrast, Figure 7B As shown, when the magnet unit 630a is swung, plasma 640 is generated between the target 600a and the substrate 660, thereby making the target 600a uniformly usable. By oscillating the magnet unit 630a, a film having uniform thickness and uniform quality can be formed.

[0209] By swinging the magnet unit 630a, the state of the magnetic field lines near the substrate 660 can also be changed. The same applies to the magnet unit 630b.

[0210] Although the magnet unit 630a and the magnet unit 630b are swung in this example, one embodiment of the present invention is not limited to this example. For example, the magnet unit 630a and the magnet unit 630b may be rotated. For example, the magnet unit 630a and the magnet unit 630b may be rotated at a beat of 0.1 Hz or more and 1 kHz or less. Alternatively, the target 600 may be rotated or moved. For example, the target 600 may be rotated or moved at a beat of 0.1 Hz or more and 1 kHz or less. Alternatively, by rotating the substrate 660, the state of the magnetic field lines on the top surface of the substrate 660 may be relatively changed. Alternatively, the above methods may be combined.

[0211] The film forming chamber 601 may also have a water channel inside or below the pads 610a and 610b. By allowing a fluid (air, nitrogen, rare gas, water, oil, etc.) to flow through the water channel, damage to the film forming chamber 601 caused by abnormal discharge or deformation of components caused by the temperature rise of the targets 600a and 600b during sputtering can be suppressed. In this case, it is preferred to bond the pad 610a and the target 600a together with an adhesive member because the cooling performance is improved. In addition, it is preferred to bond the pad 610b and the target 600b together with an adhesive member because the cooling performance is improved.

[0212] A gasket is preferably provided between the target holder 620a and the backing plate 610a, so that impurities are not easily intruded into the film forming chamber 601 from the outside or the waterway. A gasket is preferably provided between the target holder 620b and the backing plate 610b, so that impurities are not easily intruded into the film forming chamber 601 from the outside or the waterway.

[0213] In the magnet unit 630a, the magnets 630N1, 630N2, and 630S are arranged so that the surfaces on the target 600a side have opposite polarities. Here, the polarity of the magnets 630N1 and 630N2 on the target 600a side is the N pole, and the polarity of the magnet 630S on the target 600a side is the S pole. Note that the arrangement of the magnets and polarities in the magnet unit 630a is not limited to the arrangement or arrangement described here. Figure 7A The configuration shown is also the same as that of the magnet unit 630b.

[0214] When film formation is performed, the potential applied to the terminal V1 connected to the target holder 620a and the potential applied to the terminal V4 connected to the target holder 620b can be alternately switched to a high level and a low level. When the potential applied to the terminal V1 is one of a high level and a low level, the potential applied to the terminal V4 is the other of a high level and a low level. The potential applied to the terminal V2 connected to the substrate holder 670 is, for example, a ground potential. The potential applied to the terminal V3 connected to the magnet holder 632 is, for example, a ground potential. Note that the potentials applied to the terminals V1, V2, V3 and V4 are not limited to the potentials described above. It is not necessary to apply potentials to all of the target holder 620a, the target holder 620b, the substrate holder 670 and the magnet holder 632. For example, the substrate holder 670 may also be in an electrically floating state. In Figure 7A In the example shown, the potential applied to the terminal V1 connected to the target holder 620a and the potential applied to the terminal V4 connected to the target holder 620b are alternately switched to high level and low level (ie, AC sputtering method), but one embodiment of the present invention is not limited to this.

[0215] Figure 7AAn example is shown in which the backing plate 610a and target holder 620a are not electrically connected to the magnet unit 630a and magnet holder 632, but the electrical connection is not limited to this. For example, the backing plate 610a and target holder 620a may be electrically connected to the magnet unit 630a and magnet holder 632, and the backing plate 610a, target holder 620a, magnet unit 630a, and magnet holder 632 may have the same electrical potential. An example is also shown in which the backing plate 610b and target holder 620b are not electrically connected to the magnet unit 630b and magnet holder 632, but the electrical connection is not limited to this. For example, the backing plate 610a and target holder 620b may be electrically connected to the magnet unit 630b and magnet holder 632, and the backing plate 610b, target holder 620b, magnet unit 630b, and magnet holder 632 may have the same electrical potential.

[0216] To improve the crystallinity of the resulting oxide, the temperature of substrate 660 can be increased. Increasing the temperature of substrate 660 can promote the migration of sputtered particles on the top surface of substrate 660. Consequently, an oxide with higher density and higher crystallinity can be formed. For example, the temperature of substrate 660 is 100°C to 450°C, preferably 150°C to 400°C, and more preferably 170°C to 350°C.

[0217] When the oxygen partial pressure in the film-forming gas is too high, oxides containing multiple crystalline phases are easily formed. Therefore, it is preferable to use a mixture of a rare gas such as argon (other examples of rare gases include helium, neon, krypton, and xenon) and oxygen as the film-forming gas. For example, the oxygen ratio in the entire film-forming gas should be less than 50 vol%, preferably less than 33 vol%, more preferably less than 20 vol%, and even more preferably less than 15 vol%.

[0218] The vertical distance between the target 600a and the substrate 660 is 10 mm to 600 mm, preferably 20 mm to 400 mm, more preferably 30 mm to 200 mm, and even more preferably 40 mm to 100 mm. By reducing the vertical distance between the target 600a and the substrate 660 within the above range, it is sometimes possible to suppress the energy reduction of the sputtered particles before they reach the substrate 660. By increasing the vertical distance between the target 600a and the substrate 660 within the above range, it is sometimes possible to make the direction of the sputtered particles incident on the substrate 660 close to vertical, thereby reducing damage to the substrate 660 caused by the collision of the sputtered particles.

[0219] The vertical distance between the target 600b and the substrate 660 is 10 mm to 600 mm, preferably 20 mm to 400 mm, more preferably 30 mm to 200 mm, and even more preferably 40 mm to 100 mm. By reducing the vertical distance between the target 600b and the substrate 660 within the above range, it is sometimes possible to suppress the energy reduction of the sputtered particles before they reach the substrate 660. By increasing the vertical distance between the target 600b and the substrate 660 within the above range, it is sometimes possible to make the direction of the sputtered particles incident on the substrate 660 close to vertical, thereby reducing damage to the substrate 660 caused by the collision of the sputtered particles.

[0220] [Vosed Target Sputtering System (VDSP)]

[0221] Next, the opposing target type sputtering apparatus will be described. Figure 8A This is a cross-sectional view of a film forming chamber of an opposing target sputtering device. Figure 8A The film forming chamber shown includes a target 600a, a target 600b, a backing plate 610a for holding the target 600a, a backing plate 610b for holding the target 600b, a magnet unit 630a disposed on the back side of the target 600a across the backing plate 610a, and a magnet unit 630b disposed on the back side of the target 600b across the backing plate 610b. A substrate holder 670 is disposed between the target 600a and the target 600b. The substrate holder 670 is disposed above the area where the target 600a and the target 600b face each other (also referred to as the inter-target area). A substrate 660 is brought into the film forming chamber and then secured to the substrate holder 670.

[0222] like Figure 8A As shown, the substrate holder 670 is positioned above the inter-target region, but it can also be positioned below the region. Alternatively, the substrate holder 670 can be positioned above and below the region. Placing the substrate holder 670 above and below the region allows simultaneous film formation on two or more substrates, thereby improving productivity.

[0223] like Figure 8A As shown, power supplies 690 and 691 for applying potential are connected to pads 610a and 610b. It is preferable to use an AC power supply that alternately applies a high level potential and a low level potential to pads 610a and 610b. Figure 8A The power supplies 690 and 691 are shown as AC power supplies, but one embodiment of the present invention is not limited thereto. For example, RF power supplies, DC power supplies, etc. may be used as the power supplies 690 and 691. Alternatively, different types of power supplies may be used as the power supplies 690 and 691.

[0224] The substrate holder 670 is preferably connected to GND. The substrate holder 670 can also be in a floating state.

[0225] Figure 8B and Figure 8C All show along Figure 8A The potential distribution of plasma 640 along the dot-dashed line AB. Figure 8B The potential distribution when a high potential is applied to the backing plate 610a and a low potential is applied to the backing plate 610b is shown. In this case, the positive ions are accelerated toward the target 600b. Figure 8C The potential distribution when a low potential is applied to the pad 610a and a high potential is applied to the pad 610b is shown. At this time, the cations are accelerated toward the target 600a. Figure 8B Status and Figure 8C The film is formed by alternating the states.

[0226] exist Figure 8A In the embodiment, target 600a and target 600b are parallel to each other. Furthermore, magnet unit 630a and magnet unit 630b are arranged with opposite poles facing each other. At this time, magnetic lines of force extend from magnet unit 630b to magnet unit 630a. Therefore, during film formation, plasma 640 is enclosed in the magnetic field formed by magnet units 630a and 630b. Therefore, substrate holder 670 and substrate 660 are located outside plasma 640. Substrate 660 is not exposed to the high electric field region of plasma 640, thereby reducing damage caused by plasma 640.

[0227] Opposing target sputtering devices can stably generate plasma even in high vacuum conditions. This allows film formation at pressures of, for example, 0.005 Pa to 0.09 Pa. This reduces the concentration of impurities introduced during film formation.

[0228] By using a facing target sputtering device, film formation can be performed under high vacuum, or film formation with less plasma damage can be performed, so a highly crystalline film can be provided even when the temperature of the substrate 660 is low (for example, above 10°C and below 100°C).

[0229] Figure 9A The structure shown is Figure 8A The difference of the structure shown is that the opposing targets 600a and 600b are not parallel, but are arranged in a tilted (V-shaped) configuration. Figure 8A The magnet unit 630a and the magnet unit 630b are arranged in a manner that the opposite poles are opposite to each other. The substrate holder 670 and the substrate 660 are arranged on the upper side of the inter-target area. Figure 9AArranging the targets 600a and 600b as shown can increase the ratio of sputtered particles reaching the substrate 660, thereby increasing the deposition rate.

[0230] Figure 9B Another example of an opposing target sputtering apparatus will be described.

[0231] Figure 9B This is a schematic cross-sectional view of the film forming chamber of an opposing target sputtering device. Figure 8A Unlike the film-forming chamber shown, target shields 622 and 623 are installed. A power supply 691 is also provided, connected to the backing plates 610a and 610b. A substrate holder 670 is positioned above the inter-target area. This prevents the substrate 660 from being exposed to the high electric field of the plasma 640, thereby reducing damage caused by the plasma 640.

[0232] like Figure 9B As shown, the substrate holder 670 is positioned above the inter-target region, but it can also be positioned below the region. Furthermore, the substrate holder 670 can be positioned above or below the region. Placing the substrate holder 670 above or below the region allows simultaneous film formation on two or more substrates, thereby improving productivity.

[0233] like Figure 9B As shown, the target shields 622 and 623 are connected to GND. That is, the plasma 640 is generated by the potential difference between the pads 610a and 610b to which the potential of the power supply 691 is applied and the target shields 622 and 623 to which GND is applied.

[0234] In this opposed-target sputtering system, the plasma is confined by the magnetic field between the targets, reducing plasma damage to the substrate. Furthermore, by tilting the targets, the angle of incidence of sputtered particles on the substrate is reduced, improving the step coverage of the deposited film. Furthermore, by performing film formation under high vacuum, the concentration of impurities in the film can be reduced.

[0235] A parallel plate sputtering device or an ion beam sputtering device may also be provided in the film forming chamber.

[0236] <Film Forming Equipment>

[0237] Next, a film forming apparatus including a film forming chamber in which a sputtering target can be installed according to one embodiment of the present invention will be described.

[0238] First, refer to Figure 10 and Figures 11A to 11C The structure of a film forming apparatus in which impurities that are mixed into a film during film formation are minimal will be described.

[0239] Figure 10This is a schematic top view of a single wafer multi-chamber film deposition apparatus 2700. The film deposition apparatus 2700 includes an atmospheric-side substrate supply chamber 2701 equipped with a cassette port 2761 for storing substrates and an alignment port 2762 for performing substrate alignment; an atmospheric-side substrate transfer chamber 2702 for transferring substrates from the atmospheric-side substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure from atmospheric pressure to reduced pressure or vice versa; an unload lock chamber 2703b for unloading substrates and switching the pressure from reduced pressure to atmospheric pressure or vice versa; a transfer chamber 2704 for transferring substrates in a vacuum; a substrate heating chamber 2705 for heating substrates; and film deposition chambers 2706a, 2706b, and 2706c, each containing a sputtering target for film deposition. Note that regarding the film forming chambers 2706a, 2706b, and 2706c, the structure of the film forming chamber described above can be referred to.

[0240] The atmospheric side substrate transfer chamber 2702 is connected to the loading lock chamber 2703a and the unloading lock chamber 2703b, the loading lock chamber 2703a and the unloading lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the substrate heating chamber 2705, the film forming chambers 2706a, 2706b and 2706c.

[0241] Gate valves 2764 are provided at the connection points of the chambers, thereby independently maintaining the vacuum state of each chamber except for the atmospheric-side substrate supply chamber 2701 and the atmospheric-side substrate transfer chamber 2702. Transfer robots 2763 are provided in both the atmospheric-side substrate transfer chamber 2702 and the transfer chamber 2704 to enable transfer of substrates.

[0242] The substrate heating chamber 2705 preferably also serves as a plasma processing chamber. In the film formation apparatus 2700, substrates can be transferred between processes without being exposed to the atmosphere, thereby suppressing adsorption of impurities onto the substrates. Furthermore, the order of film formation and heat treatment can be freely determined. The number of transfer chambers, film formation chambers, load lock chambers, unload lock chambers, and substrate heating chambers is not limited to the numbers listed above and can be appropriately determined based on the space available for their installation and process conditions.

[0243] then, Figure 11A 、 Figure 11B and Figure 11C yes Figure 10 The film forming apparatus 2700 shown is a cross-sectional view taken along the dashed line X1 - X2 , a cross-sectional view taken along the dashed line Y1 - Y2 , and a cross-sectional view taken along the dashed line Y2 - Y3 .

[0244] Figure 11A The substrate heating chamber 2705 and the transfer chamber 2704 are shown in cross section. The substrate heating chamber 2705 has a plurality of heating stages 2765 capable of accommodating substrates. The substrate heating chamber 2705 is connected to a vacuum pump 2770 via a valve. As the vacuum pump 2770, for example, a dry pump or a mechanical booster pump can be used.

[0245] As a heating mechanism that can be used for the substrate heating chamber 2705, for example, a resistance heating element can also be used for heating. Alternatively, heat conduction or heat radiation from a medium such as a heated gas can also be used as a heating mechanism. For example, rapid thermal annealing (RTA) such as gas rapid thermal annealing (GRTA) or lamp rapid thermal annealing (LRTA) can be used. LRTA is a method of heating an object by radiation of light (electromagnetic waves) emitted by lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. In GRTA, heat treatment is performed using high-temperature gas. An inert gas is used as the gas.

[0246] Furthermore, the substrate heating chamber 2705 is connected to a refiner 2781 via a mass flow controller 2780. Note that, although a mass flow controller 2780 and a refiner 2781 may be provided for each of a plurality of gases, for ease of understanding, only one mass flow controller 2780 and one refiner 2781 are shown. As the gas introduced into the substrate heating chamber 2705, a gas having a dew point of -80°C or lower, preferably -100°C or lower, such as oxygen gas, nitrogen gas, and a rare gas (e.g., argon gas) can be used.

[0247] The transfer chamber 2704 has a transfer robot 2763. The transfer robot 2763 can transfer the substrate to each chamber. The transfer chamber 2704 is connected to the vacuum pump 2770 and the cryopump 2771 through a valve. By adopting the above structure, the vacuum pump 2770 is used to evacuate from atmospheric pressure to low vacuum or medium vacuum (0.1 Pa to several hundred Pa), and then the valve is switched and the cryopump 2771 is used to evacuate from medium vacuum to high vacuum or ultra-high vacuum (0.1 Pa to 1×10 -7 Pa).

[0248] Alternatively, two or more cryopumps 2771 may be connected in parallel to the transfer chamber 2704. This configuration allows exhaust to be performed by other cryopumps even when one cryopump is undergoing regeneration. Note that regeneration is the process of releasing molecules (or atoms) accumulated in the cryopump. When too many molecules (or atoms) accumulate in the cryopump, its exhaust capacity decreases, requiring periodic regeneration.

[0249] Figure 11B The cross sections of the film forming chamber 2706b, the transfer chamber 2704, and the load lock chamber 2703a are shown.

[0250] Here, refer to Figure 11B The detailed structure of the film forming chamber (sputtering chamber) will be described. Figure 11B The film forming chamber 2706b shown includes a target 2766a, a target 2766b, a target shield 2767a, a target shield 2767b, a magnet unit 2790a, a magnet unit 2790b, a substrate holder 2768, and a power supply 2791. Although not shown, the targets 2766a and 2766b are fixed to the target holder via a backing plate. The power supply 2791 is electrically connected to the targets 2766a and 2766b. The magnet unit 2790a is positioned on the back side of the target 2766a, and the magnet unit 2790b is positioned on the back side of the target 2766b. The target shield 2767a is positioned so as to surround the end of the target 2766a, and the target shield 2767b is positioned so as to surround the end of the target 2766b. Here, the substrate holder 2768 supports the substrate 2769. The substrate holder 2768 is fixed to the film forming chamber 2706b by a variable member 2784. The variable member 2784 allows the substrate holder 2768 to be moved. The substrate holder 2768 is positioned above the region between the target 2766a and the target 2766b (also referred to as the inter-target region). For example, by positioning the substrate holder 2768, which supports the substrate 2769, above the inter-target region, plasma damage can be reduced. Although not shown, the substrate holder 2768 may also include a substrate holding mechanism for holding the substrate 2769 or a heater for heating the substrate 2769 from the back.

[0251] like Figure 11B As shown, the substrate holder 2768 is positioned above the inter-target region, but it may also be positioned below the region. Alternatively, the substrate holder 2768 may be positioned above and below the region. Placing the substrate holder 2768 above and below the region allows for simultaneous film formation on two or more substrates, thereby improving productivity.

[0252] The target shield 2767 can prevent particles sputtered from the target 2766 from being deposited in undesired areas. Furthermore, the target shield 2767 is preferably processed to prevent the deposited sputtered particles from peeling off. For example, sandblasting can be performed to increase the surface roughness, or unevenness can be formed on the surface of the target shield 2767.

[0253] The film forming chamber 2706b is connected to the mass flow controller 2780 via a gas heating mechanism 2782, and the gas heating mechanism 2782 is connected to the refiner 2781 via the mass flow controller 2780. By utilizing the gas heating mechanism 2782, the gas introduced into the film forming chamber 2706b can be heated to a temperature of 40°C or higher and 400°C or lower. Note that although the gas heating mechanism 2782, the mass flow controller 2780, and the refiner 2781 can be provided corresponding to each of a plurality of gases, for ease of understanding, only one gas heating mechanism 2782, one mass flow controller 2780, and one refiner 2781 are shown. As the gas introduced into the film forming chamber 2706b, a gas having a dew point of -80°C or lower, preferably -100°C or lower, such as oxygen gas, nitrogen gas, and a rare gas (e.g., argon gas) can be used.

[0254] When a refiner is provided near the gas inlet, the length of the pipe between the refiner and the film forming chamber 2706b is less than 10m, preferably less than 5m, and more preferably less than 1m. When the length of the pipe is less than 10m, less than 5m or less than 1m, the influence of the released gas from the pipe can be reduced. As a gas pipe, a metal pipe whose interior is covered with ferric fluoride, aluminum oxide or chromium oxide can be used. By using the above-mentioned pipe, the amount of gas containing impurities released is less than that of the SUS316L-EP pipe, and the mixing of impurities into the gas can be reduced. In addition, as a joint of the pipe, a high-performance ultra-small metal gasket joint (UPG joint) can be used. A structure in which all materials of the pipe are metal is preferred because the influence of the released gas or external leakage generated can be reduced compared to a structure using resin or the like.

[0255] The film forming chamber 2706 b is connected to a turbo molecular pump 2772 and a vacuum pump 2770 via a valve.

[0256] In addition, the film forming chamber 2706 b is provided with a low-temperature cold trap 2751 .

[0257] The cryogenic cold trap 2751 is a mechanism that can adsorb molecules (or atoms) with a high melting point, such as water. The turbomolecular pump 2772 can stably discharge large molecules (or atoms) and has a low maintenance frequency, so it can achieve high productivity, but its ability to discharge hydrogen and water is low. Therefore, in order to improve the ability to discharge water, etc., the cryogenic cold trap 2751 is connected to the film forming chamber 2706b. The temperature of the refrigerator of the cryogenic cold trap 2751 is set to below 100K, preferably below 80K. When the cryogenic cold trap 2751 has multiple refrigerators, it is preferably set to a different temperature for each refrigerator, so that exhaust can be performed efficiently. For example, the temperature of the refrigerator in the first stage can be set to below 100K, and the temperature of the refrigerator in the second stage can be set to below 20K. When a titanium sublimation pump is used instead of a cryogenic cold trap, a higher vacuum can sometimes be obtained. By using an ion pump instead of a cryogenic cold trap or a turbomolecular pump, a higher vacuum can sometimes be obtained.

[0258] The exhaust method of the film forming chamber 2706b is not limited to the above method, and the same structure as the exhaust method of the transfer chamber 2704 (exhaust method using a cryopump and a vacuum pump) can be used. Of course, the exhaust method of the transfer chamber 2704 can also have the same structure as the exhaust method of the film forming chamber 2706b (exhaust method using a turbomolecular pump and a vacuum pump).

[0259] In the transfer chamber 2704, substrate heating chamber 2705, and film formation chamber 2706b, the back pressure (total pressure) and the partial pressures of the gas molecules (atoms) are preferably set as follows. In particular, the back pressure and the partial pressures of the gas molecules (atoms) in the film formation chamber 2706b should be carefully considered because impurities may be incorporated into the formed film.

[0260] In each of the above chambers, the back pressure (total pressure) is 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 Pa or less. In each of the above chambers, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less. In addition, in each of the above chambers, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 28 is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less. In addition, in each of the above chambers, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 44 is 3×10 -5 Pa or less, preferably 1×10-5 Pa or less, more preferably 3×10 -6 Below Pa.

[0261] The total pressure and partial pressure in the vacuum chamber can be measured using a mass analyzer. For example, a quadrupole mass analyzer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0262] In addition, it is preferable that the external leakage and internal leakage of the above-mentioned transfer chamber 2704, substrate heating chamber 2705 and film forming chamber 2706b are small.

[0263] For example, in the above-mentioned transfer chamber 2704, substrate heating chamber 2705 and film forming chamber 2706b, the leakage rate is 3×10 - 6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. The leakage rate of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. The leakage rate of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. The leakage rate of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0264] The leakage rate can be obtained from the total pressure and partial pressure measured by the mass analyzer.

[0265] The leakage rate is determined by both external and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system through tiny holes or poor seals. Internal leakage is caused by leaks through valves and other partitions within the vacuum system, or by gas release from internal components. To keep the leakage rate below the above values, measures must be taken against both external and internal leakage.

[0266] For example, a metal gasket can be used to seal the opening / closing portion of the film-forming chamber 2706b. Metals coated with ferric fluoride, aluminum oxide, or chromium oxide are preferably used as metal gaskets. Metal gaskets have higher tightness than O-rings and can reduce external leakage. By using a passive metal coated with ferric fluoride, aluminum oxide, chromium oxide, or the like, it is possible to suppress the release of gases containing impurities from the metal gasket, thereby reducing internal leakage.

[0267] Film-forming apparatus 2700 components are made of aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain impurities and release little gas. Alternatively, alloys containing iron, chromium, and nickel, etc., coated with these components, can be used. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for machining. Polishing, for example, to reduce surface irregularities and surface area can also reduce released gas.

[0268] Alternatively, the components of the film forming apparatus 2700 may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0269] It is preferable to use only metal as much as possible for the components of the film forming apparatus 2700. For example, when providing a viewing window made of quartz or the like, the surface of the viewing window is preferably covered with a thin layer of ferric fluoride, aluminum oxide, or chromium oxide to suppress outgassing.

[0270] When adsorbents are present in the film forming chamber, they do not affect the pressure of the film forming chamber because they are adsorbed to the inner wall, etc. However, when the film forming chamber is evacuated, the adsorbents cause gas to be released. Therefore, although the leakage rate is not related to the exhaust speed, it is important to remove the adsorbents present in the film forming chamber as much as possible and to pre-exhaust the chamber using a pump with high exhaust capacity. In order to promote the detachment of adsorbents, the film forming chamber can also be baked. By baking, the detachment rate of adsorbents can be increased by about 10 times. This baking can be performed at a temperature range of 100°C to 450°C. At this time, when an inert gas is introduced into the film forming chamber while removing the adsorbents, the detachment rate of water, etc., which is not easily detached by exhaust alone, can be further increased. When the introduced inert gas is heated to a temperature similar to the baking temperature, the detachment rate of adsorbents can be further increased. Here, a rare gas is preferably used as the inert gas. Depending on the type of film to be formed, oxygen or the like can also be used instead of the inert gas. For example, when forming an oxide film, it is sometimes preferable to use oxygen, which is the main component of the oxide. It is preferable to use a lamp for baking.

[0271] In addition, it is preferred to increase the pressure in the film forming chamber by introducing an inert gas such as a heated rare gas or heated oxygen, and to exhaust the film forming chamber again after a certain period of time. The adsorbent in the film forming chamber can be detached by the introduction of the heated gas, thereby reducing the impurities present in the film forming chamber. When the treatment is repeated for more than 2 times and less than 30 times, preferably more than 5 times and less than 15 times, a good effect can be obtained. Specifically, by introducing an inert gas or oxygen at a temperature of more than 40°C and less than 400°C, preferably more than 50°C and less than 200°C, the pressure in the film forming chamber is set to more than 0.1 Pa and less than 10 kPa, preferably more than 1 Pa and less than 1 kPa, more preferably more than 5 Pa and less than 100 Pa in a time range of 1 minute to 300 minutes, preferably more than 5 minutes to 120 minutes. Then, the film forming chamber is exhausted in a time range of 5 minutes to 300 minutes, preferably more than 10 minutes to 120 minutes.

[0272] The rate of adsorbate release can be further increased by performing pseudo-film formation. Pseudo-film formation refers to forming a film on a pseudo-substrate using a sputtering method or other method. A film is deposited on the pseudo-substrate and on the inner walls of the film-forming chamber, thereby trapping impurities within the chamber and adsorbates on the chamber walls within the film. Pseudo-substrates that release minimal gas are preferably used. Performing pseudo-film formation can reduce the impurity concentration in the subsequently formed film. Alternatively, pseudo-film formation can be performed simultaneously with baking in the film-forming chamber.

[0273] Next, explain Figure 11B The transfer chamber 2704 and the load lock chamber 2703a are shown as well as Figure 11C Detailed structures of the atmospheric side substrate transfer chamber 2702 and the atmospheric side substrate supply chamber 2701 are shown. Figure 11C Cross sections of the atmospheric side substrate transfer chamber 2702 and the atmospheric side substrate supply chamber 2701 are shown.

[0274] about Figure 11B The transfer chamber 2704 shown can be referred to as Figure 11A A record of the transfer chamber 2704 is shown.

[0275] The load lock chamber 2703a includes a substrate transfer stage 2752. When the pressure of the load lock chamber 2703a is increased from reduced pressure to atmospheric pressure, the substrate transfer stage 2752 receives a substrate from a transfer robot 2763 provided in the atmospheric-side substrate transfer chamber 2702. The load lock chamber 2703a is then evacuated to a reduced pressure state, and the transfer robot 2763 provided in the transfer chamber 2704 receives the substrate from the substrate transfer stage 2752.

[0276] The load lock chamber 2703a is connected to a vacuum pump 2770 and a cryopump 2771 via valves. The connection method of the exhaust system, such as the vacuum pump 2770 and the cryopump 2771, can be found in the connection method of the transfer chamber 2704, so the description thereof is omitted here. Figure 10 The unload lock chamber 2703b shown may have the same structure as the load lock chamber 2703a.

[0277] The atmospheric-side substrate transfer chamber 2702 includes a transfer robot 2763. The transfer robot 2763 can transfer substrates from the cassette interface 2761 to the load lock chamber 2703a, or vice versa. Furthermore, a mechanism such as a high-efficiency particulate air (HEPA) filter may be provided above the atmospheric-side substrate transfer chamber 2702 and the atmospheric-side substrate supply chamber 2701 to prevent the ingress of dust and particles.

[0278] The atmosphere-side substrate supply chamber 2701 has a plurality of cassette interfaces 2761. The cassette interfaces 2761 can accommodate a plurality of substrates.

[0279] The surface temperature of the target is set to below 100°C, preferably below 50°C, and more preferably around room temperature (typically 25°C). In sputtering devices corresponding to large-area substrates, large-area targets are mostly used. However, it is difficult to form a target corresponding to a large-area substrate without joints. In practice, multiple targets are arranged into a larger shape with as few gaps as possible, but there will always be a small gap anyway. When the surface temperature of the target rises, zinc and the like sometimes evaporate from the small gap, causing the gap to gradually become larger. When the gap becomes larger, sometimes the metal of the pad or the metal of the adhesive material used to bond the pad and the target is also sputtered, resulting in a higher impurity concentration. Therefore, it is preferred to fully cool the target.

[0280] Specifically, in order to effectively cool the target, a metal having high electrical conductivity and high heat dissipation properties (specifically, copper) is used as the backing plate, or a water channel is formed in the backing plate and a sufficient amount of cooling water is flowed through the water channel.

[0281] When the target contains zinc, film formation is performed in an oxygen gas atmosphere to reduce plasma damage, thereby obtaining an oxide that is less likely to volatilize zinc.

[0282] The above film forming apparatus can form a film with a hydrogen concentration of 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3less than 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 The following oxide semiconductors.

[0283] In addition, the nitrogen concentration measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 The following oxide semiconductors.

[0284] In addition, the carbon concentration measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 The following oxide semiconductors.

[0285] Oxides with few impurities and oxygen vacancies have low carrier density (specifically, less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and is 1×10 -9 / cm 3 Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has low impurity concentration and defect state density. Therefore, it can be said that CAAC-OS is an oxide with stable characteristics.

[0286] In addition, the emission amounts of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 2 (hydrogen molecules, etc.), gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18, gas molecules (atoms) with a mass-to-charge ratio (m / z) of 28, and gas molecules (atoms) with a mass-to-charge ratio (m / z) of 44 measured by TDS are all 1×1019 pieces / cm 3 Below, preferably 1×10 18 pieces / cm 3 The following oxide semiconductors.

[0287] By using the above-mentioned film forming apparatus, it is possible to suppress the incorporation of impurities into the oxide. Furthermore, when a film in contact with the oxide is formed using the above-mentioned film forming apparatus, it is possible to suppress the incorporation of impurities from the film in contact with the oxide into the oxide.

[0288] The structure described in this embodiment mode can be appropriately combined with the structures described in other embodiment modes and examples.

[0289] Implementation 3

[0290] In this embodiment, referring to 12A to 12C 、 13A to 13C 、 14A to 14C 、 Figures 15A to 15C 、 16A to 16C 、 17A to 17C 、 18A to 18C 、 Figures 19A to 19E 、 20A to 20D 、 Figures 21A to 21C as well as Figures 22A to 22C One embodiment of a semiconductor device will be described.

[0291] <Transistor Structure 1>

[0292] Next, an example of a transistor according to one embodiment of the present invention will be described. 12A to 12C 1 and 2 are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. Figure 12A It is a top view. Figure 12B It is along Figure 12A Cross-sectional view along the dotted line X1-X2. Figure 12C It is along Figure 12A Note that for the sake of clarity, Figure 12A Some components are omitted in the top view.

[0293] Transistor 200 includes: a conductor 205 (conductors 205a and 205b) and a conductor 260 used as a gate electrode; insulators 220, 222, 224 and an insulator 250 used as a gate insulating layer; an oxide 230 (oxides 230a, 230b and 230c) having a region in which a channel is formed; a conductor 240a used as one of a source and a drain; a conductor 240b used as the other of the source and the drain; an insulator 280 containing excess oxygen; and an insulator 282 having a blocking function.

[0294] Oxide 230 includes oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. When transistor 200 is turned on, current mainly flows through oxide 230b (forming a channel). On the other hand, although current flows near the interface between oxide 230b and oxide 230a or 230c (sometimes a mixed region), other regions of oxide 230a and 230c sometimes function as insulators.

[0295] like 12A to 12C As shown, oxide 230c is preferably provided to cover the side surfaces of oxides 230a and 230b. Oxide 230c provided between insulator 280 and oxide 230b including the channel forming region can prevent impurities such as hydrogen, water, and halogen from diffusing from insulator 280 to oxide 230b.

[0296] The conductor 205 is formed using a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing these elements as components (e.g., a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film). In particular, metal nitride films such as tantalum nitride films are preferred because they have barrier properties against hydrogen and oxygen and are not easily oxidized (having high oxidation resistance). Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added may be used.

[0297] For example, a conductor having hydrogen barrier properties, such as tantalum nitride, can be used as conductor 205a, and highly conductive tungsten can be stacked as conductor 205b. By using this combination of materials, hydrogen diffusion into oxide 230 can be suppressed while maintaining the electrical conductivity of the wiring. 12A to 12C Although a two-layer structure of conductors 205a and 205b is shown, one embodiment of the present invention is not limited thereto and may also employ a single-layer structure or a stacked structure of three or more layers. For example, a conductor having a high degree of compactness relative to the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0298] The insulator 224 is preferably an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film. In particular, the insulator 224 is preferably an insulator containing excess oxygen (containing more oxygen than the stoichiometric composition). When such an insulator containing excess oxygen is provided in contact with the oxide 230 in the transistor 200, it can fill oxygen vacancies in the oxide 230.

[0299] Furthermore, when the insulator 224 includes an excess oxygen region, the insulator 222 preferably has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against oxygen, oxygen in the excess oxygen region is efficiently supplied to the oxide 230 without diffusing toward the transistor 300. This can suppress the reaction between the conductor 205 and the oxygen in the excess oxygen region of the insulator 224.

[0300] The insulator 222 preferably has a single-layer structure or a stacked-layer structure using an insulator such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST). In particular, an insulating film having barrier properties against oxygen or hydrogen, such as an aluminum oxide film or a hafnium oxide film, is preferably used. The insulator 222 formed of such a material serves as a layer to prevent the release of oxygen from the oxide 230 or the incorporation of impurities such as hydrogen from the outside.

[0301] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Furthermore, the insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0302] The insulators 220, 222, and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being made of the same material, and may be a stacked structure made of different materials.

[0303] Since insulator 222 made of a high-k material is provided between insulator 220 and insulator 224, insulator 222 may capture electrons under certain conditions, thereby increasing the threshold voltage. As a result, insulator 222 may sometimes be negatively charged.

[0304] For example, when insulator 220 and insulator 224 are formed using silicon oxide, and insulator 222 is formed using a material having a large number of electron capture levels, such as hafnium oxide, aluminum oxide, or tantalum oxide, the potential of conductor 205 is maintained higher than the potential of the source electrode or drain electrode at a temperature higher than the operating temperature or storage temperature of the semiconductor device (for example, 125° C. to 450° C., typically 150° C. to 300° C.) for 10 milliseconds or longer, typically 1 minute or longer. This allows electrons to move from the oxide constituting transistor 200 to conductor 205. At this time, some of the moving electrons are captured by the electron capture levels of insulator 222.

[0305] When the required number of electrons is captured at the electron-trapping level of the insulator 222, the threshold voltage of the transistor shifts toward the positive side. By controlling the voltage of the conductor 205, the amount of electrons captured can be controlled, thereby controlling the threshold voltage. The transistor 200 having the above structure is a normally-off transistor that is in a non-conducting state (also called an off state) even when the gate voltage is 0V.

[0306] Alternatively, the electron trapping process can be performed during the transistor manufacturing process. For example, it is preferably performed at any stage before shipment, such as after forming a conductor connected to the source or drain conductor of the transistor, after a pre-process (wafer processing), after a wafer dicing process, or after packaging.

[0307] The threshold voltage can be controlled by appropriately adjusting the thickness of insulators 220, 222, and 224. For example, when the combined thickness of insulators 220, 222, and 224 is small, the voltage from conductor 205 is efficiently applied, thereby providing a transistor with low power consumption. The combined thickness of insulators 220, 222, and 224 is 65 nm or less, preferably 20 nm or less.

[0308] Therefore, a transistor with low leakage current in the off state can be provided. A transistor with stable electrical characteristics can be provided. A transistor with large on-state current can be provided. A transistor with a small subthreshold swing value can be provided. A transistor with high reliability can be provided.

[0309] The oxides 230a, 230b, and 230c are formed using a metal oxide such as In-M-Zn oxide (M is Al, Ga, Y, or Sn). In-Ga oxide or In-Zn oxide may also be used as the oxide 230.

[0310] As the oxide 230 b , the oxide semiconductor described in the above embodiment mode can be used.

[0311] When oxides 230a and 230b or oxides 230b and 230c contain a common element other than oxygen (as a main component), a mixed layer with a low defect state density can be formed. For example, when oxide 230b is an In-Ga-Zn oxide, oxides 230a and 230c are preferably In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like.

[0312] At this time, oxide 230b serves as the main path for carriers. Since the defect state density at the interface between oxides 230a and 230b and the interface between oxides 230b and 230c can be reduced, the effect of interface scattering on carrier conduction is small, thereby obtaining a large on-state current.

[0313] When electrons are trapped in a trap state, they behave like fixed charges, causing the threshold voltage of the transistor to shift positively. Oxides 230a and 230c can keep the trap states away from oxide 230b. This structure prevents the threshold voltage of the transistor from shifting positively.

[0314] Oxides 230a and 230c are made of materials having sufficiently lower conductivity than oxide 230b. In this case, oxide 230b, the interface between oxides 230b and 230a, and the interface between oxides 230b and 230c are mainly used as channel regions.

[0315] For example, when used as oxide 230b Figure 5 When the oxides forming a composite body of region A2 and region B2 are used, it is preferable to use oxides 230a and 230c having a [M] / [In] ratio of 1 or more, preferably 2 or more. Furthermore, it is preferable to use an oxide 230c having a [M] / ([Zn]+[In]) ratio of 1 or more, which can provide sufficiently high insulation properties.

[0316] As the insulator 250, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) can be used. The insulator can have a single-layer structure or a stacked-layer structure. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the above-mentioned insulator. In addition, the above-mentioned insulator can also be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can also be stacked on the above-mentioned insulator.

[0317] As with the insulator 224, an oxide insulator having an oxygen content exceeding the stoichiometric composition is preferably used as the insulator 250. When the insulator containing excess oxygen is provided in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced.

[0318] As the insulator 250, an insulating film having barrier properties against oxygen or hydrogen, formed of aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride, or the like, can be used. The insulator 250 formed of such a material serves as a layer to prevent oxygen from being released from the oxide 230 or impurities such as hydrogen from being mixed in from the outside.

[0319] Insulator 250 may also have the same stacked structure as insulators 220, 222, and 224. When insulator 250 has an amount of electrons required for electron-trapping, the threshold voltage of transistor 200 can be shifted toward the positive side. Transistor 200 having the above structure is a normally-off transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

[0320] exist 12A to 12C In the transistor shown, a barrier film may be provided between the oxide 230 and the conductor 260 in addition to the insulator 250. Alternatively, the oxide 230c may also have a barrier property.

[0321] For example, by providing an insulating film containing excess oxygen in contact with the oxide 230 and surrounding these films with a barrier film, the composition of the oxide can be made substantially consistent with the stoichiometric composition or supersaturated with oxygen exceeding the stoichiometric composition. Furthermore, the intrusion of impurities such as hydrogen into the oxide 230 can be prevented.

[0322] One of the conductors 240 a and 240 b serves as a source electrode, and the other serves as a drain electrode.

[0323] Conductors 240a and 240b can be made of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys containing these elements as main components. In particular, metal nitride films such as tantalum nitride films are preferred because they have barrier properties against hydrogen and oxygen and have high oxidation resistance.

[0324] Although 12A to 12C Although a single-layer structure is shown, a stacked structure of two or more layers may also be used. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Other examples include a two-layer structure of an aluminum film stacked on a tungsten film, a two-layer structure of a copper film stacked on a copper-magnesium-aluminum alloy film, a two-layer structure of a copper film stacked on a titanium film, and a two-layer structure of a copper film stacked on a tungsten film.

[0325] Other examples include a three-layer structure in which a titanium film or a titanium nitride film is formed, an aluminum film or a copper film is stacked on the titanium film or titanium nitride film, and a titanium film or a titanium nitride film is formed on the aluminum film or copper film; and a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed, an aluminum film or a copper film is stacked on the molybdenum film or molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed on the aluminum film or copper film. Alternatively, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0326] The conductor 260 used as the gate electrode can be formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above metals as its component, or an alloy containing a combination of the above metals. In particular, metal nitride films such as tantalum nitride films are preferred because they have barrier properties to hydrogen and oxygen and have high oxidation resistance. In addition, one or both of manganese and zirconium can also be used. In addition, semiconductors represented by polysilicon doped with impurity elements such as phosphorus, and silicides such as nickel silicide can also be used. Although in 12A to 12C Although a single-layer structure is shown in FIG, a stacked-layer structure of two or more layers may also be used.

[0327] For example, a two-layer structure can be employed in which a titanium film is stacked on an aluminum film. Other examples include a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, or a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film.

[0328] Another example is a three-layer structure in which a titanium film is formed, an aluminum film is stacked on the titanium film, and a titanium film is formed on the aluminum film. Alternatively, an alloy film or a nitride film containing aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

[0329] Conductor 260 can be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon oxide. Conductor 260 can have a stacked structure using the above-mentioned light-transmitting conductive materials and the above-mentioned metals.

[0330] Next, an insulator 280 and an insulator 282 are provided over the transistor 200 .

[0331] Insulator 280 preferably includes an oxide containing more oxygen than the stoichiometric composition. That is, a region containing more oxygen than the stoichiometric composition (hereinafter also referred to as an excess oxygen region) is preferably formed in insulator 280. In particular, when an oxide semiconductor is used for transistor 200, providing an insulator having an excess oxygen region in an interlayer film or the like near transistor 200 can reduce oxygen vacancies in transistor 200, thereby improving reliability.

[0332] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which a portion of oxygen is released by heating means that the amount of oxygen released in TDS analysis is 1.0×10 18 atoms / cm 3 above, preferably 3.0×10 20 atoms / cm 3Note that the surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower.

[0333] For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon nitride oxide" refers to a material containing more nitrogen than oxygen.

[0334] The insulator 280 covering the transistor 200 can also function as a planarization film that covers the uneven shape thereunder.

[0335] The insulator 282 is preferably formed using an insulating film having barrier properties against oxygen and hydrogen, such as aluminum oxide or hafnium oxide. The insulator 282 formed of such a material serves as a layer to prevent oxygen from being released from the oxide 230 or impurities such as hydrogen from being mixed in from the outside.

[0336] By adopting the above structure, a transistor including an oxide semiconductor having a large on-state current can be provided. Furthermore, a transistor including an oxide semiconductor having a low off-state current can be provided. Furthermore, when a transistor having the above structure is used in a semiconductor device, variations in the electrical characteristics of the semiconductor device can be reduced, thereby improving reliability. Furthermore, power consumption of the semiconductor device can be reduced.

[0337] <Transistor Structure 2>

[0338] 13A to 13C Other examples that can be applied to the transistor 200 are shown. Figure 13A The top surface of transistor 200 is shown. Figure 13A Part of the membrane is not shown. Figure 13B It is along Figure 13A The cross-sectional view along the dot-dash line X1-X2 in FIG. Figure 13C It is along Figure 13A The cross-sectional view along the dotted line Y1-Y2 in FIG.

[0339] Note that in 13A to 13C In the transistor 200 shown, the 12A to 12C Components having the same functions as those of the transistor 200 are denoted by the same reference numerals.

[0340] exist 13A to 13CIn the structure shown, the conductor 260 has a two-layer structure. For example, the conductor 260a can be formed using an oxide represented by In-Ga-Zn oxide. The oxide semiconductor represented by In-Ga-Zn oxide has a higher carrier density when supplied with nitrogen or hydrogen. In other words, the oxide semiconductor is used as an oxide conductor (OC). When a metal nitride is provided as the conductor 260b, the carrier density of the oxide semiconductor becomes higher, so the conductor 260a is used as a gate electrode.

[0341] The conductor 260a can be formed using an oxide semiconductor represented by In-Ga-Zn oxide. The conductor 260a can also be formed using a light-transmitting conductive material such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide containing silicon (In-Sn-Si oxide, also known as ITSO).

[0342] Using a metal nitride as conductor 260b produces two effects: The constituent elements of the metal nitride (particularly nitrogen) diffuse into conductor 260a, reducing the resistance of conductor 260a; and the resistance of conductor 260b is reduced due to damage (e.g., sputtering damage) during the formation of conductor 260b. Furthermore, conductor 260b may have a stacked structure of two or more layers. For example, by stacking a low-resistance metal film on a metal nitride, a transistor with a low driving voltage can be provided.

[0343] Furthermore, the conductor 260a is preferably formed by sputtering in an atmosphere containing oxygen. When the conductor 260a is formed in an atmosphere containing oxygen, an excess oxygen region can be formed in the insulator 250. The method for forming the conductor 260a is not limited to sputtering, and other methods, such as ALD, may also be used.

[0344] exist 13A to 13C In the structure shown, insulator 270 is provided to cover conductor 260. When insulator 280 is formed using an oxide material from which oxygen is released, insulator 270 is formed using a material that has oxygen barrier properties. This structure fills oxygen vacancies in conductor 260a, suppressing a decrease in carrier density, and prevents oxidation of conductor 260b by diffused oxygen.

[0345] For example, the insulator 270 can be formed using a metal oxide such as aluminum oxide. The insulator 270 is formed to have a thickness sufficient to prevent oxidation of the conductor 260 .

[0346] As shown in the drawings, a structure can also be adopted in which conductor 205c is provided using a conductor having barrier properties instead of insulators 220 and 222. With this structure, even if insulator 224 includes an excess oxygen region, the formation of oxides by reacting conductor 205b with oxygen in the excess oxygen region can be suppressed.

[0347] Alternatively, insulators 243a and 243b may be provided on conductors 240a and 240b. Insulators 243a and 243b are formed using a material that has oxygen barrier properties. This structure can suppress oxidation of conductors 240a and 240b during the formation of oxide 230c. Furthermore, it can prevent oxygen in the excess oxygen region of insulator 280 from reacting with conductors 240a and 240b and causing oxidation.

[0348] The insulator 243a and the insulator 243b can be formed using, for example, a metal oxide. In particular, an insulating film having barrier properties against oxygen or hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide, is preferably used. Alternatively, silicon nitride formed by CVD may be used.

[0349] Therefore, by adopting this structure, the range of materials that can be selected for conductors 240a, 240b, 205, and 260 can be expanded. For example, conductors 205b and 260b can be formed using a material with low oxidation resistance and high conductivity, such as aluminum. Furthermore, conductors that are easy to form or process can be used.

[0350] Furthermore, oxidation of the conductors 205 and 260 can be suppressed, and oxygen released from the insulators 224 and 280 can be efficiently supplied to the oxide 230. Furthermore, by using highly conductive conductors as the conductors 205 and 260, the transistor 200 can be provided with low power consumption.

[0351] <Transistor Structure 3>

[0352] 14A to 14C Other examples that can be applied to the transistor 200 are shown. Figure 14A The top surface of transistor 200 is shown. Figure 14A Omit part of the membrane. Figure 14B It is along Figure 14A The cross-sectional view along the dot-dash line X1-X2 in FIG. Figure 14C It is along Figure 14A The cross-sectional view along the dotted line Y1-Y2 in FIG.

[0353] Note that in 14A to 14C In the transistor 200 shown, the 12A to 12CComponents having the same functions as those of the transistor 200 are denoted by the same reference numerals.

[0354] exist 14A to 14C In the structure shown, the conductor 260 has a two-layer structure. In a two-layer structure, layers formed of the same material may be stacked. For example, the conductor 260a is formed using a thermal CVD method, an MOCVD method, or an ALD method. In particular, the conductor 260a is preferably formed using an ALD method. By using an ALD method, etc., damage to the insulator 250 during film formation can be reduced. In addition, by using an ALD method, etc., a conductor 260a that can provide high coverage can be formed. Therefore, a transistor 200 with high reliability can be provided.

[0355] Next, conductor 260b is formed by sputtering. Since conductor 260a is provided on insulator 250, damage to conductor 260b during formation can be prevented from affecting insulator 250. Since sputtering has a faster film formation rate than ALD, it can achieve a higher yield and improve productivity.

[0356] exist 14A to 14C In the structure shown, insulator 270 is provided to cover conductor 260. When insulator 280 is formed using an oxide material from which oxygen is released, insulator 270 is formed using a material that has oxygen barrier properties. This structure fills oxygen vacancies in conductor 260a, suppressing a decrease in carrier density, and prevents oxidation of conductor 260b by diffused oxygen.

[0357] For example, the insulator 270 can be formed using a metal oxide such as aluminum oxide. The insulator 270 is formed to have a thickness sufficient to prevent oxidation of the conductor 260 .

[0358] <Transistor Structure 4>

[0359] Figures 15A to 15C Other examples that can be applied to the transistor 200 are shown. Figure 15A The top surface of transistor 200 is shown. Figure 15A Omit part of the membrane. Figure 15B It is along Figure 15A The cross-sectional view along the dot-dash line X1-X2 in FIG. Figure 15C It is along Figure 15A The cross-sectional view along the dotted line Y1-Y2 in FIG.

[0360] Note that in Figures 15A to 15C In the transistor 200 shown, the 12A to 12C Components having the same functions as those of the transistor 200 are denoted by the same reference numerals.

[0361] exist Figures 15A to 15C In the structure shown, the conductor 260 used as the gate electrode includes a conductor 260a, a conductor 260b, and a conductor 260c. The oxide 230c can be cut on the insulator 224 as long as it covers the side surfaces of the oxide 230b.

[0362] exist Figures 15A to 15C In the structure shown, the conductor 260 has a three-layer structure. The conductor 260 may also have a single-layer structure, a double-layer structure, or a stacked structure of four or more layers. When a double-layer structure is adopted, layers formed of the same material may be stacked. For example, the conductor 260a is formed using a thermal CVD method, an MOCVD method, or an ALD method. In particular, the conductor 260a is preferably formed using an ALD method. By adopting an ALD method or the like, damage to the insulator 250 during film formation can be reduced. In addition, by adopting an ALD method or the like, a conductor 260a that can provide high coverage can be formed. Therefore, a transistor 200 with high reliability can be provided.

[0363] Next, conductor 260b is formed by sputtering. Since conductor 260a is provided on insulator 250, damage to conductor 260b during formation can be prevented from affecting insulator 250. Since sputtering has a faster film formation rate than ALD, it can achieve a higher yield and improve productivity.

[0364] The conductor 260b is formed of a highly conductive material such as tantalum, tungsten, copper, or aluminum. The conductor 260c formed on the conductor 260b is preferably formed of a highly oxidizing-resistant conductor such as tungsten nitride.

[0365] For example, when the insulator 280 is formed using an oxide material that desorbs oxygen, by using a highly oxidizing-resistant conductor as the conductor 260 c having a large area in contact with the insulator 280 having the excess oxygen region, it is possible to suppress absorption of oxygen desorbed from the excess oxygen region by the conductor 260. Furthermore, oxidation of the conductor 260 can be suppressed, and oxygen desorbed from the insulator 280 can be efficiently supplied to the oxide 230. Furthermore, by using a highly oxidizing conductor as the conductor 260 b, a transistor 200 with low power consumption can be provided.

[0366] like Figure 15CAs shown, in the channel width direction of the transistor 200, the oxide 230b is covered by the conductor 260. The insulator 224 has a convex portion, so that the side surface of the oxide 230b is also covered by the conductor 260. For example, it is preferable that, by adjusting the shape of the convex portion of the insulator 224, in the region where the insulator 224 and the oxide 230c are in contact with each other, the bottom surface of the conductor 260 is closer to the substrate side than the bottom surface of the oxide 230b. In other words, the transistor 200 has a structure in which the oxide 230b can be electrically surrounded by the electric field of the conductor 260. The structure in which the oxide 230b is electrically surrounded by the electric field of the conductor is called a surrounded channel (s-channel) structure. In the transistor 200 with an s-channel structure, a channel can be formed in the entire (bulk) of the oxide 230b. In the s-channel structure, the drain current of the transistor can be increased, thereby obtaining a larger on-state current (the current flowing between the source and the drain when the transistor is in the on state). Furthermore, the entire channel formation region of oxide 230b can be depleted by the electric field of conductor 260. Therefore, the off-state current of the s-channel transistor can be further reduced. Shortening the channel width enhances the effects of the s-channel structure, such as increasing on-state current and reducing off-state current.

[0367] <Transistor Structure 5>

[0368] 16A to 16C Another example that can be applied to the transistor 200 is shown. Figure 16A The top surface of transistor 200 is shown. Figure 16A Part of the membrane is not shown. Figure 16B It is along Figure 16A The cross-sectional view along the dot-dash line X1-X2 in FIG. Figure 16C It is along Figure 16A The cross-sectional view along the dotted line Y1-Y2 in FIG.

[0369] Note that in 16A to 16C In the transistor 200 shown, the 12A to 12C Components having the same functions as those of the transistor 200 are denoted by the same reference numerals.

[0370] exist 16A to 16C In the structure shown, the conductors used as the source and drain electrodes both have a stacked structure. Conductors 240a and 240b are preferably formed using a material that has good adhesion to oxide 230b, and conductors 241a and 241b are preferably formed using a highly conductive material. Conductors 240a and 240b are preferably formed using an ALD method. Using ALD, for example, can improve coverage.

[0371] For example, when a metal oxide containing indium is used as the oxide 230b, titanium nitride or the like can be used as the conductors 240a and 240b. When a highly conductive material such as tantalum, tungsten, copper, or aluminum is used as the conductors 241a and 241b, a transistor 200 with high reliability and low power consumption can be provided.

[0372] like Figure 16C As shown, the oxide 230 b is covered by the conductor 260 in the channel width direction of the transistor 200 . The insulator 222 has a convex portion, so that the side surfaces of the oxide 230 b are also covered by the conductor 260 .

[0373] Here, when a high-k material such as hafnium oxide is used as the insulator 222, the insulator 222 has a large relative dielectric constant, so the equivalent oxide (SiO2) thickness (EOT) of the insulator 222 can be reduced. Therefore, the physical thickness of the insulator 222 can increase the distance between the conductor 205 and the oxide 230 without weakening the effect of the electric field applied from the conductor 205 to the oxide 230. Therefore, by changing the thickness of the insulator 222, the distance between the conductor 205 and the oxide 230 can be adjusted.

[0374] For example, preferably, by adjusting the shape of the protrusion of insulator 222, in the region where insulator 222 and oxide 230c contact each other, the bottom surface of conductor 260 is closer to the substrate side than the bottom surface of oxide 230b. In other words, transistor 200 has a structure in which the electric field of conductor 260 electrically surrounds oxide 230b. A structure in which the electric field of a conductor electrically surrounds oxide 230b is referred to as an s-channel structure. In an s-channel transistor 200, a channel can be formed throughout the entire (bulk) portion of oxide 230b. In an s-channel structure, the drain current of the transistor can be increased, thereby achieving a higher on-state current (the current flowing between the source and drain when the transistor is in the on state). Furthermore, the electric field of conductor 260 can deplete the entire channel formation region of oxide 230b. Consequently, the off-state current of the s-channel transistor can be further reduced. Reducing the channel width enhances the effects of the s-channel structure, such as increasing on-state current and reducing off-state current.

[0375] <Transistor Structure 6>

[0376] 17A to 17C Another example that can be applied to the transistor 200 is shown. Figure 17A The top surface of transistor 200 is shown. Figure 17APart of the membrane is not shown. Figure 17B It is along Figure 17A The cross-sectional view along the dot-dash line X1-X2 in FIG. Figure 17C It is along Figure 17A The cross-sectional view along the dotted line Y1-Y2 in FIG.

[0377] Note that in 17A to 17C In the transistor 200 shown, the 12A to 12C Components having the same functions as those of the transistor 200 are denoted by the same reference numerals.

[0378] exist 17A to 17C In the illustrated transistor 200, oxide 230c, insulator 250, and conductor 260 are formed within an opening formed in insulator 280. Furthermore, one end of conductors 240a and 240b coincides with the end of the opening formed in insulator 280. Furthermore, three ends of conductors 240a and 240b coincide with portions of the ends of oxides 230a and 230b. Thus, conductors 240a and 240b can be formed simultaneously with the openings in oxide 230 or insulator 280. This reduces the number of masks and steps, and improves yield and productivity.

[0379] Conductors 240a, 240b, and oxide 230b are in contact with insulator 280 having an excess oxygen region via oxide 230d. Oxide 230d, provided between insulator 280 and oxide 230b including the channel region, can suppress diffusion of impurities such as hydrogen, water, and halogen from insulator 280 into oxide 230b.

[0380] because 17A to 17C The transistor 200 shown has a structure in which the conductors 240a and 240b and the conductor 260 hardly overlap, thereby reducing parasitic capacitance between the conductors 260 and the conductors 240a and 240b. Therefore, the transistor 200 can operate at a high frequency.

[0381] <Transistor Structure 7>

[0382] 18A to 18C Another example that can be applied to the transistor 200 is shown. Figure 18A The top surface of transistor 200 is shown. Figure 18A Part of the membrane is not shown. Figure 18B It is along Figure 18A The cross-sectional view along the dot-dash line X1-X2 in FIG. Figure 18C It is along Figure 18A The cross-sectional view along the dotted line Y1-Y2 in FIG.

[0383] Note that in 18A to 18C In the transistor 200 shown, the 17A to 17C Components having the same functions as those of the transistor 200 are denoted by the same reference numerals.

[0384] 18A to 18C The transistor 200 shown does not include the oxide 230d. For example, when the conductors 240a and 240b are formed using a highly oxidizing-resistant conductor, the oxide 230d is not required. This can reduce the number of masks and steps, and can also improve yield and productivity.

[0385] The insulator 224 may be provided only in the region overlapping with the oxide 230a and the oxide 230b. In this case, the oxide 230a, the oxide 230b, and the insulator 224 can be processed using the insulator 222 as an etch stop layer. As a result, the yield and productivity can be improved.

[0386] because 18A to 18C The transistor 200 shown has a structure in which the conductors 240a and 240b and the conductor 260 hardly overlap, thereby reducing parasitic capacitance between the conductors 260 and the conductors 240a and 240b. Therefore, the transistor 200 can operate at a high frequency.

[0387] <Method for Manufacturing Transistor>

[0388] Below, refer to Figures 19A to 19E 、 20A to 20D 、 Figures 21A to 21C as well as Figures 22A to 22C right 12A to 12C An example of a method for manufacturing the transistor shown will be described.

[0389] First, prepare a substrate (not shown). Although there are no particular limitations on the substrate, it is preferred that the substrate have heat resistance sufficient to withstand the subsequent heat treatment. For example, glass substrates such as barium borosilicate glass substrates and aluminum borosilicate glass substrates, ceramic substrates, quartz substrates, and sapphire substrates can be used. Alternatively, single crystal or polycrystalline semiconductor substrates such as silicon or silicon carbide; compound semiconductor substrates such as silicon germanium, gallium arsenide, indium arsenide, and gallium indium arsenide; SOI (silicon on insulator) substrates; and GOI (germanium on insulator) substrates can be used. Furthermore, the aforementioned substrates on which semiconductor elements are provided can also be used as substrates.

[0390] Furthermore, a flexible substrate can be used as a substrate to manufacture a semiconductor device. To manufacture a flexible semiconductor device, a transistor can be directly manufactured on a flexible substrate, or a transistor can be manufactured on a manufacturing substrate, and then the transistor can be peeled off from the manufacturing substrate and transferred to the flexible substrate. To peel off the transistor from the manufacturing substrate and transfer it to the flexible substrate, a peeling layer is preferably provided between the manufacturing substrate and the transistor including the oxide semiconductor.

[0391] Next, the insulator 214 and the insulator 216 are formed. Then, a resist mask 290 is formed on the insulator 216 by photolithography or the like, and unnecessary portions of the insulators 214 and 216 are removed ( Figure 19A ). Then, the resist mask 290 is removed, whereby an opening can be formed.

[0392] Here, the film processing method is described. Various microfabrication techniques can be used to microfabricate the film. For example, a method can be used to shrink a resist mask formed by photolithography or the like. Alternatively, a dummy pattern can be formed by photolithography or the like, sidewalls are formed in the dummy pattern, and the dummy pattern is then removed. The remaining sidewalls are used as a resist mask to etch the film. To achieve a high aspect ratio, anisotropic dry etching is preferably used for etching the film. Alternatively, a hard mask formed from an inorganic film or a metal film can be used.

[0393] As the light used to form the resist mask, i-line (wavelength 365nm) light, g-line (wavelength 436nm) light, h-line (wavelength 405nm) light, or light mixed with i-line, g-line, and h-line can be used. In addition, ultraviolet light, KrF laser, ArF laser, etc. can be used. In addition, liquid immersion exposure technology can also be used for exposure. As the light for exposure, extreme ultraviolet light (EUV:extreme ultra-violet light) or X-rays can also be used. An electron beam can be used instead of the light for exposure. It is preferred to use extreme ultraviolet light (EUV), X-rays, or electron beams because they can perform extremely fine processing. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0394] In addition, it is also possible to form an organic resin film having the function of improving the tightness of the film and the resist film before forming the resist film used as a resist mask. The organic resin film can be formed in a manner of flattening the surface by utilizing a spin coating method or the like to cover the step below the film, and the thickness deviation of the resist mask on the organic resin film can be reduced. In particular, when carrying out fine processing, it is preferably used as a material for preventing the reflection of the light for exposure as the organic resin film. As an example of an organic resin film with this function, there is a bottom anti-reflection coating (BARC) film. The organic resin film can be removed while removing the resist mask or removed after removing the resist mask.

[0395] Next, the conductor 205A and the conductor 205B are formed on the insulator 214 and the insulator 216. The conductor 205A and the conductor 205B can be formed, for example, by sputtering, evaporation, or CVD (including thermal CVD, MOCVD, PECVD, etc.). In order to reduce plasma damage, it is preferable to use thermal CVD, MOCVD, or ALD ( Figure 19B ).

[0396] Then, unnecessary portions of the conductors 205A and 205B are removed. For example, a portion of the conductor 205A and a portion of the conductor 205B are removed by etching back or chemical mechanical polishing (CMP) until the insulator 216 is exposed, thereby forming the conductor 205 ( Figure 19C At this time, the insulator 216 may be used as a stop layer, and the thickness of the insulator 216 may be reduced.

[0397] CMP is a method for flattening the surface of a workpiece through a combination of chemical and mechanical action. More specifically, CMP involves attaching an abrasive cloth to a polishing table. A slurry (polishing agent) is supplied between the workpiece and the cloth while the table and workpiece are rotated or shaken. The chemical reaction between the slurry and the workpiece surface, combined with the mechanical polishing action between the cloth and the workpiece, polishes the surface.

[0398] The CMP treatment can be performed only once or multiple times. When the CMP treatment is performed multiple times, it is preferred to first perform an initial polishing at a high polishing rate, followed by a final polishing at a low polishing rate. In this manner, polishing steps with different polishing rates can also be combined.

[0399] Then, insulators 220, 222, and 224 are formed ( Figure 19DNote that the insulator 220 and the insulator 222 are not necessarily required. For example, when the insulator 224 includes an excess oxygen region, a conductor having a barrier property may be formed on the conductor 205. The conductor having a barrier property can prevent the conductor 205 from reacting with oxygen in the excess oxygen region to form an oxide.

[0400] Insulators 220 , 222 , and 224 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride. In particular, a high-k material such as hafnium oxide is preferably used as the insulator 222 .

[0401] Insulators 220, 222, and 224 can be formed by sputtering, chemical vapor deposition (CVD) (including thermal CVD, metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), etc.), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or pulsed laser deposition (PLD). In particular, it is preferred to form the insulator by CVD, more preferably by ALD, because these methods can improve coverage. In order to reduce plasma damage, thermal CVD, MOCVD, or ALD are preferably used. In addition, the above-mentioned insulator can also be formed using a silicon oxide film with good step coverage formed by reacting tetraethoxysilane (TEOS) or silane with oxygen or nitrous oxide.

[0402] Insulators 220, 222, and 224 are preferably formed continuously. By forming them continuously, impurities are prevented from adhering to the interface between insulators 220 and 222 and the interface between insulators 222 and 224, thereby realizing an insulator with high reliability.

[0403] Then, oxide 230A, which becomes oxide 230a, and oxide 230B, which becomes oxide 230b, are sequentially formed. These oxides are preferably formed continuously without being exposed to the air.

[0404] Then, a conductive film 240A, which will become the conductors 240a and 240b, is formed on the oxide 230A. As the conductive film 240A, it is preferable to use a material that has a barrier property against hydrogen or oxygen and has high oxidation resistance. Although the conductive film 240A has a single-layer structure in the drawings, it may also have a stacked structure of two or more layers. Then, a resist mask 292 ( Figure 19E ).

[0405] Unnecessary portions of the conductive film 240A are removed by etching using the resist mask 292 to form an island-shaped conductive layer 240B ( Figure 20A Then, unnecessary portions of the oxides 230A and 230B are removed by etching using the conductive layer 240B as a mask.

[0406] In this case, insulator 224 can also be processed into an island shape. For example, even if the total thickness of insulators 220, 222, and 224 is small, using insulator 222, which has barrier properties, as an etching stopper can prevent overetching of the wiring layer below the insulator. In addition, when the total thickness of insulators 220, 222, and 224 is small, voltage can be efficiently applied from conductor 205, thereby realizing a transistor with low power consumption.

[0407] Then, the resist mask is removed. Thus, a stacked structure of the island oxide 230a, the island oxide 230b, and the island conductive layer 240B can be formed ( Figure 20B ).

[0408] Next, a heat treatment is preferably performed ( Figure 20C The arrow in the figure indicates heat treatment). The heat treatment can be performed at a temperature of 250° C. to 400° C., preferably 320° C. to 380° C., in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. In addition, the heat treatment can be performed as follows: after the heat treatment is performed in an inert gas atmosphere, another heat treatment is performed in an atmosphere containing 10 ppm or more of an oxidizing gas to fill the separated oxygen. This heat treatment can remove hydrogen that is an impurity of the oxides 230 a and 230 b. In addition, oxygen is supplied to the oxides 230 a and 230 b from the insulator formed under the oxide 230 a, thereby reducing oxygen vacancies in the oxides.

[0409] Next, a resist mask 294 ( Figure 20D ). Then, unnecessary portions of the conductive layer 240B are removed by etching, and then the resist mask 294 is removed, thereby forming the conductive body 240a and the conductive body 240b ( Figure 21AAt this time, a portion of the insulator 222 or the insulator 224 is thinned by etching, thereby obtaining an s-channel structure.

[0410] Here, a heat treatment may also be performed. Figure 20C The heat treatment is performed under the same conditions as described above. This heat treatment can remove hydrogen, which is an impurity in the oxides 230a and 230b. In addition, oxygen is supplied from the insulator formed below the oxide 230a to the oxides 230a and 230b, thereby reducing oxygen vacancies in the oxides. When the heat treatment is performed using an oxidizing gas, the oxidizing gas directly contacts the region where the channel is formed, thereby effectively reducing oxygen vacancies in the region where the channel is formed.

[0411] Next, oxide 230c is formed. Here, heat treatment may also be performed ( Figure 21B The arrow in the figure indicates a heating process. The heating process may be performed in conjunction with Figure 21C The heat treatment is performed under the same conditions as described above. This heat treatment can remove hydrogen, which is an impurity in the oxides 230a and 230b. In addition, oxygen is supplied from the insulator formed below the oxide 230a to the oxides 230a and 230b, thereby reducing oxygen vacancies in the oxides. When the heat treatment is performed using an oxidizing gas, the oxidizing gas directly contacts the region where the channel is formed, thereby effectively reducing oxygen vacancies in the region where the channel is formed.

[0412] Insulator 250 and conductive film 260A, which will become conductor 260, are sequentially formed. A material having a barrier property against hydrogen and oxygen and high oxidation resistance is preferably used for conductive film 260A. Although conductive film 260A is shown as a single-layer structure in the drawings, it may also have a stacked structure of two or more layers.

[0413] For example, the two-layer structure can be formed from the same material. The first conductive film is formed, for example, using thermal CVD, MOCVD, or ALD. ALD is particularly preferred. Using ALD or the like can reduce damage to the insulator 250 during film formation. Furthermore, using ALD or the like can form a conductive film 260A that provides high coverage. Consequently, a highly reliable transistor 200 can be provided.

[0414] Next, a second conductive film is formed by sputtering. Since the first conductive film is formed on the insulator 250, the effects of damage to the insulator 250 caused by forming the second conductive film can be minimized. Sputtering has a faster film formation rate than ALD, resulting in a high yield and improved productivity. Note that the conductive film 260A is preferably formed using a film-forming gas that does not contain chlorine.

[0415] Next, a resist mask 296 ( Figure 21C ). Then, unnecessary portions of the conductive film 260A are removed by etching to form the conductor 260. Then, the resist mask 296 ( Figure 22A ).

[0416] Next, insulator 280 is formed on conductor 260. Insulator 280 is an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film. As an insulator containing excess oxygen, a silicon oxide film or a silicon oxynitride film containing a large amount of oxygen can be formed by CVD or sputtering under appropriately set conditions. After the silicon oxide film or silicon oxynitride film is formed, oxygen can also be added by ion implantation, ion doping, or plasma treatment.

[0417] In particular, it is preferable to perform oxygen plasma treatment ( Figure 22B The arrow in the figure indicates plasma treatment. In a typical oxygen plasma treatment, the surface of the oxide semiconductor is treated using radicals generated by glow discharge plasma of an oxygen gas. However, as a gas for generating plasma, a mixed gas of oxygen gas and a rare gas may be used in addition to oxygen. For example, the oxygen plasma treatment may be performed at a temperature of 250°C to 400°C, preferably 300°C to 400°C, in an atmosphere containing an oxidizing gas or under reduced pressure.

[0418] By oxygen plasma treatment, the insulator 280 and the oxide 230 are dehydrated or dehydrogenated, and excess oxygen is introduced into the insulator 280, resulting in the formation of an excess oxygen region. In addition, oxygen vacancies are generated in the dehydrated or dehydrogenated oxide 230, and the resistance of the oxide 230 is reduced. On the other hand, the excess oxygen in the insulator 280 fills the oxygen vacancies in the oxide 230. Therefore, by oxygen plasma treatment, it is possible to remove impurity hydrogen and water from the insulator 280 while forming an excess oxygen region in the insulator 280. In addition, it is possible to remove impurity hydrogen or water from the oxide 230 while filling the oxygen vacancies in the oxide 230. Therefore, the electrical characteristics of the transistor 200 can be improved, and the unevenness of the electrical characteristics can be reduced.

[0419] Then, an insulator 282 is formed on the insulator 280 ( Figure 22C ) It is preferable to use a sputtering device to form the insulator 282. By using the sputtering method, an excess oxygen region can be more easily formed in the insulator 280 below the insulator 282.

[0420] During film formation using sputtering, ions and sputtered particles exist between the target and the substrate. For example, a target connected to a power source is applied with a potential E0. The substrate is applied with a potential E1, which is equivalent to ground potential. Note that the substrate can also be electrically floating. Furthermore, a region with a potential E2 exists between the target and the substrate. The relationship between these potentials is E2 > E1 > E0.

[0421] The ions in the plasma are accelerated by the potential difference (E2-E0) and collide with the target material, whereby the sputtered particles are ejected from the target material. The sputtered particles adhere to the film-forming surface and deposit, resulting in the formation of a film. Sometimes a portion of the ions is recoiled by the target material and, as recoil ions, is absorbed into the insulator 280 located below the formed film through the formed film. The ions in the plasma are accelerated by the potential difference (E2-E1) and collide with the film-forming surface. At this time, a portion of the ions reaches the inside of the insulator 280. The ions are absorbed into the insulator 280, thereby forming an ion-absorbed region in the insulator 280. In other words, when the ions contain oxygen, an excess oxygen region is formed in the insulator 280.

[0422] By introducing excess oxygen into insulator 280, an excess oxygen region can be formed. The excess oxygen in insulator 280 is supplied to oxide 230, thereby filling oxygen vacancies in oxide 230. Here, when conductors 260 and conductors 240a and 240b having high oxidation resistance are used as conductors in contact with insulator 280, the excess oxygen in insulator 280 is not absorbed by conductors 260, 240a, and 240b and can be efficiently supplied to oxide 230. Therefore, the electrical characteristics of transistor 200 can be improved and variations in the electrical characteristics can be reduced.

[0423] Through the above steps, the transistor 200 according to one embodiment of the present invention can be manufactured.

[0424] The structures, methods, and the like described in this embodiment mode can be appropriately combined with the structures, methods, and the like described in other embodiment modes and examples.

[0425] Implementation 4

[0426] In this embodiment, referring to Figures 23 to 28 、 Figure 29A and Figure 29B 、 Figure 30A and Figure 30B 、 Figure 31A and Figure 31B 、 Figure 32A and Figure 32B as well as Figure 33 One embodiment of a semiconductor device will be described.

[0427] [Structure example]

[0428] Figures 23 to 28 、 Figure 29A and Figure 29B as well as Figure 30A and Figure 30B An example of a semiconductor device (storage device) according to one embodiment of the present invention is shown. Figure 30A yes Figures 23 to 26 Circuit diagram. Figure 29A and Figure 29B Show Figures 23 to 26 The end portion of the semiconductor device formation region is shown.

[0429] <Circuit Structure of Semiconductor Device>

[0430] Figure 30A as well as Figures 23 to 28 The semiconductor devices shown include a transistor 300 , a transistor 200 , and a capacitor 100 .

[0431] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing an oxide semiconductor. Because transistor 200 has a low off-state current, using this transistor 200 in a semiconductor device (memory device) can retain stored data for a long period of time. In other words, this semiconductor device (memory device) does not require a refresh operation or requires an extremely low frequency of refresh operation, thereby significantly reducing power consumption.

[0432] exist Figure 30A , wiring 3001 is electrically connected to the source of transistor 300. Wiring 3002 is electrically connected to the drain of transistor 300. Wiring 3003 is electrically connected to one of the source and drain of transistor 200. Wiring 3004 is electrically connected to the gate of transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100. Wiring 3005 is electrically connected to the other electrode of capacitor 100.

[0433] Figure 30A The semiconductor device has a feature of being able to hold the potential of the gate of the transistor 300 , thereby enabling data to be written, held, and read as described below.

[0434] The writing and holding of data will be described. First, the potential of the wiring 3004 is set to a potential that puts the transistor 200 in the on state, and the transistor 200 is put in the on state. Thus, the potential of the wiring 3003 is applied to the node FG electrically connected to the gate of the transistor 300 and one electrode of the capacitor 100. In other words, a predetermined charge is applied to the gate of the transistor 300 (writing). Here, either of two charges (hereinafter referred to as low-level charge and high-level charge) providing different potential levels is applied. Then, the potential of the wiring 3004 is set to a potential that puts the transistor 200 in the non-conducting state, and the transistor 200 is put in the non-conducting state. Thus, the charge is maintained at the node FG (maintained).

[0435] When the off-state current of the transistor 200 is small, the charge at the node FG is retained for a long time.

[0436] Next, the data reading will be described. When a predetermined potential (constant potential) is applied to the wiring 3001, an appropriate potential (reading potential) is applied to the wiring 3005. This causes the potential of the wiring 3002 to change according to the amount of charge held in the node FG. This is because, when an n-channel transistor is used as the transistor 300, the apparent threshold voltage V when a high-level charge is applied to the gate of the transistor 300 is V. th_H is lower than the apparent threshold voltage V when a low level charge is applied to the gate of the transistor 300 th_L Here, the apparent threshold voltage refers to the potential of the wiring 3005 required to turn the transistor 300 into the "on state". th_H With V th_L The potential V0 between the two can distinguish the charge applied to the node FG. For example, when writing, the node FG is supplied with a high-level charge, and the potential of the wiring 3005 is V0 (> V th_H ), the transistor 300 is in the “on state”. On the other hand, when the node FG is supplied with low-level charges, even if the potential of the wiring 3005 is V0 (<V th_L ), the transistor 300 also remains in the "non-conductive state." Therefore, by distinguishing the potential of the wiring 3002, the data held in the node FG can be read.

[0437] By having Figure 30A Semiconductor devices having the structure shown are arranged in a matrix to form a memory device (memory cell array).

[0438] Note that when the memory cells are arranged in an array, the data of the desired memory cell must be read during the read operation. For example, when a p-channel transistor is used as the transistor 300, the memory cell has a NOR structure. Therefore, a potential that puts the transistor 300 in a "non-conductive state" (i.e., lower than V) can be applied to the wiring 3005 in the memory cell where the data is not to be read, regardless of the potential applied to the node FG. th_H Alternatively, when an n-channel transistor is used as the transistor 300, the memory cell has a NAND type structure. Therefore, a potential that turns the transistor 300 "on" regardless of the charge applied to the node FG (i.e., a potential higher than V th_L potential) to read only the data of the desired memory cell.

[0439] <Circuit Structure 2 of Semiconductor Device>

[0440] Figure 30B semiconductor devices and Figure 30A The difference of the semiconductor device is that the transistor 300 is not provided. In this case, it is also possible to Figure 30A The same operation is performed on the semiconductor device to write and retain data.

[0441] Will explain Figure 30B Data is read from a semiconductor device. When transistor 200 is turned on, wiring 3003 and capacitor 100, which are in a floating state, are brought into conduction, and charge is redistributed between wiring 3003 and capacitor 100. As a result, the potential of wiring 3003 changes. The amount of change in the potential of wiring 3003 varies depending on the potential of one electrode of capacitor 100 (or the charge accumulated in capacitor 100).

[0442] For example, when V is the potential of one electrode of the capacitor 100, C is the capacitance of the capacitor 100, and C B is the capacitance component of the wiring 3003, V B0 When the potential of the wiring 3003 before the redistribution of the charge is (C B ×V B0 +C×V) / (C B +C). Therefore, it can be seen that, assuming that the potential of one electrode of the capacitor 100 is in one of the two states V1 and V0 (V1>V0), the potential of the wiring 3003 when the potential V1 is maintained (=(C B ×V B0 +C×V1) / (C B+C)) is higher than the potential of the wiring 3003 when the potential V0 is maintained (=(C B ×V B0 +C×V0) / (C B +C)).

[0443] Then, data can be read by comparing the potential of the wiring 3003 with a predetermined potential.

[0444] When this structure is employed, a transistor using silicon can be used for a driver circuit for driving a memory cell, and a transistor using an oxide semiconductor can be stacked as the transistor 200 on the driver circuit.

[0445] When a transistor with a low off-state current using an oxide semiconductor is included, the semiconductor device can retain stored data for a long period of time. In other words, a refresh operation is not required or the frequency of the refresh operation can be made extremely low, thereby significantly reducing power consumption. In addition, even without power supply (note that the potential is preferably fixed), stored data can be retained for a long period of time.

[0446] Furthermore, this semiconductor device does not require high voltages when writing data, making it less susceptible to device degradation. For example, unlike conventional non-volatile memories, there is no need to inject or extract electrons into or from the floating gate, thus preventing problems such as insulator degradation. In other words, unlike conventional non-volatile memories, the semiconductor device according to one embodiment of the present invention has no limit on the number of rewrites, significantly improving its reliability. Furthermore, data is written based on the transistor's state (conductive or non-conductive), enabling high-speed operation.

[0447] <Structure of Semiconductor Device 1>

[0448] like Figure 23 As shown, the semiconductor device according to one embodiment of the present invention includes a transistor 300 , a transistor 200 , and a capacitor 100 . The transistor 200 is provided above the transistor 300 , and the capacitor 100 is provided above the transistor 300 and the transistor 200 .

[0449] The transistor 300 is provided on a substrate 311 and includes: a conductor 316, an insulator 314, a semiconductor region 312 which is a portion of the substrate 311; and low resistance regions 318a and 318b which serve as a source region and a drain region.

[0450] The transistor 300 may be a p-channel transistor or an n-channel transistor.

[0451] The channel-forming region of the semiconductor region 312, the region adjacent thereto, and the low-resistance regions 318a and 318b used as the source and drain regions are preferably comprised of a semiconductor such as a silicon-based semiconductor, more preferably single-crystalline silicon. Alternatively, materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide) may be included. Silicon may be included to control the effective mass by applying stress to the crystal lattice and changing the interplanar spacing. Furthermore, the transistor 300 may be a high-electron-mobility transistor (HEMT) using GaAs, GaAlAs, or the like.

[0452] The low-resistance regions 318 a and 318 b contain, in addition to the semiconductor material used for the semiconductor region 312 , an element imparting n-type conductivity such as arsenic and phosphorus, or an element imparting p-type conductivity such as boron.

[0453] The conductor 316 used as the gate electrode can be formed using a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0454] Furthermore, the work function of the conductor is determined by the material of the conductor, thereby adjusting the threshold voltage. Specifically, titanium nitride or tantalum nitride is preferably used as the conductor. Furthermore, to ensure the conductivity and embedding properties of the conductor, a laminate of a metal material such as tungsten and aluminum is preferably used as the conductor. In particular, tungsten is preferred due to its heat resistance.

[0455] Notice, Figure 23 The transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method. Figure 30B In the case of the circuit structure shown, the transistor 300 can also be omitted.

[0456] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 300 .

[0457] The insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0458] The insulator 322 may also be used as a planarization film for planarizing steps caused by the transistor 300 and the like provided below the insulator 322. For example, to improve the flatness of the top surface of the insulator 322, the top surface may be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0459] The insulator 324 is preferably formed using a film having barrier properties that prevents impurities such as hydrogen from diffusing from the substrate 311 or the transistor 300 into the region where the transistor 200 is formed. Here, barrier properties refer to high oxidation resistance and the ability to inhibit the diffusion of impurities such as oxygen, hydrogen, and water. For example, in an atmosphere at 350°C or 400°C, the diffusion distance of oxygen or hydrogen per hour in the film having barrier properties can be 50 nm or less. Preferably, at a temperature of 350°C or 400°C, the diffusion distance of oxygen or hydrogen per hour in the film having barrier properties is preferably 30 nm or less, and more preferably 20 nm or less.

[0460] An example of a film with hydrogen barrier properties is silicon nitride formed by CVD. Hydrogen may diffuse into a semiconductor element including an oxide semiconductor, such as transistor 200, causing degradation in the characteristics of the semiconductor element. Therefore, a film that inhibits hydrogen diffusion is preferably provided between transistor 200 and transistor 300. Specifically, the film that inhibits hydrogen diffusion is a film that prevents hydrogen from escaping easily.

[0461] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, in the range of 50°C to 500°C in TDS analysis, the amount of hydrogen released per unit area of ​​the insulator 324 in terms of hydrogen atoms is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 the following.

[0462] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 324 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less of the relative dielectric constant of the insulator 324, more preferably 0.6 times or less of the relative dielectric constant of the insulator 324. When a material with a low dielectric constant is used for the interlayer film, parasitic capacitance between wirings can be reduced.

[0463] Conductors 328 and 330, etc., electrically connected to capacitor 100 or transistor 200, are embedded in insulators 320, 322, 324, and 326. Conductors 328 and 330 also function as plugs or wiring. Note that, as described later, multiple conductor structures functioning as plugs or wiring may sometimes be denoted by the same reference numeral. Furthermore, in this specification and other text, wiring and a plug electrically connected to the wiring may be considered a single component. In other words, a portion of a conductor may function as wiring, while a portion of the conductor may function as a plug.

[0464] As the material for each plug and wiring (for example, conductor 328 and conductor 330), a single layer structure or a laminated structure of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. Preferably, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is used, with tungsten being particularly preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0465] A wiring layer may be provided on the insulator 326 and the conductor 330. Figure 23 Insulator 350, insulator 352, and insulator 354 are stacked in this order. Furthermore, conductor 356 is formed between insulator 350, insulator 352, and insulator 354. Conductor 356 is used as a plug or wiring. Conductor 356 can be formed using the same material as conductors 328 and 330.

[0466] As with insulator 324, insulator 350 preferably uses, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 356 preferably includes a conductor having a hydrogen barrier property. In particular, a conductor having a hydrogen barrier property is formed within the opening in insulator 350 having a hydrogen barrier property. This structure allows transistor 300 to be separated from transistor 200 by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 200.

[0467] Note that tantalum nitride, for example, can be used as a conductor having hydrogen barrier properties. By stacking tantalum nitride and highly conductive tungsten, hydrogen diffusion from transistor 300 can be suppressed while maintaining wiring conductivity. In this case, the tantalum nitride layer having hydrogen barrier properties is preferably in contact with insulator 350 having hydrogen barrier properties.

[0468] Insulator 358, insulator 210, insulator 212, insulator 213, insulator 214, and insulator 216 are sequentially stacked on insulator 354. Any of insulators 358, 210, 212, 213, 214, and 216 is preferably made of a material having a barrier property against oxygen or hydrogen.

[0469] For example, the insulators 358 and 212 are preferably formed using a film having a barrier property that prevents impurities such as hydrogen from diffusing from the substrate 311 or the region where the transistor 300 is formed into the region where the transistor 200 is formed. Therefore, the insulators 358 and 212 can be formed using the same material as that used for the insulator 324.

[0470] An example of a film with hydrogen barrier properties is silicon nitride formed by CVD. Hydrogen may diffuse into a semiconductor element including an oxide semiconductor, such as transistor 200, causing degradation in the characteristics of the semiconductor element. Therefore, a film that inhibits hydrogen diffusion is preferably provided between transistor 200 and transistor 300. Specifically, the film that inhibits hydrogen diffusion is a film that prevents hydrogen from escaping easily.

[0471] For example, as a film having a barrier property against hydrogen, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for each of the insulators 213 and 214 .

[0472] In particular, aluminum oxide has a high barrier effect against the permeation of impurities such as oxygen, hydrogen, and moisture that can cause changes in the electrical characteristics of transistors. Therefore, the use of aluminum oxide can prevent impurities such as hydrogen and moisture from entering transistor 200 during and after the transistor manufacturing process. Furthermore, the release of oxygen from the oxide that constitutes transistor 200 can be suppressed. Therefore, aluminum oxide is suitable for use as a protective film for transistor 200.

[0473] For example, insulators 210 and 216 can be formed using the same material as that used for insulator 320. When a material with a low dielectric constant is used for the interlayer film, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as insulator 216.

[0474] The conductor 218 and the conductor (conductor 205) included in the transistor 200 are embedded in the insulators 358, 210, 212, 213, 214, and 216. The conductor 218 is used as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be formed using the same material as that used for the conductors 328 and 330.

[0475] In particular, the conductor 218 in the region in contact with the insulators 358, 212, 213, and 214 is preferably a conductor having barrier properties to oxygen, hydrogen, and water. This structure allows the transistor 300 to be completely separated from the transistor 200 by the layer having barrier properties to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 300 into the transistor 200.

[0476] For example, when the insulator 224 includes an excess oxygen region, a conductor such as the conductor 218 that contacts the insulator 224 is preferably a conductor with high oxidation resistance. As shown in the figure, a conductor 219 having a barrier property may be provided over the conductor 218 and the conductor (conductor 205) included in the transistor 200. This structure can prevent the conductor 218 and the conductor (conductor 205) included in the transistor 200 from reacting with oxygen in the excess oxygen region to form oxides.

[0477] The transistor 200 is provided over the insulator 224. Note that as the structure of the transistor 200, the transistor structure described in the above embodiment mode can be used. Figure 23 The transistor 200 shown is just an example, and the structure is not limited to the above, and an appropriate transistor can be used according to the circuit structure or driving method.

[0478] An insulator 280 is provided above the transistor 200. An excess oxygen region is preferably formed in the insulator 280. In particular, when an oxide semiconductor is used for the transistor 200, if an insulator having an excess oxygen region is provided in an interlayer film or the like near the transistor 200, oxygen vacancies in the transistor 200 can be reduced, thereby improving reliability.

[0479] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which a portion of oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS analysis is 1.0×10 18 atoms / cm 3 above, preferably 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower.

[0480] For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon nitride oxide" refers to a material containing more nitrogen than oxygen.

[0481] The insulator 280 covering the transistor 200 can also be used as a planarization film for covering the uneven shape thereunder. The conductor 244 and the like are embedded in the insulator 280 .

[0482] The conductor 244 is used as a plug or wiring for electrically connecting the capacitor 100, the transistor 200, or the transistor 300. The conductor 244 can be formed using the same material as the conductors 328 and 330.

[0483] For example, when the conductor 244 has a laminated structure, the conductor 244 preferably includes a conductor that is not easily oxidized (highly resistant to oxidation). In particular, it is preferable to provide a conductor with high oxidation resistance in the region in contact with the insulator 280 having an excess oxygen region. By adopting this structure, it is possible to suppress the absorption of excess oxygen from the insulator 280 into the conductor 244. In addition, the conductor 244 preferably includes a conductor that has a barrier property against hydrogen. In particular, by providing a conductor that has a barrier property against impurities such as hydrogen in the region in contact with the insulator 280 having an excess oxygen region, it is possible to suppress the diffusion of impurities in the conductor 244, the diffusion of a portion of the conductor 244, and the diffusion of impurities from the outside through the conductor 244.

[0484] Conductor 246, conductor 124, conductor 112a, and conductor 112b may also be provided on conductor 244. Conductor 246 and conductor 124 serve as plugs or wiring for electrically connecting capacitor 100, transistor 200, or transistor 300. Conductor 112a and conductor 112b serve as electrodes of capacitor 100. Conductor 246 and conductor 112a may be formed simultaneously. Conductor 124 and conductor 112b may also be formed simultaneously.

[0485] As the conductor 246, the conductor 124, the conductor 112a, and the conductor 112b, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements (for example, a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

[0486] In particular, a metal nitride film such as a tantalum nitride film is preferably used as the conductor 246 and the conductor 112a because such a metal nitride film has barrier properties against hydrogen and oxygen and is not easily oxidized (has high oxidation resistance). On the other hand, the conductor 124 and the conductor 112b are preferably formed by laminating a highly conductive material such as tungsten. By using this combination of materials, hydrogen diffusion into the insulator 280 and the transistor 200 can be suppressed while maintaining the conductivity of the wiring. Figure 23Although a two-layer structure of conductor 246 and conductor 124 is shown, the structure is not limited thereto and a single-layer structure or a stacked structure of three or more layers may also be used. For example, a conductor having high adhesion to the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0487] Furthermore, a barrier layer 281 may be provided on the conductor 124. The barrier layer 281 can prevent the conductor 124 from being oxidized in subsequent steps. Furthermore, the diffusion of impurities contained in the conductor 124 or portions of the conductor 124 can be suppressed. Impurities can be prevented from diffusing through the conductor 124, the conductor 246, and the conductor 244 into the insulator 280.

[0488] Alternatively, barrier layer 281 may be formed of an insulating material. In this case, barrier layer 281 may also function as a portion of the dielectric of capacitor 100. Alternatively, barrier layer 281 may be formed of a conductive material. In this case, barrier layer 281 may also function as a portion of a wiring or electrode.

[0489] A metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as tantalum nitride, is preferably used as the barrier layer 281. Aluminum oxide is particularly effective in preventing the permeation of impurities such as oxygen, hydrogen, and moisture, which can cause changes in the electrical characteristics of the transistor. Therefore, the use of aluminum oxide can prevent the conductor 124, hydrogen, moisture, and other impurities from entering the transistor 200 during and after the semiconductor device manufacturing process.

[0490] An insulator 282 is provided over the barrier layer 281 and the insulator 280. A material having barrier properties against oxygen or hydrogen is preferably used for the insulator 282. Therefore, the insulator 282 can be formed using the same material as that used for the insulator 214. For example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 282.

[0491] In particular, aluminum oxide has a high barrier effect against the permeation of impurities such as oxygen, hydrogen, and moisture that can cause changes in the electrical characteristics of transistors. Therefore, the use of aluminum oxide can prevent impurities such as hydrogen and moisture from entering transistor 200 during and after the transistor manufacturing process. Furthermore, the release of oxygen from the oxide that constitutes transistor 200 can be suppressed. Therefore, aluminum oxide is suitable for use as a protective film for transistor 200.

[0492] Therefore, transistor 200 and insulator 280 including an excess oxygen region may be located between the stacked structure of insulators 212, 213, and 214 and insulator 282. Insulators 212, 213, 214, and 282 all have a barrier property that suppresses diffusion of oxygen or impurities such as hydrogen and water.

[0493] Oxygen released from insulator 280 and transistor 200 can be suppressed from diffusing into layers forming capacitor 100 or transistor 300. Alternatively, impurities such as hydrogen and water can be suppressed from diffusing into transistor 200 from layers above insulator 282 and layers below insulator 214.

[0494] That is, oxygen can be efficiently supplied from the excess oxygen region of insulator 280 to the oxide in transistor 200 where the channel is formed, thereby reducing oxygen vacancies. Furthermore, the formation of oxygen vacancies in the oxide in transistor 200 where the channel is formed due to impurities can be prevented. Therefore, the oxide in transistor 200 where the channel is formed can be an oxide semiconductor with a low defect state density and stable characteristics. That is, variations in the electrical characteristics of transistor 200 can be suppressed, and reliability can be improved.

[0495] Here, we will explain the dicing lines (also called dividing lines, splitting lines, or cutting lines) used when dividing a large-area substrate into individual semiconductor elements to form multiple chip-shaped semiconductor devices. As an example of a dividing method, for example, trenches (dicing lines) are formed in the substrate to separate the semiconductor elements, and then the semiconductor elements are cut along the dicing lines to obtain multiple separated semiconductor devices. Figure 29A and Figure 29B These are cross-sectional views near the cutting line.

[0496] For example, Figure 29A As shown, the cutting line formed at the edge of the memory cell including the transistor 200 (in Figure 29A Near the overlapping region (indicated by a dashed line in the figure), openings are provided in the insulators 212, 213, 214, 216, 224, and 280. In addition, an insulator 282 is provided so as to cover the side surfaces of the insulators 212, 213, 214, 216, 224, and 280.

[0497] Here, when the barrier layer 281 has insulating properties, the insulator 282 is preferably provided in the opening so that the barrier layer 281 is located between the insulator 282 and the inner surface of the opening. By using the barrier layer 281, diffusion of impurities can be further suppressed.

[0498] Therefore, in this opening, insulators 212, 213, and 214 are in contact with barrier layer 281. In this case, by forming at least one of insulators 212, 213, and 214 using the same material and method as insulator 282, the closeness between them can be improved. Furthermore, barrier layer 281 and insulator 282 are preferably formed using the same material. For example, aluminum oxide can be used. When barrier layer 281 is formed using a method capable of forming a dense film, such as ALD, and then insulator 282 is formed using a method with a high film formation rate, such as sputtering, high productivity and high barrier properties can be achieved.

[0499] In this structure, the insulator 280 and the transistor 200 can be surrounded by the insulators 212, 213, 214, and 282. Since the insulators 212, 213, 214, and 282 all have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region in which the semiconductor element of this embodiment is provided, impurities such as hydrogen and water can be prevented from entering from the side surfaces of the divided substrates and diffusing into the transistor 200.

[0500] Furthermore, in this structure, excess oxygen in insulator 280 can be prevented from diffusing outside insulators 282 and 214. Consequently, excess oxygen in insulator 280 is efficiently supplied to the oxide forming the channel in transistor 200. This oxygen can reduce oxygen vacancies in the oxide forming the channel in transistor 200. Consequently, the oxide forming the channel in transistor 200 can be an oxide semiconductor having a low defect state density and stable characteristics. In other words, variations in the electrical characteristics of transistor 200 can be suppressed, and reliability can be improved.

[0501] As other examples, Figure 29B As shown, it is also possible to cut the line (in Figure 29B In the figure, openings are provided on both sides of the insulating member 212, 213, 214, 216, 224 and 280. Although the number of openings is two in the figure, more openings may be provided as needed.

[0502] Since the insulators 212, 213, and 214 are in contact with the barrier layer 281 at least at two locations in the openings provided on both sides of the cutting line, higher adhesion can be achieved. In this case, when at least one of the insulators 212, 213, and 214 is formed using the same material and the same method as the insulator 282, adhesion between them can also be improved.

[0503] Since the plurality of openings are provided, the insulator 282 can be in contact with the insulators 212, 213, and 214 in a plurality of regions. This prevents impurities mixed in from the cutting lines from reaching the transistor 200.

[0504] This structure allows for tight sealing between transistor 200 and insulator 280. Consequently, the oxide forming the channel in transistor 200 can be an oxide semiconductor with low defect density and stable characteristics. This reduces variations in the electrical characteristics of transistor 200 and improves reliability.

[0505] The capacitor 100 is provided above the transistor 200 . The capacitor 100 includes a conductor 112 (a conductor 112 a and a conductor 112 b ), a barrier layer 281 , an insulator 282 , an insulator 130 , and a conductor 116 .

[0506] The conductor 112 is used as an electrode of the capacitor 100. For example, Figure 23 In the structure of FIG, a portion of the conductor 244 used as a plug or wiring for connecting the transistor 200 and the transistor 300 is used as the conductor 112. When the barrier layer 281 is conductive, the barrier layer 281 is used as a portion of the electrode of the capacitor 100. When the barrier layer 281 is insulating, the barrier layer 281 is used as a portion of the dielectric of the capacitor 100.

[0507] By adopting this structure, the number of steps can be reduced compared to the case where electrodes and wirings are formed separately, thereby improving productivity.

[0508] The region of insulator 282 between conductors 112 and 116 serves as a dielectric. For example, by using a high-k dielectric material such as alumina as insulator 282, sufficient capacitance of capacitor 100 can be ensured.

[0509] An insulator 130 may also be provided as part of the dielectric. The insulator 130 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or the like, and may have a single-layer structure or a stacked-layer structure.

[0510] For example, when a high-k dielectric material such as aluminum oxide is used as insulator 282, a material with high dielectric strength such as silicon oxynitride is preferably used as insulator 130. In capacitor 100 having this structure, insulator 130 increases dielectric strength, thereby suppressing electrostatic damage to capacitor 100.

[0511] Conductor 116 is provided so as to cover the side surfaces and top surface of conductor 112 via barrier layer 281, insulator 282, and insulator 130. In this structure, where conductor 116 surrounds the side surfaces of conductor 112 via the insulator, capacitance is also formed on the side surfaces of conductor 112, thereby increasing the capacitance per projected area of ​​the capacitor. Consequently, semiconductor devices can be reduced in size, highly integrated, and miniaturized.

[0512] Furthermore, the conductor 116 can be formed using a conductive material such as a metal, alloy, or metal oxide. A high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, is preferably used, with tungsten being particularly preferred. When the conductor 116 is formed simultaneously with another component such as a conductor, a low-resistance metal such as Cu (copper) or Al (aluminum) may also be used.

[0513] An insulator 150 is provided on the conductor 116 and the insulator 130. The insulator 150 can be formed using the same material as that used for the insulator 320. The insulator 150 can be used as a planarization film that covers the concavo-convex shape thereunder.

[0514] The above describes an example structure. By using this structure, variations in electrical characteristics can be suppressed in a semiconductor device having a transistor including an oxide semiconductor, thereby improving reliability. A transistor including an oxide semiconductor having a high on-state current can be provided. A transistor including an oxide semiconductor having a low off-state current can be provided. A semiconductor device with low power consumption can be provided.

[0515] <Deformation Example 1>

[0516] In a modified example of this embodiment, it is also possible to Figure 24 Conductor 244 and barrier layer 281 are formed as shown. Specifically, conductor 244, which serves as a plug or wiring, and conductor 112, which serves as a portion of the capacitor 100 electrode, can be embedded in insulator 280, and barrier layer 281 can be formed on conductor 244 using a conductor or insulator with barrier properties. In this case, barrier layer 281 is preferably formed using a conductor that not only has barrier properties but also has high oxidation resistance. In this structure, since a portion of conductor 244 serves as the capacitor electrode (conductor 112), there is no need to provide a separate conductor.

[0517] Therefore, if Figure 24 As shown, capacitor 100 includes conductor 112 , insulator 282 , insulator 130 , and conductor 116 in a region of conductor 244 .

[0518] Conductor 112, which serves as an electrode of capacitor 100, can be formed simultaneously with conductor 244. This structure improves productivity and reduces the number of steps because masks for forming capacitor electrodes are not required.

[0519] Insulator 220, insulator 222, and insulator 224 are sequentially stacked on insulator 216. A material having a barrier property against oxygen or hydrogen is preferably used for any of insulators 220, 222, and 224. Insulators 220, 222, and 224 may also serve as a portion of transistor 200 (gate insulator).

[0520] The insulator 224 preferably includes an oxide having an oxygen content exceeding that in the stoichiometric composition. That is, a region containing more oxygen than in the stoichiometric composition (hereinafter also referred to as an excess oxygen region) is preferably formed in the insulator 224. In particular, when an oxide semiconductor is used for the transistor 200, providing an insulator having an excess oxygen region in a base film or the like near the transistor 200 reduces oxygen vacancies in the transistor 200, thereby improving reliability.

[0521] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which a portion of oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS analysis is 1.0×10 18 atoms / cm 3 above, preferably 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower.

[0522] For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon nitride oxide" refers to a material containing more nitrogen than oxygen.

[0523] Furthermore, when the insulator 224 includes an excess oxygen region, the insulator 222 or the insulator 220 preferably has a barrier property against oxygen, hydrogen, and water. When the insulator 222 or the insulator 220 has a barrier property against oxygen, oxygen in the excess oxygen region is efficiently supplied to the oxide 230 included in the transistor 200 without diffusing toward the transistor 300. This prevents the conductor 218 and the conductor included in the transistor 200 (the conductor 205) from reacting with oxygen in the excess oxygen region to form an oxide.

[0524] The above is a description of a modified example. By using this structure, variations in electrical characteristics can be suppressed in a semiconductor device having a transistor including an oxide semiconductor, thereby improving reliability. A transistor including an oxide semiconductor having a large on-state current can be provided. A transistor including an oxide semiconductor having a small off-state current can be provided. A semiconductor device with low power consumption can be provided.

[0525] <Deformation Example 2>

[0526] In a modified example of this embodiment, it is also possible to Figure 25 Conductor 219, conductor 244, and conductor 246 with barrier properties are formed as shown. That is, conductor 244, which serves as a plug or wiring, can be embedded in insulator 280, and conductor 246 with barrier properties can be formed on conductor 244. In this case, conductor 246 is preferably formed using a conductor that not only has high barrier properties but also high oxidation resistance. By adopting this structure, conductor 246 and conductor 112, which serves as a capacitor electrode, can be formed simultaneously. Furthermore, since conductor 246 also serves as a barrier layer in this structure, there is no need to provide a separate barrier layer.

[0527] Therefore, if Figure 25 As shown, capacitor 100 includes conductor 112, insulator 282, insulator 130, and conductor 116. Conductor 112, which serves as an electrode of capacitor 100, may be formed simultaneously with conductor 246.

[0528] The above is a description of a modified example. By using this structure, variations in electrical characteristics can be suppressed in a semiconductor device having a transistor including an oxide semiconductor, thereby improving reliability. A transistor including an oxide semiconductor having a large on-state current can be provided. A transistor including an oxide semiconductor having a small off-state current can be provided. A semiconductor device with low power consumption can be provided.

[0529] <Deformation Example 3>

[0530] In a modified example of this embodiment, it is also possible to Figure 26 Capacitor 100 is provided as shown. Specifically, a conductor 244, used as a plug or wiring, is embedded in an insulator 280. A barrier layer 281 having barrier properties is provided on the conductor 244. Then, an insulator 282 having barrier properties and an insulator 284 are provided. Subsequently, a highly flat insulator 286 is formed on the insulator 284. Thus, capacitor 100 can be provided on the highly flat insulator 286.

[0531] Capacitor 100 is provided on insulator 286 and includes conductors 112 (conductors 112a and 112b), insulators 130, 132, 134, and conductor 116. Note that conductor 124 functions as a plug or wiring for electrically connecting capacitor 100, transistor 200, or transistor 300.

[0532] The conductor 112 can be formed using a conductive material such as a metal, alloy, or metal oxide. High-melting-point materials such as tungsten or molybdenum, which have both heat resistance and conductivity, are preferably used, with tungsten being particularly preferred. When the conductor 112 is formed simultaneously with other components such as a conductor, low-resistance metal materials such as Cu (copper) or Al (aluminum) may also be used.

[0533] Insulators 130, 132, and 134 are formed on conductor 112. Insulators 130, 132, and 134 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or the like. Although a three-layer structure is shown in the drawings, a single-layer structure, a two-layer stacked structure, or a stacked structure of four or more layers may also be employed.

[0534] For example, it is preferable to use a material with a high dielectric strength, such as silicon oxynitride, for insulators 130 and 134, and to use a material with a high dielectric constant (high-k), such as aluminum oxide, for insulator 132. In capacitor 100 having this structure, the high dielectric constant (high-k) insulator ensures sufficient capacitance, while the high dielectric strength of the insulator improves insulation strength, thereby suppressing electrostatic discharge in capacitor 100.

[0535] Conductor 116 is provided on conductor 112 via insulators 130, 132, and 134. Conductor 116 can be formed using a conductive material such as a metal, alloy, or metal oxide. High-melting-point materials such as tungsten or molybdenum, which have both heat resistance and conductivity, are preferred, with tungsten being particularly preferred. When conductor 116 is formed simultaneously with another component such as a conductor, low-resistance metal materials such as Cu (copper) or Al (aluminum) can also be used.

[0536] Furthermore, when the conductor 112 serving as one electrode includes a convex structure such as the conductor 112b, the capacitance per projected area of ​​the capacitor can be increased, thereby achieving a smaller area, higher integration, and smaller size of the semiconductor device.

[0537] The above is a description of a modified example. By using this structure, variations in electrical characteristics can be suppressed in a semiconductor device having a transistor including an oxide semiconductor, thereby improving reliability. A transistor including an oxide semiconductor having a large on-state current can be provided. A transistor including an oxide semiconductor having a small off-state current can be provided. A semiconductor device with low power consumption can be provided.

[0538] <Deformation Example 4>

[0539] Figure 27 Another modified example of this embodiment is shown. Figure 27 and Figure 23 The difference lies in the structures of transistors 300 and 200 .

[0540] exist Figure 27 In the transistor 300 shown, the semiconductor region 312 (a portion of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 312 via an insulator 314. In addition, the conductor 316 can be formed using a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, the transistor 300 is also called a FIN-type transistor. In addition, an insulator used as a mask for forming the convex portion can also be provided in a manner that contacts the top surface of the convex portion. Although the case where a portion of the semiconductor substrate is processed to form the convex portion is shown here, the SOI substrate can also be processed to form a semiconductor film having a convex portion.

[0541] Figure 27 The details of the structure of transistor 200 are described in the above embodiment. An oxide, a gate insulator, and a conductor serving as a gate are formed in the opening formed in insulator 280. Therefore, it is preferable to form conductor 246 having a barrier property at least on the conductor serving as a gate.

[0542] When the conductor 112 (conductor 246) has a stacked structure of a conductor that has barrier properties against oxygen, hydrogen, or water (e.g., tantalum nitride) and a conductor with high conductivity (e.g., tungsten or copper), the conductor with high conductivity (e.g., tungsten or copper) is completely sealed by the tantalum nitride and the barrier layer 281. Therefore, diffusion of the conductor itself (e.g., copper) can be suppressed, and intrusion of impurities from above the insulator 282 through the conductor 244 can be suppressed.

[0543] A capacitor 100 is provided above the transistor 200. Figure 27 In the structure, the capacitor 100 includes a conductor 112, a conductor 246 having a barrier property, an insulator 282, an insulator 130, and a conductor 116.

[0544] The conductor 112 is used as an electrode of the capacitor 100. For example, Figure 27 In the structure of FIG, a portion of the conductor 244 used as a plug or wiring for connecting the transistor 200 and the transistor 300 is used as the conductor 112. When the barrier layer 281 is conductive, the barrier layer 281 is used as a portion of the electrode of the capacitor 100. When the barrier layer 281 is insulating, the barrier layer 281 is used as the dielectric of the capacitor 100.

[0545] By adopting this structure, the number of steps can be reduced compared to the case where electrodes and wirings are formed separately, thereby improving productivity.

[0546] The above is a description of a modified example. By using this structure, variations in electrical characteristics can be suppressed in a semiconductor device having a transistor including an oxide semiconductor, thereby improving reliability. A transistor including an oxide semiconductor having a large on-state current can be provided. A transistor including an oxide semiconductor having a small off-state current can be provided. A semiconductor device with low power consumption can be provided.

[0547] <Variation Example 5>

[0548] Figure 28 Another modified example of this embodiment is shown. Figure 28 and Figure 26 The difference lies in the structure of transistor 200.

[0549] like Figure 28 As shown, an insulator 279 and a barrier layer 271 may also be provided. Insulator 279 may be formed using the same material and method as insulator 280. That is, insulator 279, like insulator 280, preferably contains an oxide whose oxygen content exceeds the stoichiometric composition. Therefore, insulator 279 is an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film. As an insulator containing excess oxygen, a silicon oxide film or a silicon oxynitride film containing a large amount of oxygen may be formed by a CVD method or a sputtering method under appropriately set conditions. After the insulator to become insulator 279 is formed, a planarization treatment using a CMP method or the like may be performed to improve the flatness of the top surface of the insulator. In order to form an excess oxygen region in insulator 279, oxygen may be added, for example, by ion implantation, ion doping, or plasma treatment.

[0550] The barrier layer 271 is formed using an insulator or a conductor having a barrier property against oxygen. For example, the barrier layer 271 can be formed using aluminum oxide, hafnium oxide, tantalum oxide, tantalum nitride, or the like by sputtering or atomic layer deposition (ALD).

[0551] Insulator 280 is provided on insulator 279 and barrier layer 271. When insulator 280 is formed using the same material and method as insulator 279, when insulator 280 is treated to form an excess oxygen state, the introduced excess oxygen diffuses not only into insulator 280 but also into insulator 279. To form excess oxygen regions in insulator 280 and insulator 279, oxygen may be added to insulator 280 by, for example, ion implantation, ion doping, or plasma treatment.

[0552] The above is a description of a modified example. By using this structure, variations in electrical characteristics can be suppressed in a semiconductor device having a transistor including an oxide semiconductor, thereby improving reliability. A transistor including an oxide semiconductor having a large on-state current can be provided. A transistor including an oxide semiconductor having a small off-state current can be provided. A semiconductor device with low power consumption can be provided.

[0553] <Variation Example 6>

[0554] Figure 31A and Figure 31B Another modified example of this embodiment is shown. Figure 31A and Figure 31B These are cross-sectional views of the transistor 200 in the channel length direction and the channel width direction, respectively, with the dashed line A1 - A2 as the axis.

[0555] like Figure 31A and Figure 31B As shown, a stacked structure of insulators 212 and 214 and a stacked structure of insulators 282 and 284 may be used to surround transistor 200 and insulator 280 including an excess oxygen region. In this case, the stacked structure of insulators 212 and 214 is preferably in contact with the stacked structure of insulators 282 and 284 between the through-electrode connecting transistor 300 and capacitor 100 and transistor 200.

[0556] Therefore, oxygen released from insulator 280 and transistor 200 can be suppressed from diffusing into layers forming capacitor 100 or transistor 300. Alternatively, impurities such as hydrogen and water can be suppressed from diffusing into transistor 200 from layers above insulator 282 and layers below insulator 214.

[0557] That is, oxygen can be efficiently supplied from the excess oxygen region of insulator 280 to the oxide in transistor 200 where the channel is formed, thereby reducing oxygen vacancies. Furthermore, the formation of oxygen vacancies in the oxide in transistor 200 where the channel is formed due to impurities can be prevented. Therefore, the oxide in transistor 200 where the channel is formed can be an oxide semiconductor with a low defect state density and stable characteristics. That is, variations in the electrical characteristics of transistor 200 can be suppressed, and reliability can be improved.

[0558] <Variation Example 7>

[0559] Figure 32A and Figure 32B Another modified example of this embodiment is shown. Figure 32A It will Figure 30A The circuit diagram shown is a portion of a row in which semiconductor devices are arranged in a matrix. Figure 32B corresponds to Figure 32A A cross-sectional view of a semiconductor device.

[0560] exist Figure 32A and Figure 32B In the same row, there are arranged: a semiconductor device including a transistor 300, a transistor 200, and a capacitor 100; a semiconductor device including a transistor 301, a transistor 201, and a capacitor 101; and a semiconductor device including a transistor 302, a transistor 202, and a capacitor 102.

[0561] like Figure 32B As shown, a stacked structure of insulators 212 and 214 and a stacked structure of insulators 282 and 284 may be used to surround a plurality of transistors (transistors 200 and 201 in the figure) and an insulator 280 including an excess oxygen region. In this case, it is preferable to form a structure in which the insulators 212 and 214 and the insulators 282 and 284 are stacked between the through-electrode connecting the transistor 300, 301, or 302 to the capacitor 100, 101, or 102 and the transistor 200, 201, or 202.

[0562] Therefore, oxygen released from insulator 280 and transistor 200 can be suppressed from diffusing into layers forming capacitor 100 or transistor 300. Alternatively, impurities such as hydrogen and water can be suppressed from diffusing into transistor 200 from layers above insulator 282 and layers below insulator 214.

[0563] That is, oxygen can be efficiently supplied from the excess oxygen region of insulator 280 to the oxide in transistor 200 where the channel is formed, thereby reducing oxygen vacancies. Furthermore, the formation of oxygen vacancies in the oxide in transistor 200 where the channel is formed due to impurities can be prevented. Therefore, the oxide in transistor 200 where the channel is formed can be an oxide semiconductor with a low defect state density and stable characteristics. That is, variations in the electrical characteristics of transistor 200 can be suppressed, and reliability can be improved.

[0564] <Variation Example 8>

[0565] Figure 33 Another modified example of this embodiment is shown. Figure 33 yes Figure 32A and Figure 32BFIG. 1 is a cross-sectional view of a semiconductor device in which a transistor 201 and a transistor 202 are integrated.

[0566] like Figure 33 As shown, the conductor used as the source or drain electrode of transistor 201 can also function as conductor 112, which serves as one electrode of capacitor 101. In this case, the oxide of transistor 201 and the insulator used as the gate insulator of transistor 201, extending over the conductor used as the source or drain electrode of transistor 201, serve as the insulator of capacitor 101. Therefore, conductor 116, which serves as the other electrode of capacitor 101, can also be stacked on conductor 240a via insulator 250 and oxide 230c. This structure enables reduction in the area, high integration, and miniaturization of semiconductor devices.

[0567] Alternatively, the transistor 201 and the transistor 202 may be stacked. This structure enables reduction in area, high integration, and miniaturization of the semiconductor device.

[0568] Alternatively, a stacked structure of insulators 212 and 214 and a stacked structure of insulators 282 and 284 may be used to surround a plurality of transistors (transistors 201 and 202 in the drawing) and insulator 280 including an excess oxygen region. In this case, a structure in which insulators 212 and 214 and insulators 282 and 284 are stacked is preferably formed between a through-electrode connecting the transistor 300, 301, or 302 to the capacitor 100, 101, or 102 and the transistor 200, 201, or 202.

[0569] Therefore, oxygen released from insulator 280 and transistor 200 can be suppressed from diffusing into layers forming capacitor 100 or transistor 300. Alternatively, impurities such as hydrogen and water can be suppressed from diffusing into transistor 200 from layers above insulator 282 and layers below insulator 214.

[0570] That is, oxygen can be efficiently supplied from the excess oxygen region of insulator 280 to the oxide in transistor 200 where the channel is formed, thereby reducing oxygen vacancies. Furthermore, the formation of oxygen vacancies in the oxide in transistor 200 where the channel is formed due to impurities can be prevented. Therefore, the oxide in transistor 200 where the channel is formed can be an oxide semiconductor with a low defect state density and stable characteristics. That is, variations in the electrical characteristics of transistor 200 can be suppressed, and reliability can be improved.

[0571] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0572] Implementation 5

[0573] In this embodiment, an example of a circuit including a semiconductor device such as a transistor according to one embodiment of the present invention is described.

[0574] <Circuit>

[0575] Below, refer to Figure 34 and Figure 35 An example of a circuit including a semiconductor device such as a transistor according to one embodiment of the present invention will be described.

[0576] <Storage Device 1>

[0577] Figure 34 The semiconductor device of the embodiment 1 differs from the semiconductor device described in the above embodiment in that it includes a transistor 3400 and a wiring 3006. In this case, data can also be written and retained in the same manner as in the semiconductor device described in the above embodiment. As the transistor 3400, a transistor similar to the transistor 300 described above can be used.

[0578] The wiring 3006 is electrically connected to the gate of the transistor 3400 , one of the source and the drain of the transistor 3400 is electrically connected to the drain of the transistor 300 , and the other of the source and the drain of the transistor 3400 is electrically connected to the wiring 3003 .

[0579] <Storage Device 2>

[0580] Reference Figure 35 A modified example of a semiconductor device (storage device) is described with reference to the circuit diagram of FIG.

[0581] Figure 35 The semiconductor device shown includes transistors 4100, 4200, 4300, and 4400, and capacitors 4500 and 4600. Here, the transistor 4100 can be the same as the transistor 300, and the transistors 4200 to 4400 can be the same as the transistor 200. The capacitors 4500 and 4600 can be the same as the capacitor 100. Figure 35 Not shown, but multiple Figure 35 The semiconductor devices are arranged in a matrix. Figure 35 The semiconductor device can control writing and reading of data voltage according to a signal or potential supplied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.

[0582] One of the source and drain of the transistor 4100 is connected to the wiring 4003. The other of the source and drain of the transistor 4100 is connected to the wiring 4001. Figure 35The transistor 4100 is a p-channel transistor, but the transistor 4100 may also be an n-channel transistor.

[0583] Figure 35 The semiconductor device includes two data retention units. For example, the first data retention unit retains charge between one of the source and drain of the transistor 4400 connected to the node FG1, one electrode of the capacitor 4600, and one of the source and drain of the transistor 4200. The second data retention unit retains charge between the gate of the transistor 4100 connected to the node FG2, the other of the source and drain of the transistor 4200, one of the source and drain of the transistor 4300, and one electrode of the capacitor 4500.

[0584] The other of the source and drain of the transistor 4300 is connected to the wiring 4003. The other of the source and drain of the transistor 4400 is connected to the wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4200 is connected to the wiring 4006. The gate of the transistor 4300 is connected to the wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the capacitor 4500 is connected to the wiring 4009.

[0585] Transistors 4200, 4300, and 4400 are used as switches for controlling the writing of data voltages and the retention of charges. Note that as transistors 4200, 4300, and 4400, it is preferable to use transistors having a small current (small off-state current) flowing between the source and the drain in the non-conducting state. As an example of a transistor having a small off-state current, it is preferable to use a transistor (OS transistor) including an oxide semiconductor in its channel formation region. OS transistors have the following advantages, for example: a small off-state current and can be manufactured in a manner overlapping with a transistor including silicon. Although in Figure 35 The transistors 4200, 4300, and 4400 are n-channel transistors, but the transistors 4200, 4300, and 4400 may also be p-channel transistors.

[0586] Even if the transistor 4200, the transistor 4300, and the transistor 4400 include an oxide semiconductor, the transistor 4200 and the transistor 4300 are preferably provided in a layer different from the transistor 4400. Figure 35 In the semiconductor device, it is preferable to stack the transistor 4100, the transistor 4200, the transistor 4300, and the transistor 4400. In other words, by integrating the transistors, the circuit area can be reduced, and the size of the semiconductor device can be reduced.

[0587] Next, explain Figure 35 The semiconductor device shown operates to write data.

[0588] First, the operation of writing a data voltage to the data storage unit connected to the node FG1 (hereinafter referred to as writing operation 1) will be described. In the following description, the data voltage written to the data storage unit connected to the node FG1 is referred to as V D1 , and the threshold voltage of transistor 4100 is called V th .

[0589] In the write operation 1, the wiring 4003 is set to V D1 , and after setting wiring 4001 to ground potential, wiring 4001 is placed in an electrically floating state. Wiring 4005 and 4006 are set to a high level. Wiring 4007 to 4009 are set to a low level. Then, the potential of node FG2, which is in an electrically floating state, rises, and current flows through transistor 4100. The flow of this current causes the potential of wiring 4001 to rise. Transistors 4400 and 4200 become conductive. Therefore, as the potential of wiring 4001 rises, the potential of nodes FG1 and FG2 rises. When the potential of node FG2 rises and the voltage between the gate and source of transistor 4100 (V gs ) reaches the threshold voltage V of transistor 4100 th When V is 0, the current flowing through the transistor 4100 decreases. Therefore, the potential rise of the wiring 4001 and the nodes FG1 and FG2 stops, and the potential of the nodes FG1 and FG2 is fixed to a value lower than V D1 Low V th "V D1 -V th ”.

[0590] That is, when current flows through the transistor 4100, V applied to the wiring 4003 D1 is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 rise. When the potential of the node FG2 becomes “V D1 -V th ”, the V of transistor 4100 gs Become a V th , so the current stops.

[0591] Next, the operation of writing a data voltage to the data storage unit connected to the node FG2 (hereinafter referred to as writing operation 2) will be described. In the following description, the data voltage written to the data storage unit connected to the node FG2 is referred to as V D2 .

[0592] In the write operation 2, the wiring 4001 is set to V D2, and after setting wiring 4003 to ground potential, wiring 4003 is placed in an electrically floating state. Wiring 4007 is set to a high level. Wirings 4005, 4006, 4008, and 4009 are set to a low level. Transistor 4300 is placed in an on state, and wiring 4003 is set to a low level. Therefore, the potential of node FG2 also decreases to a low level, and current flows through transistor 4100. Due to the flow of this current, the potential of wiring 4003 rises. Transistor 4300 becomes on. Therefore, as the potential of wiring 4003 rises, the potential of node FG2 rises. When the potential of node FG2 rises and the V gs becomes the V of transistor 4100 th When V is reached, the current flowing through the transistor 4100 decreases. Therefore, the potential of the wiring 4003 and FG2 stops rising, and the potential of FG2 is fixed to a value lower than V. D2 Low V th "V D2 -V th ”.

[0593] That is, when current flows through the transistor 4100, V applied to the wiring 4001 D2 is applied to the wiring 4003, and the potential of the node FG2 rises. When the potential of the node FG2 becomes "V D2 -V th ”, the V of transistor 4100 gs Become a V th , so the current stops. At this time, transistors 4200 and 4400 are in a non-conductive state, and the potential of node FG1 remains at "V D1 -V th ”.

[0594] exist Figure 35 In a semiconductor device, after writing data voltages to multiple data retention units, wiring 4009 is set to a high level, raising the potentials of nodes FG1 and FG2. Each transistor is then turned off to stop charge transfer, thereby retaining the written data voltage.

[0595] By writing the data voltage to the nodes FG1 and FG2 as described above, the data voltage can be held in a plurality of data holding units. D1 -V th ” and “V D2 -V th ”, but they are data voltages corresponding to multi-valued data. Therefore, when each data holding unit holds 4 bits of data, 16 values ​​of “V D1 -Vth ” and 16 values ​​of “V D2 -V th ”.

[0596] Next, the following is explained Figure 35 The work of reading data from a semiconductor device.

[0597] First, an operation of reading a data voltage from a data holding portion connected to the node FG2 (hereinafter referred to as a read operation 1 ) will be described.

[0598] In the read operation 1, the wiring 4003 that is in an electrically floating state after precharging is discharged. The wirings 4005 to 4008 are set to a low level. When the wiring 4009 is set to a low level, the potential of the node FG2 in an electrically floating state is set to "V D2 -V th ”. The potential of the node FG2 decreases, and thus current flows through the transistor 4100. The flow of this current decreases the potential of the wiring 4003 in the electrically floating state. As the potential of the wiring 4003 decreases, the V gs becomes smaller. When the V gs becomes the V of transistor 4100 th When , the current flowing through the transistor 4100 becomes smaller. That is, the potential of the wiring 4003 becomes lower than the potential of the node FG2 "V D2 -V th "Higher than V th "V D2 The potential of the wiring 4003 corresponds to the data voltage of the data holding unit connected to the node FG2. The read analog data voltage is A / D converted to obtain the data of the data holding unit connected to the node FG2.

[0599] That is, the precharged wiring 4003 is placed in a floating state, and the potential of the wiring 4009 is switched from a high level to a low level, thereby causing current to flow through the transistor 4100. When the current flows, the potential of the floating wiring 4003 decreases to "V D2 In transistor 4100, “V D2 -V th ” and Wiring 4003’s “V D2 "V between gs Become a V th , so the current stops. Then, in the writing operation 2, the “V D2 ” is read out to the wiring 4003.

[0600] After acquiring the data of the data holding unit connected to the node FG2, the transistor 4300 is turned on, and the voltage “VD2 -V th ”Discharge.

[0601] Then, the charge held at node FG1 is distributed between node FG1 and node FG2, and the data voltage of the data holding unit connected to node FG1 is shifted to the data holding unit connected to node FG2. Wiring 4001 and 4003 are set to a low level. Wiring 4006 is set to a high level. Wiring 4005 and wirings 4007 to 4009 are also set to a low level. When transistor 4200 is turned on, the charge at node FG1 is distributed between node FG1 and node FG2.

[0602] Here, the potential after charge distribution is changed from the written potential "V D1 -V th Therefore, the capacitance value of the capacitor 4600 is preferably greater than the capacitance value of the capacitor 4500. Alternatively, the potential "V D1 -V th " is preferably greater than the potential "V corresponding to the same data D2 -V th By increasing the potential to be written in advance by changing the ratio of the capacitance values ​​in this way, the potential drop after charge distribution can be suppressed. The potential change caused by charge distribution will be described later.

[0603] Next, an operation of reading a data voltage from the data holding section connected to the node FG1 (hereinafter referred to as a read operation 2 ) will be described.

[0604] In read operation 2, the wiring 4003 that has been in an electrically floating state after precharging is discharged. The wirings 4005 to 4008 are set to a low level. The potential of the wiring 4009 is set to a high level during precharging and then to a low level. When the wiring 4009 is set to a low level, the potential of the node FG2 that is in an electrically floating state is set to "V D1 -V th ”. The potential of the node FG2 decreases, and thus current flows through the transistor 4100. The flow of this current decreases the potential of the wiring 4003 in the electrically floating state. As the potential of the wiring 4003 decreases, the V gs becomes smaller. When the V gs becomes the V of transistor 4100 th When , the current flowing through the transistor 4100 becomes smaller. That is, the potential of the wiring 4003 becomes lower than the potential of the node FG2 "V D1 -V th "Higher than V th "V D1The potential of the wiring 4003 corresponds to the data voltage of the data holding unit connected to the node FG1. The read analog data voltage is A / D converted to obtain the data of the data holding unit connected to the node FG1. The above is the operation of reading the data voltage from the data holding unit connected to the node FG1.

[0605] That is, the precharged wiring 4003 is placed in a floating state, and the potential of the wiring 4009 is switched from a high level to a low level, thereby causing current to flow through the transistor 4100. When the current flows, the potential of the floating wiring 4003 decreases to "V D1 In transistor 4100, “V D1 -V th ” and Wiring 4003’s “V D1 "V between gs Become a V th , so the current stops. Then, in the write operation 1, the “V D1 ” is read out to the wiring 4003.

[0606] In the above-described data voltage reading operation for nodes FG1 and FG2, data voltages can be read from a plurality of data holding units. For example, by holding 4 bits (16 values) of data in each of nodes FG1 and FG2, a total of 8 bits (256 values) of data can be held. Figure 35 In the illustrated structure, the first to third layers 4021 to 4023 are provided. However, by adding the number of layers, the storage capacity can be increased without increasing the area of ​​the semiconductor device.

[0607] Note that the read potential can be higher than the written data voltage by V th Therefore, the voltage “V D1 -V th "V th or "V D2 -V th "V th As a result, the storage capacity of each memory cell can be increased, and the read data can be made close to the correct data, so good data reliability can be achieved.

[0608] The structure described in this embodiment can be combined with the structures described in other embodiment modes as appropriate.

[0609] Implementation Method 6

[0610] In this embodiment, referring to Figures 36A to 36C 、 Figures 37A to 37C 、 Figure 38A and Figure 38Bas well as Figure 39A and Figure 39B An example of a circuit configuration in which the OS transistor described in the above embodiment can be used will be described.

[0611] Figure 36A 5800 is a circuit diagram of an inverter. The inverter 5800 outputs a signal to the output terminal OUT in which the logic of the signal supplied to the input terminal IN is inverted. The inverter 5800 includes a plurality of OS transistors. The signal S BG Able to switch the electrical characteristics of the OS transistor.

[0612] Figure 36B An example of an inverter 5800 is shown. The inverter 5800 includes an OS transistor 5810 and an OS transistor 5820. The inverter 5800 can be formed using only n-channel transistors, so the inverter 5800 can be formed at a low cost compared to an inverter formed using a complementary metal oxide semiconductor (i.e., a CMOS inverter).

[0613] In addition, the inverter 5800 including the OS transistor can be provided on a CMOS circuit including the Si transistor. Since the inverter 5800 can be provided to overlap with the CMOS circuit, the additional area of ​​the inverter 5800 is not required, thereby suppressing the increase in circuit area.

[0614] The OS transistors 5810 , 5820 each include a first gate used as a front gate, a second gate used as a back gate, a first terminal used as one of a source and a drain, and a second terminal used as the other of the source and the drain.

[0615] The first gate of the OS transistor 5810 is connected to the second terminal. The second gate of the OS transistor 5810 is connected to the supply signal S BG A first terminal of the OS transistor 5810 is connected to a wiring for supplying a voltage VDD. A second terminal of the OS transistor 5810 is connected to the output terminal OUT.

[0616] The first gate of the OS transistor 5820 is connected to the input terminal IN. The second gate of the OS transistor 5820 is connected to the input terminal IN. The first terminal of the OS transistor 5820 is connected to the output terminal OUT. The second terminal of the OS transistor 5820 is connected to a wiring supplying a voltage VSS.

[0617] Figure 36C is a timing diagram showing the operation of the inverter 5800. Figure 36C The timing diagram shows the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal S BGThe signal waveform and the change in the threshold voltage of the OS transistor 5810 (FET5810) are shown.

[0618] The signal S BG Applied to the second gate of the OS transistor 5810 to control the threshold voltage of the OS transistor 5810.

[0619] Signal S BG A voltage V is provided to shift the threshold voltage negatively. BG_A And the voltage V used to shift the threshold voltage in the positive direction BG_B When a voltage V is applied to the second gate BG_A When the threshold voltage of the OS transistor 5810 is shifted to the negative direction and becomes the threshold voltage V TH_A When a voltage V is applied to the second gate BG_B When the threshold voltage of the OS transistor 5810 is shifted to the positive direction and becomes the threshold voltage V TH_B .

[0620] To visualize the above explanation, Figure 37A V, one of the electrical characteristics of a transistor g -I d curve.

[0621] When the voltage V BG_A When a high voltage is applied to the second gate, the electrical characteristics of the OS transistor 5810 can be shifted to Figure 37A The curve represented by the dotted line 5840 in FIG. BG_B When a low voltage is applied to the second gate, the electrical characteristics of the OS transistor 5810 can be shifted to Figure 37A The curve represented by the solid line 5841 in FIG. Figure 37A As shown, by the voltage V BG_A and voltage V BG_B Switch signal S BG , which can cause the threshold voltage of the OS transistor 5810 to drift in a positive or negative direction.

[0622] By shifting the threshold voltage in the positive direction to the threshold voltage V TH_B , which can make it difficult for current to flow through the OS transistor 5810. Figure 37B This state is shown visually. Figure 37B As shown, the current I flowing through the OS transistor 5810 can be B Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 5820 is in an on state (ON), the voltage of the output terminal OUT can be rapidly reduced.

[0623] Since it is possible to obtain Figure 37B The current shown does not easily flow through the state in the OS transistor 5810, so it can be Figure 36C In the timing chart of , the signal waveform 5831 at the output terminal is made steeper. This can reduce the through current between the wiring supplying the voltage VDD and the wiring supplying the voltage VSS, thereby achieving low power consumption operation.

[0624] By shifting the threshold voltage negatively to the threshold voltage V TH_A , which allows current to flow easily through the OS transistor 5810. Figure 37C This state is shown visually. Figure 37C As shown, the current flowing through A Can be at least higher than the current I B Therefore, when the signal applied to the input terminal IN is at a low level and the OS transistor 5820 is in the off state (OFF), the voltage of the output terminal OUT can be rapidly increased.

[0625] Since it is possible to obtain Figure 37C The current shown in FIG. 5A easily flows through the state in the OS transistor 5810, so it can be Figure 36C In the timing diagram, the signal waveform 5832 at the output terminal is made steep.

[0626] In addition, it is preferable to use the signal S before the state of the OS transistor 5820 is switched, that is, before time T1 or time T2. BG Controls the threshold voltage of the OS transistor 5810. For example, Figure 36C As shown, it is preferable to lower the threshold voltage of the OS transistor 5810 from the threshold voltage V to the threshold voltage V before the time T1 at which the signal applied to the input terminal IN is switched to the high level. TH_A Switching to threshold voltage V TH_B In addition, if Figure 36C As shown, it is preferable to lower the threshold voltage of the OS transistor 5810 from the threshold voltage V to the threshold voltage V before the time T2 at which the signal applied to the input terminal IN is switched to the low level. TH_B Switching to threshold voltage V TH_A .

[0627] Although Figure 36C The timing diagram shows the switching signal S according to the signal applied to the input terminal IN BG However, a different structure may be adopted. For example, a structure may be adopted in which the second gate of the OS transistor 5810 in a floating state is used to maintain a voltage for controlling the threshold voltage. Figure 38A An example of this circuit configuration is shown.

[0628] Figure 38A The circuit structure is the same as that of the OS transistor 5850. Figure 36BThe first terminal of the OS transistor 5850 is connected to the second gate of the OS transistor 5810. The second terminal of the OS transistor 5850 is connected to the supply voltage V BG_B (or voltage V BG_A ) is connected to the wiring of the OS transistor 5850. The first gate of the OS transistor 5850 is connected to the supply signal S F The second gate of the OS transistor 5850 is connected to the supply voltage V BG_B (or voltage V BG_A ) wiring connections.

[0629] Reference Figure 38B The timing diagram of Figure 38A The operation of the circuit structure will be explained.

[0630] Before time T3 when the level of the signal applied to the input terminal IN is switched to a high level, a voltage for controlling the threshold voltage of the OS transistor 5810 is applied to the second gate of the OS transistor 5810. F The OS transistor 5850 is turned on and the node N is set to high level. BG Apply a voltage V to control the threshold voltage BG_B .

[0631] At node N BG The voltage becomes V BG_B After that, the OS transistor 5850 is turned off. Since the off-state current of the OS transistor 5850 is extremely small, the OS transistor 5850 is kept off and the node N is BG For a state very close to the floating state, the node N can be kept BG The voltage V BG_B Therefore, a voltage V is applied to the second gate of the OS transistor 5850. BG_B The number of operations is reduced, so the rewriting voltage V BG_B The power consumption required.

[0632] Although Figure 36B and Figure 38A Both embodiments show a structure in which a voltage is applied to the second gate of the OS transistor 5810 through external control, but a different structure may also be adopted. For example, a structure in which a voltage for controlling the threshold voltage is generated based on a signal applied to the input terminal IN and applied to the second gate of the OS transistor 5810 may also be adopted. Figure 39A An example of this circuit configuration is shown.

[0633] Figure 39A The circuit structure is the same as that of FIG. 5 except that a CMOS inverter 5860 is provided between the input terminal IN and the second gate of the OS transistor 5810. Figure 36B The circuit structure is the same as that of CMOS inverter 5860. The input terminal of CMOS inverter 5860 is connected to input terminal IN. The output terminal of CMOS inverter 5860 is connected to the second gate of OS transistor 5810.

[0634] Reference Figure 39B The timing diagram of Figure 39A The operation of the circuit structure will be explained. Figure 39B The timing diagram shows a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, an output waveform IN_B of the CMOS inverter 5860, and changes in the threshold voltage of the OS transistor 5810 (FET5810).

[0635] The output waveform IN_B, which is equivalent to a signal that inverts the logic of the signal applied to the input terminal IN, can be used as a signal for controlling the threshold voltage of the OS transistor 5810. Figures 36A to 36C As shown, the threshold voltage of the OS transistor 5810 can be controlled. Figure 39B At time T4, the signal applied to the input terminal IN is high, and the OS transistor 5820 is turned on. At this time, the output waveform IN_B is low. Therefore, current is less likely to flow through the OS transistor 5810, and the voltage of the output terminal OUT can be sharply reduced.

[0636] In addition, Figure 39B At time T5, the signal applied to the input terminal IN is low, and the OS transistor 5820 is turned off. At this time, the output waveform IN_B is high. Therefore, current can easily flow through the OS transistor 5810, and the voltage of the output terminal OUT can be rapidly increased.

[0637] As described above, in the inverter structure including the OS transistor of this embodiment, the back gate voltage is switched according to the logic of the signal applied to the input terminal IN. This structure allows the threshold voltage of the OS transistor to be controlled. By controlling the threshold voltage of the OS transistor using the signal applied to the input terminal IN, the voltage at the output terminal OUT can be rapidly changed. Furthermore, the through-current between the wiring supplying the power supply voltage can be reduced, thereby reducing power consumption.

[0638] The structure described in this embodiment can be combined with the structures described in other embodiment modes as appropriate.

[0639] Implementation 7

[0640] In this embodiment, referring to Figures 40A to 40E 、 Figure 41A and Figure 41B 、 Figure 42A and Figure 42B、 Figures 43A to 43C 、 Figure 44A and Figure 44B 、 Figures 45A to 45C as well as Figure 46A and Figure 46B An example of a semiconductor device including a plurality of circuits including the OS transistors described in the above embodiment will be described.

[0641] Figure 40A 5900 is a block diagram of a semiconductor device 5900. The semiconductor device 5900 includes a power supply circuit 5901, a circuit 5902, a voltage generating circuit 5903, a circuit 5904, a voltage generating circuit 5905, and a circuit 5906.

[0642] The power supply circuit 5901 generates a potential V used as a reference. ORG The voltage V ORG It is not limited to one voltage, but can be multiple voltages. ORG The semiconductor device 5900 may generate a voltage V based on a power supply voltage applied from the outside. ORG Therefore, the semiconductor device 5900 can operate even without inputting a plurality of power supply voltages from the outside.

[0643] Circuits 5902, 5904, and 5906 operate using different power supply voltages. For example, the power supply voltage of circuit 5902 is based on voltage V ORG and voltage V SS (V ORG >V SS For example, the power supply voltage of circuit 5904 is based on the voltage V POG and voltage V SS (V POG >V ORG For example, the power supply voltage of circuit 5906 is based on the voltage V ORG , voltage V SS and voltage V NEG (V ORG >V SS >V NEG ) and the voltage applied. When the voltage V SS When it is equal to the ground potential (GND), the types of voltages generated in the power supply circuit 5901 can be reduced.

[0644] The voltage generating circuit 5903 generates a voltage V POG The voltage generating circuit 5903 can generate a voltage V based on the voltage V applied from the power supply circuit 5901. ORG The generated voltage V POGTherefore, the semiconductor device 5900 including the circuit 5904 can operate based on a power supply voltage applied from the outside.

[0645] The voltage generating circuit 5905 generates a voltage V NEG The voltage generating circuit 5905 can generate a voltage V based on the voltage V applied from the power supply circuit 5901. ORG The generated voltage V NEG Therefore, the semiconductor device 5900 including the circuit 5906 can operate based on a power supply voltage applied from the outside.

[0646] Figure 40B Shown using voltage V POG And the working example of circuit 5904, Figure 40C Examples of signal waveforms for operating the circuit 5904 are shown.

[0647] Figure 40B Transistor 5911 is shown. The signal applied to the gate of transistor 5911 is based on, for example, a voltage V POG and voltage V SS This signal is generated when the transistor 5911 is turned on. POG , when the transistor 5911 is turned off, the voltage V SS .like Figure 40C As shown, the voltage V POG Higher than the voltage V ORG Therefore, the conduction state between the source (S) and the drain (D) of the transistor 5911 can be obtained more reliably. As a result, the frequency of malfunction of the circuit 5904 can be reduced.

[0648] Figure 40D Shown using voltage V NEG And the working example of circuit 5906, Figure 40E Examples of signal waveforms for operating circuit 5906 are shown.

[0649] Figure 40D A transistor 5912 with a back gate is shown. The signal applied to the gate of the transistor 5912 is based on, for example, a voltage V ORG and voltage V SS This signal is generated based on the voltage V when the transistor 5911 is turned on. ORG and generates a voltage V when the transistor 5911 is turned off. SS The signal applied to the back gate of transistor 5912 is based on the voltage V NEG And generate. Figure 40E As shown, the voltage V NEG Lower than voltage V SS(GND). Therefore, the threshold voltage of transistor 5912 can be controlled to drift in the positive direction. Therefore, transistor 5912 can be more reliably placed in a non-conductive state, thereby reducing the current flowing between the source (S) and drain (D). As a result, the frequency of malfunctions in circuit 5906 can be reduced, and its power consumption can be reduced.

[0650] Voltage V NEG It can also be applied directly to the back gate of transistor 5912. Alternatively, it can be based on the voltage V ORG and voltage V NEG A signal applied to the gate of the transistor 5912 is generated, and the generated signal is applied to the back gate of the transistor 5912.

[0651] Figure 41A and Figure 41B Show Figure 40D and Figure 40E An example of deformation.

[0652] exist Figure 41A In the circuit diagram shown, a transistor 5922 whose conduction state can be controlled by a control circuit 5921 is provided between the voltage generating circuit 5905 and the circuit 5906. The transistor 5922 is an n-channel OS transistor. The control signal S output by the control circuit 5921 is BG This is a signal that controls the conduction state of the transistor 5922. The transistors 5912A and 5912B included in the circuit 5906 are OS transistors similar to the transistor 5922.

[0653] Figure 41B The timing diagram shows the control signal S BG The potential of node N BG The potential of the node N BG The potential of φ represents the potential state of the back gate of transistors 5912A and 5912B. BG When the level is high, the transistor 5922 becomes conductive and the node N BG The voltage becomes the voltage V NEG Then, the control signal S BG When the level is low, the node N BG In an electrically floating state. Since transistor 5922 is an OS transistor, its off-state current is small. Therefore, even if node N BG In the electrically floating state, it can also maintain the applied voltage V NEG .

[0654] Figure 42A An example of a circuit configuration applicable to the voltage generating circuit 5903 is shown. Figure 42AThe voltage generating circuit 5903 shown is a 5-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is applied to the capacitors C1 to C5 directly or through the inverter INV. When the power supply voltage of the inverter INV is based on the voltage V ORG and voltage V SS When the voltage is applied, it can be obtained by supplying the clock signal CLK and boosting it to the voltage V ORG A voltage of 5 times the positive voltage V POG Note that the forward voltage of diodes D1 to D5 is 0V. When the number of charge pump stages is changed, the desired voltage V POG .

[0655] Figure 42B An example of a circuit configuration applicable to the voltage generating circuit 5905 is shown. Figure 42B The voltage generating circuit 5905 shown is a 4-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is applied to the capacitors C1 to C5 directly or through the inverter INV. When the power supply voltage of the inverter INV is based on the voltage V ORG and voltage V SS When the voltage is applied, the voltage V SS Step down to voltage V ORG 4 times the negative voltage V NEG Note that the forward voltage of diodes D1 to D5 is 0V. When the number of charge pump stages is changed, the desired voltage V NEG .

[0656] The circuit structure of the voltage generating circuit 5903 is not limited to Figure 42A The structure of the circuit diagram is shown. Figures 43A to 43C 、 Figure 44A and Figure 44B A modified example of the voltage generating circuit 5903 is shown.

[0657] Figure 43A The voltage generating circuit 5903A shown includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1. The clock signal CLK is supplied to the gates of the transistors M1 to M10 directly or through the inverter INV1. The voltage V ORG 4 times the positive voltage V POG When the number of charge pump stages is changed, the desired voltage V POG .exist Figure 43AIn the voltage generating circuit 5903A, when the transistors M1 to M10 are OS transistors, the off-state currents of the transistors M1 to M10 can be reduced, thereby suppressing the leakage of the charges held in the capacitors C11 to C14. ORG Efficiently boost voltage to V POG .

[0658] Figure 43B The voltage generating circuit 5903B shown includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV2. The clock signal CLK is supplied to the gates of the transistors M11 to M14 directly or through the inverter INV2. By supplying the clock signal CLK, the voltage V ORG The voltage V is twice the positive voltage POG .exist Figure 43B In the voltage generating circuit 5903B, when the transistors M11 to M14 are OS transistors, the off-state currents of the transistors M11 to M14 can be reduced, thereby suppressing the leakage of the charge held in the capacitors C15 and C16. ORG Efficiently boost voltage to V POG .

[0659] Figure 43C The voltage generating circuit 5903C includes an inductor I11, a transistor M15, a diode D6, and a capacitor C17. The conduction state of the transistor M15 is controlled by the control signal EN. By using the control signal EN, the voltage V ORG The voltage V obtained by boosting POG .because Figure 43C The voltage generating circuit 5903C uses the inductor I11 to boost the voltage, so it can boost the voltage with high efficiency.

[0660] Figure 44A The voltage generating circuit 5903D has the following structure: diode-connected transistors M16 to M20 are provided instead of Figure 42A The voltage generating circuit 5903 includes diodes D1 to D5. Figure 44A In the voltage generating circuit 5903D, when the transistors M16 to M20 are OS transistors, the off-state currents of the transistors M16 to M20 can be reduced, thereby suppressing the leakage of the charges held in the capacitors C1 to C5. ORG Efficiently boost voltage to V POG .

[0661] Figure 44B The voltage generating circuit 5903E has the following structure: transistors M21 to M25 including back gates are provided instead of Figure 44AThe transistors M16 to M20 of the voltage generating circuit 5903D. Figure 44B In the voltage generating circuit 5903E, the same voltage as the gate can be applied to the back gate, so the amount of current flowing through the transistor can be increased. ORG Efficiently boost voltage to V POG .

[0662] Note that a modified example of the voltage generating circuit 5903 can also be applied to Figure 42B voltage generating circuit 5905. Figures 45A to 45C 、 Figure 46A and Figure 46B The structure of the circuit diagram at this time is shown in FIG. Figure 45A The voltage generating circuit 5905A shown in FIG. 5 can obtain the voltage V by supplying the clock signal CLK. SS Step down to voltage V ORG 3 times the negative voltage V NEG .exist Figure 45B The voltage generating circuit 5905B shown can obtain the voltage V by supplying the clock signal CLK SS Step down to voltage V ORG The voltage V is twice the negative voltage NEG .

[0663] Figures 45A to 45C 、 Figure 46A and Figure 46B The voltage generating circuits 5905A and 5905B and the voltage generating circuits 5905C to 5905E shown have Figures 43A to 43C 、 Figure 44A and Figure 44B The voltage generating circuits 5903A to 5903E shown in FIG. 5 are configured by changing the voltage applied to each wiring or the element arrangement. Figures 45A to 45C 、 Figure 46A and Figure 46B The voltage generating circuits 5905A to 5905E shown in FIG. 5 can generate the voltage V SS Efficiently step down to voltage V NEG .

[0664] As described above, in the structure of this embodiment, the voltage required by the circuit included in the semiconductor device can be generated inside the semiconductor device. Therefore, the types of power supply voltages applied from the outside to the semiconductor device can be reduced.

[0665] The structure described in this embodiment can be combined with the structures described in other embodiment modes as appropriate.

[0666] Implementation 8

[0667] In this embodiment, an example of a CPU including a transistor of an embodiment of the present invention and a semiconductor device such as the above-described storage device will be described.

[0668] <Structure of CPU>

[0669] Figure 47 The semiconductor device 5400 shown includes a CPU core 5401, a power management unit 5421, and a peripheral circuit 5422. The power management unit 5421 includes a power controller 5402 and a power switch 5403. The peripheral circuit 5422 includes a cache 5404 having a cache memory, a bus interface (BUS I / F) 5405, and a debug interface (Debug I / F) 5406. The CPU core 5401 includes a data bus 5423, a control device 5407, a PC (program counter) 5408, pipeline registers 5409, 5410, an ALU (arithmetic logic unit) 5411, and a register bank 5412. Data is transferred between the CPU core 5401 and the peripheral circuit 5422 such as the cache 5404 via the data bus 5423.

[0670] The semiconductor device (cell) can be used for many logic circuits typified by the power controller 5402 and the control device 5407. In particular, it can be used for all logic circuits that can be formed using standard cells. As a result, the semiconductor device 5400 can be miniaturized. The semiconductor device 5400 can have low power consumption. The semiconductor device 5400 can have a high operating speed. The semiconductor device 5400 can reduce fluctuations in the power supply voltage.

[0671] When a p-channel Si transistor and a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region described in the above embodiment are used as the semiconductor device (cell) and this semiconductor device (cell) is used for the semiconductor device 5400, the semiconductor device 5400 can be miniaturized. The semiconductor device 5400 can have low power consumption. The semiconductor device 5400 can have a high operating speed. In particular, when only p-channel transistors are used as Si transistors, the manufacturing cost can be reduced.

[0672] The control device 5407 has the following function: by overall controlling the operations of the PC 5408, the pipeline registers 5409, 5410, the ALU 5411, the register bank 5412, the cache 5404, the bus interface 5405, the debug interface 5406, and the power controller 5402, it decodes and executes the instructions included in a program such as an input application software.

[0673] ALU5411 has the function of performing various operations such as arithmetic and logical operations.

[0674] The cache 5404 has the function of temporarily storing frequently used data. PC5408 is a register that has the function of storing the address of the instruction to be executed next. Figure 47 Although not shown in the figure, the cache memory 5404 is provided with a cache controller that controls the operation of the cache memory.

[0675] The pipeline register 5409 has the function of temporarily storing instructions.

[0676] The register file 5412 includes a plurality of registers including a common register, and can store data read from the main memory or data obtained as a result of arithmetic processing by the ALU 5411 .

[0677] The pipeline register 5410 has a function of temporarily storing data used for operation processing by the ALU 5411 or data obtained from the operation processing result of the ALU 5411.

[0678] The bus interface 5405 functions as a data path between the semiconductor device 5400 and various devices outside the semiconductor device 5400. The debug interface 5406 functions as a signal path for inputting debug control instructions to the semiconductor device 5400.

[0679] The power switch 5403 controls the supply of power voltage to various circuits in the semiconductor device 5400, other than the power controller 5402. These various circuits belong to several different power domains. The power switch 5403 controls whether the power voltage is supplied to the various circuits belonging to the same power domain. The power controller 5402 also controls the operation of the power switch 5403.

[0680] The semiconductor device 5400 having the above-described structure can perform power gating. An example of the operation flow of power gating will be described.

[0681] First, the CPU core 5401 sets the timing for stopping the supply of power voltage in the register of the power controller 5402. Then, the CPU core 5401 sends an instruction to the power controller 5402 to start power gating. Then, the various registers and cache 5404 included in the semiconductor device 5400 begin data backup. Then, the power switch 5403 stops the supply of power voltage to the various circuits included in the semiconductor device 5400 other than the power controller 5402. Then, by inputting an interrupt signal to the power controller 5402, the supply of power voltage to the various circuits included in the semiconductor device 5400 begins. Alternatively, a counter may be provided in the power controller 5402 to determine the timing for starting the supply of power voltage, independent of the input of an interrupt signal. Then, the various registers and cache 5404 begin data recovery. Then, instruction execution in the control device 5407 resumes.

[0682] This power gating can be performed on the entire processor or on one or more logic circuits included in the processor. Furthermore, power supply can be stopped even for a short period of time. Thus, power consumption can be reduced at a fine granularity, both spatially and temporally.

[0683] When power gating is performed, it is preferable to back up data held by the CPU core 5401 or the peripheral circuit 5422 in a relatively short period of time. In this case, the power can be turned on or off in a relatively short period of time, thereby achieving a significant effect of reducing power consumption.

[0684] In order to back up the data maintained by the CPU core 5401 or the peripheral circuit 5422 in a shorter period, it is preferred to perform data backup in the trigger circuit (which is referred to as a trigger circuit capable of backup). In addition, it is preferred to perform data backup in the SRAM cell (which is referred to as an SRAM cell capable of backup). The trigger circuit and SRAM cell capable of backup preferably include a transistor containing an oxide semiconductor (preferably an oxide containing In, Ga and Zn) in the channel formation region. As a result, the transistor has a small off-state current, whereby the trigger circuit or SRAM cell capable of backup can maintain data for a long period without the need for power supply. When the switching speed of the transistor is fast, the trigger circuit and SRAM cell capable of backup can sometimes perform data backup and recovery in a shorter period.

[0685] Reference Figure 48 An example of a flip-flop circuit capable of backup will be described.

[0686] Figure 48The semiconductor device 5500 shown is an example of a flip-flop circuit capable of backup. The semiconductor device 5500 includes a first storage circuit 5501, a second storage circuit 5502, a third storage circuit 5503, and a readout circuit 5504. The difference between potentials V1 and V2 is supplied to the semiconductor device 5500 as a power supply voltage. One of potentials V1 and V2 is at a high level, and the other is at a low level. The following describes an example structure of the semiconductor device 5500 when potential V1 is at a low level and potential V2 is at a high level.

[0687] The first storage circuit 5501 has a function of retaining data when a signal D containing data is input while the semiconductor device 5500 is supplied with power supply voltage. Furthermore, while the semiconductor device 5500 is supplied with power supply voltage, the first storage circuit 5501 outputs a signal Q containing the retained data. On the other hand, while the semiconductor device 5500 is not supplied with power supply voltage, the first storage circuit 5501 cannot retain data. In other words, the first storage circuit 5501 can be referred to as a volatile storage circuit.

[0688] The second storage circuit 5502 has a function of reading and storing (or backing up) data held in the first storage circuit 5501. The third storage circuit 5503 has a function of reading and storing (or backing up) data held in the second storage circuit 5502. The readout circuit 5504 has a function of reading data held in the second storage circuit 5502 or the third storage circuit 5503 and storing (or restoring) it in the first storage circuit 5501.

[0689] In particular, the third storage circuit 5503 has a function of reading and storing (or backing up) the data held in the second storage circuit 5502 even when the power supply voltage is not supplied to the semiconductor device 5500.

[0690] like Figure 48 As shown, the second storage circuit 5502 includes a transistor 5512 and a capacitor 5519. The third storage circuit 5503 includes a transistor 5513, a transistor 5515, and a capacitor 5520. The readout circuit 5504 includes a transistor 5510, a transistor 5518, a transistor 5509, and a transistor 5517.

[0691] The transistor 5512 has a function of charging and discharging the capacitor 5519 according to the data stored in the first storage circuit 5501. The transistor 5512 is preferably capable of quickly charging and discharging the capacitor 5519 according to the data stored in the first storage circuit 5501. Specifically, the transistor 5512 preferably includes crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in its channel formation region.

[0692] The conductive state or non-conductive state of the transistor 5513 is determined by the charge held in the capacitor 5519. The transistor 5515 has a function of charging and discharging the capacitor 5520 according to the potential of the wiring 5544 when the transistor 5513 is in the conductive state. The off-state current of the transistor 5515 is preferably extremely small. Specifically, the transistor 5515 preferably includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region.

[0693] The specific connections between the various components will be described. One of the source and drain of transistor 5512 is connected to first storage circuit 5501. The other of the source and drain of transistor 5512 is connected to one electrode of capacitor 5519, the gate of transistor 5513, and the gate of transistor 5518. The other electrode of capacitor 5519 is connected to wiring 5542. One of the source and drain of transistor 5513 is connected to wiring 5544. The other of the source and drain of transistor 5513 is connected to one of the source and drain of transistor 5515. The other of the source and drain of transistor 5515 is connected to one electrode of capacitor 5520 and the gate of transistor 5510. The other electrode of capacitor 5520 is connected to wiring 5543. One of the source and drain of transistor 5510 is connected to wiring 5541. The other of the source and drain of transistor 5510 is connected to one of the source and drain of transistor 5518. The other of the source and drain of the transistor 5518 is connected to one of the source and drain of the transistor 5509. The other of the source and drain of the transistor 5509 is connected to one of the source and drain of the transistor 5517 and the first storage circuit 5501. The other of the source and drain of the transistor 5517 is connected to the wiring 5540. Figure 48 The gate of the transistor 5509 is connected to the gate of the transistor 5517 , but the gate of the transistor 5509 does not necessarily have to be connected to the gate of the transistor 5517 .

[0694] The transistor 5515 can be any of the transistors described in the above embodiment modes. Since the off-state current of the transistor 5515 is low, the semiconductor device 5500 can retain data for a long period of time without requiring power. Since the switching characteristics of the transistor 5515 are excellent, the semiconductor device 5500 can perform backup and recovery at high speed.

[0695] The structure described in this embodiment can be combined with the structures described in other embodiment modes as appropriate.

[0696] Implementation Method 9

[0697] In this embodiment, an example of an imaging device including a transistor and the like according to one embodiment of the present invention will be described.

[0698] <Camera>

[0699] Hereinafter, an imaging device according to an embodiment of the present invention will be described.

[0700] Figure 49A 2 is a plan view showing an example of an imaging device 2200 according to an embodiment of the present invention. The imaging device 2200 includes a pixel portion 2210 and peripheral circuits (peripheral circuits 2260, 2270, 2280, and 2290) for driving the pixel portion 2210. The pixel portion 2210 includes a plurality of pixels 2211 arranged in a matrix of p rows and q columns (p and q are integers greater than or equal to 2). The peripheral circuits 2260, 2270, 2280, and 2290 are all connected to the plurality of pixels 2211 and have a function of supplying signals for driving the plurality of pixels 2211. In this specification, etc., sometimes "peripheral circuit" or "drive circuit" refers to all of the peripheral circuits 2260, 2270, 2280, and 2290. For example, the peripheral circuit 2260 can be said to be a part of the peripheral circuit.

[0701] The imaging device 2200 preferably includes a light source 2291. The light source 2291 can emit detection light P1.

[0702] The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. Alternatively, the peripheral circuit may be formed on the substrate forming the pixel portion 2210. Alternatively, a semiconductor device such as an IC chip may be used as part or all of the peripheral circuit. Note that one or more of the peripheral circuits 2260, 2270, 2280, and 2290 may be omitted as the peripheral circuit.

[0703] like Figure 49B As shown, in the pixel portion 2210 included in the imaging device 2200, the pixels 2211 may be arranged in an inclined manner. When the pixels 2211 are arranged in an inclined manner, the pixel spacing (pitch) in the row and column directions can be reduced. This can improve the quality of images captured by the imaging device 2200.

[0704] <Pixel Structure Example 1>

[0705] A pixel 2211 included in the imaging device 2200 is formed of a plurality of sub-pixels 2212 . Each sub-pixel 2212 is combined with a filter (color filter) that transmits light in a specific wavelength range, thereby obtaining data for realizing color image display.

[0706] Figure 50A It is a plan view showing an example of a pixel 2211 for obtaining a color image. Figure 50AThe illustrated pixel 2211 includes a sub-pixel 2212 (also referred to as a sub-pixel 2212R) provided with a color filter that transmits light in the red (R) wavelength range, a sub-pixel 2212 (also referred to as a sub-pixel 2212G) provided with a color filter that transmits light in the green (G) wavelength range, and a sub-pixel 2212 (also referred to as a sub-pixel 2212B) provided with a color filter that transmits light in the blue (B) wavelength range. The sub-pixels 2212 can be used as photosensors.

[0707] Sub-pixels 2212 (sub-pixel 2212R, sub-pixel 2212G, and sub-pixel 2212B) are electrically connected to wiring 2231, wiring 2247, wiring 2248, wiring 2249, and wiring 2250. In addition, sub-pixels 2212R, sub-pixel 2212G, and sub-pixel 2212B are connected to wiring 2253 that is independently provided. In this specification, for example, wiring 2248 and wiring 2249 connected to pixel 2211 in the nth row are referred to as wiring 2248[n] and wiring 2249[n]. For example, wiring 2253 connected to pixel 2211 in the mth column is referred to as wiring 2253[m]. In addition, Figure 50A In FIG. 1 , the wiring 2253 connected to the sub-pixel 2212R, the sub-pixel 2212G, and the sub-pixel 2212B in the pixel 2211 in the mth column is referred to as wiring 2253[m]R, wiring 2253[m]G, and wiring 2253[m]B. The sub-pixel 2212 is electrically connected to the peripheral circuit via these wirings.

[0708] The imaging device 2200 has a structure in which sub-pixels 2212 provided with color filters that transmit light in the same wavelength range in adjacent pixels 2211 are electrically connected to each other via switches. Figure 50B An example of connection between a sub-pixel 2212 in a pixel 2211 located in the nth row (n is an integer greater than 1 and less than p) and the mth column (m is an integer greater than 1 and less than q) and a sub-pixel 2212 in a pixel 2211 located in the n+1th row and the mth column adjacent to the pixel 2211 is shown. Figure 50B In the embodiment, the sub-pixel 2212R arranged in the nth row and the mth column is connected to the sub-pixel 2212R arranged in the n+1th row and the mth column via a switch 2201. The sub-pixel 2212G arranged in the nth row and the mth column is connected to the sub-pixel 2212G arranged in the n+1th row and the mth column via a switch 2202. The sub-pixel 2212B arranged in the nth row and the mth column is connected to the sub-pixel 2212B arranged in the n+1th row and the mth column via a switch 2203.

[0709] The color filters used for the sub-pixels 2212 are not limited to red (R), green (G), and blue (B) filters; filters that transmit cyan (C), yellow (Y), and magenta (M) light may also be used. By providing sub-pixels 2212 that detect light in three different wavelength ranges within a single pixel 2211, a full-color image can be obtained.

[0710] In addition to sub-pixels 2212 provided with color filters that transmit red (R), green (G), and blue (B), pixels 2211 may also include sub-pixels 2212 provided with color filters that transmit yellow (Y). In addition to sub-pixels 2212 provided with color filters that transmit cyan (C), yellow (Y), and magenta (M), pixels 2211 may also include sub-pixels 2212 provided with color filters that transmit blue (B). Providing sub-pixels 2212 that detect light in four different wavelength ranges in a single pixel 2211 can improve the color reproducibility of the resulting image.

[0711] For example, in Figure 50A In the embodiment of the present invention, the pixel number ratio (or light receiving area ratio) of the sub-pixels 2212 detecting light in the red wavelength range, the sub-pixels 2212 detecting light in the green wavelength range, and the sub-pixels 2212 detecting light in the blue wavelength range is not limited to 1:1:1. For example, a Bayer arrangement may be employed in which the pixel number ratio (light receiving area ratio) of red, green, and blue is 1:2:1. Alternatively, the pixel number ratio (light receiving area ratio) of red, green, and blue may be 1:6:1.

[0712] The number of sub-pixels 2212 provided in the pixel 2211 may be one, but preferably two or more. For example, when two or more sub-pixels 2212 are provided to detect light in the same wavelength range, redundancy can be increased, thereby improving the reliability of the imaging device 2200.

[0713] When an infrared (IR) filter that reflects or absorbs visible light and transmits infrared light is used as a filter, the imaging device 2200 that detects infrared light can be realized.

[0714] Furthermore, using a neutral density (ND) filter (neutral density filter) can prevent output saturation caused by high amounts of light entering the photoelectric conversion element (light-receiving element). By combining ND filters with different light reduction levels, the dynamic range of the imaging device can be increased.

[0715] In addition to the above-mentioned filters, the pixel 2211 may also be provided with a lens. Figure 51A and Figure 51BThe cross-sectional view of FIG2 illustrates an example of the configuration of the pixel 2211, the filter 2254, and the lens 2255. By providing the lens 2255, the photoelectric conversion element can efficiently receive light. Specifically, Figure 51A As shown, light 2256 passes through a lens 2255 , a filter 2254 (a filter 2254R, a filter 2254G, and a filter 2254B), a pixel circuit 2230 , and the like provided in the pixel 2211 and enters the photoelectric conversion element 2220 .

[0716] However, as shown by the area surrounded by the dot-dash line, a part of the light 2256 indicated by the arrow is sometimes blocked by a part of the wiring 2257. Figure 51B As shown, it is preferable to adopt a structure in which a lens 2255 and a filter 2254 are provided on the side of the photoelectric conversion element 2220 so that the photoelectric conversion element 2220 can efficiently receive light 2256. When light 2256 enters the photoelectric conversion element 2220 from the side of the photoelectric conversion element 2220, the imaging device 2200 can be provided with high sensitivity.

[0717] As Figure 51A and Figure 51B The photoelectric conversion element 2220 shown may also use a photoelectric conversion element having a pn junction or a pin junction.

[0718] The photoelectric conversion element 2220 may be formed using a material capable of absorbing radiation and generating charges. Examples of materials capable of absorbing radiation and generating charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

[0719] For example, when selenium is used for the photoelectric conversion element 2220 , the photoelectric conversion element 2220 can have a light absorption coefficient in a wide wavelength range, such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays.

[0720] The camera device 2200 includes a pixel 2211. Figure 50A and Figure 50B In addition to the sub-pixel 2212 shown, a sub-pixel 2212 having a first filter may also be included.

[0721] <Pixel Structure Example 2>

[0722] Hereinafter, an example of a pixel including a transistor including silicon and a transistor including an oxide semiconductor will be described. As each transistor, the same transistor as that described in the above embodiment can be used.

[0723] Figure 52 is a cross-sectional view of elements included in the imaging device. Figure 52The illustrated imaging device includes a transistor 2351 made of silicon on a silicon substrate 2300, transistors 2352 and 2353 made of an oxide semiconductor stacked on the transistor 2351, and a photodiode 2360 provided in the silicon substrate 2300. The cathode 2362 of each transistor and the photodiode 2360 is electrically connected to various plugs 2370 and wiring 2371. In addition, the anode 2361 of the photodiode 2360 is electrically connected to the plug 2370 via a low-resistance region 2363.

[0724] The camera device includes: a layer 2310 including a transistor 2351 arranged on a silicon substrate 2300 and a photodiode 2360 arranged in the silicon substrate 2300, a layer 2320 that is in contact with the layer 2310 and includes a wiring 2371, a layer 2330 that is in contact with the layer 2320 and includes transistors 2352 and 2353, and a layer 2340 that is in contact with the layer 2330 and includes a wiring 2372 and a wiring 2373.

[0725] exist Figure 52 In the example cross-sectional view of FIG, the light-receiving surface of photodiode 2360 is provided on the side of silicon substrate 2300 opposite to the surface on which transistor 2351 is formed. This structure ensures a secure light path without being affected by various transistors or wiring. Consequently, a pixel with a high aperture ratio can be formed. Furthermore, the light-receiving surface of photodiode 2360 can be the same surface as the surface on which transistor 2351 is formed.

[0726] When a pixel is formed using only a transistor including an oxide semiconductor, the layer 2310 may include the transistor including the oxide semiconductor. Alternatively, the pixel may include only the transistor including the oxide semiconductor and the layer 2310 may be omitted.

[0727] The silicon substrate 2300 may be an SOI substrate. Alternatively, a substrate containing germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used instead of the silicon substrate 2300 .

[0728] Here, an insulator 2380 is provided between the layer 2310 including the transistor 2351 and the photodiode 2360 and the layer 2330 including the transistors 2352 and 2353. However, the position of the insulator 2380 is not limited thereto. An insulator 2379 is provided below the insulator 2380, and an insulator 2381 is provided above the insulator 2380.

[0729] Conductors 2390a to 2390e are provided in openings formed in the insulators 2379 and 2381. The conductors 2390a, 2390b, and 2390e serve as plugs and wiring. The conductor 2390c ​​serves as a back gate of the transistor 2353. The conductor 2390d serves as a back gate of the transistor 2352.

[0730] The hydrogen in the insulator provided near the channel formation region of the transistor 2351 terminates the dangling bonds of silicon, thereby improving the reliability of the transistor 2351. On the other hand, the hydrogen in the insulator provided near the transistor 2352 and the transistor 2353 becomes one of the reasons for generating carriers in the oxide semiconductor. Therefore, the hydrogen sometimes causes a decrease in the reliability of the transistor 2352 and the transistor 2353. Therefore, when a transistor including an oxide semiconductor is provided on a transistor including a silicon-based semiconductor, an insulator 2380 having a function of blocking hydrogen is preferably provided between these transistors. When hydrogen is enclosed under the insulator 2380, the reliability of the transistor 2351 can be improved. Furthermore, the diffusion of hydrogen from the layer below the insulator 2380 to the layer above the insulator 2380 can be suppressed, so the reliability of the transistor 2352 and the transistor 2353 can be improved. The conductors 2390a, 2390b, and 2390e can suppress the diffusion of hydrogen into an overlying layer through a via hole formed in the insulator 2380, thereby improving the reliability of the transistors 2352 and 2353 and the like.

[0731] exist Figure 52 In the cross-sectional view of FIG, the photodiode 2360 in the layer 2310 and the transistor in the layer 2330 can be formed so as to overlap each other. Therefore, the integration degree of the pixel can be improved. In other words, the resolution of the imaging device can be improved.

[0732] The imaging device can be partially or entirely curved. By curving the imaging device, field curvature or astigmatism can be reduced. This can facilitate the optical design of lenses used in combination with the imaging device. For example, the number of lenses used for aberration correction can be reduced, thereby miniaturizing or lightweighting electronic devices using the imaging device. Furthermore, the quality of captured images can be improved.

[0733] The structure described in this embodiment can be combined with the structures described in other embodiment modes as appropriate.

[0734] Implementation 10

[0735] In this embodiment, a semiconductor wafer, a chip, and an electronic component according to one embodiment of the present invention are described.

[0736] <Semiconductor wafers and chips>

[0737] Figure 53AFIG5 is a top view of a substrate 5711 before dicing. A semiconductor substrate (also referred to as a "semiconductor wafer") can be used as the substrate 5711, for example. Multiple circuit regions 5712 are provided on the substrate 5711. A semiconductor device, a CPU, an RF tag, an image sensor, or the like, according to an embodiment of the present invention, can be provided in the circuit regions 5712.

[0738] Each of the plurality of circuit regions 5712 is surrounded by a separation region 5713. Separation lines (also referred to as "cutting lines") 5714 are provided at positions overlapping the separation regions 5713. The substrate 5711 can be cut along the separation lines 5714 into chips 5715 including the circuit regions 5712. Figure 53B This is an enlarged view of chip 5715.

[0739] Alternatively, a conductive layer or semiconductor layer may be provided in the separation region 5713. Providing a conductive layer or semiconductor layer in the separation region 5713 mitigates ESD that may be generated during the cutting process, thereby preventing a decrease in the yield of the cutting process. Generally, to cool the substrate, remove shavings, and prevent static electricity, the cutting process is performed while pure water, for example, containing dissolved carbon dioxide gas to reduce its resistivity, is passed through the cutting portion. Providing a conductive layer or semiconductor layer in the separation region 5713 reduces the amount of pure water used. Consequently, the production cost of semiconductor devices can be reduced. This allows for the efficient manufacture of semiconductor devices.

[0740] A material having a band gap of 2.5 eV to 4.2 eV, preferably 2.7 eV to 3.5 eV, is preferably used as the semiconductor layer provided in the isolation region 5713. By using such a material, the accumulated charge can be gradually released, thereby suppressing the rapid movement of charge due to ESD and making electrostatic damage less likely to occur.

[0741] <Electronic Components>

[0742] Figure 54A and Figure 54B This example shows an electronic component using a chip 5715. Note that electronic components are also called semiconductor packages or IC packages. Electronic components have various specifications and names depending on the terminal extraction direction and terminal shape.

[0743] In an assembly step (latter step), the semiconductor device described in the above embodiment is combined with members other than the semiconductor device to complete an electronic component.

[0744] Reference Figure 54AThe subsequent process is described with reference to a flowchart. After the element substrate including the semiconductor device described in the above embodiment is completed in the previous process, a backside grinding process (step S5721) is performed to grind the backside of the element substrate (the side where the semiconductor device, etc., is not formed). By thinning the element substrate through grinding, warping of the element substrate can be reduced, and the size of the electronic component can be reduced.

[0745] Next, in the dicing step (step S5722), the component substrate is divided into multiple chips (chips 5715). Then, in the die bonding step (step S5723), the diced chips are picked up and bonded to the lead frame. To bond the chip and lead frame in the die bonding step, an appropriate method is selected depending on the product, such as bonding with resin or bonding with tape. Alternatively, the chip can be bonded to the interposer substrate instead of the lead frame.

[0746] Next, a wire bonding step (step S5724) is performed to electrically connect the leads of the lead frame to the electrodes on the chip using fine metal wires. Silver wires or gold wires can be used as the fine metal wires. Ball bonding or wedge bonding can be used for wire bonding.

[0747] A sealing step (molding step) is performed to seal the wire-bonded chip with epoxy resin or the like (step S5725). The sealing step fills the interior of the electronic component with resin, thereby protecting the circuitry mounted inside the chip and the metal wires connecting the chip to the leads from mechanical forces and reducing degradation of characteristics (reduction in reliability) caused by moisture and dust.

[0748] Next, in the lead plating process (step S5726), the leads of the lead frame are plated. This plating prevents rust on the leads, allowing for more reliable soldering when the chip is mounted on a printed circuit board in the subsequent process. Then, in the forming process (step S5727), the leads are cut and formed.

[0749] Next, a printing step is performed on the package surface (step S5728). After an inspection step (step S5729) to check the appearance and shape and the presence of any operational malfunctions, the electronic component is completed.

[0750] Figure 54BThis is a three-dimensional schematic diagram of the completed electronic component. Figure 54B It is a perspective schematic diagram showing a quad flat package (QFP) as an example of an electronic component. Figure 54B The electronic component 5750 includes a lead 5755 and a semiconductor device 5753. As the semiconductor device 5753, the semiconductor device described in the above embodiment mode can be used.

[0751] Figure 54B The electronic components 5750 are mounted on, for example, a printed circuit board 5752. Multiple electronic components 5750 that are combined and electrically connected to each other are placed on the printed circuit board 5752, thereby completing a substrate (circuit board 5754) on which electronic components are mounted. The completed circuit board 5754 is installed in an electronic device or the like.

[0752] The structure described in this embodiment can be combined with the structures described in other embodiment modes as appropriate.

[0753] Implementation 11

[0754] In this embodiment, an electronic device including a transistor and the like according to one embodiment of the present invention is described.

[0755] <Electronic equipment>

[0756] The semiconductor device according to one embodiment of the present invention can be used in a display device, a personal computer, or an image reproduction device equipped with a recording medium (typically, a device that reproduces the contents of a recording medium such as a digital versatile disc (DVD) and has a display capable of displaying the reproduced image). Other examples of electronic devices in which the semiconductor device according to one embodiment of the present invention can be installed include mobile phones, game consoles including portable game consoles, portable data terminals, e-book readers, imaging devices such as video cameras and digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (e.g., car audio systems, digital audio players), copiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), and vending machines. Figures 55A to 55F Specific examples of these electronic devices are shown.

[0757] Figure 55A 1 shows a portable game console including a housing 1901, a housing 1902, a display portion 1903, a display portion 1904, a microphone 1905, a speaker 1906, operation keys 1907, a stylus pen 1908, and the like. Figure 55A The portable game console includes two display portions 1903 and 1904, but the number of display portions included in the portable game console is not limited thereto.

[0758] Figure 55B A portable data terminal is shown, which includes a first housing 1911, a second housing 1912, a first display unit 1913, a second display unit 1914, a connector 1915, and operation keys 1916. The first display unit 1913 is disposed within the first housing 1911, while the second display unit 1914 is disposed within the second housing 1912. The first and second housings 1911 and 1912 are connected by a connector 1915, and the angle between the first and second housings 1911 and 1912 can be adjusted via the connector 1915. The image displayed on the first display unit 1913 can also be switched based on the angle between the first and second housings 1911 and 1912 via the connector 1915. Alternatively, a display device with a location input function can be used as at least one of the first and second display units 1913 and 1914. Furthermore, the location input function can be added by providing a touch screen in the display device. Alternatively, the location input function can be added by providing a photoelectric conversion element, also known as a photosensor, in the pixel portion of the display device.

[0759] Figure 55C The notebook personal computer is shown and includes a housing 1921 , a display portion 1922 , a keyboard 1923 , a pointing device 1924 , and the like.

[0760] Figure 55D An electric refrigerator-freezer is shown, which includes a frame 1931, a refrigerator door 1932, a freezer door 1933, etc.

[0761] Figure 55E The video camera is shown, which includes a first housing 1941, a second housing 1942, a display unit 1943, operating keys 1944, a lens 1945, a connector 1946, and the like. The operating keys 1944 and the lens 1945 are disposed in the first housing 1941, while the display unit 1943 is disposed in the second housing 1942. The first housing 1941 and the second housing 1942 are connected by a connector 1946, and the angle between the first housing 1941 and the second housing 1942 can be changed via the connector 1946. The image displayed on the display unit 1943 can also be switched according to the angle between the first housing 1941 and the second housing 1942 via the connector 1946.

[0762] Figure 55F A car is shown, which includes a body 1951, wheels 1952, a dashboard 1953, lights 1954, etc.

[0763] In this embodiment, one embodiment of the present invention is described. Note that one embodiment of the present invention is not limited to this. In other words, since various aspects of the present invention are described in this embodiment, one embodiment of the present invention is not limited to a specific embodiment. For example, as one embodiment of the present invention, an example is shown in which an oxide semiconductor is included in the channel formation region, source region, or drain region of a transistor, but one embodiment of the present invention is not limited to this example. Alternatively, depending on circumstances or conditions, various transistors, channel formation regions of transistors, or source regions or drain regions of transistors in one embodiment of the present invention may also include various semiconductors. Depending on circumstances or conditions, at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors may also be included in various transistors, channel formation regions of transistors, or source regions or drain regions of transistors in one embodiment of the present invention. Alternatively, for example, depending on circumstances or conditions, an oxide semiconductor may not necessarily be included in various transistors, channel formation regions of transistors, or source regions or drain regions of transistors in one embodiment of the present invention.

[0764] The structure described in this embodiment can be combined with the structures described in other embodiment modes as appropriate.

[0765] Example 1

[0766] In this example, the results of elemental analysis and crystallinity evaluation of an In—Ga—Zn oxide film (hereinafter referred to as an IGZO film) formed by the method described in the above embodiment will be described.

[0767] The IGZO film of Sample 1A in this example was deposited on a glass substrate to a thickness of 100 nm by sputtering using an In-Ga-Zn oxide target (atomic ratio of In:Ga:Zn = 4:2:4.1). The IGZO film was deposited under the following conditions: an atmosphere containing 180 sccm of argon and 20 sccm of oxygen, with the pressure controlled to 0.6 Pa, the substrate temperature at room temperature, and an applied AC power of 2.5 kW.

[0768] Energy dispersive X-ray spectroscopy (EDX) was used to measure the cross-section of the IGZO film of Sample 1A. EDX measurements were performed using a JEM-ARM200F atomic resolution electron microscope manufactured by JEOL Ltd., with an accelerating voltage of 200 kV and an electron beam diameter of approximately 0.1 nm. A JED-2300T energy dispersive X-ray analyzer manufactured by JEOL Ltd. was used as the elemental analyzer. A silicon drift detector was used to detect the X-rays emitted from Sample 1A.

[0769] In EDX measurement, an electron beam is irradiated at each point in the target analysis area of ​​a sample. The energy and frequency of the sample's characteristic X-rays generated during this process are measured to obtain an EDX spectrum at each point. In this example, the peaks in the EDX spectrum at each point are derived from electron transfers in In, Ga, Zn, and O atoms, and the ratios of each atom at each point are calculated. By performing these steps on the target analysis area of ​​sample 1A, an EDX surface analysis image showing the distribution of the ratios of each atom can be obtained.

[0770] Figure 56 An EDX surface analysis image of In atoms in the cross section of the IGZO film of sample 1A is shown. Figure 56 The EDX surface analysis image shows the ratio of In atoms [atomic %] at each point of the IGZO film. Figure 56 The darker areas have lower In atomic ratios, with the lowest ratio being 10.85 atomic%. Figure 56 The lighter-colored areas in the image have a higher In atomic ratio, with the highest ratio being 25.21 atomic%.

[0771] Figure 56 The EDX surface analysis image shows a light-dark distribution, which indicates the segregation of In atoms in the cross section of the IGZO film. Here, there are more roughly circular or elliptical regions in the lighter-colored region in the EDX surface analysis image. In addition, a region formed by connecting a plurality of roughly circular or elliptical regions is observed. In other words, the roughly circular or elliptical regions are formed in a mesh shape. As described above, the lighter-colored region is a region where In is present at a high concentration, which corresponds to the region A shown in the above embodiment. Note that region A is not large enough to span across or across the analysis object region, and is surrounded by a darker-colored region (corresponding to the region B shown in the above embodiment) to form an island shape. A region with an intermediate color depth is also formed between region A and region B, and in a certain part, the interface between region A and region B is unclear. Most of the roughly circular or elliptical regions A have a diameter in the range of 0.1 nm to 5 nm.

[0772] As described above, the IGZO film of Sample 1A is a composite oxide semiconductor formed with an In-rich region A and an In-poor region B. Region A contributes to the transistor's on-state current and field-effect mobility, while region B contributes to the transistor's switching characteristics. Therefore, using this composite oxide semiconductor enables the manufacture of a transistor with excellent electrical characteristics.

[0773] Furthermore, since the region A is formed in an island shape and is surrounded by the region B, an increase in off-state current caused by the source and drain of the transistor being connected through the region A can be suppressed.

[0774] Unlike the IGZO film of Sample 1A, the IGZO film of Sample 1B was formed in an atmosphere containing 140 sccm of argon gas and 60 sccm of oxygen gas at a substrate temperature of 170° C. Note that the other film formation conditions for the IGZO film of Sample 1B were the same as those for the IGZO film of Sample 1A.

[0775] Bright-field scanning transmission electron microscopy (BF-STEM) images of cross sections of samples 1A and 1B were taken at a magnification of 2,000,000 times. Figure 57A The BF-STEM image of sample 1A is shown. Figure 57B A BF-STEM image of sample 1B is shown.

[0776] like Figure 57A As shown in FIG, although its area is narrow, a layered crystal part is formed in the IGZO film of sample 1A, and a crystal part with c-axis orientation is observed. Figure 57B The IGZO film of Sample 1B shown here shows a wider layered crystal portion than that of Sample 1A. These layered crystal portions were also observed in the IGZO film of Sample 1A, which shows the segregation of In atoms. This also suggests that increasing the oxygen flow rate and substrate temperature during IGZO film formation can improve the crystallinity of IGZO films.

[0777] More samples were fabricated by forming IGZO films at varying oxygen flow rates and substrate temperatures, and their crystallinity was evaluated. The IGZO film formation conditions for these samples were as follows: oxygen flow ratios of 10% (20 sccm oxygen, 180 sccm argon), 30% (60 sccm oxygen, 140 sccm argon), 50% (100 sccm oxygen, 100 sccm argon), 70% (140 sccm oxygen, 60 sccm argon), or 100% (200 sccm oxygen); and substrate temperatures of room temperature, 130°C, or 170°C. Other film formation conditions for each sample were the same as those for Sample 1A.

[0778] The ...

Claims

1. A semiconductor device comprising: A transistor comprising: gate electrode; a gate insulating film; and an oxide semiconductor layer containing indium, element M and zinc, in, The element M is one or more of Al, Ga, Y and Sn, The oxide semiconductor layer includes a first region and a plurality of second regions, The ratio of the number of atoms of In to the element M in each of the plurality of second regions is greater than the ratio of the number of atoms of In to the element M in the first region, Each of the plurality of second areas is surrounded by the first area, The first region is provided between each of the plurality of second regions and in contact with each of the second regions, and one of the plurality of second regions and another of the plurality of second regions are provided to be separated from each other.

2. A semiconductor device comprising: A transistor comprising: gate electrode; a gate insulating film; and an oxide semiconductor layer containing indium, element M and zinc, in, The element M is one or more of Al, Ga, Y and Sn, The oxide semiconductor layer includes a first region and a plurality of second regions, The ratio of the number of atoms of In to the element M in each of the plurality of second regions is greater than the ratio of the number of atoms of In to the element M in the first region, The first region and the plurality of second regions are mixed, One of the plurality of second regions and another one of the plurality of second regions overlap with the first region provided therebetween, Furthermore, the one of the plurality of second regions and the other of the plurality of second regions do not contact each other.

3. A semiconductor device comprising: A transistor comprising: gate electrode; a gate insulating film; and an oxide semiconductor layer containing indium, element M and zinc, in, The element M is one or more of Al, Ga, Y and Sn, The oxide semiconductor layer includes a first region and a plurality of second regions, The ratio of the number of atoms of In to the element M in each of the plurality of second regions is greater than the ratio of the number of atoms of In to the element M in the first region, The first region and the plurality of second regions are mixed, One of the plurality of second regions is connected to another of the plurality of second regions, A second region of the plurality of second regions that is different from the one of the plurality of second regions and the other of the plurality of second regions is not connected to the one of the plurality of second regions and the other of the plurality of second regions, And, the first region is provided between and in contact with the one of the plurality of second regions and the second region different from the one of the plurality of second regions and the other of the plurality of second regions.

4. The semiconductor device according to any one of claims 1 to 3, wherein The atomic ratio of indium to the element M and zinc (In:M:Zn) in the oxide semiconductor layer is 5:1:

6.

5. The semiconductor device according to any one of claims 1 to 3, wherein The atomic ratio of indium to the element M and zinc (In:M:Zn) in the first region is 4:2:

3.

6. The semiconductor device according to any one of claims 1 to 3, wherein The atomic ratio of indium to the element M and zinc (In:M:Zn) in the second region is 2:0:

3.

7. The semiconductor device according to any one of claims 1 to 3, wherein The atomic ratio of indium to the element M and zinc (In:M:Zn) in the oxide semiconductor layer is 4:2:

3.

8. The semiconductor device according to any one of claims 1 to 3, wherein The atomic ratio of indium to the element M and zinc (In:M:Zn) in the first region is 1:1:

1.

9. The semiconductor device according to any one of claims 1 to 3, wherein The atomic ratio of indium to the element M and zinc (In:M:Zn) in the second region is 2:0:

1.

10. The semiconductor device according to any one of claims 1 to 3, wherein The first region is non-single crystal, Furthermore, the second region is non-single crystal.

11. The semiconductor device according to any one of claims 1 to 3, wherein The second region has a higher electrical conductivity than the first region.

12. The semiconductor device according to any one of claims 1 to 3, wherein The atomic number ratio of In to the element M in the second region is 1.1 to 10 times higher than the atomic number ratio of In to the element M in the first region.

13. The semiconductor device according to any one of claims 1 to 3, wherein The atomic number ratio of In to the element M in the second region is 2 to 10 times higher than the atomic number ratio of In to the element M in the first region.

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