Analog front-end chip, analog front-end circuit and signal processing device

Abstract

This application provides an analog front-end chip, an analog front-end circuit, and a signal processing device, including: a first operational amplifier module for amplitude adjustment of an electrical signal connected to a first input impedance network; and a second operational amplifier module for amplitude adjustment of an electrical signal connected to a second input impedance network. The second input impedance network has a different impedance than the first input impedance network. The first and second operational amplifier modules are integrated within the same chip. This solves the problem of parasitic capacitance and resistance sensitivity caused by external chip interconnections; avoids the influence of process deviations on the bandwidth of the signal transmission path; and easily achieves high bandwidth performance for the analog front-end circuit. Simultaneously, since all critical signal paths are within a single chip, the temperature characteristics are consistent, resulting in minimal system temperature drift.

Description

Technical Field

[0001] This invention relates to the field of test and measurement technology, and in particular to an analog front-end chip, an analog front-end circuit, and a signal processing device. Background Technology

[0002] Currently, various signal processing devices, such as oscilloscopes and data acquisition cards, can process and analyze the signals they receive. Typically, signal processing devices include analog front-end circuitry. The main function of the analog front-end circuitry is to condition the amplitude of the input analog signal, that is, to condition a signal with a large dynamic range of input to a signal with a fixed output range for use by the next stage circuit, such as the analog-to-digital converter (ADC) located at the back end. Analog front-end circuitry generally needs to have technical specifications such as high stability, large bandwidth, and in-band flatness. In addition, it also needs to have the following two obvious characteristics: 1) a wide range of variable gain, and stability across the entire gain range; 2) variable input impedance, supporting both high and low input impedance. Considering the simplicity and convenience of system implementation, the analog front-end circuitry should ideally minimize the use of peripheral devices when building the system.

[0003] However, analog front-end circuits contain numerous components, and signals propagate through the circuit in a voltage manner, placing high demands on the signal propagation path and the performance of each component. Long signal transmission lines are highly sensitive to parasitic resistance and capacitance, and process variations can affect the bandwidth of the signal transmission path. Furthermore, inconsistent temperature characteristics among individual chips can lead to poor overall system temperature drift. Summary of the Invention

[0004] In view of the above, this application provides an analog front-end chip, an analog front-end circuit, and a signal processing device to solve at least one problem existing in the background art.

[0005] In a first aspect, one embodiment of this application provides an analog front-end chip, comprising:

[0006] The first operational amplifier module is used to adjust the amplitude of the electrical signal on the path connected to the first input impedance network;

[0007] The second operational amplifier module is used to adjust the amplitude of the electrical signal on the path connected to the second input impedance network; the impedance of the second input impedance network is different from that of the first input impedance network.

[0008] The first operational amplifier module and the second operational amplifier module are integrated into the same chip.

[0009] In conjunction with the first aspect of this application, in an alternative embodiment, a multiplexer is further included, wherein,

[0010] The multiplexer includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the output terminal of the first operational amplifier module, and the second input terminal is connected to the output terminal of the second operational amplifier module.

[0011] The multiplexer is used to select between an electrical signal received through the first input terminal and an electrical signal received through the second input terminal, and outputs the selected electrical signal through the output terminal.

[0012] The multiplexer is integrated with the first operational amplifier module and the second operational amplifier module in the same chip.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, a third operational amplification module is further included, wherein,

[0014] The input terminal of the third operational amplifier module is connected to the output terminal of the multiplexer, and is used to adjust the amplitude of the electrical signal received from the output terminal of the multiplexer.

[0015] The third operational amplifier module is integrated into the same chip as the first operational amplifier module and the second operational amplifier module.

[0016] In conjunction with the first aspect of this application, in an optional embodiment, the first operational amplifier module includes an input buffer, a first amplifier, and a second amplifier; wherein,

[0017] The input terminal of the input buffer is used to receive electrical signals on the path connected to the first input impedance network;

[0018] The first amplifier and the second amplifier are connected in parallel between the output of the input buffer and the output of the first operational amplifier module.

[0019] In conjunction with the first aspect of this application, in an optional embodiment, the second operational amplifier module includes a variable gain amplifier; wherein,

[0020] The variable gain amplifier is connected between the output of the second input impedance network and the output of the second operational amplifier module.

[0021] In conjunction with the first aspect of this application, in an optional embodiment, it further includes a first input impedance network portion and / or a second input impedance network portion integrated within the same chip as the first operational amplifier module and the second operational amplifier module, wherein,

[0022] The first input impedance network portion is a part of the first input impedance network, and the second input impedance network portion is a part of the second input impedance network;

[0023] The input terminal of the first operational amplifier module is connected to the output terminal of the first input impedance network section, and the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network section.

[0024] In conjunction with a first aspect of this application, the impedance of the first input impedance network is lower than the impedance of the second input impedance network; the first input impedance network is disposed outside the analog front-end chip;

[0025] The analog front-end chip also includes a second input impedance network section integrated within the same chip as the second operational amplifier module; the second input impedance network section is a part of the second input impedance network; the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network section.

[0026] Secondly, embodiments of this application provide an analog front-end circuit, including: an analog front-end chip as described in any one of the first aspects above.

[0027] In conjunction with a second aspect of this application, in an optional embodiment, a relay is also included, wherein,

[0028] The relay is located at the front end of the first input impedance network and the second input impedance network, and is used to selectively connect to a path connected to the first input impedance network or a path connected to the second input impedance network.

[0029] Thirdly, embodiments of this application provide a signal processing apparatus, including: an analog front-end circuit as described in any one of the second aspects above.

[0030] The analog front-end chip, analog front-end circuit, and signal processing device provided in this application include: a first operational amplifier module for amplitude adjustment of an electrical signal connected to a first input impedance network; a second operational amplifier module for amplitude adjustment of an electrical signal connected to a second input impedance network; the second input impedance network has a different impedance than the first input impedance network; wherein the first operational amplifier module and the second operational amplifier module are integrated in the same chip; thus, the problem of parasitic capacitance and parasitic resistance sensitivity caused by external chip interconnections is solved; the first operational amplifier module and the second operational amplifier module are formed under the same process conditions, avoiding the influence of process deviations and other factors on the bandwidth of the signal transmission path, and easily achieving high bandwidth performance of the analog front-end circuit; at the same time, the key signal paths are all in one chip, with consistent temperature characteristics and small system temperature drift.

[0031] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0033] Figure 1 This is a schematic diagram of the structure of an oscilloscope;

[0034] Figure 2 This is a schematic diagram of the structure of a simulated front-end chip in one embodiment of this application;

[0035] Figure 3 This is a schematic diagram of the structure of the simulated front-end chip in another embodiment of this application;

[0036] Figure 4 This is a schematic diagram of the structure of the simulated front-end chip in another embodiment of this application;

[0037] Figure 5 This is a schematic diagram of the structure of the simulated front-end chip in another embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the structure of the simulated front-end circuit in a specific example of this application;

[0039] Figure 7 This is a schematic diagram of the structure of the simulated front-end circuit in another specific example of this application. Detailed Implementation

[0040] To make the technical solutions and beneficial effects of the present invention more apparent and understandable, the technical solutions in the embodiments of this application are clearly and completely described below by listing specific examples. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor. When “first” is described, it does not imply the necessary presence of a “second”; and when “second” is discussed, it does not imply the necessary presence of a first element, component, region, layer, or portion. As used herein, the singular forms “a,” “an,” and “the” may also be intended to include the plural forms unless the context clearly indicates otherwise. “A plurality” means two or more, unless otherwise explicitly specified. It should also be understood that the term “comprising,” when used in this specification, identifies the presence of the stated feature but does not exclude the presence or addition of one or more other features. As used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] This invention provides an analog front-end chip capable of adjusting the gain of an input signal to varying degrees. This analog front-end chip can be applied to an analog front-end circuit, which can be integrated into a signal processing device. This signal processing device includes, but is not limited to, an oscilloscope. Specifically, the oscilloscope is, for example, a digital oscilloscope.

[0044] Next, using an oscilloscope as an example, we will introduce the application of analog front-end circuits in signal processing devices. Please refer to [link / reference needed]. Figure 1 , Figure 1 This is a schematic diagram of an oscilloscope. An oscilloscope typically includes multiple analog front-end circuits, such as analog front-end circuit 1, analog front-end circuit 2, ..., analog front-end circuit n in the diagram. The analog front-end circuits are responsible for conditioning the input signal data to a suitable size before sending it to the acquisition module. The acquisition module mainly includes an analog-to-digital converter chip and a clock module (not shown in the diagram) that provides the sampling clock. It converts the input analog signal data into digital signal data. The digital signal data is output to the data processing module for processing, waveform reconstruction, and display on the screen. The communication interface is responsible for communicating with the outside world, such as USB, Ethernet, serial port, etc.

[0045] Next, please refer to Figure 2 One embodiment of this application provides an analog front-end chip, including: a first operational amplifier module for amplitude adjustment of an electrical signal on a path connected to a first input impedance network; a second operational amplifier module for amplitude adjustment of an electrical signal on a path connected to a second input impedance network; the second input impedance network has a different impedance than the first input impedance network; wherein the first operational amplifier module and the second operational amplifier module are integrated in the same chip.

[0046] It is understood that the specific implementation of the first and second operational amplifier modules is related to their respective functions, and those skilled in the art can set them according to the actual situation; no specific limitations are made here. The first and second operational amplifier modules are integrated into the same chip; one possibility is that this chip is an analog front-end chip; another possibility is that the analog front-end chip may include a chip integrating the first and second operational amplifier modules, as well as other components.

[0047] To achieve variable input impedance, analog front-end circuits typically have two input resistance modes: low-impedance input (generally 50Ω or 75Ω) and high-impedance input (generally 1MΩ). These two input resistance modes require two input impedance networks with different impedances, switched via an external relay. To achieve a wide range of variable gain and system stability across the entire gain range, a typical approach uses two operational amplifier modules (hereinafter referred to as "AOP1 group" and "AOP2 group"), specifically multiple AOP chips (amplifier chips) to achieve the large gain variation range. In other words, AOP1 group and AOP2 group are actually generic terms; they could be multiple AOP chips connected in series, multiple VGA chips (variable gain amplifiers) connected in series, or even multiple AOP chips and multiple VGA chips connected in series and parallel. The reason a single general-purpose op-amp chip or a single VGA chip cannot be used is that a single chip is unlikely to achieve a large gain variation range; and in general applications, oscilloscope analog front-ends may require a large dynamic range of continuously adjustable gain from 0.005 to 400 times. Secondly, within such a wide range of gain variations, it is difficult for a single chip to maintain stability. This design would make the system more complex. Finally, because multiple discrete chips are used and configured with different gain stages to achieve the gain, the inconsistent temperature characteristics of each chip will lead to poor overall system temperature drift. In addition, the signal path constantly traverses from on-chip to off-chip, making it susceptible to the effects of parasitic resistance and capacitance on the chip package and PCB, making it difficult to achieve high bandwidth.

[0048] This embodiment integrates the first operational amplifier module and the second operational amplifier module into the same chip to form an analog front-end chip. This not only meets the gain requirements of the analog front-end circuit, but also solves the problem of parasitic capacitance and resistance sensitivity caused by external interconnections. The first operational amplifier module and the second operational amplifier module are formed under the same process conditions, avoiding the influence of process deviations on the bandwidth of the signal transmission path, and making it easy to achieve high bandwidth performance of the analog front-end circuit. At the same time, the key signal paths are all in one chip, with consistent temperature characteristics and small system temperature drift.

[0049] Here, the second input impedance network has a different impedance than the first input impedance network. Specifically, one of them can be a high input impedance network and the other can be a low input impedance network. For example, a high input impedance network is a 1MΩ input impedance network; for example, a low input impedance network is a 50Ω or 75Ω input impedance network (the following explanation will use a 50Ω input impedance network as an example).

[0050] As an alternative implementation, the analog front-end chip may also include a multiplexer. Please refer to [link / reference]. Figure 3 The multiplexer includes a first input terminal I31, a second input terminal I32, and an output terminal O3. The first input terminal I31 is connected to the output terminal O1 of the first operational amplifier module, and the second input terminal I32 is connected to the output terminal O2 of the second operational amplifier module. The multiplexer is used to select between the electrical signal received through the first input terminal and the electrical signal received through the second input terminal, and outputs the selected electrical signal through the output terminal O3. The multiplexer, the first operational amplifier module, and the second operational amplifier module are integrated into the same chip.

[0051] Understandably, for analog front-end circuits using discrete chips, it's difficult to create parallel output paths with 1MΩ and 50Ω input impedance networks, followed by multiplexing to select the output. This is because the output impedances of discrete components often differ. Connecting their outputs to the input of a multiplexer would result in inconsistent input impedances received by the multiplexer, making it difficult for the multiplexer to perfectly match the inputs of various components. This compromises the high-speed, high-precision performance required by the analog front-end, easily leading to signal distortion. Therefore, relays are typically used after the first and second operational amplifier modules, or between them, to switch between the two paths. However, in this configuration, the relay is positioned in the middle of the critical signal transmission path. The relay needs to be high-speed and low-leakage; otherwise, it will negatively impact signal transmission. This undoubtedly places higher demands on the selection of relays, increasing costs.

[0052] In this embodiment, since the first operational amplifier module and the second operational amplifier module are integrated in parallel within the same chip, a multiplexer can be further integrated within this chip. The signal enters the multiplexer, is selected by the multiplexer, and then continues to be output to the next stage. This results in relatively small parasitic capacitance, parasitic inductance, and parasitic resistance caused by wiring, making it easier to achieve high bandwidth performance in the analog front-end.

[0053] As an optional implementation, the analog front-end chip may also include a third operational amplifier module. Please refer to [reference needed]. Figure 4The input terminal I41 of the third operational amplifier module is connected to the output terminal O3 of the multiplexer and is used to adjust the amplitude of the electrical signal received from the output terminal O3 of the multiplexer. The third operational amplifier module is integrated with the first operational amplifier module and the second operational amplifier module in the same chip. The third operational amplifier module may be referred to as "AOP3 group" in the following text.

[0054] Thus, the input signal undergoes the first stage of amplitude conditioning via either AOP1 or AOP2. Afterward, the two input signals enter a multiplexer, are selected, and then enter AOP3 for the second stage of amplitude conditioning. By employing at least two stages of amplitude conditioning, the problems of wide-range continuous gain adjustment, system stability across the entire gain range, and poor system temperature characteristics are better addressed. Furthermore, by setting at least two operational amplifier modules (the first stage being AOP1 and AOP2 connected to each input impedance network, and the second stage being AOP3), it is beneficial to flexibly design each gain stage in the chip according to actual gain requirements, maximizing the multiplexing rate of the gain stages. Moreover, the gain distribution of each input impedance network does not affect each other. Finally, the gain of each gain stage can be flexibly implemented using AOP or VGA, and the gain combination is not affected by the stability of isolated chips, achieving a wide range of variable gain while ensuring the stability of each stage. The solution provided in this embodiment can theoretically achieve the maximum adjustable gain range using a single signal path.

[0055] It should be understood that the solution proposed in this application is not limited to this; of course, multiple stages of variable gain operational amplifiers can also be integrated on the same chip. Furthermore, after the final stage of amplitude adjustment, the signal is output from the analog front-end chip.

[0056] By integrating all gain stages into the same chip, the interconnections between the gain stages are short. At the same time, the multiplexer is integrated on-chip, which reduces the parasitic capacitance, parasitic inductance, and parasitic resistance caused by interconnections. This makes it easier to achieve high bandwidth performance in the analog front end and improves the frequency response.

[0057] The specific implementation of the first, second, and third operational amplifier modules is related to their respective functions, and those skilled in the art can flexibly configure them according to the actual situation. For example... Figure 6As shown, the first, second, and third operational amplifier modules can be multiple AOP chips connected in series, or multiple VGA chips connected in series (VGA1, VGA2...VGAn in the figure), or at least one AOP chip and at least one VGA chip connected in series and parallel. Of course, at least one of the first, second, and third operational amplifier modules can also include one AOP chip or one VGA chip. Therefore, it can be a single stage or form a multi-stage gain combination. The specific structures of the first, second, and third operational amplifier modules can be the same or different.

[0058] The following provides an exemplary description of the structures of the first operational amplifier module, the second operational amplifier module, and the third operational amplifier module, using typical examples.

[0059] Please refer to Figure 7 As shown in the figure, the first operational amplifier module includes an input buffer, a first amplifier, and a second amplifier.

[0060] The input buffer is shown as AOP1_1 in the diagram, and AOP1_1, as an input buffer, mainly works in conjunction with the external first input impedance network. Specifically, the input terminal of the input buffer is used to receive electrical signals on the path connected to the first input impedance network.

[0061] Please refer to AOP1_2 in the diagram for the first amplifier and AOP1_3 for the second amplifier. It can be seen that AOP1_2 and AOP1_3 are connected in parallel between the output of the input buffer and the output of the first operational amplifier module. Specifically, the inputs of AOP1_2 and AOP1_3 are connected together, both connected to the output of the input buffer; the outputs of AOP1_2 and AOP1_3 are connected together, both connected to the input of the multiplexer (MUX).

[0062] Furthermore, the first and second amplifiers each implement two different gains. Both the first and second amplifiers are selected via an enable signal, with only one amplifier operating at a time, thus achieving variable gain.

[0063] Please continue to refer to this. Figure 7 The second operational amplifier module may include a variable gain amplifier. Please refer to VGA2_1 in the figure for the variable gain amplifier. The variable gain amplifier is connected between the output of the second input impedance network and the output of the second operational amplifier module, specifically between the second input impedance network and the multiplexer. When the second operational amplifier module includes only the variable gain amplifier, the output of the variable gain amplifier serves as the output of the second operational amplifier module.

[0064] Optionally, the second operational amplifier module may include only a variable gain amplifier, which itself can provide variable gain functionality, enabling the second operational amplifier module to achieve locally adjustable gain.

[0065] like Figure 7 As shown, the analog front-end chip may also include an impedance calibration network integrated within the chip; please refer to the 1MΩ impedance calibration network in the figure for details. The second operational amplifier module can be connected to the impedance calibration network. Specifically, one input terminal of the variable gain amplifier is connected to the impedance calibration network, and the other input terminal is used to connect to the first input impedance network; the impedance calibration network is used to calibrate the second input impedance network. The impedance calibration network will be further explained in the description of the second input impedance network below.

[0066] Please continue to refer to this. Figure 7 The third operational amplifier module may include a third amplifier and an output buffer. The third amplifier, as shown in the diagram (VGA3_1), can be a variable gain amplifier; this third amplifier enables the second stage of variable gain. The output buffer, as shown in the diagram (AOP3_2), is used as an output buffer to improve front-end driving capability.

[0067] For example, both VGA2_1 and VGA3_1 have 3 adjustable gain levels, and AOP1_2, AOP1_3, and AOP3_1 can each achieve one gain. Therefore, this analog front-end chip can achieve 6 gain combinations for the first input impedance network path and 9 gain combinations for the second input impedance network path. This rich variety of gain combinations can meet the needs of analog front-end circuits.

[0068] Next, please refer to Figure 5 As an optional implementation, the analog front-end chip may further include a first input impedance network portion and / or a second input impedance network portion integrated within the same chip as the first operational amplifier module and the second operational amplifier module, wherein the first input impedance network portion is a part of the first input impedance network, and the second input impedance network portion is a part of the second input impedance network; the input terminal of the first operational amplifier module is connected to the output terminal of the first input impedance network portion, and the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network portion.

[0069] In this embodiment, as is readily understood, a portion of the first input impedance network is integrated inside the chip and a portion is located outside the chip, while the second input impedance network is located outside the chip; alternatively, a portion of the second input impedance network is integrated inside the chip and a portion is located outside the chip, while the first input impedance network is located outside the chip; or, both the first and second input impedance networks are partially integrated inside the chip and partially located outside the chip. This allows for more flexible achievement of optimal performance. In practical applications, the input impedance network portion integrated inside the chip can primarily integrate various programmable resistor and capacitor arrays, thereby calibrating the impedance of the entire network; input impedance calibration can be achieved through configuration registers, resulting in higher accuracy.

[0070] Optionally, in each input impedance network, the device values ​​of the components located outside the chip are greater than the device values ​​of the components located inside the chip; specifically, components with larger device values ​​are designed outside the chip, while components with relatively smaller device values ​​are designed inside the chip. Here, components with larger device values ​​include, for example, large capacitors, large resistors, and large inductors; specifically, resistors with resistance values ​​of MΩ or higher, capacitors with resistance values ​​of 100pF or higher, and inductors with resistance values ​​of tens of nH or higher. Conversely, the components with smaller device values, as described here, are considered in contrast.

[0071] Optionally, in each input impedance network, the absolute temperature drift of devices located outside the chip is smaller than that of devices located inside the chip; specifically, devices with smaller absolute temperature drift are designed outside the chip, while devices with relatively larger absolute temperature drift are designed inside the chip. Devices located outside the chip require higher accuracy than those located inside. Thus, devices located outside the chip have the characteristics of small absolute temperature drift, accurate absolute values, diverse packaging, and a wider range of selectable device values.

[0072] Optionally, in each input impedance network, the components located inside the chip are those that need to form feedback with the operational amplifier to function. Specifically, these are components closely related to high-frequency performance. In this way, the parasitic interconnections between the components and the operational amplifier are minimized, resulting in better high-frequency performance.

[0073] Optionally, in each input impedance network, the components located inside the chip must have the same temperature drift as the operational amplifier. This ensures that the component temperature drift matches the chip temperature drift, resulting in good temperature characteristics.

[0074] Optionally, the components located within the chip in each input impedance network can be adjustable. This allows the components to be implemented using programmable technology, facilitating easy adjustment.

[0075] In one specific implementation, the impedance of the first input impedance network is lower than the impedance of the second input impedance network; the first input impedance network is located outside the analog front-end chip; the analog front-end chip also includes a second input impedance network portion integrated with the second operational amplifier module within the same chip; the second input impedance network portion is a part of the second input impedance network; the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network portion. In other words, the low input impedance network is located outside the analog front-end chip, while the high input impedance network is partly located outside the analog front-end chip and partly located inside the analog front-end chip.

[0076] Taking a low-impedance input of 50Ω and a high-impedance input of 1MΩ as an example, the 50Ω resistor is placed externally on the chip primarily because it allows for accurate selection and has minimal error. The 1MΩ resistor, however, is divided into two parts: one external and one internal. This is because resistor accuracy is calculated as a percentage, and for the same level of precision, the error of a 1MΩ resistor will be significantly higher than that of a 50Ω resistor. Therefore, assuming the 1MΩ resistor is divided into two equal parts, with 500KΩ external and 500KΩ internal, and the internal 500KΩ is programmable with an adjustable range from 500KΩ to 600KΩ, it can be ensured that in multiple PCB applications or batches of PCB applications, the final overall input impedance is very close to 1MΩ, guaranteeing sufficient accuracy. Furthermore, since the 1MΩ signal transmission network requires matching and calibration, therefore, combined with... Figure 7 As shown, the 1MΩ input impedance calibration network can be integrated on-chip.

[0077] Based on the same inventive concept, one embodiment of this application also provides an analog front-end circuit, including: the analog front-end chip as described in the foregoing embodiments. Therefore, the analog front-end circuit provided in this embodiment includes the technical features of the analog front-end chip provided in the foregoing embodiments, and can achieve the technical effects of the analog front-end chip provided in the foregoing embodiments. Similarities can be found in the above description of the analog front-end chip provided in the foregoing embodiments, and will not be repeated here.

[0078] Next, please refer to Figure 6 As an optional implementation, the analog front-end circuit may further include a relay, wherein the relay is located in front of the first input impedance network and the second input impedance network, and is used to selectively connect a path connected to the first input impedance network or a path connected to the second input impedance network.

[0079] Understandably, for discrete component implementations, if the relay is placed between the AOP1 and AOP2 chip groups, it would be positioned in the middle of the critical signal transmission path, requiring the relay to possess high speed and low leakage current characteristics, necessitating the use of more expensive relays. However, in this embodiment, the relay responsible for impedance selection is located at the voltage signal input terminal. The relay's leakage characteristics and parasitic parameters have a smaller impact on the overall input impedance and the analog performance of the entire signal path. Furthermore, if necessary, corresponding compensation networks can be set up in the AOP1 and AOP2 groups to further offset the non-ideal factors introduced by the relay. Therefore, this embodiment has lower requirements for off-chip relays, a simpler design, and reduced costs.

[0080] Based on the same inventive concept, one embodiment of this application also provides a signal processing apparatus, including: the analog front-end circuit as described in the foregoing embodiments. Therefore, the signal processing apparatus provided in this embodiment includes the technical features of the analog front-end circuit and analog front-end chip provided in the foregoing embodiments, and can achieve the technical effects of the analog front-end chip provided in the foregoing embodiments. The similarities can be referred to the above description of the analog front-end chip provided in the foregoing embodiments, and will not be repeated here.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An oscilloscope analog front end chip, characterized by, include: The first operational amplifier module is used to adjust the amplitude of the electrical signal on the path connected to the first input impedance network; The second operational amplifier module is used to adjust the amplitude of the electrical signal on the path connected to the second input impedance network; the impedance of the second input impedance network is different from that of the first input impedance network. A multiplexer MUX includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the output terminal of the first operational amplifier module, and the second input terminal is connected to the output terminal of the second operational amplifier module. The multiplexer MUX is used to select between an electrical signal received through the first input terminal and an electrical signal received through the second input terminal, and outputs the selected electrical signal through the output terminal; The first operational amplifier module includes an input buffer, a first amplifier, and a second amplifier; the input terminal of the input buffer is used to receive electrical signals on a path connected to a first input impedance network; the first amplifier and the second amplifier are connected in parallel between the output terminal of the input buffer and the output terminal of the first operational amplifier module; the first amplifier and the second amplifier respectively implement two different gains; The multiplexer MUX is integrated with the first operational amplifier module and the second operational amplifier module in the same chip; It also includes an impedance calibration network integrated in the same chip as the second operational amplifier module. The impedance calibration network is connected to the second operational amplifier module and is used to perform impedance calibration on the second input impedance network.

2. The oscilloscope analog front end chip of claim 1, wherein, It also includes a third operational amplifier module, in which, The input terminal of the third operational amplifier module is connected to the output terminal of the multiplexer MUX, and is used to adjust the amplitude of the electrical signal received from the output terminal of the multiplexer MUX. The third operational amplifier module is integrated into the same chip as the first operational amplifier module and the second operational amplifier module.

3. The oscilloscope analog front end chip of claim 1, wherein, The second operational amplifier module includes a variable gain amplifier; wherein, The variable gain amplifier is connected between the output of the second input impedance network and the output of the second operational amplifier module.

4. The oscilloscope analog front-end chip according to claim 1, characterized in that, It also includes a first input impedance network portion and / or a second input impedance network portion integrated within the same chip as the first operational amplifier module and the second operational amplifier module, wherein, The first input impedance network portion is a part of the first input impedance network, and the second input impedance network portion is a part of the second input impedance network; The input terminal of the first operational amplifier module is connected to the output terminal of the first input impedance network section, and the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network section.

5. The oscilloscope analog front end chip of claim 1, wherein, The impedance of the first input impedance network is lower than the impedance of the second input impedance network; the first input impedance network is located outside the analog front-end chip; The analog front-end chip also includes a second input impedance network section integrated within the same chip as the second operational amplifier module; the second input impedance network section is a part of the second input impedance network; the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network section.

6. An oscilloscope analog front end circuit, comprising: The oscilloscope analog front-end chip as described in any one of claims 1-5.

7. The oscilloscope analog front end circuit of claim 6, wherein, It also includes relays, among which, The relay is located at the front end of the first input impedance network and the second input impedance network, and is used to selectively connect to a path connected to the first input impedance network or a path connected to the second input impedance network.

8. A signal processing device, characterized by include: The oscilloscope analog front-end circuit as described in claim 6 or 7.

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