A data synchronization method for multi-core heterogeneous systems

Abstract

The invention relates to the technical field of power master control chips, and specifically discloses an efficient multi-core heterogeneous system data synchronization method. The multi-core processor comprises a master core and at least two slave cores, each slave core establishes a communication channel with the master core respectively, and the message sending between the master core and the slave core adopts a balanced mode, and the balanced mode comprises: the master core and the slave core can both start message sending; the master core sends a data frame message to the slave core and starts frame counting and slave core response time timing; if the master core does not receive a slave core response message within a set time, it is considered that the communication is interrupted, and an internal communication interruption alarm flag is set; when the data frame count reaches a set number of frames, the master core needs to wait for a slave core response message before continuing to transmit; after receiving the data frame, the slave core starts frame counting and response time timing, and sends and receives response messages when the set number of frames are received cumulatively or the response time exceeds the set time. The invention can realize fast and efficient data synchronization between multi-cores, high communication efficiency and fast response.

Description

Technical Field

[0001] The present invention belongs to the technical field of power main control chips, and in particular relates to a multi-core heterogeneous system data synchronization method. Background Art

[0002] When developing embedded application systems, if a single processor cannot meet the system requirements, a common practice is to use two or more processors and assign part of the "miscellaneous work" to another low-end processor with "assistant" nature. However, the disadvantages of using two processors are also obvious, especially in terms of chip and PCB costs, system reliability and power consumption. With the development of chip technology and actual application needs, multi-core processors are currently widely used, which can be backward compatible and communicate efficiently in terms of architecture.

[0003] Fuxi main control chip uses multiple heterogeneous processors and MailBox for communication between heterogeneous processors. Based on this hardware foundation, the software can use AMP (asymmetric multi-processing) mode. AMP mode runs different operating systems or bare metal programs independently on multiple heterogeneous processors, and uses MailBox, shared memory and other mechanisms to achieve efficient communication and data synchronization, thereby achieving multi-core efficient collaborative work.

[0004] The application of multi-core processors in the power industry is generally divided into management core and protection core according to their functions. This is specifically reflected in the real-time requirements. Modules with high real-time requirements such as sampling, input and output, and protection logic operations are implemented in the protection core, while modules with low real-time requirements such as communication, interface display, and file management are implemented in the management core. Data synchronization between cores is particularly important and affects the stability and performance of the entire system.

[0005] The prior art uses a master-slave mode to transmit data in plain text. In a question-and-answer mode, the master core sequentially queries the slave cores to control data transmission. The master core is the starter station, which starts all message transmissions; the slave cores are slave stations, which can only transmit when they are queried. In addition, the master core runs the Linux system. When the master and slave communicate, the slave core responds quickly. The master-slave mode communication has a low communication rate and a slow response time. For large data transmissions such as wave recording files in distribution network devices, plain text byte stream transmission is adopted, which has a large number of transmission frames, a long time consumption, and low transmission efficiency. Therefore, a multi-core heterogeneous system data synchronization method is needed to improve the communication rate and response speed. Summary of the invention

[0006] The purpose of the present invention is to provide a multi-core heterogeneous system data synchronization method to solve the shortcomings of the existing master core running the Linux system, the slave core responding quickly during master-slave communication, the master-slave mode communication, the low communication rate and the slow response time.

[0007] To achieve the above object, the present invention provides a multi-core heterogeneous system data synchronization method, comprising: the multi-core processor comprises a master core and at least two slave cores, each slave core establishes a communication channel with the master core, and the message transmission between the master core and the slave core adopts a balanced mode, and the balanced mode includes:

[0008] Both the master core and the slave core can initiate message sending;

[0009] During downlink transmission, the master core sends a data frame message to the slave core and starts frame counting and slave core response time timing;

[0010] If the master core does not receive a response message from the slave core within the set time, it is considered that the communication is interrupted and the internal communication interruption alarm flag is set; when the data frame count reaches the set number of frames, the master core needs to wait for the slave core response message before it can continue transmission;

[0011] After receiving the data frame from the core, the frame counting and response time timing are started. When the set number of frames are received cumulatively or the response time exceeds the set time, a receive response message is sent.

[0012] As a preferred implementation, the main core actively transmitting data specifically includes the following steps:

[0013] S11, the main core sends data frames;

[0014] S12, after the main core sends the data frame, it starts the first timer and frame counting. If the number of frames obtained by the frame counting is greater than or equal to the frame number threshold, it goes to step S14; if the number of frames obtained by the frame counting is less than the frame number threshold, it goes to step S13;

[0015] S13, determining whether the main core continues to have subsequent frames, if yes, returning to steps S11-S12; otherwise, proceeding to step S14;

[0016] S14, determine whether the waiting response time for the main core to receive the response message exceeds the first threshold time. If it exceeds, a communication interruption alarm flag is set. If it does not exceed, the main core receives the response message, continues normal communication interaction, and returns to step S11.

[0017] As a preferred implementation, the first timing is 12 seconds.

[0018] As a preferred implementation, the frame number threshold is 8.

[0019] As a preferred implementation, the active transmission of data from the core specifically includes the following steps:

[0020] S21, the slave core receives the data frame sent by the master core;

[0021] S22, after receiving the data frame sent by the master core, the slave core starts the second timer and frame counting. If the number of frames obtained by the frame counting is greater than or equal to the frame number threshold, the process proceeds to step S24; if the number of frames obtained by the frame counting is less than the frame number threshold, the process proceeds to step S23;

[0022] S23, judging whether a subsequent frame is received within the third time period, if no subsequent frame is received, returning to steps S21-S22; if a subsequent frame is received, proceeding to step S24;

[0023] S24. The slave core sends a response message to the master core.

[0024] As a preferred implementation, the second timing is 10s timing.

[0025] As a preferred implementation, the third timing is 10s timing.

[0026] As a preferred implementation, it also includes: when transmitting large data, using the LZMA algorithm to encrypt and transmit, that is, setting the encryption flag in the message header to 1; when the receiving end receives the message header, if the encryption flag is 1, using the LZMA algorithm to decrypt and then process the data.

[0027] As a preferred implementation, the main core uses a power main control chip.

[0028] As a preferred implementation, the main core adopts the Fuxi main control chip CK860MP.

[0029] Compared with the existing technology, the present invention has the following beneficial effects:

[0030] 1. The multi-core heterogeneous system data synchronization method provided by the present invention, the multi-core processor includes a master core and at least two slave cores, each slave core establishes a communication channel with the master core respectively, and the message transmission between the master core and the slave core adopts a balanced mode, and the balanced mode includes: the master core and the slave core can both start message transmission; during downlink transmission, the master core sends a data frame message to the slave core, and starts frame counting and slave core response time timing; if the master core does not receive the slave core response message within the set time, it is considered that the communication is interrupted, and the internal communication interruption alarm flag is set; when the data frame count reaches the set number of frames, the master core needs to wait for the slave core response message before continuing to transmit; after the slave core receives the data frame, the frame counting and response time timing are started, and when the set number of frames are received cumulatively or the response time exceeds the set time, the response message is sent and received. That is, the present invention adopts a large data transmission scheme in a balanced mode to achieve fast and efficient data synchronization between multi-cores, high communication efficiency, and fast response.

[0031] 2. The multi-core heterogeneous system data synchronization method provided by the present invention uses compressed transmission and post-decompression data processing when transmitting large data such as network recording files, thereby reducing the number of data transmission frames, increasing the communication rate, and responding quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 is a schematic diagram of the structure of a multi-core processor according to an embodiment of the present invention;

[0034] Figure 2 It is a schematic diagram of the transmission process flow of the master core and slave core transmission of the present invention;

[0035] Figure 3 It is a schematic diagram of the transmission process of the main starting station of the present invention;

[0036] Figure 4 It is a schematic diagram of the transmission process from the starting station of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] In the description of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "top", "bottom", "top surface", "bottom surface", "inside", "outside", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0039] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself. If the terms "first", "second", "third" are described, they are only used for the purpose of description and distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0040] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "set" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. The following is an explanation of the embodiments of the present invention based on its overall structure.

[0041] Example 1

[0042] The multi-core heterogeneous system data synchronization method of the present invention comprises: the multi-core processor in the efficient multi-core heterogeneous system comprises a master core and at least two slave cores, each slave core establishes a communication channel with the master core, and the message transmission between the master core and the slave core adopts a balanced mode, and the balanced mode comprises:

[0043] Both the master core and the slave core can initiate message sending, which is a peer-to-peer transmission method. Figure 2 The figure shows the transmission process between the master core and the slave core. The master core actively transmits messages to the slave core, which is downlink transmission. The slave core actively sends messages to the master core, which is uplink transmission.

[0044] During downlink transmission, the master core sends a data frame message to the slave core and starts frame counting and slave core response time timing;

[0045] If the master core does not receive a response message from the slave core within the set time, it is considered that the communication is interrupted and the internal communication interruption alarm flag is set; when the data frame count reaches the set number of frames, the master core needs to wait for the slave core response message before it can continue to transmit. The set time is 12s;

[0046] After receiving the data frame from the core, the frame counting and response time timing are started. When the set number of frames are received cumulatively or the response time exceeds the set time, a receive response message is sent and received. The set number of frames is 8 frames and the set time is 10s.

[0047] The above-mentioned multi-core heterogeneous system data synchronization method adopts a balanced mode to improve the communication rate of multi-core heterogeneous system data and respond quickly.

[0048] Figure 1 The structure of a multi-core processor is shown. The main core uses a power master chip. The main core uses the Fuxi master chip CK860MP. The Fuxi master chip CK860MP is used as the main core and runs the Linux operating system. The CK810.0 core and the CK810.1 core run nakedly as slave cores. When the system is initially powered on, the CK860MP master core establishes two internal communication channels to communicate with the CK810.0 and CK810.1 slave cores respectively. After the communication is established, the slave core sends its own data to the main core through the internal communication channel. The main core also transmits configuration, constant data and other information to each slave core through the internal communication channel to achieve data synchronization between cores.

[0049] As shown in Table 1, the messages sent by the master core and the slave core include: message header, data segment, and check code. The message header includes the start character 0x68, the data segment length, the message source address, and the compression mark, a total of 7 bytes. The data segment length corresponds to the length in the message header. The check code is the message header and the data segment and the check. The total message length is the data segment length + 8.

[0050] Table 1 Message structure

[0051]

[0052] The above message framing format is simple, and the communication module development is unified and clear.

[0053] Figure 3 The main initiator station transmission process is shown, that is, in the balanced mode, the main core actively transmits data, which specifically includes the following steps:

[0054] S11, the main core sends data frames;

[0055] S12, after the main core sends the data frame, the first timing and frame counting are started. If the number of frames obtained by the frame counting is greater than or equal to the frame number threshold, the process proceeds to step S14; if the number of frames obtained by the frame counting is less than the frame number threshold, the process proceeds to step S13; wherein, the first timing is 12s timing, and the frame number threshold is 8;

[0056] S13, determining whether the main core continues to have subsequent frames, if yes, returning to steps S11-S12; otherwise, proceeding to step S14;

[0057] S14. Determine whether the waiting response time for the main core to receive the response message exceeds the first threshold time, where the first threshold time is 12s. If it exceeds, a communication interruption alarm flag is set. If it does not exceed, the main core receives the response message, continues normal communication interaction, and returns to step S11.

[0058] Figure 4The transmission process from the initiator station is shown, that is, in the balanced mode, the active data transmission from the core specifically includes the following steps:

[0059] S21, the slave core receives the data frame sent by the master core;

[0060] S22, after receiving the data frame sent by the master core, the slave core starts the second timer and frame count. If the number of frames obtained by the frame count is greater than or equal to the frame number threshold, the process proceeds to step S24; if the number of frames obtained by the frame count is less than the frame number threshold, the process proceeds to step S23, wherein the second timer is 10s and the frame number threshold is 8;

[0061] S23, judging whether a subsequent frame is received within the third time period, if no subsequent frame is received, returning to steps S21-S22; if a subsequent frame is received, entering step S24, wherein the third time period is 10s;

[0062] S24. The slave core sends a response message to the master core.

[0063] In addition, the data synchronization method of the multi-core heterogeneous system also includes: when transmitting large data such as distribution network recording files, use the LZMA algorithm to encrypt and transmit, that is, set the encryption flag in the message header to 1; when the receiving end receives the message header, if the encryption flag is 1, use the LZMA algorithm to decrypt and then process the data. The LZMA algorithm is the default algorithm for the 7z format. It is a compression algorithm improved and optimized from the Deflate and LZ77 algorithms. The decompression code size of the LZMA algorithm is generally about 5kB. In actual applications, the decompression memory occupied is small and supports multi-threaded processing.

[0064] The foregoing descriptions of specific exemplary embodiments of the present invention are for the purpose of explanation and illustration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is obvious that many changes and variations can be made based on the above teachings. Although an embodiment of the present invention has been shown and described, this specific embodiment is only an explanation of the present invention and is not a limitation of the invention. The specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can make modifications, substitutions, variations and various selections and changes to the embodiments without creative contribution as needed without departing from the principles and purpose of the present invention after reading this specification, but they are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A method for synchronizing data in a multi-core heterogeneous system, wherein the multi-core processor includes a master core and at least two slave cores, characterized in that: Each slave core establishes a communication channel with the master core respectively, and the message transmission between the master core and the slave core adopts a balanced mode, and the balanced mode includes: Both the master core and the slave core can initiate message sending; During downlink transmission, the master core sends a data frame message to the slave core and starts frame counting and slave core response time timing; If the master core does not receive a response message from the slave core within the set time, it is considered that the communication is interrupted and the internal communication interruption alarm flag is set; when the data frame count reaches the set number of frames, the master core needs to wait for the response message from the slave core before it can continue transmission; After receiving the data frame, the slave core starts the frame counting and response time timing. When the set number of frames are received or the response time exceeds the set time, the slave core sends a receive response message. The main core actively transmits data including the following steps: S11, the main core sends data frames; S12, after the main core sends the data frame, it starts the first timer and frame counting. If the number of frames obtained by the frame counting is greater than or equal to the frame number threshold, it goes to step S14; if the number of frames obtained by the frame counting is less than the frame number threshold, it goes to step S13; S13, determining whether the main core continues to have subsequent frames, if yes, returning to steps S11-S12; otherwise, proceeding to step S14; S14, determining whether the waiting response time for the main core to receive the response message exceeds the first threshold time, if it exceeds, setting a communication interruption alarm flag, if it does not exceed, the main core receives the response message, continues normal communication interaction, and returns to step S11; Active data transmission from the core specifically includes the following steps: S21, the slave core receives the data frame sent by the master core; S22, after receiving the data frame sent by the master core, the slave core starts the second timer and frame counting. If the number of frames obtained by the frame counting is greater than or equal to the frame number threshold, the process proceeds to step S24; if the number of frames obtained by the frame counting is less than the frame number threshold, the process proceeds to step S23; S23, determining whether a subsequent frame is received within the third time period, if a subsequent frame is received, returning to steps S21-S22; if no subsequent frame is received, proceeding to step S24; S24, the slave core sends a response message to the master core; It also includes: when transmitting the distribution network recording file, the LZMA algorithm is used to encrypt the file and the encryption flag in the message header is set to 1; when the receiving end receives the message header, if the encryption flag is 1, the LZMA algorithm is used to decrypt the file and then the data is processed.

2. The multi-core heterogeneous system data synchronization method according to claim 1, characterized in that: The first timing is 12 seconds.

3. The multi-core heterogeneous system data synchronization method according to claim 1, characterized in that: The frame number threshold is 8.

4. The multi-core heterogeneous system data synchronization method according to claim 1, characterized in that: The second time is 10 seconds.

5. The multi-core heterogeneous system data synchronization method according to claim 1, characterized in that: The third time is 10 seconds.

6. The multi-core heterogeneous system data synchronization method according to claim 1, characterized in that: The main core adopts a power main control chip.

7. The multi-core heterogeneous system data synchronization method according to claim 6, characterized in that: The main core adopts Fuxi main control chip CK860MP.

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