Delay measurement circuit, method, chip and electronic device

Abstract

Embodiments of the present application provide a time delay measurement circuit, method, chip and electronic device. The time delay measurement circuit is applied to a chip. The time delay measurement circuit comprises a measurement circuit, a copy circuit and a crosstalk circuit. The chip further comprises a timing circuit. The copy circuit is a copy of the timing circuit. The measurement circuit is connected to the copy circuit. The copy circuit is further connected to the crosstalk circuit. The copy circuit is used to simulate a data signal in the timing circuit. The crosstalk circuit is used to generate a crosstalk signal. The crosstalk signal is used to interfere with the data signal. The measurement circuit is used to measure a path delay of the copy circuit interfered by the crosstalk signal. The path delay of the copy circuit is used to predict a time delay or a frequency of the chip. The accuracy of predicting the time delay or the frequency of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a delay measurement circuit, method, chip, and electronic device. Background Technology

[0002] During chip operation, in order to keep the chip's operating frequency within a suitable range, the chip's time delay is usually measured, and the chip's operating voltage is adjusted based on the time delay, thereby keeping the chip's operating frequency within a suitable range.

[0003] In related technologies, a Critical Path Monitor (CPM) is installed in the chip to obtain the chip's latency. The CPM has... Figure 1 The structure shown is as follows: Figure 1 As shown, the CPM includes a synchronizer, a delay synthesis module, two edge detection modules, and a data analysis module. The delay synthesis module includes a 4-input NAND gate sequence, a 3-input NOR gate sequence, an adder path, a wire-dominated path, a transmission gate sequence, a first selector, a second selector, and a third selector.

[0004] In the aforementioned prior art, CPM is a universal detector that can be set in any chip and is independent of the timing circuits in the chip, resulting in poor accuracy of the chip's time delay. Summary of the Invention

[0005] This application provides a delay measurement circuit, method, chip, and electronic device to improve the accuracy of predicting the delay or frequency of a chip.

[0006] In a first aspect, embodiments of this application provide a time delay measurement circuit applied in a chip. The time delay measurement circuit includes: a measurement circuit, a replica circuit, and a crosstalk circuit. The chip also includes a timing circuit, and the replica circuit is the target circuit corresponding to the timing circuit.

[0007] The measurement circuit and the replica circuit are connected, and the replica circuit is also connected to the crosstalk circuit.

[0008] The replica circuit is used to simulate the data signals generated in the sequential circuit;

[0009] Crosstalk circuits are used to generate crosstalk signals, which are used to interfere with data signals.

[0010] The measurement circuit is used to measure the path delay of the replica circuit affected by crosstalk signals, and the path delay of the replica circuit is used to predict the delay or frequency of the chip.

[0011] In a possible design, the copy circuit includes a first component, a second component, and a first connection line; the first connection line connects the first component and the second component, and the first connection line is a connection line whose interference value caused by a crosstalk signal is greater than or equal to a preset value;

[0012] The crosstalk circuit includes a third component, a fourth component, and a second connection line; the second connection line connects the third component and the fourth component.

[0013] The third component is connected to a component that provides a data signal to the first component.

[0014] In a possible design, the first connection line and the second connection line are arranged in parallel in the chip.

[0015] In a possible design, the first connection line and the second connection line have a preset polyline shape in the chip.

[0016] In a possible design, the third component is an inverse logic component of the first component.

[0017] In a possible design, the first connection line corresponds to N crosstalk circuits, and N is an integer greater than or equal to 2.

[0018] The second connection lines in the N crosstalk circuits are arranged in parallel, and the first connection line is arranged in parallel between the second connection lines in the N crosstalk circuits.

[0019] In a possible design, the distance between the first connection line and each second connection line in the N crosstalk circuits is less than or equal to a preset distance.

[0020] In a possible design, the crosstalk control circuit further includes a crosstalk control circuit.

[0021] The crosstalk control circuit is connected to the crosstalk circuit and the copy circuit respectively.

[0022] The crosstalk control circuit is configured to control the crosstalk circuit and the copy circuit to be turned on or turned off.

[0023] In a possible design, the measurement circuit includes a first flip-flop, a second flip-flop, and a processing circuit; wherein,

[0024] The input end of the first flip-flop is connected to the output end of the processing circuit, the output end of the first flip-flop is connected to the input end of the copy circuit, the output end of the copy circuit is connected to the input end of the second flip-flop, and the output end of the second flip-flop is connected to the input end of the processing circuit.

[0025] In a second aspect, the embodiments of the present application provide a time delay measurement method, which is applied to a chip. The time delay measurement circuit in the chip comprises a measurement circuit, a replica circuit and a crosstalk circuit. The chip further comprises a timing circuit. The method comprises the following steps:

[0026] Determining the replica circuit corresponding to the timing circuit;

[0027] Respectively controlling the replica circuit to generate a data signal and the crosstalk circuit to generate a crosstalk signal, wherein the crosstalk signal is used to interfere with the data signal;

[0028] Controlling the measurement circuit to measure the path time delay of the replica circuit interfered by the crosstalk signal.

[0029] In a possible design, the target circuit corresponding to the timing circuit is determined, comprising the following steps:

[0030] Performing static timing analysis on all timing circuits to obtain a static timing analysis (STA) report corresponding to each timing circuit, wherein the STA report at least comprises gate-level delay of each timing circuit;

[0031] Determining at least one candidate circuit from the all timing circuits according to the gate-level delay of each timing circuit;

[0032] Respectively performing timing analysis on each candidate circuit to obtain a pipe-level timing analysis result corresponding to each candidate circuit, wherein the pipe-level timing analysis result at least comprises pipe-level delay of each candidate circuit and working parameters of each candidate circuit;

[0033] Determining delay sensitivity of each candidate circuit according to the pipe-level delay and the working parameters of each candidate circuit;

[0034] Classifying all candidate circuits according to the delay sensitivity of each candidate circuit to obtain at least one type of circuit;

[0035] Determining the target circuit from the at least one type of circuit;

[0036] Determining the replica circuit corresponding to the timing circuit according to the target circuit.

[0037] In a possible design, the pipe-level timing analysis result further comprises an identifier of each component in the candidate circuit and an identifier of each connection line. The replica circuit corresponding to the timing circuit is determined according to the target circuit, comprising the following steps:

[0038] Obtaining the pipe-level timing analysis result of the target circuit from the pipe-level timing analysis result of all candidate circuits;

[0039] Determining the identifiers of at least three components included in the target circuit according to the pipe-level timing analysis result of the target circuit; and

[0040] Identify the identifiers of at least two connection lines that connect at least three components included in the target circuit;

[0041] Determine the replica circuit corresponding to the timing circuit based on the identifiers of at least three components and at least two connection lines.

[0042] Thirdly, embodiments of this application provide a chip including a delay measurement circuit according to any one of the first aspects described above.

[0043] Fourthly, embodiments of this application provide an electronic device, which includes the chip described in the third aspect above.

[0044] This application provides a time delay measurement circuit, method, chip, and electronic device. The time delay measurement circuit is applied to a chip and includes a measurement circuit, a replica circuit, and a crosstalk circuit. The chip also includes a timing circuit. The measurement circuit and the replica circuit are connected, and the replica circuit is also connected to the crosstalk circuit. The replica circuit is a replica of the timing circuit, so that the designed replica circuit has a strong correlation with the timing circuit. The replica circuit is used to simulate the data signal in the timing circuit, and the crosstalk circuit is used to generate a crosstalk signal. The crosstalk signal is used to interfere with the data signal, thereby constructing the crosstalk circuit to interfere with the replica circuit, improving the correlation between the replica circuit and the timing circuit, and enabling the replica circuit to realistically simulate the data signal in the timing circuit, thereby improving the accuracy of predicting the chip's time delay or frequency. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A schematic diagram of the structure of CPM provided in an embodiment of this application;

[0047] Figure 2 A schematic diagram of the delay measurement circuit for the chip provided in this application embodiment. Figure 1 ;

[0048] Figure 3 This is a schematic diagram of the crosstalk circuit and the copy circuit provided in the embodiments of this application;

[0049] Figure 4 A schematic diagram illustrating the connection principle of the copy circuit and crosstalk circuit provided in the embodiments of this application;

[0050] Figure 5 A circuit timing diagram provided for an embodiment of this application;

[0051] Figure 6 The on-chip wiring diagram of the crosstalk circuit and the copy circuit provided in the embodiments of this application;

[0052] Figure 7 A schematic diagram of the time delay measurement circuit provided in the embodiments of this application. Figure 2 ;

[0053] Figure 8 A flowchart illustrating the time delay measurement method provided in the embodiments of this application. Figure 1 ;

[0054] Figure 9 A flowchart illustrating the time delay measurement method provided in the embodiments of this application. Figure 2 . Detailed Implementation

[0055] Before describing the time delay measurement circuit provided in this application, let's first combine... Figure 1 This application describes the CPM in the prior art. For details, please refer to [link / reference needed]. Figure 1 Example.

[0056] Figure 1 This is a schematic diagram of a CPM structure provided in an embodiment of this application. Figure 1 As shown, the CPM includes: a synchronizer 11, an inverter 12, a delay path module 13, two edge detector modules 14 and 15, a data analysis module 16, a decoder module 17, a configuration module 18, and an output module 19. The delay path module 13 includes: an adjustable delay module 130, a 4-input AND4 sequence 131, a 3-input NOR3 sequence 132, an adder path 133, a wire-dominated path 134, a pass gate sequence 135, a first selector 136, a second selector 137, and a third selector 138. For a detailed description of the connections between the modules in the CPM, please refer to [link to documentation]. Figure 1 For a description of the CPM process, please refer to existing technologies; it will not be repeated here.

[0057] Figure 2The CPM shown can be used to predict the delay or frequency of a chip. This CPM is a universal detector that can be set in any chip. The CPM is independent of the timing circuit of the chip it is located in. Moreover, when predicting the delay or frequency of a chip using the CPM, crosstalk signals are not considered, resulting in poor accuracy in predicting the delay or frequency of the chip.

[0058] In this application, in order to improve the accuracy of predicting the delay or frequency of a chip, the inventors conceived of designing a replica circuit based on the timing circuit in the chip, so that the replica circuit is correlated with the timing circuit. Furthermore, a crosstalk circuit is added to construct the interference of the crosstalk circuit on the replica circuit, thereby predicting the delay or frequency of the chip based on the interfered replica circuit, thus improving the accuracy of predicting the delay or frequency of the chip.

[0059] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0060] Figure 1 A schematic diagram of the time delay measurement circuit provided in the embodiments of this application. Figure 2 .like Figure 8 As shown, the delay measurement circuit includes: a measurement circuit, a replica circuit, and a crosstalk circuit; the replica circuit is a replica of the timing circuit.

[0061] The measurement circuit and the replica circuit are connected, and the replica circuit is also connected to the crosstalk circuit.

[0062] The replica circuit is used to simulate the data signals generated in the sequential circuit;

[0063] Crosstalk circuits are used to generate crosstalk signals, which are used to interfere with data signals.

[0064] The measurement circuit is used to measure the path delay of a replica circuit affected by crosstalk signals. The path delay of the replica circuit is used to predict the chip's delay or frequency.

[0065] A replica circuit is a copy of a sequential circuit. The term "replica" can refer to either a circuit that is a copy of the sequential circuit, or it can refer to a circuit whose component attributes (such as size and operating voltage) have been adjusted.

[0066] The following explanation uses a time delay measurement circuit that includes a replica circuit as an example.

[0067] The replica circuit includes: at least three components and at least two connecting lines. The at least two connecting lines are used to connect the at least three components. One of the at least two connecting lines is a first connecting line whose interference value due to crosstalk is greater than or equal to a preset value. The at least three components are obtained based on the component information of the target circuit, and the at least two connecting lines are obtained based on the wiring information of the target circuit. The component information includes identifiers corresponding to the at least three components (for example, when one component is an inverter, the inverter's identifier can be Inv). The wiring information includes the lengths of the at least two connecting lines and the identifiers of the metal layers in which the at least two connecting lines are located within the chip. For a detailed description of the target circuit, its component information, and its wiring information, please refer to [link to relevant documentation]. Figure 4 Example. For an explanation of the interference value and preset value, please refer to [link to example]. Figure 3 Example.

[0068] The replication circuit is used to simulate the data signals generated in the sequential circuit. The crosstalk circuit is used to generate crosstalk signals that interfere with the data signals.

[0069] Optionally, the number of crosstalk circuits can be the same as or different from the number of first connecting lines. When the number of crosstalk circuits is the same as the number of first connecting lines, one first connecting line corresponds to one crosstalk circuit. When the number of crosstalk circuits is different from the number of first connecting lines, one first connecting line can correspond to multiple crosstalk circuits, and the multiple crosstalk circuits can be the same or different.

[0070] The following example uses the scenario where the number of crosstalk circuits is the same as the number of first connecting lines, with one first connecting line corresponding to one crosstalk circuit. Figure 3 The structure of the crosstalk circuit and the copy circuit is explained. Figure 3 This is a schematic diagram of the crosstalk circuit and the copy circuit provided in an embodiment of this application. An example is shown below. Figure 3 As shown, at least three components in the replica circuit include P, A, B, C, D, and E, and at least two connection lines in the replica circuit include b1, b2, b3, a1, and a2, with the first connection line being a1 and a2. Figure 2 In this circuit, different first connection lines correspond to different crosstalk circuits. For example, V1 is the crosstalk circuit corresponding to a1, and V2 is the crosstalk circuit corresponding to a1. Optionally, V1 includes a reverse component of A, a load component F1, and a connection line connecting the reverse component and F1. Optionally, V2 includes a reverse component of D, a load component F2, and a connection line connecting the reverse component and F2. F1 and F2 can be any load component (e.g., a resistor).

[0071] Optionally, the measurement circuit can be connected to the replica circuit via one or two connecting lines, so that the measurement circuit and the replica circuit form a closed loop.

[0072] For example, when the measuring circuit is connected to the replica circuit via a connecting line, this connecting line includes two mutually isolated wires. The measuring circuit provides a first input signal to the replica circuit through one metal wire and receives the first output signal after the first input signal has passed through the replica circuit through the other metal wire. The first input signal can be 0 or 1, and the first output signal can be 0 or 1. For example, when the first input signal is 0, the first output signal can be 0 or 1; when the first input signal is 1, the first output signal can be 0 or 1. It should be noted that whether the first output signal is 0 or 1 is determined by the multiple components within the replica circuit and their interconnections.

[0073] For example, when the measurement circuit is connected to the replica circuit through two connection lines, the measurement circuit and the replica circuit constitute a ring circuit. The measurement circuit provides a first input signal to the replica circuit through one connection line and receives the first output signal after the first input signal passes through the replica circuit through the other connection line.

[0074] Alternatively, the measurement circuit can obtain the path delay of the replica circuit using the following (Formula 1):

[0075]

[0076] Among them, t path The path delay of the replica circuit is T, the preset duration is n, the count value of the measurement circuit is n, and t is n. m This is for measuring the path delay of the circuit.

[0077] Figure 4 The time delay measurement circuit provided in this embodiment is applied in a chip. The time delay measurement circuit includes a measurement circuit, a replica circuit, and a crosstalk circuit. The chip also includes a timing circuit. The measurement circuit and the replica circuit are connected, and the replica circuit is also connected to the crosstalk circuit. The replica circuit is a replica of the timing circuit, so that the designed replica circuit has a strong correlation with the timing circuit. The replica circuit is used to simulate the data signal in the timing circuit, and the crosstalk circuit is used to generate a crosstalk signal. The crosstalk signal is used to interfere with the data signal, thereby constructing the interference of the crosstalk circuit on the replica circuit, improving the correlation between the replica circuit and the timing circuit, so that the replica circuit can truly simulate the data signal in the timing circuit, thereby improving the accuracy of predicting the chip's time delay or frequency.

[0078] In practical applications, chip timing is typically evaluated using chip latency (or frequency). In existing technologies, the accuracy of predicted chip latency or frequency is poor, making accurate chip timing evaluation impossible. However, this application improves the accuracy of predicted chip latency or frequency, thus enabling more accurate chip timing evaluation.

[0079] Based on the above embodiments, the following example uses a replica circuit comprising three components and two connecting lines connecting the three components, combined with... Figure 4 The connection principles of the copy circuit and the crosstalk circuit are explained.

[0080] Figure 4 A schematic diagram illustrating the connection principle of the copy circuit and crosstalk circuit provided in the embodiments of this application. (See attached diagram.) Figure 4 As shown, the replica circuit includes three components P, A, and B, and two connecting lines b1 and b2. b1 connects P and A, and b2 connects A and B.

[0081] Optionally, the sequential circuit corresponding to the replica circuit also includes P, A, B, b1, and b2. For example, the replica circuit differs from the sequential circuit in that the dimensions of P, A, and B may be different.

[0082] Optionally, the timing circuit corresponding to the replica circuit can be analyzed using a static timing analysis (STA) tool to obtain the interference values ​​corresponding to b1 and b2 respectively. The interference value indicates the magnitude of interference of crosstalk signal on the data signal transmitted on the connection line. The connection line with the interference value of b1 and b2 that is greater than or equal to the preset value is determined as the first connection line.

[0083] Optionally, the preset value can be 0, or it can be the preset measurement accuracy of the measurement circuit.

[0084] In an exemplary replica circuit, with the first connection line b2, the first component A, and the second component B, the crosstalk circuit includes a third component A1, a fourth component C, and a second connection line b3. b3 connects A1 and C. The third component A1 is connected to component P, which provides data signals to the first component A. The crosstalk signal transmitted on b3 interferes with the data signal transmitted on b2. In a practical design, A1 can be placed near B, and C can be placed near A (e.g., ...). Figure 4 (As shown).

[0085] A1 can be the inverse logic device of A, and C can be any load device.

[0086] In practical applications, interference from the crosstalk signal can only occur when the amplitudes and transmission directions of the data signal and the crosstalk signal are opposite. For example, when the amplitude of the data signal flips from 0 to 1, the amplitude of the crosstalk signal flips from 1 to 0. Therefore, when A1 is the inverting logic device of A, it ensures that when the amplitude of the data signal flips from 0 to 1, the amplitude of the crosstalk signal flips from 1 to 0, thus creating interference from the crosstalk signal. Moreover, when A1 is the inverting logic device of A, the amplitudes and transmission directions of the data signal and the crosstalk signal are opposite, making the interference experienced by the data signal relatively stable within each ring oscillation cycle.

[0087] exist Figure 4 In the diagram, the lengths of the connecting line b1 between P and A and the connecting line b4 between P and A1 are usually different. It should be noted that the difference in line length between b1 and b4 generally does not affect the magnitude of the interference (i.e., it does not affect the extent to which the crosstalk signal transmitted on b3 interferes with the data signal transmitted on b2). In practical applications, if it is necessary to adjust the magnitude of the interference, the distance (L) between b2 and b3 and / or the size of C can be adjusted. For example, increasing L reduces the interference; decreasing L increases the interference. Similarly, increasing the size of C increases the interference; decreasing the size of C decreases the interference.

[0088] Optionally, b2 and b3 can be arranged parallel to each other in the chip, or they can be arranged superimposed at a preset angle (e.g., a preset angle of 90 degrees, i.e., perpendicular and non-intersecting) in the chip. Figure 5 This explanation uses the example of b2 and b3 being arranged in parallel within the chip.

[0089] In practical applications, in order to prevent interference from crosstalk signals when the amplitude of the data signal reverses, the first connection line b2 and the second connection line b3 are arranged in parallel in the chip. This ensures that as the amplitude of the data signal flips from 0 to 1, the amplitude of the crosstalk signal flips from 1 to 0. In other words, it ensures that the amplitudes of the data signal and the crosstalk signal meet within the flipping timing window, thereby creating interference from the crosstalk signal on the data signal.

[0090] The following is combined Figure 4 ,right Figure 5 The timing sequence of the replica circuit and crosstalk circuit shown is explained.

[0091] Figure 4 This is a circuit timing diagram provided for an embodiment of this application. Figure 5 On the basis of, such as Figure 6 As shown, this includes the timing sequences corresponding to P, A, A1, b2, and b3.

[0092] “1” represents the data signal transmission delay between P and A (i.e., on b1), and “2” represents the data signal transmission delay between P and A1 (i.e., on b4).

[0093] “a”, “b”, and “c” all represent the flip timing window on b2 and b3, which is the approximate position where the amplitude of the data signal flips.

[0094] The data signal on b2 is interfered with by the crosstalk signal on b3 at the amplitude inversion position "d" within "a", "b", and "c".

[0095] Based on the above embodiments, the following example illustrates how the number of crosstalk circuits differs from the number of first connecting lines, and how one first connecting line can correspond to multiple crosstalk circuits. Figure 6 The on-chip wiring diagram illustrating the connection relationship between the crosstalk circuit and the copy circuit is explained.

[0096] Figure 6 This is an on-chip wiring diagram of the crosstalk circuit and the copy circuit provided in the embodiments of this application. (See diagram below.) Figure 6 As shown, the first connecting line corresponds to N crosstalk circuits, where N is an integer greater than or equal to 2; the second connecting lines in the N crosstalk circuits are arranged in parallel, and the first connecting line is arranged in parallel between the second connecting lines in the N crosstalk circuits. The N crosstalk circuits can be different or not.

[0097] It should be noted that, Figure 4 The explanation is based on the example of N equaling 2, where the crosstalk circuits are different. Specifically, the explanation is based on the example of the first connection line corresponding to the first crosstalk circuit and the second crosstalk circuit.

[0098] For example, the replica circuit includes at least three components, namely components P, A, and B, and two connecting lines, namely L1 and L2. For instance, L2 is the first connecting line with an interference value greater than or equal to a preset value, A is the first component, and B is the second component.

[0099] The first crosstalk circuit includes a third component A1, a fourth component C1, and a connecting line L31, which connects A1 and C1. L31 is the second connecting line in the first crosstalk circuit. Figure 5 In the middle, connecting line L41 connects P and A1.

[0100] L2 and L31 are arranged parallel to each other in the chip, and the routing shape of L2 and L31 in the chip is a preset polygonal shape (e.g., as shown in the image). Figure 6(The diagram shows a serpentine routing shape). In practical applications, to save space occupied by the delay measurement circuit in the chip, the delay measurement circuit needs to be placed in a smaller space. However, during routing, in order to make the connection lines close to the connection lines in the timing circuit, multiple interconnect lines of several hundred micrometers can be implemented in a small space. In this embodiment of the invention, the metal layers where the connection lines are located are alternately distributed during routing, and the connection lines are arranged in a serpentine routing shape (or a zigzag routing shape), which can achieve the purpose of reducing the occupied space.

[0101] In practical applications, when the target interference value cannot be achieved by adjusting the distance between L2 and L31 and / or the size of C1, a second crosstalk circuit can be added.

[0102] For example, the second crosstalk circuit includes: a third component A2, a fourth component C2, and a connecting line L32, where L32 connects A2 and C2. L32 is the second connecting line in the second crosstalk circuit. Figure 6 In the middle, connecting wire L42 connects P and A2.

[0103] Optionally, A2 can be the same as A1 or different.

[0104] The fact that A2 is the same as A1 means that A2 and A1 have the same attribute information, such as size and internal structure.

[0105] Here, A2 being different from A1 indicates that A2 and A1 have different attribute information. For example, if A2 and A1 have different dimensions, it means that A2 and A1 are not the same.

[0106] Optionally, C2 and C1 can be the same or different.

[0107] The first connecting line L2 is positioned parallel to the second connecting line L31 and the second connecting line L32. The distance between L2 and both L31 and L32 is less than or equal to a preset distance. This preset distance is the maximum distance at which the interference value generated by the crosstalk signals in the second connecting line L31 and the second connecting line L32 on the data signal on the first connecting line L2 reaches a preset threshold value. This preset threshold value can be set according to actual conditions.

[0108] In this embodiment of the invention, the distance between L2 and L31 and L32 is less than or equal to a preset distance, which can avoid the problem that the distance between L2 and L31 and L32 is too large, resulting in the inability to construct a more ideal interference value.

[0109] Furthermore, the routing shapes of L2, L31, and L32 in the chip are preset polygonal shapes (e.g., Figure 7 The serpentine trace shape shown can save space occupied by the delay measurement circuit in the chip.

[0110] Figure 2 A schematic diagram of the time delay measurement circuit provided in the embodiments of this application. Figure 2 .exist Figure 7 On the basis of, such as Figure 3 As shown, the measurement circuit includes: a first flip-flop, a second flip-flop, and a processing circuit; wherein,

[0111] The input terminal of the first flip-flop is connected to the output terminal of the processing circuit, the output terminal of the first flip-flop is connected to the input terminal of the replica circuit, the output terminal of the replica circuit is connected to the input terminal of the second flip-flop, and the output terminal of the second flip-flop is connected to the input terminal of the processing circuit.

[0112] The processing circuit obtains the path delay of the replica circuit affected by crosstalk signal interference according to Formula 1 above. It should be noted that the preset measurement accuracy of the measurement circuit is the same as the preset measurement accuracy of the processing circuit.

[0113] The first trigger is the Calibration Launch Flip-flop (CLFF), and the second trigger is the Calibration Capture Flip-flop (CCFF).

[0114] Wherein, CLFF includes ports CI, D, and Q, and CCFF includes ports O, D, and Q. The input of the first flip-flop is port CI of CLFF, and the output of the first flip-flop is port Q of CLFF. The input of the second flip-flop is port D of CCFF, and the output of the second flip-flop is port O of CCFF.

[0115] Specifically, the processing circuit provides a first signal to port CI of the CLFF. Based on this first signal, the CLFF provides a first input signal to the replica circuit through port Q. After passing through the replica circuit, the replica circuit outputs a first output signal. The CCFF receives the first output signal through port D and provides a second signal to the processing circuit through port O based on this first output signal. Here, n in Formula 1 is the count value between the processing circuit providing the first signal to the CLFF and the CCFF receiving the first output signal.

[0116] Specifically, the input of the replica circuit is the primary component (e.g., Figure 4 The input terminal of P in the circuit is the terminal of the replica circuit, and the output terminal of the replica circuit is the final stage component (e.g., P). Figure 8 The output terminal of E in the middle.

[0117] The time delay measurement circuit may further include: a crosstalk control (CC) circuit; the crosstalk control circuit is connected to both the crosstalk circuit and the replica circuit; the crosstalk control circuit is used to control the conduction or disconnection of the crosstalk circuit and the replica circuit.

[0118] Optionally, when there are multiple crosstalk circuits, each crosstalk circuit has its own corresponding crosstalk control circuit. For a single crosstalk control circuit, it is connected to both the replica circuit and its corresponding crosstalk circuit. For example, in... Figure 8 Based on this, component P in the replica circuit is connected to the third component A1 through a crosstalk control circuit.

[0119] Specifically, an enable signal is provided to the crosstalk control circuit, which then controls the switching on and off of the crosstalk circuit and the replica circuit based on the enable signal. When there are multiple crosstalk circuits, each crosstalk circuit has its own corresponding crosstalk control circuit and can share the same enable signal.

[0120] When the crosstalk control circuit turns on the crosstalk circuit, the path delay t1 of the replica circuit after adding the crosstalk signal is obtained using the above formula (1). When the crosstalk control circuit turns off the crosstalk circuit, the path delay t2 of the replica circuit after not adding the crosstalk signal is obtained using the above formula (1). The difference between t2 and t1 equals the interference value.

[0121] In this application, by controlling the crosstalk circuit to be turned on or off by the crosstalk control circuit, the interference value of the replica circuit after silicon can be obtained. The interference value of the replica circuit before silicon can be obtained by the STA tool. By comparing the interference value of the replica circuit after silicon and the interference value of the replica circuit before silicon, the difference between the two can be analyzed, the rules can be summarized, and guidance can be provided for better design of the replica circuit.

[0122] This application provides a chip including the delay measurement circuit described in any of the above embodiments. The chip provided in this application has the same beneficial effects as the delay measurement circuit in the above embodiments, and will not be repeated here.

[0123] This application provides an electronic device, which includes a chip equipped with the time delay measurement circuit described in any of the above embodiments. The electronic device provided in this application has the same beneficial effects as the chip described above, and will not be repeated here.

[0124] Based on the above embodiments, this application also provides a time delay measurement method, which is described below in conjunction with... Figure 1 The time delay measurement method provided in the embodiments of this application will be described.

[0125] Figure 8 A flowchart illustrating the time delay measurement method provided in the embodiments of this application.Figure 9 The delay measurement method is applied to the delay measurement circuit in any of the above embodiments. The delay measurement circuit includes a measurement circuit, a replication circuit, and a crosstalk circuit. This delay measurement circuit is disposed in a chip, which also includes multiple timing circuits. Figure 8 As shown, the method includes:

[0126] S801, Determine the replica circuit corresponding to the sequential circuit.

[0127] In one possible design, the sequential circuit in S801 is the sequential circuit with the largest gate delay among all the sequential circuits included in the chip; determining the replica circuit corresponding to the sequential circuit includes:

[0128] Using the STA tool, static timing analysis is performed on all sequential circuits included in the chip, and a static timing analysis report is obtained for each sequential circuit. The STA report includes the gate delay of each sequential circuit. The replica circuit corresponding to the sequential circuit with the maximum gate delay in the gate delay of each sequential circuit in the STA report is determined.

[0129] In another possible design, it can be achieved through the following... Figure 9 The methods in S901 to S909 of the embodiment determine the replica circuit corresponding to the timing circuit.

[0130] S803 controls the replica circuit to generate data signals and controls the crosstalk circuit to generate crosstalk signals, which are used to interfere with the data signals.

[0131] S804, The path delay of the control measurement circuit for the replica circuit affected by crosstalk signal interference is measured.

[0132] Figure 9 The time delay measurement method provided in the embodiments has the same beneficial effects as the time delay measurement circuit provided in the above embodiments, and will not be described again here.

[0133] Based on the above embodiments, the following is combined with Figure 9 The delay measurement method provided in the embodiments of this application will be further described in detail. For specific details, please refer to [link to relevant documentation]. Figure 2 Example.

[0134] Figure 9 A flowchart illustrating the time delay measurement method provided in the embodiments of this application. Figure 9 .like ​ As shown, the method includes:

[0135] S901. Perform static timing analysis on all timing circuits included in the chip to obtain the STA report corresponding to each timing circuit. The STA report includes the gate delay of each timing circuit, the identifier of each component contained in each timing circuit, and the identifier of each connection line contained in each timing circuit.

[0136] Optionally, a static timing analysis can be performed on all the aforementioned sequential circuits using a first analysis tool to obtain a STA report for each sequential circuit. For example, the first analysis tool can be an STA tool, or other tools capable of generating STA reports.

[0137] S902. Based on the gate delay of each sequential circuit, determine at least one alternative circuit among all sequential circuits.

[0138] Alternatively, at least one alternative circuit can be determined in one of the following two feasible ways.

[0139] Method 1: Select a predetermined number of sequential circuits with the largest gate delays from all sequential circuits as at least one candidate circuit.

[0140] The preset quantity is less than the number of sequential circuits. For example, the preset quantity can be 200, 500, etc.

[0141] Method 2: Select at least one sequential circuit as a candidate circuit if the gate delay is greater than or equal to a preset gate delay threshold.

[0142] S903. Perform timing analysis on each candidate circuit to obtain the transistor-level timing analysis results for each candidate circuit; wherein, the transistor-level timing analysis results include at least the transistor-level delay and the operating parameters of each candidate circuit.

[0143] Specifically, using the second analysis tool, timing analysis is performed on each candidate circuit, the process library corresponding to the feature size, the calculation model corresponding to the process library, and the operating parameters of each candidate circuit to obtain the transistor-level timing analysis results for each candidate circuit.

[0144] For example, the second analysis tool is a pipeline-level time series analysis tool.

[0145] Optionally, the operating parameters can be temperature, voltage, etc.

[0146] Specifically, the transistor-level timing analysis results include the identifier of each component in each candidate circuit, the transistor-level delay of each candidate circuit, the operating parameters of each candidate circuit, and the identifier of each connection line. The transistor-level delay of each candidate circuit is determined based on the transistor-level delay of each component within that candidate circuit; similarly, the operating parameters of each candidate circuit are determined by the operating parameters of each component within that candidate circuit.

[0147] S904. Determine the delay sensitivity of each candidate circuit based on its transistor delay and operating parameters.

[0148] Specifically, for any candidate circuit, there are multiple transistor delays and operating parameters corresponding to that candidate circuit, where each operating parameter corresponds to a transistor delay;

[0149] By using a pre-defined polynomial fitting algorithm, curve fitting is performed on multiple tube-level delays and multiple operating parameters to obtain the operating curve.

[0150] The delay sensitivity of the candidate circuit is obtained by taking the derivative of the working curve.

[0151] Currently, an increasing number of practical applications require chips to operate correctly under a wide range of conditions (e.g., the chip can operate correctly at both low and high supply voltages). For example, when the load is light and power consumption needs to be reduced, the chip will operate at a low supply voltage; when the load is heavy and overclocking is required, the chip needs to switch to a high supply voltage. Furthermore, in certain special application scenarios, chips are also required to operate correctly and stably in harsh operating environments such as ultra-low or ultra-high temperatures.

[0152] Existing representative critical path (RCP) and design-dependent ring oscillator (DDRO) methods primarily address fluctuations in operating parameters (such as temperature and voltage) within a small range near typical operating parameters. While the linear models involved in RCP and DDRO achieve good accuracy (i.e., the delay sensitivity determined by the linear model is relatively accurate) under these conditions, larger fluctuations in operating parameters lead to significant errors in the determined delay sensitivity, reducing its accuracy. Therefore, they are unsuitable for scenarios where the chip operates under a wide range of conditions. In this application, a pre-defined polynomial fitting algorithm is used to obtain the operating curve. The derivative of the operating curve is then calculated to obtain the delay sensitivity. This allows for a more accurate delay sensitivity even when the operating parameters fluctuate within a large range near typical operating parameters, making it applicable to scenarios where the chip operates under a wide range of conditions.

[0153] S905. Based on the delay sensitivity of each candidate circuit, classify all candidate circuits to obtain at least one class of circuits; wherein, the similarity of the delay sensitivity of the candidate circuits included in each class of circuits is less than or equal to a first preset similarity.

[0154] Each type of circuit corresponds to a first preset similarity score. The first preset similarity scores for different types of circuits are different.

[0155] In practical applications, a first preset similarity is first determined, and then a type of circuit corresponding to the first preset similarity is determined from at least one candidate circuit. The first preset similarity is a value determined based on the actual condition of the circuit.

[0156] S906. Determine the target circuit in at least one class of circuits.

[0157] Alternatively, the target circuit can be determined in at least one class of circuits using the following three methods.

[0158] Method 1: Determine the target circuit in at least one type of circuit, including: selecting the target type of circuit from all types of circuits, wherein the target type of circuit is the type of circuit with the highest average delay sensitivity among all types of circuits;

[0159] Obtain the delay sensitivity of each candidate circuit included in the target class circuit, and determine the candidate circuit with the highest similarity between its delay sensitivity and the average delay sensitivity of the target class circuit as the target circuit.

[0160] Method 2: Determine a target circuit in each type of circuit, including: for all candidate circuits included in each type of circuit, determine the candidate circuit with the highest similarity between the delay sensitivity and the average delay sensitivity in that type of circuit as the target circuit, where the average delay sensitivity is the average of the delay sensitivity of all candidate circuits included in that type of circuit.

[0161] Method 3: Determine a target circuit in each type of circuit, including: for all candidate circuits included in each type of circuit, determine the candidate circuit with the highest similarity between the delay sensitivity and the average delay sensitivity in that type of circuit as the initial circuit, and the average delay sensitivity is the average of the delay sensitivity of all candidate circuits included in that type of circuit.

[0162] Obtain at least one dimension corresponding to each component included in the initial circuit;

[0163] By combining at least one dimension corresponding to each component, at least one combination can be obtained;

[0164] For each combination, at least one component is sized according to the combination, and the initial circuit after sizing adjustment is processed by S903 and S904 to obtain the delay sensitivity corresponding to the combination.

[0165] For all combinations, the combination with the highest similarity between the latency sensitivity and the average latency sensitivity mentioned above is determined as the target combination;

[0166] The initial circuit with the target combination is identified as the target circuit.

[0167] When manufacturing processes differ (i.e., when feature dimensions differ), the dimensions of the same component (such as an amplifier or inverter) may differ. Multiple dimensions for a component refer to its dimensions across multiple feature dimensions, where each feature dimension corresponds to only one component dimension.

[0168] S907. Based on the target circuit, determine the replica circuit corresponding to the timing circuit.

[0169] It should be noted that in this step, based on method 1 in S906, the number of target circuits is 1, the number of replica circuits is 1, and the target circuit is the timing circuit in S907.

[0170] Based on method 2 in S906, there are multiple target circuits, multiple sequential circuits in S907, and multiple replica circuits. One target circuit is one sequential circuit in S907, and one sequential circuit corresponds to one replica circuit.

[0171] Based on method 3 in S906, there are multiple target circuits, multiple sequential circuits in S907, and multiple replica circuits. When a target circuit is obtained, the corresponding alternative circuit is a sequential circuit in S907, and a sequential circuit corresponds to a replica circuit.

[0172] Specifically, the transistor timing analysis results of the target circuit are obtained from the transistor timing analysis results of all candidate circuits.

[0173] Based on the transistor-level timing analysis results of the target circuit, determine the identifiers of at least three components included in the target circuit; and

[0174] Identify at least two connection lines for at least three components included in the target circuit;

[0175] Determine the replica circuit corresponding to the timing circuit based on the identifiers of at least three components and at least two connection lines.

[0176] Optionally, the identifiers of at least three components included in the target circuit can be determined in the STA report of the target circuit. Specifically, the STA report or transistor-level timing analysis results include the correspondence between the identifiers of at least three components and the identifiers of at least two connection lines connecting the at least three components. After determining the identifiers of the at least three components, the identifiers of the at least two connection lines connecting the at least three components can be determined based on the STA report or transistor-level timing analysis results.

[0177] Further, based on the identifiers of at least three components, at least three components are obtained from the component library; based on the identifiers of at least two connection lines, the wiring information of the target circuit is obtained from the wiring information corresponding to each of the pre-stored timing circuits, the wiring information including the length of the connection line corresponding to the identifier of the connection line and the identifier of the metal layer corresponding to the identifier of the connection line (indicating the metal layer where the connection line is located in the chip); based on the obtained at least three components and wiring information, circuit design is performed to obtain a replica circuit.

[0178] S908 controls the replica circuit to generate data signals and controls the crosstalk circuit to generate crosstalk signals, which are used to interfere with the data signals.

[0179] S909, The control measurement circuit measures the path delay of the replica circuit affected by crosstalk signal interference.

[0180] ​ The time delay measurement method provided in the embodiments has the same beneficial effects as the time delay measurement circuit provided in the above embodiments, and will not be described again here.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that various modifications and variations can still be made to the technical solutions described in the foregoing embodiments without departing from the spirit and scope of this application. Thus, if these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

[0182] In this application, the term "comprising" and its variations can refer to non-limiting inclusion; the term "or" and its variations can refer to "and / or". The terms "first", "second", etc., in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. In this application, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

Claims

1. A time delay measurement circuit, applied in a chip, characterized in that, The delay measurement circuit includes a measurement circuit, a replica circuit, and a crosstalk circuit; the chip also includes a timing circuit, the replica circuit being a copy circuit of the timing circuit, and the attribute information of the components included in the copy circuit is adjusted based on the gate-level delay of the timing circuit; The measurement circuit includes: a first flip-flop, a second flip-flop, and a processing circuit; the input terminal of the first flip-flop is connected to the output terminal of the processing circuit, the output terminal of the first flip-flop is connected to the input terminal of the replica circuit, the output terminal of the replica circuit is connected to the input terminal of the second flip-flop, and the output terminal of the second flip-flop is connected to the input terminal of the processing circuit; the replica circuit is also connected to the crosstalk circuit; the replica circuit is used to simulate the data signal in the timing circuit. The crosstalk circuit generates a crosstalk signal to interfere with the data signal. The measurement circuit measures the path delay of the replica circuit affected by the crosstalk signal, and the path delay of the replica circuit is used to predict the chip's delay or frequency. The replica circuit includes a first component, a second component, and a first connection line. The first connection line connects the first component and the second component, and the first connection line is a connection line whose interference value generated by the crosstalk signal is greater than or equal to a preset value. The crosstalk circuit includes a third component, a fourth component, and a second connection line. The second connection line connects the third component and the fourth component. The third component is connected to a component that provides a data signal to the first component. The number of crosstalk circuits is N, where N is an integer greater than or equal to 2. The second connection lines in the N crosstalk circuits are arranged in parallel, and the first connection lines are arranged in parallel between the second connection lines in the N crosstalk circuits. The routing shape of the first connection line and the second connection line in the chip is a preset zigzag shape, and the distance between the first connection line and each second connection line is less than or equal to a preset distance.

2. The time delay measurement circuit according to claim 1, characterized in that, The third component is the inverse logic device of the first component.

3. The time delay measurement circuit according to claim 1, characterized in that, Also includes: Crosstalk control circuit; The crosstalk control circuit is connected to both the crosstalk circuit and the replica circuit. The crosstalk control circuit is used to control the connection or disconnection of the crosstalk circuit and the replica circuit.

4. A time delay measurement method, characterized in that, Applied in a chip, the delay measurement circuit includes a measurement circuit, a replica circuit, and a crosstalk circuit. The chip also includes a timing circuit. The method includes: A replica circuit corresponding to the sequential circuit is determined; the replica circuit is a copy of the sequential circuit, and the attribute information of the components included in the copy circuit is adjusted based on the gate delay of the sequential circuit. The system controls the replica circuit to generate a data signal and controls the crosstalk circuit to generate a crosstalk signal, the crosstalk signal being used to interfere with the data signal. The measurement circuit is controlled to measure the path delay of the replica circuit affected by the crosstalk signal. The measurement circuit includes a first flip-flop, a second flip-flop, and a processing circuit. The input of the first flip-flop is connected to the output of the processing circuit, the output of the first flip-flop is connected to the input of the replica circuit, the output of the replica circuit is connected to the input of the second flip-flop, and the output of the second flip-flop is connected to the input of the processing circuit. The replica circuit includes a first component, a second component, and a first connecting line. The first connecting line connects the first component and the second component, and the first connecting line is a connecting line whose interference value generated by the crosstalk signal is greater than or equal to a preset value. The crosstalk... The circuit includes a third component, a fourth component, and a second connecting line; the second connecting line connects the third component and the fourth component; the third component is connected to a component that provides data signals to the first component; the number of crosstalk circuits is N, where N is an integer greater than or equal to 2; the second connecting lines in the N crosstalk circuits are arranged in parallel, and the first connecting lines are arranged in parallel between the second connecting lines in the N crosstalk circuits, and the routing shape of the first connecting line and the second connecting line in the chip is a preset broken line shape, and the distance between the first connecting line and each second connecting line is less than or equal to a preset distance.

5. The method according to claim 4, characterized in that, The step of determining the replica circuit corresponding to the timing circuit includes: Static timing analysis is performed on all sequential circuits to obtain a static timing analysis (STA) report for each sequential circuit. The STA report includes at least the gate-level delay of each sequential circuit. Based on the gate-level delay of each sequential circuit, at least one alternative circuit is determined among all the sequential circuits; Timing analysis is performed on each candidate circuit to obtain the corresponding transistor-level timing analysis results for each candidate circuit; wherein, the transistor-level timing analysis results include at least the transistor-level delay and the operating parameters of each candidate circuit; Determine the delay sensitivity of each candidate circuit based on its transistor delay and operating parameters. Based on the delay sensitivity of each candidate circuit, all candidate circuits are classified to obtain at least one class of circuits; Determine the target circuit from at least one class of circuits; Based on the target circuit, determine the replica circuit corresponding to the timing circuit.

6. The method according to claim 5, characterized in that, The timing analysis results also include the identifiers of each component and each connection line in the candidate circuit; determining the replica circuit corresponding to the timing circuit based on the target circuit includes: Obtain the transistor-level timing analysis results of the target circuit from the transistor-level timing analysis results corresponding to all candidate circuits; Based on the transistor-level timing analysis results of the target circuit, determine the identifiers of at least three components included in the target circuit; and Identify the identifiers of at least two connection lines that connect at least three components included in the target circuit; The replica circuit corresponding to the timing circuit is determined based on the identifiers of the at least three components and the identifiers of the at least two connection lines.

7. A chip, characterized in that, The delay measurement circuit includes any one of claims 1-3 above.

8. An electronic device, characterized in that, The electronic device includes the chip described in claim 7.

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