Memory system resource isolation and monitoring table resolution method, apparatus, and program product

Abstract

The present disclosure provides a memory system resource isolation and monitoring table parsing network monitoring method, device, electronic equipment, medium and program product, the method comprises: obtaining the memory system resource isolation and monitoring table; obtaining the resource identifier and the processor set identifier corresponding to the resource identifier from the memory system resource isolation and monitoring table; determining whether the processor set identifier exists in the specified data set, the specified data set includes the processor set identifier corresponding to the resource identifier of the parsing success; if the processor set identifier exists in the specified data set, the resource identifier is stored in association with the processor set identifier.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to a method, apparatus, electronic device, medium, and program product for memory system resource isolation and monitoring table parsing network monitoring. Background Technology

[0002] Memory System Resource Partitioning and Monitoring (MPAM) tables can partition cache resources from a hardware perspective to address performance degradation of critical services or overall system performance caused by shared resource contention during CPU memory access. This is particularly important for the deployment of mixed services. The operating system (e.g., Linux) kernel obtains MPAM resource information by parsing the MPAM table issued by the Basic Input / Output System (BIOS). Since the resource information contained in the MPAM table is related to the number of Central Processing Units (CPUs) and NUMA (Non-Uniform Memory Access) nodes, the more CPUs and NUMA nodes a computing device (e.g., a server) contains, the more complex and time-consuming the MPAM table parsing becomes. This leads to longer startup times for the computing device, impacting service performance and user experience. Summary of the Invention

[0003] To address the problems in related technologies, embodiments of this disclosure provide a method, apparatus, electronic device, medium, and program product for memory system resource isolation and monitoring table parsing network monitoring.

[0004] In a first aspect, this disclosure provides a method for memory system resource isolation and monitoring table parsing, including:

[0005] Obtain the memory system resource isolation and monitoring table;

[0006] Obtain the resource identifier and the processor set identifier corresponding to the resource identifier from the memory system resource isolation and monitoring table;

[0007] Determine whether the processor set identifier exists in a specified data set, wherein the specified data set includes the processor set identifier corresponding to the successfully parsed resource identifier;

[0008] If the processor set identifier exists in the specified data set, the resource identifier is stored in association with the processor set identifier.

[0009] According to embodiments of this disclosure, the method further includes:

[0010] If the processor set identifier does not exist in the specified data set, then the processor attribute topology table is searched to determine whether the processor set identifier exists in the processor attribute topology table.

[0011] According to embodiments of this disclosure, the method further includes:

[0012] If the processor set identifier exists in the processor attribute topology table, then the processor set identifier is added to the specified data set, and the resource identifier is stored in association with the processor set identifier.

[0013] According to embodiments of this disclosure, the method further includes:

[0014] If the processor set identifier corresponding to the resource identifier does not exist in the processor attribute topology table, the parsing of the resource identifier is skipped.

[0015] According to embodiments of this disclosure, the method further includes, after storing the resource identifier in association with the processor set identifier, or skipping the parsing of the resource identifier:

[0016] Obtain another resource identifier and the processor set identifier corresponding to the other resource identifier from the memory system resource isolation and monitoring table;

[0017] Determine whether a processor set identifier corresponding to the other resource identifier exists in the specified data set;

[0018] If a processor set identifier corresponding to the other resource identifier exists in the specified data set, then the other resource identifier is stored in association with the processor set identifier.

[0019] According to embodiments of this disclosure, the process of looking up the processor attribute topology table includes looking up the processor attribute topology table in the basic input / output system firmware.

[0020] According to embodiments of this disclosure, the resources include a cache region or a memory region, and the processor set includes NUMA nodes.

[0021] According to embodiments of this disclosure, wherein:

[0022] The specified data set is implemented as variables accessed by the operating system kernel; and / or

[0023] The specified data set is stored in memory.

[0024] According to embodiments of this disclosure, storing the resource identifier in association with the processor set identifier includes:

[0025] The resource identifier is stored in the structure corresponding to the processor set identifier.

[0026] According to embodiments of this disclosure, obtaining the memory system resource isolation and monitoring table includes obtaining the memory system resource isolation and monitoring table from the basic input / output system firmware through the operating system kernel.

[0027] Secondly, embodiments of this disclosure provide a memory system resource isolation and monitoring table parsing apparatus, comprising:

[0028] The first acquisition module is configured to acquire the memory system resource isolation and monitoring table;

[0029] The second acquisition module is configured to acquire a resource identifier and a processor set identifier corresponding to the resource identifier from the memory system resource isolation and monitoring table.

[0030] The determination module is configured to determine whether the processor set identifier exists in a specified data set, wherein the specified data set includes the processor set identifier corresponding to the successfully parsed resource identifier;

[0031] A first storage module is configured to store the resource identifier in association with the processor set identifier if the processor set identifier exists in the specified data set.

[0032] According to embodiments of this disclosure, the apparatus further includes:

[0033] The lookup module is configured to search the processor attribute topology table to determine whether the processor set identifier exists in the processor attribute topology table if the processor set identifier does not exist in the specified data set.

[0034] According to embodiments of this disclosure, the apparatus further includes:

[0035] The second storage module is configured to add the processor set identifier to the specified data set and store the resource identifier in association with the processor set identifier if the processor set identifier exists in the processor attribute topology table.

[0036] According to embodiments of this disclosure, the apparatus further includes:

[0037] The skip module is configured to skip parsing the resource identifier if the processor set identifier corresponding to the resource identifier does not exist in the processor attribute topology table.

[0038] According to embodiments of this disclosure, after storing the resource identifier in association with the processor set identifier, or skipping the parsing of the resource identifier:

[0039] The second acquisition module first obtains another resource identifier and the processor set identifier corresponding to the other resource identifier from the memory system resource isolation and monitoring table;

[0040] The determining module determines whether a processor set identifier corresponding to the other resource identifier exists in the specified data set.

[0041] If the first storage module stores the other resource identifier in association with the processor set identifier if there is a processor set identifier in the specified data set.

[0042] According to embodiments of this disclosure, the process of looking up the processor attribute topology table includes looking up the processor attribute topology table in the basic input / output system firmware.

[0043] According to embodiments of this disclosure, the resources include a cache region or a memory region, and the processor set includes NUMA nodes.

[0044] According to embodiments of this disclosure, wherein:

[0045] The specified data set is implemented as variables accessed by the operating system kernel; and / or

[0046] The specified data set is stored in memory.

[0047] According to embodiments of this disclosure, storing the resource identifier in association with the processor set identifier includes:

[0048] The resource identifier is stored in the structure corresponding to the processor set identifier.

[0049] According to embodiments of this disclosure, obtaining the memory system resource isolation and monitoring table includes obtaining the memory system resource isolation and monitoring table from the basic input / output system firmware through the operating system kernel.

[0050] Thirdly, embodiments of this disclosure provide an electronic device including a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method as described in any of the first aspects.

[0051] Fourthly, this disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any of the first aspects.

[0052] Fifthly, this disclosure provides a computer program product including computer instructions that, when executed by a processor, implement the method as described in any of the first aspects.

[0053] According to the technical solution provided in the embodiments of this disclosure, the processor set identifier corresponding to the successfully parsed resource identifier is stored in a specified data set. When parsing the resource identifier, the specified data set is searched first. If the corresponding processor set identifier exists in the specified data set, there is no need to search the processor attribute topology table, thereby significantly improving the parsing efficiency of the memory system resource isolation and monitoring table and optimizing the startup speed of the operating system.

[0054] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0055] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0056] Figure 1 A schematic diagram of a NUMA architecture according to an embodiment of the present disclosure is shown.

[0057] Figure 2 An example of an MPAM according to an embodiment of this disclosure is shown.

[0058] Figure 3 A flowchart illustrating a memory system resource isolation and monitoring table parsing method according to an embodiment of the present disclosure is shown.

[0059] Figure 4 An overall flowchart of a memory system resource isolation and monitoring table parsing method according to an embodiment of the present disclosure is shown.

[0060] Figure 5 A structural block diagram of a memory system resource isolation and monitoring table parsing apparatus according to an embodiment of the present disclosure is shown.

[0061] Figure 6 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0062] Figure 7 A schematic diagram of the structure of a computer system suitable for implementing the method according to embodiments of the present disclosure is shown. Detailed Implementation

[0063] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0064] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0065] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0066] As mentioned above, the kernel of an operating system (e.g., Linux) obtains MPAM resource information by parsing the MPAM table issued by the BIOS. Since the resource information contained in the MPAM table is related to the number of CPUs and NUMA nodes, the more CPUs and NUMA nodes a computing device contains, the more complex and time-consuming the MPAM table parsing becomes. This leads to longer startup times for the computing device, affecting the performance and user experience of providing services to users.

[0067] Figure 1 A schematic diagram of a NUMA architecture according to an embodiment of the present disclosure is shown.

[0068] like Figure 1 As shown, a computing device may include one or more CPU sockets, for example, Figure 1 The diagram shows two CPU sockets, socket 0 and socket 1, each capable of housing multiple physical CPU cores (CPUs). As an example, socket 0 includes CPUs 1 through 8. Using a NUMA architecture, the CPUs in socket 0 are grouped into two NUMA nodes: NUMA node 1 and NUMA node 2. NUMA node 1 includes CPUs 1 through 4, and NUMA node 2 includes CPUs 5 through 8. Socket 1 includes CPUs 9 through 16. Using a NUMA architecture, the CPUs in socket 1 are grouped into two NUMA nodes: NUMA node 3 and NUMA node 4. NUMA node 3 includes CPUs 9 through 12, and NUMA node 4 includes CPUs 13 through 16.

[0069] According to embodiments of this disclosure, resources can be allocated to applications according to NUMA distribution, thereby isolating the resources required by the applications. According to embodiments of this disclosure, resources may include, but are not limited to, cache regions or memory regions. For example, different NUMA nodes in a CPU socket can share the cache space of that CPU socket. According to embodiments of this disclosure, the entire cache space shared by multiple NUMA nodes can be divided into multiple cache regions, and one or more cache regions can be allocated to each application, thereby achieving cache isolation between multiple NUMA nodes. As another example, the entire memory space shared by multiple NUMA nodes can be divided into multiple memory regions, and one or more memory regions can be allocated to each application, thereby achieving memory isolation between multiple NUMA nodes.

[0070] For example, the cache space shared by NUMA nodes in socket 0 is divided into four cache regions, namely CA0 to CA3. It is understood that although this disclosure uses four cache regions as an example, the cache space can also be divided into more or fewer cache regions. Furthermore, this disclosure uses the allocation of a cache region corresponding to a CPU socket to an application running on a NUMA node in that CPU socket as an example; however, it is also possible to allocate a cache region corresponding to a CPU socket to an application running on a NUMA node in another CPU socket.

[0071] According to embodiments of this disclosure, the cache region can be a cache way, but is not limited to this. The cache region can be divided into other forms according to actual needs.

[0072] According to embodiments of this disclosure, a Cache Area ID (CAID) is assigned to each cache area, and the identifier of the processor set corresponding to each CAID is recorded in the MPAM table. According to embodiments of this disclosure, the processor set can be a NUMA node, but is not limited thereto. A processor set can be obtained by partitioning multiple processors according to other rules, and the processor set may include one or more processors.

[0073] For example, the shared memory space of NUMA nodes in socket 0 can be divided into four memory regions, namely MA0 to MA3. It is understood that although this disclosure uses four memory regions as an example, the memory space can also be divided into more or fewer memory regions. Furthermore, this disclosure uses the allocation of a memory region corresponding to a CPU socket to an application running on a NUMA node in that CPU socket as an example; however, it is also possible to allocate a memory region corresponding to a CPU socket to an application running on a NUMA node in another CPU socket.

[0074] According to embodiments of this disclosure, a memory region identifier (MA ID) is assigned to each memory region, and the identifier of the processor set corresponding to each MA ID is recorded in the MPAM table.

[0075] Figure 2 An example of an MPAM according to an embodiment of this disclosure is shown. For simplicity, a cache region is used as an example for illustration.

[0076] exist Figure 2 In the example, the processor set is a NUMA node, and correspondingly, the processor set identifier is the NUMA node identifier (NUMA ID). It is important to note that... Figure 2 This illustrates the mapping between cache region identifier (CA ID) and processor set identifier (NUMA ID), but it does not mean that the CA ID and the corresponding NUMA ID must be identical. Figure 2 The table format shown is used for storage. For example, the NUMA ID can also be stored in a specified field of the record corresponding to the CA ID in the MPAM table.

[0077] like Figure 2 As shown, the CA IDs of the four cache regions obtained by dividing the cache space of socket 0 are CA0, CA1, CA2, and CA3, and their corresponding NUMA IDs are NUMA0, NUMA1, NUMA1, and NUMA0, respectively. That is, cache regions CA0 and CA3 are assigned to the application running on the NUMA node NUMA0, and cache regions CA1 and CA2 are assigned to the application running on the NUMA node NUMA1.

[0078] Understandable. Figure 2 As an example, the MPAM table shows the CA IDs and their corresponding NUMA IDs of the four cache regions obtained by partitioning the cache space of socket 0. However, the MPAM table can also record the CA IDs and their corresponding NUMA IDs of other cache regions. For example, it can also record the CA IDs and their corresponding NUMA IDs of the cache regions obtained by partitioning the cache space of socket 1, and so on.

[0079] Figure 3 A flowchart illustrating a memory system resource isolation and monitoring table parsing method according to an embodiment of the present disclosure is shown.

[0080] like Figure 3 As shown, the memory system resource isolation and monitoring table parsing method includes the following steps S301–S304:

[0081] In step S301, the memory system resource isolation and monitoring table is obtained;

[0082] In step S302, the resource identifier and the processor set identifier corresponding to the resource identifier are obtained from the memory system resource isolation and monitoring table;

[0083] In step S303, it is determined whether the processor set identifier exists in the specified data set, wherein the specified data set includes the processor set identifier corresponding to the successfully parsed resource identifier;

[0084] In step S304, if the processor set identifier exists in the specified data set, the resource identifier is stored in association with the processor set identifier.

[0085] According to embodiments of this disclosure, the resources include a cache region or a memory region, and the processor set includes NUMA nodes.

[0086] According to embodiments of this disclosure, obtaining the memory system resource isolation and monitoring table includes obtaining the memory system resource isolation and monitoring table from the basic input / output system firmware through the operating system kernel. Specifically, after the operating system kernel of the computing device starts, the operating system kernel loads the MPAM driver and obtains the MPAM table issued by the BIOS.

[0087] According to embodiments of this disclosure, a resource identifier and a processor set identifier corresponding to the resource identifier can be obtained from the memory system resource isolation and monitoring table.

[0088] According to embodiments of this disclosure, resource identifiers can be information used to distinguish different resources, such as identifiers. For example, different cache region identifiers can be assigned to different cache regions to distinguish them, and different memory region identifiers can be assigned to different memory regions to distinguish them, and so on.

[0089] According to embodiments of this disclosure, the processor set identifier can be information used to distinguish different processor sets, such as an identifier. For example, different NUMA node identifiers can be assigned to different NUMA nodes to distinguish them.

[0090] According to embodiments of this disclosure, a processor set identifier corresponding to a successfully parsed resource identifier can be stored in a specified data set. After obtaining the resource identifier and the processor set identifier corresponding to the resource identifier, it is determined whether the processor set identifier exists in the specified data set. If the processor set identifier exists in the specified data set, the resource identifier is stored in association with the processor set identifier.

[0091] If the processor set identifier does not exist in the specified data set, the processor attribute topology table is searched to determine if the processor set identifier exists in the processor attribute topology table. If the processor set identifier exists in the processor attribute topology table, the processor set identifier is added to the specified data set, and the resource identifier is stored in association with the processor set identifier. Storing the resource identifier in association with the processor set identifier includes storing the resource identifier in a structure corresponding to the processor set identifier.

[0092] If the processor set identifier corresponding to the resource identifier does not exist in the processor attribute topology table, the parsing of the resource identifier is skipped.

[0093] For example, in Figure 2 In the MPAM table shown, the first record is parsed to obtain the resource identifier CA0 and the processor set identifier NUMA0 corresponding to the resource identifier.

[0094] Then, the specified data set is searched. Since this is the first record parsed in the MPAM table, NUMA0 does not exist in the specified data set. Therefore, the Processor Properties Topology Table (PPTT) is searched to determine whether the processor set identifier, i.e., whether NUMA0 exists, exists in the processor properties topology table. According to an embodiment of this disclosure, the PPTT is stored in the BIOS, and the search for the PPTT includes searching for the PPTT in the BIOS.

[0095] PPTT is a table used to describe CPUs, caches, etc. If NUMA0 exists in PPTT, it means that NUMA0 is a NUMA node existing in the computing device. Therefore, NUMA0 is added to the specified data set, and CA0 is stored in association with NUMA0. For example, the resource identifier is stored in the structure corresponding to NUMA0, and the resolution of CA0 is successful.

[0096] According to embodiments of this disclosure, a corresponding structure can be created for each processor set identifier. Each structure includes multiple fields, and resource identifiers corresponding to the processor set identifier can be stored in these fields. When a processor set has multiple corresponding resources, the corresponding resource identifiers can be stored in the multiple fields of the structure corresponding to the processor set identifier. For example, the structure corresponding to the processor set identifier may include field 1, field 2, field 3, etc., and the resource identifiers corresponding to the processor set identifier may include S1, S2, and S3. Therefore, S1 can be stored in field 1, S2 in field 2, and S3 in field 3.

[0097] According to embodiments of this disclosure, if NUMA0 does not exist in PPTT, it means that NUMA0 is not a NUMA node present in the computing device, therefore the resolution of CA0 fails and the resolution of CA0 is skipped.

[0098] According to embodiments of this disclosure, the designated data set is implemented as a variable accessed by the operating system kernel; and / or the designated data set is stored in memory. According to embodiments of this disclosure, the designated data set is implemented as a linked list.

[0099] According to embodiments of this disclosure, after storing the resource identifier in association with the processor set identifier, or skipping the parsing of the resource identifier: obtaining another resource identifier and the processor set identifier corresponding to the other resource identifier from the memory system resource isolation and monitoring table; determining whether a processor set identifier corresponding to the other resource identifier exists in a specified data set; if a processor set identifier corresponding to the other resource identifier exists in the specified data set, then storing the other resource identifier in association with the processor set identifier.

[0100] For example, after successfully resolving CA0 and storing CA0 in the structure corresponding to NUMA0, or after skipping the resolution of CA0 due to resolution failure, the data can be retrieved. Figure 2 The next record in the MPAM table shown includes the resource identifier CA1 and the corresponding processor set identifier NUMA1.

[0101] If NUMA1 is not found in the specified data set, it is then searched for in the BIOS's PPTT. If NUMA1 exists in the PPTT, it is added to the specified data set, and CA1 is stored in the structure corresponding to NUMA1. For example, CA1 is stored in field 1 of the structure corresponding to NUMA1, and the parsing of CA1 is successful.

[0102] As can be seen from the embodiments of this disclosure, the successfully parsed resource identifiers include resource identifiers whose corresponding processor identifiers exist in a specified data set and / or exist in PPTT.

[0103] Then, obtain Figure 2 The next record in the MPAM table shown includes the resource identifier CA2 and the corresponding processor set identifier NUMA1.

[0104] If a search is performed in the specified data set and NUMA1 is found, then CA2 is stored in field 2 of the structure corresponding to NUMA1, and the parsing of CA2 is successful.

[0105] The remaining records of MPAM are parsed in a similar manner until all records in the MPAM table have been parsed.

[0106] According to the embodiments of this disclosure, since the efficiency of the operating system kernel accessing the specified data set is much higher than the efficiency of searching for the PPTT, the processor set identifier corresponding to the successfully parsed resource identifier is stored in the specified data set. When parsing the resource identifier, the specified data set is searched first. If the corresponding processor set identifier exists in the specified data set, there is no need to search for the PPTT again, thereby significantly improving the parsing efficiency of the MPAM table and optimizing the startup speed of the operating system.

[0107] Figure 4 An overall flowchart of a memory system resource isolation and monitoring table parsing method according to an embodiment of the present disclosure is shown.

[0108] like Figure 4 As shown, after the operating system kernel loads the MPAM driver, it obtains the MPAM table issued by the BIOS and begins parsing the MPAM table resources.

[0109] Retrieve the resource identifier and the processor set identifier corresponding to the resource identifier from the MPAM table. Search for the processor set identifier corresponding to the resource identifier in the specified data set. If the specified set contains a processor set identifier corresponding to the resource identifier, store the resource identifier of the resource in association with the corresponding processor set identifier. The parsing of the resource identifier is successful.

[0110] If the specified set does not contain a processor set identifier corresponding to the resource identifier, the corresponding processor set identifier is searched in the PPTT. If a processor set identifier corresponding to the resource identifier is found in the PPTT table, it is added to the specified data set, and the resource identifier is stored in association with its corresponding processor set identifier. The parsing of the resource identifier is considered successful. If no processor set identifier corresponding to the resource identifier is found in the PPTT table, the parsing of the resource identifier fails, and the parsing of the resource identifier is skipped.

[0111] After a resource identifier resolution is successful or unsuccessful, another resource identifier and its corresponding processor set identifier are obtained from the MPAM table. The above resolution process is repeated until all resource identifiers in the MPAM table are resolved.

[0112] Figure 5 A structural block diagram of a memory system resource isolation and monitoring table parsing apparatus according to an embodiment of the present disclosure is shown. This apparatus can be implemented as part or all of an electronic device through software, hardware, or a combination of both.

[0113] like Figure 5 As shown, the memory system resource isolation and monitoring table parsing device 500 includes:

[0114] The first acquisition module 501 is configured to acquire the memory system resource isolation and monitoring table;

[0115] The second acquisition module 502 is configured to acquire a resource identifier and a processor set identifier corresponding to the resource identifier from the memory system resource isolation and monitoring table.

[0116] The determination module 503 is configured to determine whether the processor set identifier exists in a specified data set, wherein the specified data set includes the processor set identifier corresponding to the successfully parsed resource identifier;

[0117] The first storage module 504 is configured to store the resource identifier in association with the processor set identifier if the processor set identifier exists in the specified data set.

[0118] According to embodiments of this disclosure, the device 500 further includes:

[0119] The lookup module 505 is configured to look up the processor attribute topology table to determine whether the processor set identifier exists in the processor attribute topology table if the processor set identifier does not exist in the specified data set.

[0120] According to embodiments of this disclosure, the device 500 further includes:

[0121] The second storage module 506 is configured to add the processor set identifier to the specified data set and store the resource identifier in association with the processor set identifier if the processor set identifier exists in the processor attribute topology table.

[0122] According to embodiments of this disclosure, the device 500 further includes:

[0123] Skip module 507 is configured to skip parsing the resource identifier if the processor set identifier corresponding to the resource identifier does not exist in the processor attribute topology table.

[0124] According to embodiments of this disclosure, after storing the resource identifier in association with the processor set identifier, or skipping the parsing of the resource identifier:

[0125] The second acquisition module 502 first acquires another resource identifier and the processor set identifier corresponding to the other resource identifier from the memory system resource isolation and monitoring table;

[0126] The determining module 503 determines whether there is a processor set identifier in the specified data set that corresponds to the other resource identifier;

[0127] If the first storage module 504 stores the other resource identifier in association with the processor set identifier if there is a processor set identifier in the specified data set.

[0128] According to embodiments of this disclosure, the process of looking up the processor attribute topology table includes looking up the processor attribute topology table in the basic input / output system firmware.

[0129] According to embodiments of this disclosure, the resources include a cache region or a memory region, and the processor set includes NUMA nodes.

[0130] According to embodiments of this disclosure, wherein:

[0131] The specified data set is implemented as variables accessed by the operating system kernel; and / or

[0132] The specified data set is stored in memory.

[0133] According to embodiments of this disclosure, storing the resource identifier in association with the processor set identifier includes:

[0134] The resource identifier is stored in the structure corresponding to the processor set identifier.

[0135] According to embodiments of this disclosure, obtaining the memory system resource isolation and monitoring table includes obtaining the memory system resource isolation and monitoring table from the basic input / output system firmware through the operating system kernel.

[0136] This disclosure also discloses an electronic device. Figure 6 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0137] like Figure 6 As shown, the electronic device includes a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method according to embodiments of the present disclosure.

[0138] This disclosure provides a method for memory system resource isolation and monitoring table parsing, including:

[0139] Obtain the memory system resource isolation and monitoring table;

[0140] Obtain the resource identifier and the processor set identifier corresponding to the resource identifier from the memory system resource isolation and monitoring table;

[0141] Determine whether the processor set identifier exists in a specified data set, wherein the specified data set includes the processor set identifier corresponding to the successfully parsed resource identifier;

[0142] If the processor set identifier exists in the specified data set, the resource identifier is stored in association with the processor set identifier.

[0143] According to embodiments of this disclosure, the method further includes:

[0144] If the processor set identifier does not exist in the specified data set, then the processor attribute topology table is searched to determine whether the processor set identifier exists in the processor attribute topology table.

[0145] According to embodiments of this disclosure, the method further includes:

[0146] If the processor set identifier exists in the processor attribute topology table, then the processor set identifier is added to the specified data set, and the resource identifier is stored in association with the processor set identifier.

[0147] According to embodiments of this disclosure, the method further includes:

[0148] If the processor set identifier corresponding to the resource identifier does not exist in the processor attribute topology table, the parsing of the resource identifier is skipped.

[0149] According to embodiments of this disclosure, the method further includes, after storing the resource identifier in association with the processor set identifier, or skipping the parsing of the resource identifier:

[0150] Obtain another resource identifier and the processor set identifier corresponding to the other resource identifier from the memory system resource isolation and monitoring table;

[0151] Determine whether a processor set identifier corresponding to the other resource identifier exists in the specified data set;

[0152] If a processor set identifier corresponding to the other resource identifier exists in the specified data set, then the other resource identifier is stored in association with the processor set identifier.

[0153] According to embodiments of this disclosure, the process of looking up the processor attribute topology table includes looking up the processor attribute topology table in the basic input / output system firmware.

[0154] According to embodiments of this disclosure, the resources include a cache region or a memory region, and the processor set includes NUMA nodes.

[0155] According to embodiments of this disclosure, wherein:

[0156] The specified data set is implemented as variables accessed by the operating system kernel; and / or

[0157] The specified data set is stored in memory.

[0158] According to embodiments of this disclosure, storing the resource identifier in association with the processor set identifier includes:

[0159] The resource identifier is stored in the structure corresponding to the processor set identifier.

[0160] According to embodiments of this disclosure, obtaining the memory system resource isolation and monitoring table includes obtaining the memory system resource isolation and monitoring table from the basic input / output system firmware through the operating system kernel.

[0161] Figure 7 A schematic diagram of the structure of a computer system suitable for implementing the method according to embodiments of the present disclosure is shown.

[0162] like Figure 7 As shown, the computer system includes a processing unit that can execute various methods described above based on a program stored in a read-only memory (ROM) or a program loaded from a storage portion into a random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer system. The processing unit, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0163] The following components are connected to the I / O interface: input sections including keyboards, mice, etc.; output sections including cathode ray tubes (CRTs), liquid crystal displays (LCDs), and speakers; storage sections including hard disks, etc.; and communication sections including network interface cards such as LAN cards and modems. The communication section performs communication processes via a network such as the Internet. Drives are also connected to the I / O interface as needed. Removable media, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive as needed so that computer programs read from them can be installed into the storage section as needed. The processing unit can be implemented as a CPU, GPU, TPU, FPGA, NPU, etc.

[0164] In particular, according to embodiments of this disclosure, the methods described above can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program containing program code for performing the methods described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium.

[0165] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0166] The units or modules described in the embodiments of this disclosure can be implemented in software or programmable hardware. The described units or modules can also be located in a processor, and the names of these units or modules do not necessarily constitute a limitation on the unit or module itself.

[0167] In another aspect, this disclosure also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system described above; or it may be a standalone computer-readable storage medium not assembled into a device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to perform the methods described in this disclosure.

[0168] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A method for memory system resource isolation and monitoring table parsing, comprising: Obtain the memory system resource isolation and monitoring table; Obtain the resource identifier and the processor set identifier corresponding to the resource identifier from the memory system resource isolation and monitoring table; Determine whether the processor set identifier exists in a specified data set, wherein the specified data set includes the processor set identifier corresponding to the successfully parsed resource identifier; If the processor set identifier exists in the specified data set, the resource identifier is stored in association with the processor set identifier; If the processor set identifier does not exist in the specified data set, then the processor attribute topology table is searched to determine whether the processor set identifier exists in the processor attribute topology table; If the processor set identifier exists in the processor attribute topology table, then the processor set identifier is added to the specified data set, and the resource identifier is stored in association with the processor set identifier.

2. The method according to claim 1, further comprising: If the processor set identifier corresponding to the resource identifier does not exist in the processor attribute topology table, the parsing of the resource identifier is skipped.

3. The method of claim 2, further comprising, after storing the resource identifier in association with the processor set identifier, or skipping the parsing of the resource identifier: Obtain another resource identifier and the processor set identifier corresponding to the other resource identifier from the memory system resource isolation and monitoring table; Determine whether a processor set identifier corresponding to the other resource identifier exists in the specified data set; If a processor set identifier corresponding to the other resource identifier exists in the specified data set, then the other resource identifier is stored in association with the processor set identifier.

4. The method according to claim 1, wherein, The process of finding the processor attribute topology table includes searching for the processor attribute topology table in the basic input / output system firmware.

5. The method according to claim 1, wherein, The resources include cache regions or memory regions, and the processor set includes NUMA nodes.

6. The method according to claim 1, wherein: The specified data set is implemented as variables accessed by the operating system kernel; and / or The specified data set is stored in memory.

7. The method according to claim 1, wherein, The storage of the resource identifier associated with the processor set identifier includes: The resource identifier is stored in the structure corresponding to the processor set identifier.

8. The method according to claim 1, wherein, The step of obtaining the memory system resource isolation and monitoring table includes obtaining the memory system resource isolation and monitoring table from the basic input / output system firmware through the operating system kernel.

9. A memory system resource isolation and monitoring table parsing device, comprising: The first acquisition module is configured to acquire the memory system resource isolation and monitoring table; The second acquisition module is configured to acquire a resource identifier and a processor set identifier corresponding to the resource identifier from the memory system resource isolation and monitoring table. The determination module is configured to determine whether the processor set identifier exists in a specified data set, wherein the specified data set includes the processor set identifier corresponding to the successfully parsed resource identifier; A first storage module is configured to store the resource identifier in association with the processor set identifier if the processor set identifier exists in the specified data set; The lookup module is configured to search the processor attribute topology table to determine whether the processor set identifier exists in the processor attribute topology table if the processor set identifier does not exist in the specified data set. The second storage module is configured to add the processor set identifier to the specified data set and store the resource identifier in association with the processor set identifier if the processor set identifier exists in the processor attribute topology table.

10. An electronic device, characterized in that, The method includes a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium storing computer instructions thereon, characterized in that, When executed by a processor, the computer instructions implement the steps of the method described in any one of claims 1 to 8.

12. A computer program product comprising computer instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 8.

Images