Data driver and display device

Abstract

The present application discloses a data driver and a display device. The data driver includes a cache module and at least two data processing branches. The cache module synchronizes the picture data corresponding to at least two rows of sub-pixels. The at least two data processing branches can synchronously output corresponding data signals to at least two rows of sub-pixels. In this way, at least two rows of sub-pixels can be charged simultaneously, effectively alleviating the technical problem of insufficient charging time under higher-frequency display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a data driver and a display device. Background Art

[0002] Currently, the mainstream, high-volume refresh rate for mass production is 144Hz. However, with the advancement of display technology and the diversification of customer application scenarios, the demand for higher-frequency displays is growing. However, during the development of higher-frequency displays, it was discovered that as the refresh rate increases, the charging time of sub-pixels becomes increasingly limited, which can easily lead to display issues such as poor visual quality due to insufficient charging time. Summary of the Invention

[0003] The present application provides a data driver and a display device to alleviate the technical problem of insufficient charging time under higher frequency display.

[0004] In a first aspect, the present application provides a data driver comprising a cache module and at least two data processing branches, the cache module being used to synchronously output picture data corresponding to at least two rows of sub-pixels; each data processing branch being connected to the cache module and a group of data lines, and the at least two data processing branches being used to synchronously output corresponding data signals to at least two rows of sub-pixels based on the received picture data.

[0005] In some embodiments, the cache module includes at least two line buffers connected in series, the output end of each line buffer is correspondingly connected to the input end of a data processing branch, and each line buffer is used to temporarily store image data corresponding to a row of sub-pixels.

[0006] In some embodiments, the data driver further includes a register storing a selection parameter, wherein the selection parameter is used to control the number of data processing branches in an operating state and / or the number of line buffers in an operating state.

[0007] In some embodiments, the data driver further includes a counter connected to the cache module, and the counter is used to count the number of rows of screen data temporarily stored in the cache module to trigger the cache module to output.

[0008] In some embodiments, each data processing branch includes a data latch, a digital-to-analog converter, and a data mapping module. The input end of the data latch is connected to the cache module for capturing the image data of the corresponding row sub-pixels row by row; the input end of the digital-to-analog converter is connected to the output end of the data latch; the input end of the data mapping module is connected to the output end of the digital-to-analog converter, and each output end of the data mapping module is connected to a group of data lines for outputting corresponding data signals in the arranged order.

[0009] In some embodiments, the data driver further includes an amplifying module, each input end of the amplifying module is correspondingly connected to the output ends of at least two data processing branches, and each output end of the amplifying module is correspondingly connected to at least two groups of data lines.

[0010] In a second aspect, the present application provides a display device, which includes a data driver according to at least one of the above embodiments, and the data driver is applied to higher frequency display.

[0011] In some embodiments, the display device further includes a plurality of sub-pixels distributed in an array, at least one group of scan lines, and at least two groups of data lines, each group of scan lines being connected to at least two rows of sub-pixels; each group of data lines being connected to one row of the at least two rows of sub-pixels to synchronously provide data signals to the at least two rows of sub-pixels.

[0012] In some embodiments, the number of rows of sub-pixels connected to each group of scan lines is the same as the number of groups of data lines.

[0013] In some embodiments, at least two groups of data lines include odd data lines as one group of data lines and even data lines as the other group of data lines, and the odd data lines and the even data lines are alternately arranged in sequence along the first direction; each column of sub-pixels includes odd sub-pixels and even sub-pixels alternately arranged along the second direction, the odd sub-pixels are connected to one of the odd data lines or the even data lines, and the even sub-pixels are connected to the other of the odd data lines or the even data lines.

[0014] In some embodiments, the display device further includes a start signal line and at least two gate drive circuits, the start signal line is connected to the at least two gate drive circuits; each group of scan lines includes at least two adjacent scan lines, one of the scan lines in each group is connected to one of the at least two rows of sub-pixels and one of the two gate drive circuits, and the other of the scan lines in each group is connected to the other row of the at least two rows of sub-pixels and the other of the two gate drive circuits.

[0015] The data driver and display device provided in the present application synchronize the picture data corresponding to at least two rows of sub-pixels through a cache module, and at least two data processing branches can synchronously output corresponding data signals to at least two rows of sub-pixels. In this way, at least two rows of sub-pixels can be charged simultaneously. Compared with the row-by-row charging in traditional technology, the charging time required at the same refresh frequency is shorter, effectively alleviating the technical problem of insufficient charging time under higher-frequency display. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0017] Figure 1Schematic diagram of the structure of a display device in related technology.

[0018] Figure 2 for Figure 1 Schematic diagram of driving timing of the display device shown.

[0019] Figure 3 for Figure 1 Schematic diagram of the data driver structure.

[0020] Figure 4 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0021] Figure 5 for Figure 4 A driving timing diagram of the display device shown.

[0022] Figure 6 for Figure 4 Schematic diagram of the data driver structure.

[0023] Figure 7 This is a first working diagram of the register selection parameters provided in an embodiment of the present application.

[0024] Figure 8 This is a second working diagram of the register selection parameters provided in an embodiment of the present application.

[0025] Figure 9 A schematic diagram of the operation of the cache module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0027] Figure 1 1 is a schematic diagram of the structure of a display device in the related art, which includes a plurality of scan lines, a plurality of data lines, arrayed sub-pixels, and a data driver 100. The sub-pixels may be red sub-pixels R, blue sub-pixels B, or green sub-pixels G.

[0028] Each scan line is connected to a row of sub-pixels, turning on the corresponding sub-pixels row by row. For example, scan signal G1 is input from one or both ends of the first scan line to turn on the sub-pixels in the first row; scan signal G2 is input from one or both ends of the second scan line to turn on the sub-pixels in the second row; scan signal G3 is input from one or both ends of the third scan line to turn on the sub-pixels in the third row; and scan signal G4 is input from one or both ends of the fourth scan line to turn on the sub-pixels in the fourth row.

[0029] Each data line is connected to a column of sub-pixels, charging the sub-pixels in the same row column by column.

[0030] Each output terminal of the data driver 100 is connected to a corresponding data line, providing a corresponding data signal for each data line. For example, if the above-mentioned display device is provided with 2160 columns of sub-pixels, there are corresponding 2160 data lines, and the data driver 100 needs to provide the first data signal S1 to the 2160th data signal S2160 accordingly.

[0031] Figure 2 for Figure 1 The driving timing diagram of the display device is shown. When the scan signal turns on the corresponding row of sub-pixels row by row, the data signal set DS charges each row of sub-pixels one by one. The data signal set DS may include the aforementioned data signal S1 through data signal S2160. For example, when the scan signal G1 turns on the first row of sub-pixels during its negative pulse, the data signal set DS charges each sub-pixel in the first row one by one. When the scan signal G2 turns on the second row of sub-pixels during its negative pulse, the data signal set DS charges each sub-pixel in the second row one by one. When the scan signal G3 turns on the third row of sub-pixels during its negative pulse, the data signal set DS charges each sub-pixel in the third row one by one. When the scan signal G4 turns on the fourth row of sub-pixels during its negative pulse, the data signal set DS charges each sub-pixel in the fourth row one by one. The driving timings for the sub-pixels in the other rows can be deduced in the same way.

[0032] Correspondingly, the driving structure and driving timing of the above display device require the data driver 100 to have the following characteristics: Figure 3 As shown in the structure, the data driver 100 includes a front-end processor 10, a mobile industry processor interface 20, a random access memory 30, a mid-end processor 40, a data latch 50, a digital-to-analog converter 60, a data mapper, and an amplifier module 80, which are connected in sequence. The front-end processor 10 receives video data, and the amplifier module 80 outputs data signals to the corresponding data lines.

[0033] However, with the continuous development of high-frequency display, the above-mentioned driving architecture and driving timing have been unable to provide the required charging time for the corresponding sub-pixels under higher-frequency display. In view of this, this embodiment provides a data driver 100, see Figures 4 to 9 ,like Figure 6 As shown, the data driver 100 includes a cache module 41 and at least two data processing branches. The cache module 41 is used to synchronously output picture data corresponding to at least two rows of sub-pixels; each data processing branch is connected to the cache module 41 and a group of data lines, and the at least two data processing branches are used to synchronously output corresponding data signals to at least two rows of sub-pixels based on the received picture data.

[0034] It should be noted that compared with Figure 3 The data driver 100 shown in this embodiment is further provided with a buffer module 41 and a data processing branch, which can cooperate to synchronously process the image data processed by the mid-end processor 40 to synchronously output data signals to corresponding data lines.

[0035] It can be understood that the data driver 100 and the display device provided in this embodiment synchronize the picture data corresponding to at least two rows of sub-pixels through the cache module 41, and at least two data processing branches can synchronously output corresponding data signals to at least two rows of sub-pixels. In this way, at least two rows of sub-pixels can be charged simultaneously. Compared with the row-by-row charging in traditional technology, the charging time required at the same refresh frequency is shorter, which effectively alleviates the technical problem of insufficient charging time under higher frequency display.

[0036] The input end of the cache module 41 is connected to the output end of the mid-end processor 40 .

[0037] In one embodiment, each data processing branch includes a data latch 50, a digital-to-analog converter 60, and a data mapping module 70. The input end of the data latch 50 is connected to the cache module 41 for capturing the image data of the corresponding row of sub-pixels row by row; the input end of the digital-to-analog converter 60 is connected to the output end of the data latch 50; the input end of the data mapping module 70 is connected to the output end of the digital-to-analog converter 60, and each output end of the data mapping module 70 is connected to a group of data lines for outputting corresponding data signals in the arranged order.

[0038] For example, the first data processing branch 571 may include a first data latch 51, a first digital-to-analog converter 61, and a first data mapping module 71 connected in sequence, and the second data processing branch 572 may include a second data latch 52, a second digital-to-analog converter 62, and a second data mapping module 72 connected in sequence. The first data latch 51 and the second data latch 52 may have the same function as the corresponding data latch 50, the first digital-to-analog converter 61 and the second digital-to-analog converter 62 may have the same function as the corresponding digital-to-analog converter 60, and the first data mapping module 71 and the second data mapping module 72 may have the same function as the corresponding data mapping module 70.

[0039] It should be noted that the number of data processing branches may be the same as the number of data line groups or the number of sub-pixel rows connected to the same group of scan lines.

[0040] In one embodiment, Figure 6 As shown, the data driver 100 further includes an amplifying module 80, each input end of the amplifying module 80 is correspondingly connected to the output ends of at least two data processing branches, and each output end of the amplifying module 80 is correspondingly connected to at least two groups of data lines.

[0041] Specifically, the input end of the amplification module 80 is connected to the output end of each data mapping module 70, for example, it can be connected to the output end of the first data mapping module 71 and the output end of the second data mapping module 72. The amplification module 80 can amplify the current and / or voltage of the data signal to improve the driving capability of the data signal.

[0042] In one embodiment, Figure 7 、 Figure 8 As shown, the data driver 100 further includes a register 90 , which stores selection parameters for controlling the number of data processing branches in working state and / or the number of line buffers in working state.

[0043] It should be noted that, in one embodiment, Figure 7 As shown, the aforementioned selection parameter can be 2 bits. When the 2 bits are 00, only one data processing branch in the data driver 100 is in operation. At this time, after the buffer module 41 receives the corresponding image data, it sequentially passes through the first data latch 51, the first digital-to-analog converter 61, the first data mapping module 71, and the amplification module 80, and then outputs data signals S1-S2160 to the corresponding sub-pixels in the display panel 300. The corresponding sub-pixels are then charged under the control of the scanning signals G1 and G2. Here, an example is taken where there are 2160 columns of sub-pixels in the display panel 300.

[0044] In one embodiment, Figure 8 As shown, the selection parameter can be 2 bits. When the 2 bits are 01, two data processing branches in the data driver 100 are in operation. At this time, after receiving the corresponding picture data, the buffer module 41 sequentially passes through the first data latch 51, the first digital-to-analog converter 61, the first data mapping module 71, and the amplification module 80, and then outputs the odd-numbered data signals of the data signals S1-S2160 to the corresponding sub-pixels in the display panel 300. At the same time, the even-numbered data signals of the data signals S1-S2160 sequentially pass through the second data latch 52, the second digital-to-analog converter 62, the second data mapping module 72, and the amplification module 80, and then outputs the even-numbered data signals of the data signals S1-S2160 to the corresponding sub-pixels in the display panel 300. Then, under the control of the scanning signals G1 and G2, the corresponding sub-pixels are charged. Here, the example is taken as having 2160 columns of sub-pixels in the display panel 300.

[0045] Similarly, the selection parameter can be 2 bits. When the 2 bits are 10, three data processing branches in the data driver 100 are in operation. Alternatively, the selection parameter can be 2 bits. When the 2 bits are 11, four data processing branches in the data driver 100 are in operation.

[0046] In one embodiment, the buffer module 41 includes at least two line buffers connected in series. The output end of each line buffer is correspondingly connected to the input end of a data processing branch. Each line buffer is used to temporarily store image data corresponding to a row of sub-pixels.

[0047] It should be noted that the above-mentioned selection parameter can be 2 bits. When the 2 bits are 00, the number of line buffers can be 0 or 1; when the 2 bits are 01, the number of line buffers can be 2; when the 2 bits are 10, the number of line buffers can be 3; when the 2 bits are 11, the number of line buffers can be 4.

[0048] like Figure 9 As shown, when the above selection parameter is 11, the data driver 100 has four data processing branches in a working state and four line buffers in a working state.

[0049] and Figure 8In comparison, the input end of the first data latch 51 is connected to the output end of the first line buffer 411, the input end of the second data latch 52 is connected to the output end of the second line buffer 412, the input end of the third data latch 53 is connected to the output end of the third line buffer 413, and the input end of the fourth data latch 54 is connected to the output end of the fourth line buffer 414. A third data processing branch and a fourth data processing branch are also newly added. The third data processing branch includes a third data latch 53, a third digital-to-analog converter 63, and a third data mapping module 73 connected in sequence. The fourth data processing branch includes a fourth data latch 54, a fourth digital-to-analog converter 64, and a fourth data mapping module 74 connected in sequence.

[0050] The output end of the third data mapping module 73 and the output end of the fourth data mapping module 74 are respectively connected to the input end of the amplification module 80 , and then the data signal is amplified by the amplification module 80 and then output to the display panel 300 .

[0051] It should be noted that the first segment of the image data output by the mid-end processor 40 first enters the first line buffer 411. Then, when the second segment of the image data enters the first line buffer 411, the first segment of the data simultaneously enters the second line buffer 412. Then, when the third segment of the image data enters the first line buffer 411, the second segment of the data simultaneously enters the second line buffer 412, and the first segment of the data simultaneously enters the third line buffer 413. Then, when the fourth segment of the image data enters the first line buffer 411, the third segment of the data simultaneously enters the second line buffer 412, the second segment of the data simultaneously enters the third line buffer 413, and the first segment of the data simultaneously enters the fourth line buffer 414. At this point, each line buffer stores one segment of data, and the counter 91 counts that a total of four segments of data have been entered, which triggers the cache module 41 to simultaneously output these four segments of data to the corresponding data processing branches.

[0052] Each piece of data may be a line or multiple lines of picture data, or a part of the picture data.

[0053] In one embodiment, the data driver 100 further includes a counter 91 . The counter 91 is connected to the buffer module 41 . The counter 91 is used to count the number of rows of screen data temporarily stored in the buffer module 41 to trigger the output of the buffer module 41 .

[0054] In one embodiment, this embodiment provides a display device, which includes the data driver according to at least one of the above embodiments, and the data driver is applied to higher frequency display.

[0055] It can be understood that the display device provided in this embodiment synchronizes the picture data corresponding to at least two rows of sub-pixels through the cache module 41, and at least two data processing branches can synchronously output corresponding data signals to at least two rows of sub-pixels, so that at least two rows of sub-pixels can be charged at the same time. Compared with the row-by-row charging in traditional technology, the charging time required at the same refresh frequency is shorter, which effectively alleviates the technical problem of insufficient charging time under higher frequency display.

[0056] It should be noted that the display device may be, but is not limited to, a self-luminous display device such as an organic light emitting diode display device, a micro light emitting diode display device, a mini light emitting diode display device or a quantum dot light emitting diode display device, or may be a liquid crystal display device.

[0057] In one embodiment, Figure 4 、 Figure 5 As shown, the display device also includes a plurality of sub-pixels distributed in an array, at least one group of scan lines, and at least two groups of data lines, each group of scan lines is connected to at least two rows of sub-pixels; each group of data lines is connected to one row of the at least two rows of sub-pixels to synchronously provide data signals to the at least two rows of sub-pixels.

[0058] It can be understood that the display device provided in this embodiment can simultaneously turn on at least two rows of sub-pixels by connecting each group of scan lines to at least two rows of sub-pixels, and each group of data lines is connected to one of the at least two rows of sub-pixels, and can synchronously provide data signals to at least two rows of sub-pixels. In this way, at least two rows of sub-pixels can be charged at the same time. Compared with the row-by-row charging in traditional technology, the charging time required at the same refresh frequency is shorter, which effectively alleviates the technical problem of insufficient charging time under higher frequency display.

[0059] It should be noted that each group of scan lines can be one or more. For example, scan line GL1 can be a group of scan lines that are connected to at least two rows of sub-pixels to simultaneously turn on the at least two rows of sub-pixels. Scan line GL1 and scan line GL2 can be a group of scan lines, wherein scan line GL1 is connected to the first row of sub-pixels to turn on the first row of sub-pixels, and scan line GL2 is connected to the second row of sub-pixels to turn on the second row of sub-pixels; scan line GL3 and scan line GL4 can be a group of scan lines, wherein scan line GL3 is connected to the third row of sub-pixels to turn on the third row of sub-pixels, and scan line GL4 is connected to the fourth row of sub-pixels to turn on the fourth row of sub-pixels; and the same applies to other groups of scan lines. Similarly, each group of scan lines can include three, four, or more scan lines, etc., to simultaneously turn on the sub-pixels of the corresponding rows.

[0060] The scan lines in the same group of scan lines may be adjacent or separated, and the same group of scan lines may also connect sub-pixels in adjacent rows or sub-pixels in non-adjacent rows. Preferably, the scan lines in the same group of scan lines are adjacent and connect sub-pixels in adjacent rows, which can reduce the crossing of lines within the display panel 300 and reduce the wiring distance.

[0061] In one embodiment, at least two groups of data lines include odd data lines as one group of data lines and even data lines as the other group of data lines, and the odd data lines and the even data lines are alternately arranged in sequence along the first direction DR1; each column of sub-pixels includes odd sub-pixels and even sub-pixels alternately arranged along the second direction DR2, the odd sub-pixels are connected to one of the odd data lines or the even data lines, and the even sub-pixels are connected to the other of the odd data lines or the even data lines.

[0062] Specifically, if Figure 4 As shown, two groups of data lines are used. One group of data lines consists of odd-numbered data lines, such as data line DL1, data line DL3, data line DL4317, and so on. This group of data lines provides corresponding data signals to the first row of sub-pixels, the third row of sub-pixels, and so on. The other group of data lines consists of even-numbered data lines, such as data line DL2, data line DL4, data line DL4320, and so on. This group of data lines provides corresponding data signals to the second row of sub-pixels, the fourth row of sub-pixels, and so on. Alternatively, odd-numbered data lines can be connected to corresponding even-numbered sub-pixels, and vice versa.

[0063] Among them, data line DL1 is used to transmit data signal S1 from data driver 100, data line DL2 is used to transmit data signal S2 from data driver 100, data line DL3 is used to transmit data signal S3 from data driver 100, data line DL4 is used to transmit data signal S4 from data driver 100... and so on.

[0064] Based on the above records, it can be understood that in some embodiments, three groups of data lines can also be used, wherein one group of data lines can provide corresponding data signals for some rows of sub-pixels, for example, the 1st, 4th, 7th... and so on rows of sub-pixels; wherein another group of data lines can provide corresponding data signals for other rows of sub-pixels, for example, the 2nd, 3rd, 8th... and so on rows of sub-pixels; wherein yet another group of data lines can provide corresponding data signals for yet another rows of sub-pixels, for example, the 3rd, 6th, 9th... and so on rows of sub-pixels.

[0065] It can be understood that in the above embodiment, the time that each frame can occupy in a higher frequency display is also less, and the more data lines are grouped, the shorter the writing time of the data signal in a frame is, which can meet the time requirement of charging the data signal to the corresponding sub-pixel in each frame.

[0066] In one embodiment, Figure 4 As shown, the display device also includes a start signal line STVL and at least two gate drive circuits 200, the start signal line STVL is connected to the at least two gate drive circuits 200; each group of scan lines includes at least two adjacent scan lines, one of the scan lines in each group is connected to one of the at least two rows of sub-pixels and one of the two gate drive circuits 200, and the other of the scan lines in each group is connected to the other row of the at least two rows of sub-pixels and the other of the two gate drive circuits 200.

[0067] It should be noted that the two gate drive circuits 200 of this embodiment are located on the left and right sides of the display area, respectively, and can simultaneously provide corresponding scan signals for the same scan line. Each gate drive circuit 200 includes multiple cascaded gate drive units, for example, gate drive unit GU11, gate drive unit GU12, gate drive unit GU13, gate drive unit GU14, etc., wherein gate drive unit GU11 is cascaded with gate drive unit GU13, gate drive unit GU12 is cascaded with gate drive unit GU14, and the same applies to the others.

[0068] The two ends of the scan line GL1 used to transmit the scan signal G1 are respectively connected to two gate drive units GU11. The two ends of the scan line GL2 used to transmit the scan signal G2 are respectively connected to two gate drive units GU12. The two ends of the scan line GL3 used to transmit the scan signal G3 are respectively connected to two gate drive units GU13. The two ends of the scan line GL4 used to transmit the scan signal G4 are respectively connected to two gate drive units GU14. The same applies to the other scan lines. This reduces the transmission loss of each scan signal in the corresponding scan line and improves the driving force of the scan signal.

[0069] The start signal line STVL is used to transmit a start signal STV. The start signal STV can control the two gate driving circuits 200 to work synchronously and output the same corresponding scan signal.

[0070] In one embodiment, the display device may use one gate driving circuit 200, which can also achieve the same driving timing as two gate driving circuits 200. This not only saves one gate driving circuit 200, but also reduces the space occupied by the frame of the display device.

[0071] Figure 5 for Figure 4 The following is a driving timing diagram of a display device, in which scan signals G1 and G2 have identical waveforms and simultaneously turn on the first and second rows of sub-pixels during their negative pulses. During this period, corresponding groups of data signals are simultaneously written to the first and second rows of sub-pixels. For example, data signals S1, etc. transmitted by odd-numbered data lines are written to the first row of sub-pixels, while data signals S2, etc. transmitted by even-numbered data lines are written to the second row of sub-pixels. Next, negative pulses of scan signals G3 and G4, each with the same waveform, arrive, and corresponding data signals are simultaneously written to the third and fourth rows of sub-pixels. This cycle repeats until all sub-pixels are fully charged. At the same refresh rate, this reduces the charging time per frame by half. Similarly, when more rows of sub-pixels are simultaneously written with data signals, the charging time per frame can be further reduced.

[0072] In one embodiment, the number of rows of sub-pixels connected to each group of scan lines is the same as the number of groups of data lines.

[0073] It should be noted that in this embodiment, each group of data lines charges a row of sub-pixels. As the number of data line groups or the number of rows of sub-pixels connected to each group of scan lines increases, more rows of sub-pixels will be written with data signals at the same time, which can reduce the charging time in each frame.

[0074] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] The above is a detailed introduction to the data driver and display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data driver, characterized in that: include: A buffer module, configured to synchronously output picture data corresponding to at least two rows of sub-pixels; and at least two data processing branches, each of the data processing branches being connected to the buffer module and a group of data lines, and configured to synchronously output corresponding data signals to the at least two rows of sub-pixels according to the received picture data; The cache module includes at least two line buffers connected in series, the output end of each line buffer is correspondingly connected to the input end of one of the data processing branches, and each line buffer is used to temporarily store the image data corresponding to a row of sub-pixels; The data driver further includes a register storing a selection parameter, wherein the selection parameter is used to control the number of the data processing branches in working state and the number of the line buffers in working state.

2. The data driver according to claim 1, wherein The data driver further includes a counter connected to the cache module, and configured to count the number of rows of the picture data temporarily stored in the cache module, so as to trigger the cache module to output.

3. The data driver according to claim 1, wherein: Each of the data processing branches includes: A data latch, wherein an input end of the data latch is connected to the cache module and is used to capture the picture data of the sub-pixels in the corresponding row row by row; a digital-to-analog converter, wherein an input terminal of the digital-to-analog converter is connected to an output terminal of the data latch; A data mapping module, wherein the input end of the data mapping module is connected to the output end of the digital-to-analog converter, and each output end of the data mapping module is correspondingly connected to the group of data lines, for outputting corresponding data signals in the arranged order.

4. The data driver according to claim 1, wherein: The data driver further includes an amplifying module, each input end of the amplifying module is correspondingly connected to the output end of the at least two data processing branches, and each output end of the amplifying module is correspondingly connected to the at least two groups of data lines.

5. A display device, characterized in that: The data driver according to any one of claims 1 to 4 is applied to higher frequency display.

6. The display device according to claim 5, wherein: The display device further includes: A plurality of sub-pixels distributed in an array; at least one group of scan lines, each group of scan lines being connected to at least two rows of sub-pixels; and At least two groups of data lines are provided, each group of data lines being connected to one of the at least two rows of sub-pixels to synchronously provide data signals to the at least two rows of sub-pixels.

7. The display device according to claim 6, wherein: The number of rows of sub-pixels connected to each group of scan lines is the same as the number of groups of data lines.

8. The display device according to claim 6, wherein: The at least two groups of data lines include odd-numbered data lines as one group of data lines and even-numbered data lines as another group of data lines, and the odd-numbered data lines and the even-numbered data lines are alternately arranged in sequence along a first direction; Each column of sub-pixels includes odd sub-pixels and even sub-pixels alternately arranged along the second direction, the odd sub-pixels are connected to one of the odd data lines or the even data lines, and the even sub-pixels are connected to the other of the odd data lines or the even data lines.

9. The display device according to claim 6, wherein: The display device further includes a start signal line and at least two gate driving circuits, wherein the start signal line is connected to the at least two gate driving circuits; Each group of scan lines includes at least two adjacent scan lines, one of the scan lines in each group is connected to one row of the at least two rows of sub-pixels and one of the two gate drive circuits, and the other scan line in each group is connected to the other row of the at least two rows of sub-pixels and the other of the two gate drive circuits.

Images