Semiconductor Packaging Structure and Fabrication Method

Abstract

This invention provides a semiconductor packaging structure and its fabrication method. The semiconductor packaging structure includes a lead frame, a chip mounted on a base island of the lead frame, bonding wires electrically connecting the chip to the inner pins of the lead frame, and a molding compound covering the chip and the bonding wires. The inner pins have bonding areas that bond to second solder joints of the bonding wires. The bonding areas have grooves, the groove opening size of which is smaller than the groove's internal size, and the second solder joint is bonded to the groove. A filler is placed in the groove, and the filler composition includes epoxy resin forming the molding compound. This enhances the bonding force between the second solder joint and the inner pin, improves the problem of second solder joint detachment or insufficient tensile strength, and enhances the bonding force between the filler and the molding compound, thereby making it less prone to delamination between the lead frame and the molding compound, and improving the reliability of the semiconductor packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] Currently, semiconductor packaging structures generally use lead frames as the carrier of chips. The chip is electrically connected to the inner pins of the lead frame by bonding wires (gold, silver, copper wires, etc.) to achieve circuit connection. In addition, the chip is connected to the PCB board through the outer pins on the lead frame.

[0003] However, the second solder joint, which connects the wire to the inner pin, is formed by pressing down with a wedge, meaning it's bonded to the wire bonding area of ​​the inner pin through a pressing process. This inherently results in weak bonding strength between the second solder joint and the inner pin. Furthermore, after the second solder joint is wire bonded, subsequent processes and environmental temperature and humidity can easily cause it to detach or result in insufficient tensile strength, affecting product reliability and ultimately impacting product lifespan.

[0004] In view of this, it is necessary to provide a new semiconductor packaging structure and fabrication method to solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor packaging structure and its preparation method.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: a semiconductor packaging structure, comprising a lead frame, a chip mounted on a base island of the lead frame, bonding wires electrically connecting the chip to the inner pins of the lead frame, and a molding compound covering the chip and the bonding wires, wherein the inner pins have a bonding area that combines with a second solder joint of the bonding wire; the bonding area has:

[0007] A groove, wherein the opening size of the groove is smaller than the internal size of the groove, and the second weld point is bonded to the groove;

[0008] A filler is provided to fill the groove, wherein the filler comprises an epoxy resin that forms the encapsulation.

[0009] As a further improvement of the present invention, the filler material is conductive epoxy resin.

[0010] As a further improvement of the present invention, the groove has a silver plating layer, and the conductive material in the composition of the filler is silver.

[0011] As a further improvement of the present invention, the material of the filler is the same as the material of the encapsulation body; the filler and the encapsulation body are integrally formed.

[0012] As a further improvement of the present invention, the bonding area has a substrate layer and a silver plating layer located on the upper surface of the substrate layer, the groove is formed on the substrate layer, and the silver plating layer is formed in the groove.

[0013] As a further improvement of the present invention, the bonding area has a substrate layer, the groove is formed on the substrate layer, and the depth of the groove is half the thickness of the substrate layer.

[0014] As a further improvement of the present invention, the inner pin has a substrate layer, the substrate layer has a first region corresponding to the wire bonding area and a second region located on the periphery of the wire bonding area; the roughness of the first region is greater than the roughness of the second region.

[0015] To achieve the above-mentioned objectives, the present invention also provides a method for fabricating a semiconductor packaging structure, the method comprising the following steps:

[0016] A groove is formed in the bonding area of ​​the lead frame pin for bonding with the second solder joint of the wire, the groove opening size being smaller than the groove internal size;

[0017] The chip is mounted on the base island of the lead frame, and wire bonding is performed between the chip and the groove to form an electrical connection between the chip and the inner pin.

[0018] The groove is filled with liquid filler and then solidified to form a filler body;

[0019] A molding compound is used to form a molding encapsulation that covers the chip and the bonding wires;

[0020] Both the filler and the molding compound contain epoxy resin.

[0021] As a further improvement of the present invention, the filler is a conductive epoxy resin.

[0022] As a further improvement of the present invention, the groove has a silver-plated layer, and the filler is a silver-containing conductive epoxy resin.

[0023] As a further improved technical solution of the present invention, the filler is the same as the molding compound; "filling the groove with liquid filler and curing to form a filler body" and "using molding compound to form a molding compound covering the chip and the lead frame" specifically means: using molding compound to fill the groove and cover the chip and the bonding wire, and curing to form the filler body and the molding compound.

[0024] As a further improvement to the present invention, "forming a groove in the bonding area of ​​the lead frame pin for combining with the second solder joint of the solder wire, wherein the groove opening size is smaller than the groove internal size" specifically includes the following steps:

[0025] A groove is formed on the substrate layer corresponding to the inner pin and the wire bonding area, wherein the groove opening size is smaller than the groove internal size;

[0026] A silver plating layer is formed on the substrate layer in the area corresponding to the wire bonding area.

[0027] As a further improved technical solution of the present invention, "forming a silver plating layer in the area corresponding to the wire bonding area on the substrate layer" specifically means: forming a silver plating layer in the groove.

[0028] As a further improvement of the present invention, the depth of the groove is half the thickness of the substrate layer.

[0029] As a further improvement of the present invention, after the step of "forming a groove on the substrate layer corresponding to the inner pin and the wire bonding area" and before the step of "forming a silver plating layer on the substrate layer in the area corresponding to the wire bonding area", the method for preparing the semiconductor packaging structure further includes the following steps:

[0030] Roughen the area on the substrate layer corresponding to the wire bonding area.

[0031] The beneficial effects of this invention are as follows: In the semiconductor packaging structure of this invention, a groove is provided in the bonding area of ​​the inner pin to connect with the second solder joint of the bonding wire, and the size of the groove opening is set to be smaller than the internal size of the groove. Simultaneously, an epoxy resin filler is included in the molding component within the groove. This increases the bonding area between the bonding wire and the inner pin, enhances the bonding force between the second solder joint and the inner pin, improves the problem of wire detachment or insufficient pull force of the second solder joint, improves the reliability and electrical performance of the semiconductor packaging structure, and enhances the bonding force between the filler and the molding compound, thereby making it less prone to delamination between the lead frame and the molding compound, and improving the reliability of the semiconductor packaging structure. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a semiconductor packaging structure according to a specific embodiment of the present invention, wherein the molding compound is omitted;

[0033] Figure 2 for Figure 1 A schematic diagram of the pin structure, wherein the second solder joint of the solder wire is bonded to the groove;

[0034] Figure 3 for Figure 2 Sectional view along axis AA;

[0035] Figure 4 This is a flowchart of the preparation method in this invention. Detailed Implementation

[0036] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. Please refer to the accompanying drawings for further details. Figures 1-4 The figures shown represent preferred embodiments of the present invention. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent modifications or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0037] Meanwhile, the accompanying drawings are all in a very simplified form and use non-precise proportions, only to facilitate and clearly illustrate the various embodiments of the present invention.

[0038] It should be noted that the method for fabricating the semiconductor package structure described herein includes a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which these steps can be performed. Some of the steps described herein may be omitted, or other steps not described herein may be added to the method for fabricating the semiconductor package structure.

[0039] Please refer to Figures 1-3 As shown, the present invention provides a semiconductor packaging structure 10, including a lead frame 1, a chip 2 attached to a base island 11 of the lead frame 1, bonding wires 3 electrically connecting the chip 2 to the inner pins 12 of the lead frame 1, and a plastic encapsulation covering the chip 2 and the bonding wires 3.

[0040] The bonding wire 3 has a first solder joint that connects to an external terminal on the chip 2 and a second solder joint 31 that connects to a bonding area on the inner pin 12, thereby achieving an electrical connection between the chip 2 and the inner pin 12.

[0041] Furthermore, the wire bonding area has a downwardly recessed groove 121, and the second solder joint 31 is bonded to the groove 121. The groove 121 is filled with a filler 122, which effectively increases the bonding area between the solder wire 3 and the inner pin 12, enhancing the bonding force between the second solder joint 31 and the inner pin 12. This improves the problem of the second solder joint 31 detaching or having insufficient tensile strength, preventing the second solder joint 31 from falling off, thereby improving the reliability and electrical performance of the semiconductor package structure 10.

[0042] Specifically, the inner pin 12 has a substrate layer 123 and a silver plating layer 124 disposed on the upper surface of the substrate layer 123. The substrate layer 123 has a first region corresponding to the bonding area and a second region located on the periphery of the bonding area, and the silver plating layer 124 is disposed in the first region.

[0043] It is understood that all regions in the substrate layer 123 except for the first region corresponding to the bonding area are the second region.

[0044] The groove 121 is formed on the substrate layer 123 and located in the first region, that is, the groove 121 is formed on the substrate layer 123 before the silver plating layer 124 is formed.

[0045] In one specific embodiment, the silver plating layer 124 is formed only within the groove 121, thereby reducing the contact between the molding compound and the silver plating layer 124, making it less likely for the lead frame 1 to delaminate from the molding compound, and improving the reliability of the semiconductor package structure 10. Of course, this is not a limitation; in other embodiments, the silver plating layer 124 may be formed on the entire substrate layer 123 at positions corresponding to the wire bonding area.

[0046] Furthermore, the depth of the groove 121 is half the thickness of the substrate layer 123. This is to balance the strength of the lead frame 1 and the bonding force between the solder wire 3 and the inner pin 12.

[0047] Furthermore, the groove opening size of the groove 121 is smaller than the internal size of the groove 121, which makes it difficult for the filler 122 to detach from the groove 121, indirectly preventing the second solder joint 31 from falling off, thereby improving the reliability and electrical performance of the semiconductor packaging structure 10.

[0048] Specifically, the cross-section of the groove 121 can be circular, and the longitudinal section of the groove 121 can be trapezoidal or... Figure 3 The shape shown is small at the top and bottom and large in the middle. Of course, it is not limited to this.

[0049] Furthermore, since the roughness of the first region is greater than that of the second region, it is understood that the inner side of the groove 121 also belongs to the first region. This can improve the bonding force between the second solder joint 31 and the groove 121, and at the same time improve the bonding force between the filler 122 and the groove 121, thereby enhancing the bonding force between the second solder joint 31 and the inner pin 12, improving the problem of the second solder joint 31 being detached or having insufficient tensile strength, and preventing the second solder joint 31 from falling off. At the same time, it can also improve the bonding force between the molding compound and the inner pin 12, thereby improving the reliability and electrical performance of the semiconductor package structure 10.

[0050] Furthermore, the filler 122 comprises epoxy resin, which forms the encapsulation body. That is, the filler material forming the filler 122 contains epoxy resin, which improves the bonding strength between the filler 122 and the encapsulation body, making it less prone to delamination between the lead frame 1 and the encapsulation body, thus improving the reliability of the semiconductor packaging structure 10. Simultaneously, the filler 122 has a certain degree of fluidity before curing, facilitating its injection into and filling of the groove 121.

[0051] In this embodiment, the filler 122 is made of conductive epoxy resin, which helps to improve the conductivity between the bonding wire 3 and the inner pin 12. Simultaneously, the conductive material in the conductive epoxy resin, combined with the silver plating layer 124 in the groove 121, also improves the bonding force between the filler 122 and the groove 121, further making the filler 122 less likely to detach from the groove 121. Of course, this is not a limitation; in other embodiments, the material of the filler 122 can also be the same as the material of the encapsulation body. In this case, the filler 122 and the encapsulation body can be integrally molded, simplifying the fabrication process of the semiconductor packaging structure 10.

[0052] Furthermore, in an embodiment where the material of the filler 122 is the conductive epoxy resin with conductive properties, the second solder point 31 can be directly soldered to the silver plating layer 124 within the groove 121, or the second solder point 31 can be located within the filler 122 and electrically connected to the silver plating layer 124 through the filler 122.

[0053] Specifically, in an embodiment where the conductive metal layer within the groove 121 is a silver-plated layer 124, the conductive epoxy resin can be a conductive epoxy resin with silver as its conductive material. However, this is not a limitation. Further, please refer to... Figure 4 As shown, combined with Figures 1-3 The present invention also provides a method for preparing the above-mentioned semiconductor package structure 10, comprising the following steps:

[0054] A groove 121 is formed in the bonding area of ​​the lead frame 12 to be combined with the second solder point 31 of the solder wire 3. The groove opening size of the groove 121 is smaller than the internal size of the groove 121.

[0055] Chip 2 is mounted on the base island 11 of lead frame 1, and wire bonding is performed between chip 2 and the groove 121 to form a bonding wire 3 that electrically connects chip 2 and inner pin 12;

[0056] The groove 121 is filled with liquid filler and solidified to form filler 122;

[0057] A molding compound is used to form a molding compound that encapsulates the chip 2 and the lead frame 1;

[0058] Both the filler and the molding compound contain epoxy resin.

[0059] In the method for fabricating the semiconductor package structure 10 of the present invention, by providing a groove 121 in the bonding area of ​​the inner pin 12 to bond with the second solder joint 31 of the bonding wire 3, and simultaneously forming a filler 122 in the groove 121, the bonding area between the bonding wire 3 and the inner pin 12 is increased. This enhances the bonding force between the second solder joint 31 and the inner pin 12, improves the problem of the second solder joint 31 detaching or insufficient tensile strength, and prevents the second solder joint 31 from falling off, thereby improving the reliability and electrical performance of the semiconductor package structure 10. Furthermore, both the filler and the molding compound forming the filler 122 contain epoxy resin, which enhances the bonding force between the filler 122 and the molding compound, making it less likely for the lead frame 1 and the molding compound to delaminate, thus improving the reliability of the semiconductor package structure 10.

[0060] Meanwhile, the dimensions of the groove 121 are set such that the groove opening size is smaller than the internal dimensions of the groove 121, which makes it difficult for the filler 122 to detach from the groove 121, indirectly preventing the second solder joint 31 from falling off, thereby improving the reliability and electrical performance of the semiconductor packaging structure 10.

[0061] Furthermore, "forming a groove 121 in the bonding area of ​​the lead frame 12 for bonding with the second solder point 31 of the solder wire 3, wherein the groove opening size of the groove 121 is smaller than the internal size of the groove 121" specifically includes the following steps:

[0062] A groove 121 is formed on the substrate layer 123 corresponding to the inner pin 12 and the wire bonding area, wherein the groove opening size of the groove 121 is smaller than the internal size of the groove 121;

[0063] A silver plating layer 124 is formed on the substrate layer 123 in the area corresponding to the wire bonding area.

[0064] In one specific embodiment, a groove 121 is formed on the substrate layer 123 corresponding to the inner pin 12 and the wire bonding area by an etching process, so that the groove opening size of the groove 121 is smaller than the internal size of the groove 121. Of course, this is not a limitation.

[0065] The etching process can use existing etching processes, which will not be elaborated here.

[0066] Specifically, the depth of the groove 121 is half the thickness of the substrate layer 123. This balances the strength of the lead frame 1 and the bonding force between the solder wire 3 and the inner pin 12.

[0067] Furthermore, "forming a silver plating layer 124 in the area corresponding to the wire bonding area on the substrate layer 123" specifically means forming a silver plating layer 124 within the groove 121. This reduces the contact between the molding compound and the silver plating layer 124, making delamination between the lead frame 1 and the molding compound less likely, and improving the reliability of the semiconductor package structure 10. Of course, this is not a limitation; in other embodiments, the silver plating layer 124 can be formed on the entire substrate layer 123 at the position corresponding to the wire bonding area.

[0068] Furthermore, the filler is a conductive epoxy resin. This is beneficial for improving the conductivity between the bonding wire 3 and the inner pin 12; simultaneously, the conductive material in the conductive epoxy resin, combined with the silver plating layer 124 in the groove 121, also improves the bonding force between the filler 122 and the groove 121, further making the filler 122 less likely to detach from the groove 121. At this point, after wire bonding is completed, the groove 121 is first filled with liquid filler and cured to form the filler 122, and then a molding compound is used to form a molding compound covering the chip 2 and the lead frame 1.

[0069] Of course, this is not a limitation. In other embodiments, the material of the filler 122 can also be the same as the material of the encapsulation body. In this case, "filling the groove 121 with liquid filler and curing to form the filler 122" and "forming an encapsulation body covering the chip 2 and the lead frame 1 using encapsulation material" specifically means: filling the groove 121 with encapsulation material and covering the chip 2 and the lead frame 1, and curing to form the filler 122 and the encapsulation body. That is, the filler 122 and the encapsulation body can be integrally formed, simplifying the fabrication process of the semiconductor packaging structure 10.

[0070] In an embodiment where the conductive metal layer within the groove 121 is a silver-plated layer 124, the filler is a silver-containing conductive epoxy resin to further enhance the bonding force between the filler 122 and the silver-plated layer 124, and to enhance the bonding force between the filler 122 and the groove 121. However, this is not a limitation.

[0071] Furthermore, after the step of "forming a groove 121 on the substrate layer 123 corresponding to the wire bonding area of ​​the inner pin 12", and before the step of "forming a silver plating layer 124 on the substrate layer 123 corresponding to the wire bonding area", the method for fabricating the semiconductor package structure 10 further includes the following steps:

[0072] The area on the substrate layer 123 corresponding to the wire bonding area is roughened.

[0073] It is understood that the inner side of the groove 121 also belongs to the area on the substrate layer 123 corresponding to the wire bonding area, which can improve the bonding force between the second solder joint 31 and the groove 121, and at the same time improve the bonding force between the filler 122 and the groove 121, so as to enhance the bonding force between the second solder joint 31 and the inner pin 12, improve the problem of the second solder joint 31 being detached or having insufficient tensile strength, and prevent the second solder joint 31 from falling off; at the same time, it can also improve the bonding force between the molding compound and the inner pin 12, thereby improving the reliability and electrical performance of the semiconductor package structure 10.

[0074] Compared with the prior art, in the semiconductor packaging structure 10 of the present invention, a groove 121 is provided in the bonding area of ​​the inner pin 12 to connect with the second solder joint 31 of the bonding wire 3, and the size of the groove opening is set to be smaller than the internal size of the groove 121. At the same time, the epoxy resin filler 122 is included in the molding component within the groove 121. This increases the bonding area between the bonding wire 3 and the inner pin 12, enhances the bonding force between the second solder joint 31 and the inner pin 12, improves the problem of wire detachment or insufficient tensile strength of the second solder joint 31, improves the reliability and electrical performance of the semiconductor packaging structure 10, and enhances the bonding force between the filler 122 and the molding compound, thereby making it less likely for the lead frame 1 and the molding compound to delaminate, and improving the reliability of the semiconductor packaging structure 10.

[0075] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0076] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, comprising a lead frame, a chip mounted on a base island of the lead frame, bonding wires electrically connecting the chip to an inner pin of the lead frame, and a molding compound covering the chip and the bonding wires, wherein the inner pin has a bonding area that combines with a second solder joint of the bonding wire; characterized in that: The bonding area has: A groove, wherein the opening size of the groove is smaller than the internal size of the groove, and the second weld point is bonded to the groove; A filler is provided in the groove, the filler having an epoxy resin that forms the encapsulation, the filler filling the groove completely; The sidewalls and bottomwalls of the groove are silver-plated, and the filler material is silver-containing conductive epoxy resin.

2. The semiconductor packaging structure as described in claim 1, characterized in that: The bonding area has a substrate layer, and the groove is formed on the substrate layer, the depth of which is half the thickness of the substrate layer.

3. The semiconductor packaging structure as described in claim 1, characterized in that: The inner pin has a substrate layer, the substrate layer has a first region corresponding to the wire bonding area and a second region located on the periphery of the wire bonding area; the roughness of the first region is greater than the roughness of the second region.

4. A method for fabricating a semiconductor packaging structure, characterized in that: The preparation method includes the following steps: A groove is formed in the bonding area of ​​the lead frame pin for bonding with the second solder joint of the wire, the groove opening size being smaller than the groove internal size; The chip is mounted on the base island of the lead frame, and wire bonding is performed between the chip and the groove to form an electrical connection between the chip and the inner pin. The groove is filled with liquid filler and solidified to form a filler body, which fills the groove completely; A molding compound is used to form a molding encapsulation that covers the chip and the bonding wires; The filler and molding compound both contain epoxy resin; the sidewalls and bottomwalls of the groove have silver plating layers, and the filler is a silver-containing conductive epoxy resin.

5. The method for fabricating the semiconductor packaging structure as described in claim 4, characterized in that: "Forming a groove in the bonding area of ​​the lead frame pin for bonding with the second solder joint of the wire, wherein the groove opening size is smaller than the groove internal size" specifically includes the following steps: A groove is formed on the substrate layer corresponding to the inner pin and the wire bonding area, wherein the groove opening size is smaller than the groove internal size; A silver plating layer is formed on the substrate layer in the area corresponding to the wire bonding area.

6. The method for fabricating a semiconductor packaging structure as described in claim 5, characterized in that: The depth of the groove is half the thickness of the substrate layer.

7. The method for fabricating a semiconductor packaging structure as described in claim 5, characterized in that: After the step of "forming a groove on the substrate layer corresponding to the wire bonding area of ​​the inner pin" and before the step of "forming a silver plating layer on the substrate layer in the area corresponding to the wire bonding area", the method for fabricating the semiconductor package structure further includes the following steps: Roughen the area on the substrate layer corresponding to the wire bonding area.

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