Wafer alignment mark, manufacturing method, wafer alignment apparatus, and wafer alignment method

Abstract

The present invention provides a wafer alignment mark, a manufacturing method, a wafer alignment device and a wafer alignment method. The wafer alignment mark can generate self-emitted infrared light when forward-biased and turned on. By using the self-emitted infrared light to replace the externally incident infrared light, when using this wafer alignment mark for alignment, since the infrared light is directly generated from within the wafer, the optical path loss generated when the external infrared light enters the substrate from the epitaxial layer is avoided. The wafer alignment mark has a wide range of applications and can be applied to the manufacturing processes of semiconductor devices such as power MOS, IGBT, BCD, and superjunction devices. In addition, the wafer alignment device used in conjunction with the wafer alignment mark has a simple structure, does not require an additional configuration of a He-Ne laser, and can also use the light source to improve the signal-to-noise ratio of the infrared light, having high practical value in existing lithography equipment.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor lithography, and in particular to a wafer alignment mark, a manufacturing method, a wafer alignment device, and a wafer alignment method. Background Art

[0002] In the semiconductor manufacturing process, lithography is the core of chip manufacturing. The production of a chip requires dozens of lithography processes to be completed, and some structural layers even require multiple lithography processes to be formed. Among them, interlayer alignment is the most important step in lithography, which ensures the alignment between the mask pattern and the pattern already existing on the silicon wafer. To complete interlayer alignment, an on-chip reference object, that is, an alignment mark, is required. A unified alignment mark is used as a reference object between each layer structure for alignment to prevent misalignment between process layers.

[0003] Early, before epitaxy and chip manufacturing process were carried out on the substrate, a certain number of trenches were fabricated on the substrate, as shown in FIGS. 1(a) and 1(b). The substrate trenches 111 on the substrate 11 were used as alignment marks. However, when the epitaxial layer 12 was grown on the substrate 11, due to the influence of factors such as epitaxial layer material and process, the epitaxial layer trenches 121 formed in the area above the substrate trenches 111 did not completely replicate the trench pattern of the substrate trenches 111. Usually, the trench pattern of the epitaxial layer trenches 121 would have an offset or deformation. Moreover, due to the absorption and reflection of visible light 31 by the epitaxial layer 12, ordinary visible light 31 was difficult to penetrate the epitaxial layer 12 to reach the surface of the substrate 11. Therefore, it was difficult to observe the substrate trenches 111 on the substrate 11 by means of visible light 31. The original substrate trenches 111 used as alignment reference objects could not play the alignment role, and only the epitaxial layer trenches 121 could be used as new alignment reference objects. However, due to the offset, deformation and other situations of the epitaxial layer trenches 121, it caused difficulties in alignment. Later, technicians proposed a "SMASH scheme" (SMart Alignment Sensor Hybrid) used in ASML lithography machines, such as Figure 2As shown in the figure, the "SMASH solution" utilizes the penetrability of infrared light through the epitaxial layer and the principle of light diffraction. First, the depth of the substrate trench used as an alignment mark is controlled within a suitable numerical range. After the epitaxial process is completed, the wafer 1 is placed on the stage 2, and the wafer is irradiated with infrared light emitted by the He-Ne laser 3. Since infrared light is not easily absorbed by the epitaxial layer, the infrared light can penetrate the epitaxial layer to reach the substrate. With the help of the light diffraction effect, bright and dark diffraction fringes will appear after the incident infrared light is reflected by the substrate trench. The microscope 5 and the infrared sensor 4 are used to detect the fringe information, and then by moving the position of the stage 2 for placing the wafer 1, the substrate trench is moved to a preset position, thereby achieving precise alignment. As shown in FIGS. 3(a) and 3(b), this method utilizes the penetrability of the incident infrared light 32 through the epitaxial layer 12. The incident infrared light 32 can reach the surface of the substrate 11 without being affected by the epitaxial layer 12. Therefore, during the alignment process, the substrate trench 111 is always used as the alignment mark, while ignoring the effects of offsets, deformations, etc. that occur in the epitaxial layer trench 121.

[0004] However, the above "SMASH solution" requires a dedicated He-Ne laser, and most of the existing lithography equipment does not have the above He-Ne laser and its adapted optical path system. Assembling an incident system of a He-Ne laser on the original equipment requires expensive costs and it is difficult to ensure compatibility. Therefore, a new wafer alignment mark needs to be proposed to solve the alignment problem. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a wafer alignment mark, a manufacturing method, a wafer alignment device and a wafer alignment method, which are used to solve the problem of wafer alignment in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a wafer alignment mark, and the wafer alignment mark includes an infrared emitter, and the infrared emitter includes:

[0007] A substrate;

[0008] A local buried layer formed on the substrate;

[0009] An epitaxial layer formed on the substrate and the local buried layer;

[0010] Wherein, at least one pn junction is formed between the substrate, the local buried layer and the epitaxial layer to constitute the infrared emitter, and self-emitted infrared light is generated through the infrared emitter for alignment.

[0011] Optionally, the conductivity type of the substrate is p-type or n-type, and the conductivity type of the local buried layer and / or the epitaxial layer is opposite to the conductivity type of the substrate.

[0012] Optionally, the wafer alignment mark further includes a substrate trench, and diffraction fringes are generated when the substrate trench is irradiated by the self-emitting infrared light.

[0013] The present invention provides a method for manufacturing a wafer alignment mark, and the manufacturing method includes the following steps:

[0014] S1: Provide a substrate, and coat a photoresist layer on the surface of the substrate;

[0015] S2: Pattern the photoresist layer through a photolithography process;

[0016] S3: Perform ion implantation on the area where the photoresist layer is removed to form a local buried layer;

[0017] S4: Remove the remaining photoresist layer;

[0018] S5: Deposit an epitaxial layer on the substrate and the local buried layer;

[0019] Wherein, at least one pn junction is formed among the substrate, the local buried layer and the epitaxial layer to constitute an infrared emitter, and self-emitting infrared light is generated through the infrared emitter for alignment.

[0020] Optionally, the conductivity type of the substrate is p-type or n-type, and the conductivity type of the local buried layer and / or the epitaxial layer is opposite to that of the substrate.

[0021] Optionally, the manufacturing method further includes:

[0022] Before step S5, form a substrate trench on the substrate through an etching process, and diffraction fringes are generated when the substrate trench is irradiated by the self-emitting infrared light.

[0023] The present invention provides a wafer alignment device, and the wafer alignment device includes a conductive stage for placing a wafer, and a microscope, an infrared sensor and an ion generator are arranged above the conductive stage, and the wafer is provided with the wafer alignment mark.

[0024] Optionally, the light source of the wafer alignment device includes a broadband light source or a visible light source, the light source is a pulsed light source, and the duty cycle of the pulsed light source is in the range of 30%-70%.

[0025] The present invention provides a wafer alignment method, and the wafer alignment method includes the following steps:

[0026] D1: Provide a wafer, and the wafer is provided with the wafer alignment mark according to any one of claims 1-3;

[0027] D2: Apply power to the wafer alignment mark to forward bias and turn on the infrared emitter;

[0028] D3: Use the self-emitted infrared light generated by the infrared emitter or the diffraction fringes generated by irradiating the substrate trench with the self-emitted infrared light as the alignment reference object, and complete the alignment by moving the wafer to make the alignment reference object reach a predetermined position.

[0029] Optionally, in step D3, a light source is used to irradiate the surface of the wafer to improve the signal-to-noise ratio of the alignment reference object. The light source includes a broadband light source or a visible light source. The light source is a pulsed light source, and the duty cycle of the pulsed light source is in the range of 30%-70%.

[0030] As described above, the wafer alignment mark, manufacturing method, wafer alignment device, and wafer alignment method of the present invention have the following beneficial effects: The wafer alignment mark provided by the present invention can generate self-emitted infrared light when forward-biased and turned on. Using the self-emitted infrared light to replace the externally incident infrared light, when using this wafer alignment mark for alignment, since the infrared light is directly generated from within the wafer, the optical path loss generated when the externally incident infrared light enters the substrate from the epitaxial layer is avoided. This wafer alignment mark has a wide range of applications and can be applied to the manufacturing processes of semiconductor devices such as power MOS, IGBT, BCD, and superjunction devices. In addition, the wafer alignment device used in conjunction with the wafer alignment mark has a simple structure, does not require an additional He-Ne laser, and can also use a light source to improve the signal-to-noise ratio of the infrared light, which has high practical value in existing lithography equipment. Description of the Drawings

[0031] Figures 1(a) and 1(b) show schematic diagrams of alignment using visible light in the prior art.

[0032] Figure 2 Shows a schematic diagram of the device structure of the "SMASH scheme" in the prior art.

[0033] Figures 3(a) and 3(b) show schematic diagrams of alignment using incident infrared light in the "SMASH scheme" in the prior art.

[0034] Figure 4 Shows a schematic diagram of the structure of the infrared emitter of the wafer alignment mark in the embodiment of the present invention.

[0035] Figures 5(a) to 5(c) Shows a schematic diagram of the structure of the wafer alignment mark with a substrate trench in the embodiment of the present invention.

[0036] Figure 6 Shows a schematic diagram of the structure of the wafer alignment device in the embodiment of the present invention.

[0037] Description of Element Numbers

[0038] 1 Wafer

[0039] 2. Stage

[0040] 3. He-Ne Laser

[0041] 4. Infrared Sensor

[0042] 5. Microscope

[0043] 6. Ion Generator

[0044] 20. Conductive Stage

[0045] 30. Light Source

[0046] 11. Substrate

[0047] 12. Epitaxial Layer

[0048] 31. Visible Light

[0049] 32. Incident Infrared Light

[0050] 33. Self-Emitted Infrared Light

[0051] 111. Substrate Trench

[0052] 121. Epitaxial Layer Trench

[0053] 112. Local Buried Layer Detailed Implementation Modes

[0054] The following uses specific specific examples to illustrate the implementation modes of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] When detailing the embodiments of the present invention, for the convenience of explanation, the cross-sectional views showing the device structure will be locally enlarged out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0056] For ease of description, spatial relationship terms such as "under", "below", "beneath", "underlying", "above", "over" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can be one or more intervening layers. As used herein, "between... and..." means including the endpoint values.

[0057] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0058] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, numbers, and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0059] Embodiment 1

[0060] This embodiment provides a wafer alignment mark, and the wafer alignment mark includes an infrared emitter for generating infrared light.

[0061] As Figure 4 shown, the infrared emitter specifically includes:

[0062] Substrate 11;

[0063] Local buried layer 112, formed on the substrate 11;

[0064] Epitaxial layer 12, formed on the substrate 11 and the local buried layer 112;

[0065] Wherein, at least one pn junction is formed between the substrate 11, the local buried layer 112, and the epitaxial layer 12 to constitute the infrared emitter, and self-emitted infrared light is generated through the infrared emitter for alignment.

[0066] As an example, the conductivity type of the substrate 11 is p-type or n-type, and the conductivity type of the local buried layer 112 and / or the epitaxial layer 12 is opposite to the conductivity type of the substrate 11.

[0067] Specifically, as shown in Table 1, the conduction types of the substrate 11, the local buried layer 112, and the epitaxial layer 12 include at least 6 combinations listed in Table 1.

[0068] Table 1

[0069] Epitaxial layer 12 n-type p-type n-type p-type p-type n-type Local buried layer 112 p-type n-type n-type p-type n-type p-type Substrate 11 p-type p-type p-type n-type n-type n-type

[0070] When the pn junction formed by the substrate 11, the local buried layer 112, and the epitaxial layer 12 conducts electricity, radiative recombination of electrons and holes occurs, and the generated emission spectrum can be divided into three regions: the first region, i.e., the region below the bandgap energy related to the radiative transition of holes; the second region, i.e., the near band-edge region related to the radiative recombination of electrons and holes; the third region, i.e., the high-energy region, such as the visible light wavelength range generated by the thermal electron transition in the conduction band. The photon energy corresponding to the emission spectrum in the second region is 1.1 eV and is located in the infrared light band. Thus, when the infrared emitter conducts electricity, the pn junction formed between the substrate 11, the local buried layer 112, and the epitaxial layer 12 generates the self-emitted infrared light 33. The self-emitted infrared light 33 can penetrate the epitaxial layer 12 without being reflected or absorbed and is not affected by the epitaxial layer 12. Therefore, the self-emitted infrared light 33 can be used as an alignment reference. Thus, the self-emitted infrared light 33 can be generated through the infrared emitter for alignment without adding an additional He-Ne laser.

[0071] This embodiment also provides a method for fabricating a wafer alignment mark. The fabrication method includes the following steps:

[0072] S1: Provide a substrate and coat a photoresist layer on the surface of the substrate;

[0073] S2: Pattern the photoresist layer through a photolithography process;

[0074] S3: Perform ion implantation on the area where the photoresist layer is removed to form a local buried layer;

[0075] S4: Remove the remaining photoresist layer;

[0076] S5: Deposit an epitaxial layer on the substrate and the local buried layer;

[0077] Wherein, at least one pn junction is formed between the substrate, the local buried layer, and the epitaxial layer to form an infrared emitter, and self-emitted infrared light is generated through the infrared emitter for alignment.

[0078] Specifically, the conductivity type of the substrate 11 is p-type or n-type, and the conductivity type of the local buried layer 112 and / or the epitaxial layer 12 is opposite to that of the substrate 11, so that at least one pn junction is formed between the substrate 11, the local buried layer 112 and the epitaxial layer 12 to constitute the infrared emitter, and self-emitted infrared light 33 is generated through the infrared emitter for alignment. As shown in Table 1 above, the conductivity types of the substrate 11, the local buried layer 112 and the epitaxial layer 12 include at least 6 combinations listed in Table 1.

[0079] When the wafer alignment mark formed by the manufacturing method is energized and turned on, a pn junction is formed between the substrate 11, the local buried layer 112 and the epitaxial layer 12 to generate the self-emitted infrared light 33. The self-emitted infrared light 33 can penetrate the epitaxial layer 12 without being reflected or absorbed and is not affected by the epitaxial layer 12. Therefore, the self-emitted infrared light 33 can be used as an alignment reference object. Using the self-emitted infrared light 33 for alignment does not require adding an additional He-Ne laser.

[0080] Embodiment 2

[0081] On the basis of the infrared emitter in Embodiment 1, a substrate trench is provided on the substrate to form a wafer alignment mark with a substrate trench. The specific structure is as Figures 5(a) to 5(c) shown. The wafer alignment mark further includes:

[0082] A substrate trench 111, the substrate trench 111 is located on the substrate 11, and the substrate trench 111 generates diffraction fringes when irradiated by the self-emitted infrared light 33.

[0083] As an example, the substrate trench 111 is located in the intrinsic region and / or the surrounding region of the infrared emitter, and specifically includes three setting methods shown in FIG. 5:

[0084] As shown in FIG. 5(a), the substrate trench 111 is located in the intrinsic region of the infrared emitter, that is, the substrate trench 111 is included in the infrared emitter;

[0085] As shown in FIG. 5(b), the substrate trench 111 is located in the surrounding region of the infrared emitter, that is, the substrate trench 111 is formed around the infrared emitter;

[0086] As shown in FIG. 5(c), the substrate trench 111 is located in the intrinsic region and the surrounding region of the infrared emitter.

[0087] Specifically, the substrate trench 111 is used to generate diffraction fringes. When the infrared emitter is powered on to emit the self-emitted infrared light 33, the substrate trench 111 will further generate diffraction fringes under the irradiation of the self-emitted infrared light 33. The diffraction fringes have obvious characteristics of alternating bright and dark. Therefore, the diffraction fringes can be used as an alignment reference, which is more accurate than the self-emitted infrared light 33 in the first embodiment.

[0088] When the substrate trench 111 is located in the surrounding area of the infrared emitter, that is, in the setting mode shown in FIG. 5(b), the photons in the self-emitted infrared light 33 swim in the substrate material and are reflected at the interface. Therefore, the substrate trench 111 can be illuminated to generate diffraction fringes.

[0089] When the substrate trench 111 is located in the intrinsic region and the surrounding area of the infrared emitter, that is, in the setting mode shown in FIG. 5(c), the self-emitted infrared light 33 directly emits from the position of the substrate trench 111 and illuminates the substrate trench 111 to generate diffraction fringes. Therefore, this structure combines the structural characteristics of FIGS. 5(a) and 5(b), and thus can achieve a better irradiation effect.

[0090] Among them, regarding the manufacturing method of the wafer alignment mark with the substrate trench 111, on the basis of the manufacturing method of the wafer alignment mark in the first embodiment, the formation step of the substrate trench 111 can be added. Specifically, it can be:

[0091] Before step S5, the substrate trench 111 is formed on the substrate 11 by an etching process. The substrate trench 111 generates diffraction fringes when irradiated by the self-emitted infrared light 33.

[0092] As an example, the substrate trench 111 is located in the intrinsic region and / or the surrounding area of the infrared emitter, specifically including the three setting modes shown in FIG. 5:

[0093] As shown in FIG. 5(a), the substrate trench 111 is located in the intrinsic region of the infrared emitter, that is, the infrared emitter includes the substrate trench 111;

[0094] As shown in FIG. 5(b), the substrate trench 111 is located in the surrounding area of the infrared emitter, that is, the substrate trench 111 is formed around the infrared emitter;

[0095] As shown in FIG. 5(c), the substrate trench 111 is located in the intrinsic region and the surrounding area of the infrared emitter.

[0096] Embodiment 3

[0097] This embodiment provides a wafer alignment device, which is used in cooperation with the wafer alignment marks in the above-mentioned Embodiment 1 and Embodiment 2 to complete alignment. The wafer alignment device includes: a conductive stage 20 for placing the wafer 1, the conductive stage 20 is conductive, a microscope 5 and an infrared sensor 4 are arranged above the conductive stage 20, and the microscope 5 and the infrared sensor 4 are used to observe the self-emitted infrared light emitted from the wafer 1. An ion generator 6 is arranged above the conductive stage 20, and a light source 30 may further be provided. The ion generator 6 is used to eject ions to electrically conduct the pn junction in the infrared emitter through the ion generator 6 and the conductive stage 20 to generate the self-emitted infrared light, so as to capture the self-emitted infrared light through the microscope 5 and the infrared sensor 4 for alignment. The light source 30 can be used to provide illumination to improve the signal-to-noise ratio (S / N ratio) of the infrared light. The light source 30 includes a broadband light source or a visible light source.

[0098] The specific usage method of this wafer alignment device is as follows: Place the wafer 1 with the above-mentioned wafer alignment marks on the conductive stage 20, the lower surface of the wafer 1 contacts the conductive stage 20, then energize the conductive stage 20, and at the same time use the ion generator 6 to eject charged ions onto the upper surface of the wafer 1. Among them, the positive and negative polarities of the power supply to the conductive stage 20 and the positive and negative polarities of the charged ions ejected by the ion generator 6 should be determined according to the conductive type of the wafer alignment marks on the wafer 1, so that the infrared emitter in the wafer alignment marks is forward-biased and conducts, thereby generating the self-emitted infrared light 33. Then, detect the self-emitted infrared light 33 or the diffraction fringes generated by the self-emitted infrared light 33 irradiating the substrate trench 111 through the microscope 5 and the infrared sensor 4, use the self-emitted infrared light 33 or the diffraction fringes generated via the substrate trench 111 as the alignment reference object, and complete the alignment by moving the conductive stage 20 to make the alignment reference object reach the predetermined position.

[0099] In addition, during the alignment process, the light source 30 can also be used to irradiate the surface of the wafer 1 to improve the signal-to-noise ratio of the infrared light. As an example, the light source 30 can be a pulsed light source, and the duty cycle of the pulsed light source is in the range of 30%-70% to obtain a higher signal-to-noise ratio, and the duty cycle is preferably 50%.

[0100] Embodiment 4

[0101] This embodiment provides a wafer alignment method, and the wafer alignment method includes the following steps:

[0102] D1: Provide a wafer, and the wafer has the wafer alignment marks in the above-mentioned Embodiment 1 or Embodiment 2;

[0103] D2: Energize the wafer alignment mark to forward bias and turn on the infrared emitter;

[0104] D3: Use the self-emitted infrared light generated by the infrared emitter or the diffraction fringes generated by irradiating the substrate trench with the self-emitted infrared light as the alignment reference object, and complete the alignment by moving the wafer to make the alignment reference object reach a predetermined position.

[0105] As an example, in step D3, the signal-to-noise ratio of the alignment reference object can be improved by irradiating the surface of the wafer with a light source. The light source includes a broadband light source or a visible light source. Further, the light source can be a pulsed light source, and the duty cycle of the pulsed light source is in the range of 30%-70% to obtain a higher signal-to-noise ratio. The duty cycle is preferably 50%.

[0106] In summary, the wafer alignment mark provided by the present invention can generate self-emitted infrared light when forward biased and turned on. By using the self-emitted infrared light to replace the externally incident infrared light, when using this wafer alignment mark for alignment, since the infrared light is directly generated from within the wafer, the optical path loss generated when the externally incident infrared light enters the substrate from the epitaxial layer is avoided. This wafer alignment mark has a wide range of applications and can be applied to the manufacturing processes of semiconductor devices such as power MOS, IGBT, BCD, and superjunction devices. In addition, the wafer alignment device used in conjunction with the wafer alignment mark has a simple structure, does not require an additional He-Ne laser, and can also use a light source to improve the signal-to-noise ratio of the infrared light, which has high practical value in existing lithography equipment.

[0107] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer alignment mark, characterized in that, the wafer alignment mark includes an infrared emitter, and the infrared emitter includes: a substrate; a local buried layer formed on the substrate; an epitaxial layer formed on the substrate and the local buried layer; wherein, at least one pn junction is formed between the substrate, the local buried layer and the epitaxial layer to constitute the infrared emitter, and self-emitted infrared light is generated by the infrared emitter for alignment.

2. The wafer alignment mark according to claim 1, characterized in that, the conductivity type of the substrate is p-type or n-type, and the conductivity type of the local buried layer and / or the epitaxial layer is opposite to that of the substrate.

3. The wafer alignment mark according to claim 1, characterized in that, the wafer alignment mark further includes a substrate trench, and diffraction fringes are generated when the self-emitted infrared light irradiates the substrate trench.

4. A manufacturing method of a wafer alignment mark, characterized in that, the manufacturing method includes the following steps: S1: Provide a substrate and coat a photoresist layer on the surface of the substrate; S2: Pattern the photoresist layer through a photolithography process; S3: Perform ion implantation on the area where the photoresist layer is removed to form a local buried layer; S4: Remove the remaining photoresist layer; S5: Deposit an epitaxial layer on the substrate and the local buried layer; wherein, at least one pn junction is formed between the substrate, the local buried layer and the epitaxial layer to constitute an infrared emitter, and self-emitted infrared light is generated by the infrared emitter for alignment.

5. The manufacturing method according to claim 4, characterized in that, the conductivity type of the substrate is p-type or n-type, and the conductivity type of the local buried layer and / or the epitaxial layer is opposite to that of the substrate.

6. The manufacturing method according to claim 4, characterized in that, the manufacturing method further includes: Before step S5, form a substrate trench on the substrate through an etching process, and diffraction fringes are generated when the self-emitted infrared light irradiates the substrate trench.

7. A wafer alignment device, characterized in that, the wafer alignment device includes a conductive stage for placing a wafer, and a microscope, an infrared sensor and an ion generator are arranged above the conductive stage, and the wafer is provided with the wafer alignment mark according to any one of claims 1-3.

8. The wafer alignment device according to claim 7, characterized in that, the wafer alignment device further includes a light source for providing illumination and for improving the signal-to-noise ratio of infrared light, the light source of the wafer alignment device includes a broadband light source or a visible light source, the light source is a pulsed light source, and the duty cycle of the pulsed light source is in the range of 30%-70%.

9. A wafer alignment method, characterized in that, the wafer alignment method includes the following steps: D1: Provide a wafer, and the wafer is provided with the wafer alignment mark according to any one of claims 1-3; D2: Apply power to the wafer alignment mark to make the infrared emitter forward-biased and conduct; D3: Using the self-emitted infrared light generated by the infrared emitter or the diffraction fringes generated by irradiating the substrate trench with the self-emitted infrared light as the alignment reference object, the alignment is completed by moving the wafer to make the alignment reference object reach a predetermined position.

10. The wafer alignment method according to claim 9, wherein, in step D3, a light source is used to irradiate the surface of the wafer to improve the signal-to-noise ratio of the alignment reference object. The light source includes a broadband light source or a visible light source. The light source is a pulsed light source, and the duty cycle of the pulsed light source is in the range of 30%-70%.

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